1/* 2 * Google Gru (and derivatives) board device tree source 3 * 4 * Copyright 2016-2017 Google, Inc 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/input/input.h> 46#include "rk3399.dtsi" 47#include "rk3399-op1-opp.dtsi" 48 49/ { 50 chosen { 51 stdout-path = "serial2:115200n8"; 52 }; 53 54 /* 55 * Power Tree 56 * 57 * In general an attempt is made to include all rails called out by 58 * the schematic as long as those rails interact in some way with 59 * the AP. AKA: 60 * - Rails that only connect to the EC (or devices that the EC talks to) 61 * are not included. 62 * - Rails _are_ included if the rails go to the AP even if the AP 63 * doesn't currently care about them / they are always on. The idea 64 * here is that it makes it easier to map to the schematic or extend 65 * later. 66 * 67 * If two rails are substantially the same from the AP's point of 68 * view, though, we won't create a full fixed regulator. We'll just 69 * put the child rail as an alias of the parent rail. Sometimes rails 70 * look the same to the AP because one of these is true: 71 * - The EC controls the enable and the EC always enables a rail as 72 * long as the AP is running. 73 * - The rails are actually connected to each other by a jumper and 74 * the distinction is just there to add clarity/flexibility to the 75 * schematic. 76 */ 77 78 ppvar_sys: ppvar-sys { 79 compatible = "regulator-fixed"; 80 regulator-name = "ppvar_sys"; 81 regulator-always-on; 82 regulator-boot-on; 83 }; 84 85 pp900_ap: pp900-ap { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp900_ap"; 88 89 /* EC turns on w/ pp900_ap_en; always on for AP */ 90 regulator-always-on; 91 regulator-boot-on; 92 regulator-min-microvolt = <900000>; 93 regulator-max-microvolt = <900000>; 94 95 vin-supply = <&ppvar_sys>; 96 }; 97 98 pp1200_lpddr: pp1200-lpddr { 99 compatible = "regulator-fixed"; 100 regulator-name = "pp1200_lpddr"; 101 102 /* EC turns on w/ lpddr_pwr_en; always on for AP */ 103 regulator-always-on; 104 regulator-boot-on; 105 regulator-min-microvolt = <1200000>; 106 regulator-max-microvolt = <1200000>; 107 108 vin-supply = <&ppvar_sys>; 109 }; 110 111 pp1800: pp1800 { 112 compatible = "regulator-fixed"; 113 regulator-name = "pp1800"; 114 115 /* Always on when ppvar_sys shows power good */ 116 regulator-always-on; 117 regulator-boot-on; 118 regulator-min-microvolt = <1800000>; 119 regulator-max-microvolt = <1800000>; 120 121 vin-supply = <&ppvar_sys>; 122 }; 123 124 pp3000: pp3000 { 125 compatible = "regulator-fixed"; 126 regulator-name = "pp3000"; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pp3000_en>; 129 130 enable-active-high; 131 gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; 132 133 regulator-always-on; 134 regulator-boot-on; 135 regulator-min-microvolt = <3000000>; 136 regulator-max-microvolt = <3000000>; 137 138 vin-supply = <&ppvar_sys>; 139 }; 140 141 pp3300: pp3300 { 142 compatible = "regulator-fixed"; 143 regulator-name = "pp3300"; 144 145 /* Always on; plain and simple */ 146 regulator-always-on; 147 regulator-boot-on; 148 regulator-min-microvolt = <3300000>; 149 regulator-max-microvolt = <3300000>; 150 151 vin-supply = <&ppvar_sys>; 152 }; 153 154 pp5000: pp5000 { 155 compatible = "regulator-fixed"; 156 regulator-name = "pp5000"; 157 158 /* EC turns on w/ pp5000_en; always on for AP */ 159 regulator-always-on; 160 regulator-boot-on; 161 regulator-min-microvolt = <5000000>; 162 regulator-max-microvolt = <5000000>; 163 164 vin-supply = <&ppvar_sys>; 165 }; 166 167 ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { 168 compatible = "pwm-regulator"; 169 regulator-name = "ppvar_bigcpu_pwm"; 170 171 pwms = <&pwm1 0 3337 0>; 172 pwm-supply = <&ppvar_sys>; 173 pwm-dutycycle-range = <100 0>; 174 pwm-dutycycle-unit = <100>; 175 176 /* EC turns on w/ ap_core_en; always on for AP */ 177 regulator-always-on; 178 regulator-boot-on; 179 regulator-min-microvolt = <800107>; 180 regulator-max-microvolt = <1302232>; 181 }; 182 183 ppvar_bigcpu: ppvar-bigcpu { 184 compatible = "vctrl-regulator"; 185 regulator-name = "ppvar_bigcpu"; 186 187 regulator-min-microvolt = <800107>; 188 regulator-max-microvolt = <1302232>; 189 190 ctrl-supply = <&ppvar_bigcpu_pwm>; 191 ctrl-voltage-range = <800107 1302232>; 192 193 regulator-settling-time-up-us = <322>; 194 min-slew-down-rate = <225>; 195 ovp-threshold-percent = <16>; 196 }; 197 198 ppvar_litcpu_pwm: ppvar-litcpu-pwm { 199 compatible = "pwm-regulator"; 200 regulator-name = "ppvar_litcpu_pwm"; 201 202 pwms = <&pwm2 0 3337 0>; 203 pwm-supply = <&ppvar_sys>; 204 pwm-dutycycle-range = <100 0>; 205 pwm-dutycycle-unit = <100>; 206 207 /* EC turns on w/ ap_core_en; always on for AP */ 208 regulator-always-on; 209 regulator-boot-on; 210 regulator-min-microvolt = <797743>; 211 regulator-max-microvolt = <1307837>; 212 }; 213 214 ppvar_litcpu: ppvar-litcpu { 215 compatible = "vctrl-regulator"; 216 regulator-name = "ppvar_litcpu"; 217 218 regulator-min-microvolt = <797743>; 219 regulator-max-microvolt = <1307837>; 220 221 ctrl-supply = <&ppvar_litcpu_pwm>; 222 ctrl-voltage-range = <797743 1307837>; 223 224 regulator-settling-time-up-us = <384>; 225 min-slew-down-rate = <225>; 226 ovp-threshold-percent = <16>; 227 }; 228 229 ppvar_gpu_pwm: ppvar-gpu-pwm { 230 compatible = "pwm-regulator"; 231 regulator-name = "ppvar_gpu_pwm"; 232 233 pwms = <&pwm0 0 3337 0>; 234 pwm-supply = <&ppvar_sys>; 235 pwm-dutycycle-range = <100 0>; 236 pwm-dutycycle-unit = <100>; 237 238 /* EC turns on w/ ap_core_en; always on for AP */ 239 regulator-always-on; 240 regulator-boot-on; 241 regulator-min-microvolt = <786384>; 242 regulator-max-microvolt = <1217747>; 243 }; 244 245 ppvar_gpu: ppvar-gpu { 246 compatible = "vctrl-regulator"; 247 regulator-name = "ppvar_gpu"; 248 249 regulator-min-microvolt = <786384>; 250 regulator-max-microvolt = <1217747>; 251 252 ctrl-supply = <&ppvar_gpu_pwm>; 253 ctrl-voltage-range = <786384 1217747>; 254 255 regulator-settling-time-up-us = <390>; 256 min-slew-down-rate = <225>; 257 ovp-threshold-percent = <16>; 258 }; 259 260 ppvar_centerlogic_pwm: ppvar-centerlogic-pwm { 261 compatible = "pwm-regulator"; 262 regulator-name = "ppvar_centerlogic_pwm"; 263 264 pwms = <&pwm3 0 3337 0>; 265 pwm-supply = <&ppvar_sys>; 266 pwm-dutycycle-range = <100 0>; 267 pwm-dutycycle-unit = <100>; 268 269 /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ 270 regulator-always-on; 271 regulator-boot-on; 272 regulator-min-microvolt = <799434>; 273 regulator-max-microvolt = <1049925>; 274 }; 275 276 ppvar_centerlogic: ppvar-centerlogic { 277 compatible = "vctrl-regulator"; 278 regulator-name = "ppvar_centerlogic"; 279 280 regulator-min-microvolt = <799434>; 281 regulator-max-microvolt = <1049925>; 282 283 ctrl-supply = <&ppvar_centerlogic_pwm>; 284 ctrl-voltage-range = <799434 1049925>; 285 286 regulator-settling-time-up-us = <378>; 287 min-slew-down-rate = <225>; 288 ovp-threshold-percent = <16>; 289 }; 290 291 /* Schematics call this PPVAR even though it's fixed */ 292 ppvar_logic: ppvar-logic { 293 compatible = "regulator-fixed"; 294 regulator-name = "ppvar_logic"; 295 296 /* EC turns on w/ ppvar_logic_en; always on for AP */ 297 regulator-always-on; 298 regulator-boot-on; 299 regulator-min-microvolt = <900000>; 300 regulator-max-microvolt = <900000>; 301 302 vin-supply = <&ppvar_sys>; 303 }; 304 305 /* EC turns on w/ pp900_ddrpll_en */ 306 pp900_ddrpll: pp900-ap { 307 }; 308 309 /* EC turns on w/ pp900_pcie_en */ 310 pp900_pcie: pp900-ap { 311 }; 312 313 /* EC turns on w/ pp900_pll_en */ 314 pp900_pll: pp900-ap { 315 }; 316 317 /* EC turns on w/ pp900_pmu_en */ 318 pp900_pmu: pp900-ap { 319 }; 320 321 /* EC turns on w/ pp900_usb_en */ 322 pp900_usb: pp900-ap { 323 }; 324 325 /* EC turns on w/ pp1800_s0_en_l */ 326 pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { 327 }; 328 329 /* EC turns on w/ pp1800_avdd_en_l */ 330 pp1800_avdd: pp1800 { 331 }; 332 333 /* EC turns on w/ pp1800_lid_en_l */ 334 pp1800_lid: pp1800_mic: pp1800 { 335 }; 336 337 /* EC turns on w/ lpddr_pwr_en */ 338 pp1800_lpddr: pp1800 { 339 }; 340 341 /* EC turns on w/ pp1800_pmu_en_l */ 342 pp1800_pmu: pp1800 { 343 }; 344 345 /* EC turns on w/ pp1800_usb_en_l */ 346 pp1800_usb: pp1800 { 347 }; 348 349 pp1500_ap_io: pp1500-ap-io { 350 compatible = "regulator-fixed"; 351 regulator-name = "pp1500_ap_io"; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pp1500_en>; 354 355 enable-active-high; 356 gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; 357 358 regulator-always-on; 359 regulator-boot-on; 360 regulator-min-microvolt = <1500000>; 361 regulator-max-microvolt = <1500000>; 362 363 vin-supply = <&pp1800>; 364 }; 365 366 pp1800_audio: pp1800-audio { 367 compatible = "regulator-fixed"; 368 regulator-name = "pp1800_audio"; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pp1800_audio_en>; 371 372 enable-active-high; 373 gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; 374 375 regulator-always-on; 376 regulator-boot-on; 377 378 vin-supply = <&pp1800>; 379 }; 380 381 /* gpio is shared with pp3300_wifi_bt */ 382 pp1800_pcie: pp1800-pcie { 383 compatible = "regulator-fixed"; 384 regulator-name = "pp1800_pcie"; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&wlan_module_pd_l>; 387 388 enable-active-high; 389 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; 390 391 /* 392 * Need to wait 1ms + ramp-up time before we can power on WiFi. 393 * This has been approximated as 8ms total. 394 */ 395 regulator-enable-ramp-delay = <8000>; 396 397 vin-supply = <&pp1800>; 398 }; 399 400 /* 401 * This is a bit of a hack. The WiFi module should be reset at least 402 * 1ms after its regulators have ramped up (max rampup time is ~7ms). 403 * With some stretching of the imagination, we can call the 1.8V 404 * regulator a supply. 405 */ 406 wlan_pd_n: wlan-pd-n { 407 compatible = "regulator-fixed"; 408 regulator-name = "wlan_pd_n"; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&wlan_module_reset_l>; 411 412 enable-active-high; 413 gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; 414 415 vin-supply = <&pp1800_pcie>; 416 }; 417 418 /* Always on; plain and simple */ 419 pp3000_ap: pp3000_emmc: pp3000 { 420 }; 421 422 pp3000_sd_slot: pp3000-sd-slot { 423 compatible = "regulator-fixed"; 424 regulator-name = "pp3000_sd_slot"; 425 pinctrl-names = "default"; 426 pinctrl-0 = <&sd_slot_pwr_en>; 427 428 enable-active-high; 429 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 430 431 vin-supply = <&pp3000>; 432 }; 433 434 /* 435 * Technically, this is a small abuse of 'regulator-gpio'; this 436 * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are 437 * always on though, so it is sufficient to simply control the mux 438 * here. 439 */ 440 ppvar_sd_card_io: ppvar-sd-card-io { 441 compatible = "regulator-gpio"; 442 regulator-name = "ppvar_sd_card_io"; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; 445 446 enable-active-high; 447 enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; 448 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; 449 states = <1800000 0x1 450 3000000 0x0>; 451 452 regulator-min-microvolt = <1800000>; 453 regulator-max-microvolt = <3000000>; 454 }; 455 456 /* EC turns on w/ pp3300_trackpad_en_l */ 457 pp3300_trackpad: pp3300-trackpad { 458 }; 459 460 /* EC turns on w/ pp3300_usb_en_l */ 461 pp3300_usb: pp3300 { 462 }; 463 464 pp3300_disp: pp3300-disp { 465 compatible = "regulator-fixed"; 466 regulator-name = "pp3300_disp"; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pp3300_disp_en>; 469 470 enable-active-high; 471 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 472 473 startup-delay-us = <2000>; 474 vin-supply = <&pp3300>; 475 }; 476 477 /* gpio is shared with pp1800_pcie and pinctrl is set there */ 478 pp3300_wifi_bt: pp3300-wifi-bt { 479 compatible = "regulator-fixed"; 480 regulator-name = "pp3300_wifi_bt"; 481 482 enable-active-high; 483 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; 484 485 vin-supply = <&pp3300>; 486 }; 487 488 /* EC turns on w/ usb_a_en */ 489 pp5000_usb_a_vbus: pp5000 { 490 }; 491 492 gpio_keys: gpio-keys { 493 compatible = "gpio-keys"; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&bt_host_wake_l>; 496 497 wake-on-bt { 498 label = "Wake-on-Bluetooth"; 499 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 500 linux,code = <KEY_WAKEUP>; 501 wakeup-source; 502 }; 503 }; 504 505 max98357a: max98357a { 506 compatible = "maxim,max98357a"; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&sdmode_en>; 509 sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 510 sdmode-delay = <2>; 511 #sound-dai-cells = <0>; 512 status = "okay"; 513 }; 514 515 sound { 516 compatible = "rockchip,rk3399-gru-sound"; 517 rockchip,cpu = <&i2s0 &i2s2>; 518 rockchip,codec = <&max98357a &headsetcodec 519 &codec &wacky_spi_audio &cdn_dp>; 520 }; 521}; 522 523&cdn_dp { 524 status = "okay"; 525 extcon = <&usbc_extcon0>, <&usbc_extcon1>; 526}; 527 528/* 529 * Set some suspend operating points to avoid OVP in suspend 530 * 531 * When we go into S3 ARM Trusted Firmware will transition our PWM regulators 532 * from wherever they're at back to the "default" operating point (whatever 533 * voltage we get when we set the PWM pins to "input"). 534 * 535 * This quick transition under light load has the possibility to trigger the 536 * regulator "over voltage protection" (OVP). 537 * 538 * To make extra certain that we don't hit this OVP at suspend time, we'll 539 * transition to a voltage that's much closer to the default (~1.0 V) so that 540 * there will not be a big jump. Technically we only need to get within 200 mV 541 * of the default voltage, but the speed here should be fast enough and we need 542 * suspend/resume to be rock solid. 543 */ 544 545&cluster0_opp { 546 opp05 { 547 opp-suspend; 548 }; 549}; 550 551&cluster1_opp { 552 opp06 { 553 opp-suspend; 554 }; 555}; 556 557&cpu_l0 { 558 cpu-supply = <&ppvar_litcpu>; 559}; 560 561&cpu_l1 { 562 cpu-supply = <&ppvar_litcpu>; 563}; 564 565&cpu_l2 { 566 cpu-supply = <&ppvar_litcpu>; 567}; 568 569&cpu_l3 { 570 cpu-supply = <&ppvar_litcpu>; 571}; 572 573&cpu_b0 { 574 cpu-supply = <&ppvar_bigcpu>; 575}; 576 577&cpu_b1 { 578 cpu-supply = <&ppvar_bigcpu>; 579}; 580 581 582&cru { 583 assigned-clocks = 584 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 585 <&cru PLL_NPLL>, 586 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 587 <&cru PCLK_PERIHP>, 588 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 589 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 590 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 591 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 592 <&cru ACLK_GIC_PRE>, 593 <&cru PCLK_DDR>; 594 assigned-clock-rates = 595 <600000000>, <800000000>, 596 <1000000000>, 597 <150000000>, <75000000>, 598 <37500000>, 599 <100000000>, <100000000>, 600 <50000000>, <800000000>, 601 <100000000>, <50000000>, 602 <400000000>, <400000000>, 603 <200000000>, 604 <200000000>; 605}; 606 607&emmc_phy { 608 status = "okay"; 609}; 610 611&gpu { 612 mali-supply = <&ppvar_gpu>; 613 status = "okay"; 614}; 615 616ap_i2c_mic: &i2c1 { 617 status = "okay"; 618 619 clock-frequency = <400000>; 620 621 /* These are relatively safe rise/fall times */ 622 i2c-scl-falling-time-ns = <50>; 623 i2c-scl-rising-time-ns = <300>; 624 625 headsetcodec: rt5514@57 { 626 compatible = "realtek,rt5514"; 627 reg = <0x57>; 628 realtek,dmic-init-delay-ms = <20>; 629 }; 630}; 631 632ap_i2c_ts: &i2c3 { 633 status = "okay"; 634 635 clock-frequency = <400000>; 636 637 /* These are relatively safe rise/fall times */ 638 i2c-scl-falling-time-ns = <50>; 639 i2c-scl-rising-time-ns = <300>; 640}; 641 642ap_i2c_tp: &i2c5 { 643 status = "okay"; 644 645 clock-frequency = <400000>; 646 647 /* These are relatively safe rise/fall times */ 648 i2c-scl-falling-time-ns = <50>; 649 i2c-scl-rising-time-ns = <300>; 650 651 /* 652 * Note strange pullup enable. Apparently this avoids leakage but 653 * still allows us to get nice 4.7K pullups for high speed i2c 654 * transfers. Basically we want the pullup on whenever the ap is 655 * alive, so the "en" pin just gets set to output high. 656 */ 657 pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>; 658}; 659 660ap_i2c_audio: &i2c8 { 661 status = "okay"; 662 663 clock-frequency = <400000>; 664 665 /* These are relatively safe rise/fall times */ 666 i2c-scl-falling-time-ns = <50>; 667 i2c-scl-rising-time-ns = <300>; 668 669 codec: da7219@1a { 670 compatible = "dlg,da7219"; 671 reg = <0x1a>; 672 interrupt-parent = <&gpio1>; 673 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 674 clocks = <&cru SCLK_I2S_8CH_OUT>; 675 clock-names = "mclk"; 676 dlg,micbias-lvl = <2600>; 677 dlg,mic-amp-in-sel = "diff"; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&headset_int_l>; 680 VDD-supply = <&pp1800>; 681 VDDMIC-supply = <&pp3300>; 682 VDDIO-supply = <&pp1800>; 683 684 da7219_aad { 685 dlg,adc-1bit-rpt = <1>; 686 dlg,btn-avg = <4>; 687 dlg,btn-cfg = <50>; 688 dlg,mic-det-thr = <500>; 689 dlg,jack-ins-deb = <20>; 690 dlg,jack-det-rate = "32ms_64ms"; 691 dlg,jack-rem-deb = <1>; 692 693 dlg,a-d-btn-thr = <0xa>; 694 dlg,d-b-btn-thr = <0x16>; 695 dlg,b-c-btn-thr = <0x21>; 696 dlg,c-mic-btn-thr = <0x3E>; 697 }; 698 }; 699}; 700 701&i2s0 { 702 status = "okay"; 703}; 704 705&i2s2 { 706 status = "okay"; 707}; 708 709&io_domains { 710 status = "okay"; 711 712 audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ 713 bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ 714 gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ 715 sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ 716}; 717 718&pcie0 { 719 status = "okay"; 720 721 ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; 722 pinctrl-names = "default"; 723 pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; 724 vpcie3v3-supply = <&pp3300_wifi_bt>; 725 vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ 726 vpcie0v9-supply = <&pp900_pcie>; 727 728 pci_rootport: pcie@0,0 { 729 reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; 730 #address-cells = <3>; 731 #size-cells = <2>; 732 ranges; 733 734 mvl_wifi: wifi@0,0 { 735 compatible = "pci1b4b,2b42"; 736 reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 737 0x83010000 0x0 0x00100000 0x0 0x00100000>; 738 interrupt-parent = <&gpio0>; 739 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&wlan_host_wake_l>; 742 wakeup-source; 743 }; 744 }; 745}; 746 747&pcie_phy { 748 status = "okay"; 749}; 750 751&pmu_io_domains { 752 status = "okay"; 753 754 pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ 755}; 756 757&pwm0 { 758 status = "okay"; 759}; 760 761&pwm1 { 762 status = "okay"; 763}; 764 765&pwm2 { 766 status = "okay"; 767}; 768 769&pwm3 { 770 status = "okay"; 771}; 772 773&sdhci { 774 /* 775 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the 776 * same (or nearly the same) performance for all eMMC that are intended 777 * to be used. 778 */ 779 assigned-clock-rates = <150000000>; 780 781 bus-width = <8>; 782 mmc-hs400-1_8v; 783 mmc-hs400-enhanced-strobe; 784 non-removable; 785 status = "okay"; 786}; 787 788&sdmmc { 789 status = "okay"; 790 791 /* 792 * Note: configure "sdmmc_cd" as card detect even though it's actually 793 * hooked to ground. Because we specified "cd-gpios" below dw_mmc 794 * should be ignoring card detect anyway. Specifying the pin as 795 * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) 796 * turned on that the system will still make sure the port is 797 * configured as SDMMC and not JTAG. 798 */ 799 pinctrl-names = "default"; 800 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_gpio 801 &sdmmc_bus4>; 802 803 bus-width = <4>; 804 cap-mmc-highspeed; 805 cap-sd-highspeed; 806 cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 807 disable-wp; 808 sd-uhs-sdr12; 809 sd-uhs-sdr25; 810 sd-uhs-sdr50; 811 sd-uhs-sdr104; 812 vmmc-supply = <&pp3000_sd_slot>; 813 vqmmc-supply = <&ppvar_sd_card_io>; 814}; 815 816&spi1 { 817 status = "okay"; 818 819 pinctrl-names = "default", "sleep"; 820 pinctrl-1 = <&spi1_sleep>; 821 822 spiflash@0 { 823 compatible = "jedec,spi-nor"; 824 reg = <0>; 825 826 /* May run faster once verified. */ 827 spi-max-frequency = <10000000>; 828 }; 829}; 830 831&spi2 { 832 status = "okay"; 833 834 wacky_spi_audio: spi2@0 { 835 compatible = "realtek,rt5514"; 836 reg = <0>; 837 interrupt-parent = <&gpio1>; 838 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; 839 pinctrl-names = "default"; 840 pinctrl-0 = <&mic_int>; 841 /* May run faster once verified. */ 842 spi-max-frequency = <10000000>; 843 wakeup-source; 844 }; 845}; 846 847&spi5 { 848 status = "okay"; 849 850 cros_ec: ec@0 { 851 compatible = "google,cros-ec-spi"; 852 reg = <0>; 853 interrupt-parent = <&gpio0>; 854 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 855 pinctrl-names = "default"; 856 pinctrl-0 = <&ec_ap_int_l>; 857 spi-max-frequency = <3000000>; 858 859 i2c_tunnel: i2c-tunnel { 860 compatible = "google,cros-ec-i2c-tunnel"; 861 google,remote-bus = <4>; 862 #address-cells = <1>; 863 #size-cells = <0>; 864 }; 865 866 cros_ec_pwm: ec-pwm { 867 compatible = "google,cros-ec-pwm"; 868 #pwm-cells = <1>; 869 }; 870 871 usbc_extcon0: extcon@0 { 872 compatible = "google,extcon-usbc-cros-ec"; 873 google,usb-port-id = <0>; 874 875 #extcon-cells = <0>; 876 }; 877 878 usbc_extcon1: extcon@1 { 879 compatible = "google,extcon-usbc-cros-ec"; 880 google,usb-port-id = <1>; 881 882 #extcon-cells = <0>; 883 }; 884 }; 885}; 886 887&tsadc { 888 status = "okay"; 889 890 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 891 rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 892}; 893 894&tcphy0 { 895 status = "okay"; 896 extcon = <&usbc_extcon0>; 897}; 898 899&tcphy1 { 900 status = "okay"; 901 extcon = <&usbc_extcon1>; 902}; 903 904&u2phy0 { 905 status = "okay"; 906}; 907 908&u2phy1 { 909 status = "okay"; 910}; 911 912&u2phy0_host { 913 status = "okay"; 914}; 915 916&u2phy1_host { 917 status = "okay"; 918}; 919 920&u2phy0_otg { 921 status = "okay"; 922}; 923 924&u2phy1_otg { 925 status = "okay"; 926}; 927 928&uart2 { 929 status = "okay"; 930}; 931 932&usb_host0_ehci { 933 status = "okay"; 934}; 935 936&usb_host0_ohci { 937 status = "okay"; 938}; 939 940&usb_host1_ehci { 941 status = "okay"; 942}; 943 944&usb_host1_ohci { 945 status = "okay"; 946}; 947 948&usbdrd3_0 { 949 status = "okay"; 950 extcon = <&usbc_extcon0>; 951}; 952 953&usbdrd_dwc3_0 { 954 status = "okay"; 955 dr_mode = "host"; 956}; 957 958&usbdrd3_1 { 959 status = "okay"; 960 extcon = <&usbc_extcon1>; 961}; 962 963&usbdrd_dwc3_1 { 964 status = "okay"; 965 dr_mode = "host"; 966}; 967 968&vopb { 969 status = "okay"; 970}; 971 972&vopb_mmu { 973 status = "okay"; 974}; 975 976&vopl { 977 status = "okay"; 978}; 979 980&vopl_mmu { 981 status = "okay"; 982}; 983 984#include <arm/cros-ec-keyboard.dtsi> 985#include <arm/cros-ec-sbs.dtsi> 986 987&pinctrl { 988 /* 989 * pinctrl settings for pins that have no real owners. 990 * 991 * At the moment settings are identical for S0 and S3, but if we later 992 * need to configure things differently for S3 we'll adjust here. 993 */ 994 pinctrl-names = "default"; 995 pinctrl-0 = < 996 &ap_pwroff /* AP will auto-assert this when in S3 */ 997 &clk_32k /* This pin is always 32k on gru boards */ 998 >; 999 1000 pcfg_output_low: pcfg-output-low { 1001 output-low; 1002 }; 1003 1004 pcfg_output_high: pcfg-output-high { 1005 output-high; 1006 }; 1007 1008 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1009 bias-disable; 1010 drive-strength = <8>; 1011 }; 1012 1013 backlight-enable { 1014 bl_en: bl-en { 1015 rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_none>; 1016 }; 1017 }; 1018 1019 cros-ec { 1020 ec_ap_int_l: ec-ap-int-l { 1021 rockchip,pins = <RK_GPIO0 1 RK_FUNC_GPIO &pcfg_pull_up>; 1022 }; 1023 }; 1024 1025 discrete-regulators { 1026 pp1500_en: pp1500-en { 1027 rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO 1028 &pcfg_pull_none>; 1029 }; 1030 1031 pp1800_audio_en: pp1800-audio-en { 1032 rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO 1033 &pcfg_pull_down>; 1034 }; 1035 1036 pp3300_disp_en: pp3300-disp-en { 1037 rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO 1038 &pcfg_pull_none>; 1039 }; 1040 1041 pp3000_en: pp3000-en { 1042 rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO 1043 &pcfg_pull_none>; 1044 }; 1045 1046 sd_io_pwr_en: sd-io-pwr-en { 1047 rockchip,pins = <RK_GPIO2 2 RK_FUNC_GPIO 1048 &pcfg_pull_none>; 1049 }; 1050 1051 sd_pwr_1800_sel: sd-pwr-1800-sel { 1052 rockchip,pins = <RK_GPIO2 28 RK_FUNC_GPIO 1053 &pcfg_pull_none>; 1054 }; 1055 1056 sd_slot_pwr_en: sd-slot-pwr-en { 1057 rockchip,pins = <RK_GPIO4 29 RK_FUNC_GPIO 1058 &pcfg_pull_none>; 1059 }; 1060 1061 wlan_module_pd_l: wlan-module-pd-l { 1062 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO 1063 &pcfg_pull_down>; 1064 }; 1065 }; 1066 1067 codec { 1068 /* Has external pullup */ 1069 headset_int_l: headset-int-l { 1070 rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_none>; 1071 }; 1072 1073 mic_int: mic-int { 1074 rockchip,pins = <1 13 RK_FUNC_GPIO &pcfg_pull_down>; 1075 }; 1076 }; 1077 1078 max98357a { 1079 sdmode_en: sdmode-en { 1080 rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_down>; 1081 }; 1082 }; 1083 1084 pcie { 1085 pcie_clkreqn_cpm: pci-clkreqn-cpm { 1086 /* 1087 * Since our pcie doesn't support ClockPM(CPM), we want 1088 * to hack this as gpio, so the EP could be able to 1089 * de-assert it along and make ClockPM(CPM) work. 1090 */ 1091 rockchip,pins = <2 26 RK_FUNC_GPIO &pcfg_pull_none>; 1092 }; 1093 }; 1094 1095 sdmmc { 1096 /* 1097 * We run sdmmc at max speed; bump up drive strength. 1098 * We also have external pulls, so disable the internal ones. 1099 */ 1100 sdmmc_bus4: sdmmc-bus4 { 1101 rockchip,pins = 1102 <4 8 RK_FUNC_1 &pcfg_pull_none_8ma>, 1103 <4 9 RK_FUNC_1 &pcfg_pull_none_8ma>, 1104 <4 10 RK_FUNC_1 &pcfg_pull_none_8ma>, 1105 <4 11 RK_FUNC_1 &pcfg_pull_none_8ma>; 1106 }; 1107 1108 sdmmc_clk: sdmmc-clk { 1109 rockchip,pins = 1110 <4 12 RK_FUNC_1 &pcfg_pull_none_8ma>; 1111 }; 1112 1113 sdmmc_cmd: sdmmc-cmd { 1114 rockchip,pins = 1115 <4 13 RK_FUNC_1 &pcfg_pull_none_8ma>; 1116 }; 1117 1118 /* 1119 * In our case the official card detect is hooked to ground 1120 * to avoid getting access to JTAG just by sticking something 1121 * in the SD card slot (see the force_jtag bit in the TRM). 1122 * 1123 * We still configure it as card detect because it doesn't 1124 * hurt and dw_mmc will ignore it. We make sure to disable 1125 * the pull though so we don't burn needless power. 1126 */ 1127 sdmmc_cd: sdmmc-cd { 1128 rockchip,pins = 1129 <0 7 RK_FUNC_1 &pcfg_pull_none>; 1130 }; 1131 1132 /* This is where we actually hook up CD; has external pull */ 1133 sdmmc_cd_gpio: sdmmc-cd-gpio { 1134 rockchip,pins = <4 24 RK_FUNC_GPIO &pcfg_pull_none>; 1135 }; 1136 }; 1137 1138 spi1 { 1139 spi1_sleep: spi1-sleep { 1140 /* 1141 * Pull down SPI1 CLK/CS/RX/TX during suspend, to 1142 * prevent leakage. 1143 */ 1144 rockchip,pins = <1 9 RK_FUNC_GPIO &pcfg_pull_down>, 1145 <1 10 RK_FUNC_GPIO &pcfg_pull_down>, 1146 <1 7 RK_FUNC_GPIO &pcfg_pull_down>, 1147 <1 8 RK_FUNC_GPIO &pcfg_pull_down>; 1148 }; 1149 }; 1150 1151 touchscreen { 1152 touch_int_l: touch-int-l { 1153 rockchip,pins = <3 13 RK_FUNC_GPIO &pcfg_pull_up>; 1154 }; 1155 1156 touch_reset_l: touch-reset-l { 1157 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_pull_none>; 1158 }; 1159 }; 1160 1161 trackpad { 1162 ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { 1163 rockchip,pins = <3 12 RK_FUNC_GPIO &pcfg_output_high>; 1164 }; 1165 1166 trackpad_int_l: trackpad-int-l { 1167 rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_up>; 1168 }; 1169 }; 1170 1171 wifi { 1172 wifi_perst_l: wifi-perst-l { 1173 rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>; 1174 }; 1175 1176 wlan_module_reset_l: wlan-module-reset-l { 1177 rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>; 1178 }; 1179 1180 bt_host_wake_l: bt-host-wake-l { 1181 /* Kevin has an external pull up, but Gru does not */ 1182 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; 1183 }; 1184 }; 1185 1186 write-protect { 1187 ap_fw_wp: ap-fw-wp { 1188 rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>; 1189 }; 1190 }; 1191}; 1192