1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Collabora Ltd.
4 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
5 *
6 * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw
7 */
8
9/dts-v1/;
10#include "rk3399-rock960.dtsi"
11
12/ {
13	model = "96boards RK3399 Ficus";
14	compatible = "vamrs,ficus", "rockchip,rk3399";
15
16	chosen {
17		stdout-path = "serial2:1500000n8";
18	};
19
20	clkin_gmac: external-gmac-clock {
21		compatible = "fixed-clock";
22		clock-frequency = <125000000>;
23		clock-output-names = "clkin_gmac";
24		#clock-cells = <0>;
25	};
26};
27
28&gmac {
29	assigned-clocks = <&cru SCLK_RMII_SRC>;
30	assigned-clock-parents = <&clkin_gmac>;
31	clock_in_out = "input";
32	phy-supply = <&vcc3v3_sys>;
33	phy-mode = "rgmii";
34	pinctrl-names = "default";
35	pinctrl-0 = <&rgmii_pins>;
36	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
37	snps,reset-active-low;
38	snps,reset-delays-us = <0 10000 50000>;
39	tx_delay = <0x28>;
40	rx_delay = <0x11>;
41	status = "okay";
42};
43
44&pcie0 {
45	ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
46};
47
48&pinctrl {
49	gmac {
50		rgmii_sleep_pins: rgmii-sleep-pins {
51			rockchip,pins =
52				<3 15 RK_FUNC_GPIO &pcfg_output_low>;
53		};
54	};
55
56	pcie {
57		pcie_drv: pcie-drv {
58			rockchip,pins =
59				<1 24 RK_FUNC_GPIO &pcfg_pull_none>;
60			};
61	};
62
63	usb2 {
64		host_vbus_drv: host-vbus-drv {
65			rockchip,pins =
66				<4 27 RK_FUNC_GPIO &pcfg_pull_none>;
67		};
68	};
69};
70
71&usbdrd_dwc3_0 {
72	dr_mode = "host";
73};
74
75&usbdrd_dwc3_1 {
76	dr_mode = "host";
77};
78
79&vcc3v3_pcie {
80	gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
81};
82
83&vcc5v0_host {
84	gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
85};
86