1/* 2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3368-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/irq.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/thermal/thermal.h> 49 50/ { 51 compatible = "rockchip,rk3368"; 52 interrupt-parent = <&gic>; 53 #address-cells = <2>; 54 #size-cells = <2>; 55 56 aliases { 57 ethernet0 = &gmac; 58 i2c0 = &i2c0; 59 i2c1 = &i2c1; 60 i2c2 = &i2c2; 61 i2c3 = &i2c3; 62 i2c4 = &i2c4; 63 i2c5 = &i2c5; 64 serial0 = &uart0; 65 serial1 = &uart1; 66 serial2 = &uart2; 67 serial3 = &uart3; 68 serial4 = &uart4; 69 spi0 = &spi0; 70 spi1 = &spi1; 71 spi2 = &spi2; 72 }; 73 74 cpus { 75 #address-cells = <0x2>; 76 #size-cells = <0x0>; 77 78 cpu-map { 79 cluster0 { 80 core0 { 81 cpu = <&cpu_b0>; 82 }; 83 core1 { 84 cpu = <&cpu_b1>; 85 }; 86 core2 { 87 cpu = <&cpu_b2>; 88 }; 89 core3 { 90 cpu = <&cpu_b3>; 91 }; 92 }; 93 94 cluster1 { 95 core0 { 96 cpu = <&cpu_l0>; 97 }; 98 core1 { 99 cpu = <&cpu_l1>; 100 }; 101 core2 { 102 cpu = <&cpu_l2>; 103 }; 104 core3 { 105 cpu = <&cpu_l3>; 106 }; 107 }; 108 }; 109 110 idle-states { 111 entry-method = "psci"; 112 113 cpu_sleep: cpu-sleep-0 { 114 compatible = "arm,idle-state"; 115 arm,psci-suspend-param = <0x1010000>; 116 entry-latency-us = <0x3fffffff>; 117 exit-latency-us = <0x40000000>; 118 min-residency-us = <0xffffffff>; 119 }; 120 }; 121 122 cpu_l0: cpu@0 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53", "arm,armv8"; 125 reg = <0x0 0x0>; 126 cpu-idle-states = <&cpu_sleep>; 127 enable-method = "psci"; 128 129 #cooling-cells = <2>; /* min followed by max */ 130 }; 131 132 cpu_l1: cpu@1 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a53", "arm,armv8"; 135 reg = <0x0 0x1>; 136 cpu-idle-states = <&cpu_sleep>; 137 enable-method = "psci"; 138 }; 139 140 cpu_l2: cpu@2 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a53", "arm,armv8"; 143 reg = <0x0 0x2>; 144 cpu-idle-states = <&cpu_sleep>; 145 enable-method = "psci"; 146 }; 147 148 cpu_l3: cpu@3 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a53", "arm,armv8"; 151 reg = <0x0 0x3>; 152 cpu-idle-states = <&cpu_sleep>; 153 enable-method = "psci"; 154 }; 155 156 cpu_b0: cpu@100 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a53", "arm,armv8"; 159 reg = <0x0 0x100>; 160 cpu-idle-states = <&cpu_sleep>; 161 enable-method = "psci"; 162 163 #cooling-cells = <2>; /* min followed by max */ 164 }; 165 166 cpu_b1: cpu@101 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a53", "arm,armv8"; 169 reg = <0x0 0x101>; 170 cpu-idle-states = <&cpu_sleep>; 171 enable-method = "psci"; 172 }; 173 174 cpu_b2: cpu@102 { 175 device_type = "cpu"; 176 compatible = "arm,cortex-a53", "arm,armv8"; 177 reg = <0x0 0x102>; 178 cpu-idle-states = <&cpu_sleep>; 179 enable-method = "psci"; 180 }; 181 182 cpu_b3: cpu@103 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a53", "arm,armv8"; 185 reg = <0x0 0x103>; 186 cpu-idle-states = <&cpu_sleep>; 187 enable-method = "psci"; 188 }; 189 }; 190 191 arm-pmu { 192 compatible = "arm,armv8-pmuv3"; 193 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 201 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, 202 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, 203 <&cpu_b2>, <&cpu_b3>; 204 }; 205 206 psci { 207 compatible = "arm,psci-0.2"; 208 method = "smc"; 209 }; 210 211 timer { 212 compatible = "arm,armv8-timer"; 213 interrupts = <GIC_PPI 13 214 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 215 <GIC_PPI 14 216 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 217 <GIC_PPI 11 218 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 219 <GIC_PPI 10 220 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 221 }; 222 223 xin24m: oscillator { 224 compatible = "fixed-clock"; 225 clock-frequency = <24000000>; 226 clock-output-names = "xin24m"; 227 #clock-cells = <0>; 228 }; 229 230 sdmmc: dwmmc@ff0c0000 { 231 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 232 reg = <0x0 0xff0c0000 0x0 0x4000>; 233 clock-freq-min-max = <400000 150000000>; 234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 235 clock-names = "biu", "ciu"; 236 fifo-depth = <0x100>; 237 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 238 status = "disabled"; 239 }; 240 241 sdio0: dwmmc@ff0d0000 { 242 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 243 reg = <0x0 0xff0d0000 0x0 0x4000>; 244 clock-freq-min-max = <400000 150000000>; 245 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 246 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 247 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 248 fifo-depth = <0x100>; 249 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 250 status = "disabled"; 251 }; 252 253 emmc: dwmmc@ff0f0000 { 254 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 255 reg = <0x0 0xff0f0000 0x0 0x4000>; 256 clock-freq-min-max = <400000 150000000>; 257 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 258 clock-names = "biu", "ciu"; 259 fifo-depth = <0x100>; 260 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 261 status = "disabled"; 262 }; 263 264 saradc: saradc@ff100000 { 265 compatible = "rockchip,saradc"; 266 reg = <0x0 0xff100000 0x0 0x100>; 267 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 268 #io-channel-cells = <1>; 269 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 270 clock-names = "saradc", "apb_pclk"; 271 status = "disabled"; 272 }; 273 274 spi0: spi@ff110000 { 275 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 276 reg = <0x0 0xff110000 0x0 0x1000>; 277 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 278 clock-names = "spiclk", "apb_pclk"; 279 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 status = "disabled"; 285 }; 286 287 spi1: spi@ff120000 { 288 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 289 reg = <0x0 0xff120000 0x0 0x1000>; 290 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 291 clock-names = "spiclk", "apb_pclk"; 292 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 status = "disabled"; 298 }; 299 300 spi2: spi@ff130000 { 301 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 302 reg = <0x0 0xff130000 0x0 0x1000>; 303 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 304 clock-names = "spiclk", "apb_pclk"; 305 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 status = "disabled"; 311 }; 312 313 i2c1: i2c@ff140000 { 314 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 315 reg = <0x0 0xff140000 0x0 0x1000>; 316 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 clock-names = "i2c"; 320 clocks = <&cru PCLK_I2C1>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&i2c1_xfer>; 323 status = "disabled"; 324 }; 325 326 i2c3: i2c@ff150000 { 327 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 328 reg = <0x0 0xff150000 0x0 0x1000>; 329 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 clock-names = "i2c"; 333 clocks = <&cru PCLK_I2C3>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&i2c3_xfer>; 336 status = "disabled"; 337 }; 338 339 i2c4: i2c@ff160000 { 340 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 341 reg = <0x0 0xff160000 0x0 0x1000>; 342 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 clock-names = "i2c"; 346 clocks = <&cru PCLK_I2C4>; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&i2c4_xfer>; 349 status = "disabled"; 350 }; 351 352 i2c5: i2c@ff170000 { 353 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 354 reg = <0x0 0xff170000 0x0 0x1000>; 355 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clock-names = "i2c"; 359 clocks = <&cru PCLK_I2C5>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&i2c5_xfer>; 362 status = "disabled"; 363 }; 364 365 uart0: serial@ff180000 { 366 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 367 reg = <0x0 0xff180000 0x0 0x100>; 368 clock-frequency = <24000000>; 369 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 370 clock-names = "baudclk", "apb_pclk"; 371 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 372 reg-shift = <2>; 373 reg-io-width = <4>; 374 status = "disabled"; 375 }; 376 377 uart1: serial@ff190000 { 378 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 379 reg = <0x0 0xff190000 0x0 0x100>; 380 clock-frequency = <24000000>; 381 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 382 clock-names = "baudclk", "apb_pclk"; 383 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 384 reg-shift = <2>; 385 reg-io-width = <4>; 386 status = "disabled"; 387 }; 388 389 uart3: serial@ff1b0000 { 390 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 391 reg = <0x0 0xff1b0000 0x0 0x100>; 392 clock-frequency = <24000000>; 393 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 394 clock-names = "baudclk", "apb_pclk"; 395 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 396 reg-shift = <2>; 397 reg-io-width = <4>; 398 status = "disabled"; 399 }; 400 401 uart4: serial@ff1c0000 { 402 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 403 reg = <0x0 0xff1c0000 0x0 0x100>; 404 clock-frequency = <24000000>; 405 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 406 clock-names = "baudclk", "apb_pclk"; 407 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 408 reg-shift = <2>; 409 reg-io-width = <4>; 410 status = "disabled"; 411 }; 412 413 thermal-zones { 414 #include "rk3368-thermal.dtsi" 415 }; 416 417 tsadc: tsadc@ff280000 { 418 compatible = "rockchip,rk3368-tsadc"; 419 reg = <0x0 0xff280000 0x0 0x100>; 420 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 422 clock-names = "tsadc", "apb_pclk"; 423 resets = <&cru SRST_TSADC>; 424 reset-names = "tsadc-apb"; 425 pinctrl-names = "init", "default", "sleep"; 426 pinctrl-0 = <&otp_gpio>; 427 pinctrl-1 = <&otp_out>; 428 pinctrl-2 = <&otp_gpio>; 429 #thermal-sensor-cells = <1>; 430 rockchip,hw-tshut-temp = <95000>; 431 status = "disabled"; 432 }; 433 434 gmac: ethernet@ff290000 { 435 compatible = "rockchip,rk3368-gmac"; 436 reg = <0x0 0xff290000 0x0 0x10000>; 437 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 438 interrupt-names = "macirq"; 439 rockchip,grf = <&grf>; 440 clocks = <&cru SCLK_MAC>, 441 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 442 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 443 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 444 clock-names = "stmmaceth", 445 "mac_clk_rx", "mac_clk_tx", 446 "clk_mac_ref", "clk_mac_refout", 447 "aclk_mac", "pclk_mac"; 448 status = "disabled"; 449 }; 450 451 usb_host0_ehci: usb@ff500000 { 452 compatible = "generic-ehci"; 453 reg = <0x0 0xff500000 0x0 0x100>; 454 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&cru HCLK_HOST0>; 456 clock-names = "usbhost"; 457 status = "disabled"; 458 }; 459 460 usb_otg: usb@ff580000 { 461 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", 462 "snps,dwc2"; 463 reg = <0x0 0xff580000 0x0 0x40000>; 464 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&cru HCLK_OTG0>; 466 clock-names = "otg"; 467 dr_mode = "otg"; 468 g-np-tx-fifo-size = <16>; 469 g-rx-fifo-size = <275>; 470 g-tx-fifo-size = <256 128 128 64 64 32>; 471 g-use-dma; 472 status = "disabled"; 473 }; 474 475 i2c0: i2c@ff650000 { 476 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 477 reg = <0x0 0xff650000 0x0 0x1000>; 478 clocks = <&cru PCLK_I2C0>; 479 clock-names = "i2c"; 480 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&i2c0_xfer>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 status = "disabled"; 486 }; 487 488 i2c2: i2c@ff660000 { 489 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 490 reg = <0x0 0xff660000 0x0 0x1000>; 491 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 clock-names = "i2c"; 495 clocks = <&cru PCLK_I2C2>; 496 pinctrl-names = "default"; 497 pinctrl-0 = <&i2c2_xfer>; 498 status = "disabled"; 499 }; 500 501 pwm0: pwm@ff680000 { 502 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 503 reg = <0x0 0xff680000 0x0 0x10>; 504 #pwm-cells = <3>; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&pwm0_pin>; 507 clocks = <&cru PCLK_PWM1>; 508 clock-names = "pwm"; 509 status = "disabled"; 510 }; 511 512 pwm1: pwm@ff680010 { 513 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 514 reg = <0x0 0xff680010 0x0 0x10>; 515 #pwm-cells = <3>; 516 pinctrl-names = "default"; 517 pinctrl-0 = <&pwm1_pin>; 518 clocks = <&cru PCLK_PWM1>; 519 clock-names = "pwm"; 520 status = "disabled"; 521 }; 522 523 pwm2: pwm@ff680020 { 524 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 525 reg = <0x0 0xff680020 0x0 0x10>; 526 #pwm-cells = <3>; 527 clocks = <&cru PCLK_PWM1>; 528 clock-names = "pwm"; 529 status = "disabled"; 530 }; 531 532 pwm3: pwm@ff680030 { 533 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 534 reg = <0x0 0xff680030 0x0 0x10>; 535 #pwm-cells = <3>; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pwm3_pin>; 538 clocks = <&cru PCLK_PWM1>; 539 clock-names = "pwm"; 540 status = "disabled"; 541 }; 542 543 uart2: serial@ff690000 { 544 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 545 reg = <0x0 0xff690000 0x0 0x100>; 546 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 547 clock-names = "baudclk", "apb_pclk"; 548 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 549 pinctrl-names = "default"; 550 pinctrl-0 = <&uart2_xfer>; 551 reg-shift = <2>; 552 reg-io-width = <4>; 553 status = "disabled"; 554 }; 555 556 pmugrf: syscon@ff738000 { 557 compatible = "rockchip,rk3368-pmugrf", "syscon"; 558 reg = <0x0 0xff738000 0x0 0x1000>; 559 }; 560 561 cru: clock-controller@ff760000 { 562 compatible = "rockchip,rk3368-cru"; 563 reg = <0x0 0xff760000 0x0 0x1000>; 564 rockchip,grf = <&grf>; 565 #clock-cells = <1>; 566 #reset-cells = <1>; 567 }; 568 569 grf: syscon@ff770000 { 570 compatible = "rockchip,rk3368-grf", "syscon"; 571 reg = <0x0 0xff770000 0x0 0x1000>; 572 }; 573 574 wdt: watchdog@ff800000 { 575 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; 576 reg = <0x0 0xff800000 0x0 0x100>; 577 clocks = <&cru PCLK_WDT>; 578 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 579 status = "disabled"; 580 }; 581 582 timer@ff810000 { 583 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; 584 reg = <0x0 0xff810000 0x0 0x20>; 585 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 586 }; 587 588 gic: interrupt-controller@ffb71000 { 589 compatible = "arm,gic-400"; 590 interrupt-controller; 591 #interrupt-cells = <3>; 592 #address-cells = <0>; 593 594 reg = <0x0 0xffb71000 0x0 0x1000>, 595 <0x0 0xffb72000 0x0 0x1000>, 596 <0x0 0xffb74000 0x0 0x2000>, 597 <0x0 0xffb76000 0x0 0x2000>; 598 interrupts = <GIC_PPI 9 599 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 600 }; 601 602 pinctrl: pinctrl { 603 compatible = "rockchip,rk3368-pinctrl"; 604 rockchip,grf = <&grf>; 605 rockchip,pmu = <&pmugrf>; 606 #address-cells = <0x2>; 607 #size-cells = <0x2>; 608 ranges; 609 610 gpio0: gpio0@ff750000 { 611 compatible = "rockchip,gpio-bank"; 612 reg = <0x0 0xff750000 0x0 0x100>; 613 clocks = <&cru PCLK_GPIO0>; 614 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; 615 616 gpio-controller; 617 #gpio-cells = <0x2>; 618 619 interrupt-controller; 620 #interrupt-cells = <0x2>; 621 }; 622 623 gpio1: gpio1@ff780000 { 624 compatible = "rockchip,gpio-bank"; 625 reg = <0x0 0xff780000 0x0 0x100>; 626 clocks = <&cru PCLK_GPIO1>; 627 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; 628 629 gpio-controller; 630 #gpio-cells = <0x2>; 631 632 interrupt-controller; 633 #interrupt-cells = <0x2>; 634 }; 635 636 gpio2: gpio2@ff790000 { 637 compatible = "rockchip,gpio-bank"; 638 reg = <0x0 0xff790000 0x0 0x100>; 639 clocks = <&cru PCLK_GPIO2>; 640 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; 641 642 gpio-controller; 643 #gpio-cells = <0x2>; 644 645 interrupt-controller; 646 #interrupt-cells = <0x2>; 647 }; 648 649 gpio3: gpio3@ff7a0000 { 650 compatible = "rockchip,gpio-bank"; 651 reg = <0x0 0xff7a0000 0x0 0x100>; 652 clocks = <&cru PCLK_GPIO3>; 653 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; 654 655 gpio-controller; 656 #gpio-cells = <0x2>; 657 658 interrupt-controller; 659 #interrupt-cells = <0x2>; 660 }; 661 662 pcfg_pull_up: pcfg-pull-up { 663 bias-pull-up; 664 }; 665 666 pcfg_pull_down: pcfg-pull-down { 667 bias-pull-down; 668 }; 669 670 pcfg_pull_none: pcfg-pull-none { 671 bias-disable; 672 }; 673 674 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 675 bias-disable; 676 drive-strength = <12>; 677 }; 678 679 emmc { 680 emmc_clk: emmc-clk { 681 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 682 }; 683 684 emmc_cmd: emmc-cmd { 685 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>; 686 }; 687 688 emmc_pwr: emmc-pwr { 689 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>; 690 }; 691 692 emmc_bus1: emmc-bus1 { 693 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>; 694 }; 695 696 emmc_bus4: emmc-bus4 { 697 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 698 <1 19 RK_FUNC_2 &pcfg_pull_up>, 699 <1 20 RK_FUNC_2 &pcfg_pull_up>, 700 <1 21 RK_FUNC_2 &pcfg_pull_up>; 701 }; 702 703 emmc_bus8: emmc-bus8 { 704 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 705 <1 19 RK_FUNC_2 &pcfg_pull_up>, 706 <1 20 RK_FUNC_2 &pcfg_pull_up>, 707 <1 21 RK_FUNC_2 &pcfg_pull_up>, 708 <1 22 RK_FUNC_2 &pcfg_pull_up>, 709 <1 23 RK_FUNC_2 &pcfg_pull_up>, 710 <1 24 RK_FUNC_2 &pcfg_pull_up>, 711 <1 25 RK_FUNC_2 &pcfg_pull_up>; 712 }; 713 }; 714 715 gmac { 716 rgmii_pins: rgmii-pins { 717 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 718 <3 24 RK_FUNC_1 &pcfg_pull_none>, 719 <3 19 RK_FUNC_1 &pcfg_pull_none>, 720 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 721 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 722 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>, 723 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>, 724 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>, 725 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 726 <3 15 RK_FUNC_1 &pcfg_pull_none>, 727 <3 16 RK_FUNC_1 &pcfg_pull_none>, 728 <3 17 RK_FUNC_1 &pcfg_pull_none>, 729 <3 18 RK_FUNC_1 &pcfg_pull_none>, 730 <3 25 RK_FUNC_1 &pcfg_pull_none>, 731 <3 20 RK_FUNC_1 &pcfg_pull_none>; 732 }; 733 734 rmii_pins: rmii-pins { 735 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 736 <3 24 RK_FUNC_1 &pcfg_pull_none>, 737 <3 19 RK_FUNC_1 &pcfg_pull_none>, 738 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 739 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 740 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 741 <3 15 RK_FUNC_1 &pcfg_pull_none>, 742 <3 16 RK_FUNC_1 &pcfg_pull_none>, 743 <3 20 RK_FUNC_1 &pcfg_pull_none>, 744 <3 21 RK_FUNC_1 &pcfg_pull_none>; 745 }; 746 }; 747 748 i2c0 { 749 i2c0_xfer: i2c0-xfer { 750 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 751 <0 7 RK_FUNC_1 &pcfg_pull_none>; 752 }; 753 }; 754 755 i2c1 { 756 i2c1_xfer: i2c1-xfer { 757 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>, 758 <2 22 RK_FUNC_1 &pcfg_pull_none>; 759 }; 760 }; 761 762 i2c2 { 763 i2c2_xfer: i2c2-xfer { 764 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>, 765 <3 31 RK_FUNC_2 &pcfg_pull_none>; 766 }; 767 }; 768 769 i2c3 { 770 i2c3_xfer: i2c3-xfer { 771 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>, 772 <1 17 RK_FUNC_1 &pcfg_pull_none>; 773 }; 774 }; 775 776 i2c4 { 777 i2c4_xfer: i2c4-xfer { 778 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>, 779 <3 25 RK_FUNC_2 &pcfg_pull_none>; 780 }; 781 }; 782 783 i2c5 { 784 i2c5_xfer: i2c5-xfer { 785 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>, 786 <3 27 RK_FUNC_2 &pcfg_pull_none>; 787 }; 788 }; 789 790 pwm0 { 791 pwm0_pin: pwm0-pin { 792 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; 793 }; 794 }; 795 796 pwm1 { 797 pwm1_pin: pwm1-pin { 798 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; 799 }; 800 }; 801 802 pwm3 { 803 pwm3_pin: pwm3-pin { 804 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; 805 }; 806 }; 807 808 sdio0 { 809 sdio0_bus1: sdio0-bus1 { 810 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; 811 }; 812 813 sdio0_bus4: sdio0-bus4 { 814 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>, 815 <2 29 RK_FUNC_1 &pcfg_pull_up>, 816 <2 30 RK_FUNC_1 &pcfg_pull_up>, 817 <2 31 RK_FUNC_1 &pcfg_pull_up>; 818 }; 819 820 sdio0_cmd: sdio0-cmd { 821 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>; 822 }; 823 824 sdio0_clk: sdio0-clk { 825 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>; 826 }; 827 828 sdio0_cd: sdio0-cd { 829 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>; 830 }; 831 832 sdio0_wp: sdio0-wp { 833 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>; 834 }; 835 836 sdio0_pwr: sdio0-pwr { 837 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>; 838 }; 839 840 sdio0_bkpwr: sdio0-bkpwr { 841 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>; 842 }; 843 844 sdio0_int: sdio0-int { 845 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>; 846 }; 847 }; 848 849 sdmmc { 850 sdmmc_clk: sdmmc-clk { 851 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>; 852 }; 853 854 sdmmc_cmd: sdmmc-cmd { 855 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; 856 }; 857 858 sdmmc_cd: sdmmc-cd { 859 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; 860 }; 861 862 sdmmc_bus1: sdmmc-bus1 { 863 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>; 864 }; 865 866 sdmmc_bus4: sdmmc-bus4 { 867 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>, 868 <2 6 RK_FUNC_1 &pcfg_pull_up>, 869 <2 7 RK_FUNC_1 &pcfg_pull_up>, 870 <2 8 RK_FUNC_1 &pcfg_pull_up>; 871 }; 872 }; 873 874 spi0 { 875 spi0_clk: spi0-clk { 876 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>; 877 }; 878 spi0_cs0: spi0-cs0 { 879 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>; 880 }; 881 spi0_cs1: spi0-cs1 { 882 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>; 883 }; 884 spi0_tx: spi0-tx { 885 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>; 886 }; 887 spi0_rx: spi0-rx { 888 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>; 889 }; 890 }; 891 892 spi1 { 893 spi1_clk: spi1-clk { 894 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>; 895 }; 896 spi1_cs0: spi1-cs0 { 897 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>; 898 }; 899 spi1_cs1: spi1-cs1 { 900 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>; 901 }; 902 spi1_rx: spi1-rx { 903 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>; 904 }; 905 spi1_tx: spi1-tx { 906 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>; 907 }; 908 }; 909 910 spi2 { 911 spi2_clk: spi2-clk { 912 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>; 913 }; 914 spi2_cs0: spi2-cs0 { 915 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; 916 }; 917 spi2_rx: spi2-rx { 918 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>; 919 }; 920 spi2_tx: spi2-tx { 921 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; 922 }; 923 }; 924 925 tsadc { 926 otp_gpio: otp-gpio { 927 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; 928 }; 929 930 otp_out: otp-out { 931 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; 932 }; 933 }; 934 935 uart0 { 936 uart0_xfer: uart0-xfer { 937 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>, 938 <2 25 RK_FUNC_1 &pcfg_pull_none>; 939 }; 940 941 uart0_cts: uart0-cts { 942 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>; 943 }; 944 945 uart0_rts: uart0-rts { 946 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>; 947 }; 948 }; 949 950 uart1 { 951 uart1_xfer: uart1-xfer { 952 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>, 953 <0 21 RK_FUNC_3 &pcfg_pull_none>; 954 }; 955 956 uart1_cts: uart1-cts { 957 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>; 958 }; 959 960 uart1_rts: uart1-rts { 961 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>; 962 }; 963 }; 964 965 uart2 { 966 uart2_xfer: uart2-xfer { 967 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>, 968 <2 5 RK_FUNC_2 &pcfg_pull_none>; 969 }; 970 /* no rts / cts for uart2 */ 971 }; 972 973 uart3 { 974 uart3_xfer: uart3-xfer { 975 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>, 976 <3 30 RK_FUNC_3 &pcfg_pull_none>; 977 }; 978 979 uart3_cts: uart3-cts { 980 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>; 981 }; 982 983 uart3_rts: uart3-rts { 984 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>; 985 }; 986 }; 987 988 uart4 { 989 uart4_xfer: uart4-xfer { 990 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>, 991 <0 26 RK_FUNC_3 &pcfg_pull_none>; 992 }; 993 994 uart4_cts: uart4-cts { 995 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>; 996 }; 997 998 uart4_rts: uart4-rts { 999 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>; 1000 }; 1001 }; 1002 }; 1003}; 1004