1/* 2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3368-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/irq.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48 49/ { 50 compatible = "rockchip,rk3368"; 51 interrupt-parent = <&gic>; 52 #address-cells = <2>; 53 #size-cells = <2>; 54 55 aliases { 56 i2c0 = &i2c0; 57 i2c1 = &i2c1; 58 i2c2 = &i2c2; 59 i2c3 = &i2c3; 60 i2c4 = &i2c4; 61 i2c5 = &i2c5; 62 serial0 = &uart0; 63 serial1 = &uart1; 64 serial2 = &uart2; 65 serial3 = &uart3; 66 serial4 = &uart4; 67 spi0 = &spi0; 68 spi1 = &spi1; 69 spi2 = &spi2; 70 }; 71 72 cpus { 73 #address-cells = <0x2>; 74 #size-cells = <0x0>; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&cpu_b0>; 80 }; 81 core1 { 82 cpu = <&cpu_b1>; 83 }; 84 core2 { 85 cpu = <&cpu_b2>; 86 }; 87 core3 { 88 cpu = <&cpu_b3>; 89 }; 90 }; 91 92 cluster1 { 93 core0 { 94 cpu = <&cpu_l0>; 95 }; 96 core1 { 97 cpu = <&cpu_l1>; 98 }; 99 core2 { 100 cpu = <&cpu_l2>; 101 }; 102 core3 { 103 cpu = <&cpu_l3>; 104 }; 105 }; 106 }; 107 108 idle-states { 109 entry-method = "psci"; 110 111 cpu_sleep: cpu-sleep-0 { 112 compatible = "arm,idle-state"; 113 arm,psci-suspend-param = <0x1010000>; 114 entry-latency-us = <0x3fffffff>; 115 exit-latency-us = <0x40000000>; 116 min-residency-us = <0xffffffff>; 117 }; 118 }; 119 120 cpu_l0: cpu@0 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53", "arm,armv8"; 123 reg = <0x0 0x0>; 124 cpu-idle-states = <&cpu_sleep>; 125 enable-method = "psci"; 126 }; 127 128 cpu_l1: cpu@1 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a53", "arm,armv8"; 131 reg = <0x0 0x1>; 132 cpu-idle-states = <&cpu_sleep>; 133 enable-method = "psci"; 134 }; 135 136 cpu_l2: cpu@2 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a53", "arm,armv8"; 139 reg = <0x0 0x2>; 140 cpu-idle-states = <&cpu_sleep>; 141 enable-method = "psci"; 142 }; 143 144 cpu_l3: cpu@3 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a53", "arm,armv8"; 147 reg = <0x0 0x3>; 148 cpu-idle-states = <&cpu_sleep>; 149 enable-method = "psci"; 150 }; 151 152 cpu_b0: cpu@100 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a53", "arm,armv8"; 155 reg = <0x0 0x100>; 156 cpu-idle-states = <&cpu_sleep>; 157 enable-method = "psci"; 158 }; 159 160 cpu_b1: cpu@101 { 161 device_type = "cpu"; 162 compatible = "arm,cortex-a53", "arm,armv8"; 163 reg = <0x0 0x101>; 164 cpu-idle-states = <&cpu_sleep>; 165 enable-method = "psci"; 166 }; 167 168 cpu_b2: cpu@102 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-a53", "arm,armv8"; 171 reg = <0x0 0x102>; 172 cpu-idle-states = <&cpu_sleep>; 173 enable-method = "psci"; 174 }; 175 176 cpu_b3: cpu@103 { 177 device_type = "cpu"; 178 compatible = "arm,cortex-a53", "arm,armv8"; 179 reg = <0x0 0x103>; 180 cpu-idle-states = <&cpu_sleep>; 181 enable-method = "psci"; 182 }; 183 }; 184 185 arm-pmu { 186 compatible = "arm,armv8-pmuv3"; 187 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 195 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, 196 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, 197 <&cpu_b2>, <&cpu_b3>; 198 }; 199 200 psci { 201 compatible = "arm,psci-0.2"; 202 method = "smc"; 203 }; 204 205 timer { 206 compatible = "arm,armv8-timer"; 207 interrupts = <GIC_PPI 13 208 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 209 <GIC_PPI 14 210 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 211 <GIC_PPI 11 212 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 213 <GIC_PPI 10 214 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 215 }; 216 217 xin24m: oscillator { 218 compatible = "fixed-clock"; 219 clock-frequency = <24000000>; 220 clock-output-names = "xin24m"; 221 #clock-cells = <0>; 222 }; 223 224 sdmmc: dwmmc@ff0c0000 { 225 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 226 reg = <0x0 0xff0c0000 0x0 0x4000>; 227 clock-freq-min-max = <400000 150000000>; 228 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 229 clock-names = "biu", "ciu"; 230 fifo-depth = <0x100>; 231 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 232 status = "disabled"; 233 }; 234 235 sdio0: dwmmc@ff0d0000 { 236 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 237 reg = <0x0 0xff0d0000 0x0 0x4000>; 238 clock-freq-min-max = <400000 150000000>; 239 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 240 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 241 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 242 fifo-depth = <0x100>; 243 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 244 status = "disabled"; 245 }; 246 247 emmc: dwmmc@ff0f0000 { 248 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 249 reg = <0x0 0xff0f0000 0x0 0x4000>; 250 clock-freq-min-max = <400000 150000000>; 251 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 252 clock-names = "biu", "ciu"; 253 fifo-depth = <0x100>; 254 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 255 status = "disabled"; 256 }; 257 258 saradc: saradc@ff100000 { 259 compatible = "rockchip,saradc"; 260 reg = <0x0 0xff100000 0x0 0x100>; 261 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 262 #io-channel-cells = <1>; 263 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 264 clock-names = "saradc", "apb_pclk"; 265 status = "disabled"; 266 }; 267 268 spi0: spi@ff110000 { 269 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 270 reg = <0x0 0xff110000 0x0 0x1000>; 271 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 272 clock-names = "spiclk", "apb_pclk"; 273 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 status = "disabled"; 279 }; 280 281 spi1: spi@ff120000 { 282 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 283 reg = <0x0 0xff120000 0x0 0x1000>; 284 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 285 clock-names = "spiclk", "apb_pclk"; 286 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 status = "disabled"; 292 }; 293 294 spi2: spi@ff130000 { 295 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 296 reg = <0x0 0xff130000 0x0 0x1000>; 297 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 298 clock-names = "spiclk", "apb_pclk"; 299 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 status = "disabled"; 305 }; 306 307 i2c1: i2c@ff140000 { 308 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 309 reg = <0x0 0xff140000 0x0 0x1000>; 310 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 clock-names = "i2c"; 314 clocks = <&cru PCLK_I2C1>; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&i2c1_xfer>; 317 status = "disabled"; 318 }; 319 320 i2c3: i2c@ff150000 { 321 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 322 reg = <0x0 0xff150000 0x0 0x1000>; 323 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 clock-names = "i2c"; 327 clocks = <&cru PCLK_I2C3>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&i2c3_xfer>; 330 status = "disabled"; 331 }; 332 333 i2c4: i2c@ff160000 { 334 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 335 reg = <0x0 0xff160000 0x0 0x1000>; 336 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 clock-names = "i2c"; 340 clocks = <&cru PCLK_I2C4>; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&i2c4_xfer>; 343 status = "disabled"; 344 }; 345 346 i2c5: i2c@ff170000 { 347 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 348 reg = <0x0 0xff170000 0x0 0x1000>; 349 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 clock-names = "i2c"; 353 clocks = <&cru PCLK_I2C5>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&i2c5_xfer>; 356 status = "disabled"; 357 }; 358 359 uart0: serial@ff180000 { 360 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 361 reg = <0x0 0xff180000 0x0 0x100>; 362 clock-frequency = <24000000>; 363 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 364 clock-names = "baudclk", "apb_pclk"; 365 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 366 reg-shift = <2>; 367 reg-io-width = <4>; 368 status = "disabled"; 369 }; 370 371 uart1: serial@ff190000 { 372 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 373 reg = <0x0 0xff190000 0x0 0x100>; 374 clock-frequency = <24000000>; 375 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 376 clock-names = "baudclk", "apb_pclk"; 377 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 378 reg-shift = <2>; 379 reg-io-width = <4>; 380 status = "disabled"; 381 }; 382 383 uart3: serial@ff1b0000 { 384 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 385 reg = <0x0 0xff1b0000 0x0 0x100>; 386 clock-frequency = <24000000>; 387 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 388 clock-names = "baudclk", "apb_pclk"; 389 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 390 reg-shift = <2>; 391 reg-io-width = <4>; 392 status = "disabled"; 393 }; 394 395 uart4: serial@ff1c0000 { 396 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 397 reg = <0x0 0xff1c0000 0x0 0x100>; 398 clock-frequency = <24000000>; 399 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 400 clock-names = "baudclk", "apb_pclk"; 401 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 402 reg-shift = <2>; 403 reg-io-width = <4>; 404 status = "disabled"; 405 }; 406 407 gmac: ethernet@ff290000 { 408 compatible = "rockchip,rk3368-gmac"; 409 reg = <0x0 0xff290000 0x0 0x10000>; 410 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 411 interrupt-names = "macirq"; 412 rockchip,grf = <&grf>; 413 clocks = <&cru SCLK_MAC>, 414 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 415 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 416 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 417 clock-names = "stmmaceth", 418 "mac_clk_rx", "mac_clk_tx", 419 "clk_mac_ref", "clk_mac_refout", 420 "aclk_mac", "pclk_mac"; 421 status = "disabled"; 422 }; 423 424 usb_host0_ehci: usb@ff500000 { 425 compatible = "generic-ehci"; 426 reg = <0x0 0xff500000 0x0 0x100>; 427 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&cru HCLK_HOST0>; 429 clock-names = "usbhost"; 430 status = "disabled"; 431 }; 432 433 usb_otg: usb@ff580000 { 434 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", 435 "snps,dwc2"; 436 reg = <0x0 0xff580000 0x0 0x40000>; 437 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cru HCLK_OTG0>; 439 clock-names = "otg"; 440 dr_mode = "otg"; 441 g-np-tx-fifo-size = <16>; 442 g-rx-fifo-size = <275>; 443 g-tx-fifo-size = <256 128 128 64 64 32>; 444 g-use-dma; 445 status = "disabled"; 446 }; 447 448 i2c0: i2c@ff650000 { 449 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 450 reg = <0x0 0xff650000 0x0 0x1000>; 451 clocks = <&cru PCLK_I2C0>; 452 clock-names = "i2c"; 453 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&i2c0_xfer>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 status = "disabled"; 459 }; 460 461 i2c2: i2c@ff660000 { 462 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 463 reg = <0x0 0xff660000 0x0 0x1000>; 464 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 clock-names = "i2c"; 468 clocks = <&cru PCLK_I2C2>; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&i2c2_xfer>; 471 status = "disabled"; 472 }; 473 474 uart2: serial@ff690000 { 475 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 476 reg = <0x0 0xff690000 0x0 0x100>; 477 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 478 clock-names = "baudclk", "apb_pclk"; 479 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&uart2_xfer>; 482 reg-shift = <2>; 483 reg-io-width = <4>; 484 status = "disabled"; 485 }; 486 487 pmugrf: syscon@ff738000 { 488 compatible = "rockchip,rk3368-pmugrf", "syscon"; 489 reg = <0x0 0xff738000 0x0 0x1000>; 490 }; 491 492 cru: clock-controller@ff760000 { 493 compatible = "rockchip,rk3368-cru"; 494 reg = <0x0 0xff760000 0x0 0x1000>; 495 rockchip,grf = <&grf>; 496 #clock-cells = <1>; 497 #reset-cells = <1>; 498 }; 499 500 grf: syscon@ff770000 { 501 compatible = "rockchip,rk3368-grf", "syscon"; 502 reg = <0x0 0xff770000 0x0 0x1000>; 503 }; 504 505 wdt: watchdog@ff800000 { 506 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; 507 reg = <0x0 0xff800000 0x0 0x100>; 508 clocks = <&cru PCLK_WDT>; 509 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 510 status = "disabled"; 511 }; 512 513 gic: interrupt-controller@ffb71000 { 514 compatible = "arm,gic-400"; 515 interrupt-controller; 516 #interrupt-cells = <3>; 517 #address-cells = <0>; 518 519 reg = <0x0 0xffb71000 0x0 0x1000>, 520 <0x0 0xffb72000 0x0 0x1000>, 521 <0x0 0xffb74000 0x0 0x2000>, 522 <0x0 0xffb76000 0x0 0x2000>; 523 interrupts = <GIC_PPI 9 524 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 525 }; 526 527 pinctrl: pinctrl { 528 compatible = "rockchip,rk3368-pinctrl"; 529 rockchip,grf = <&grf>; 530 rockchip,pmu = <&pmugrf>; 531 #address-cells = <0x2>; 532 #size-cells = <0x2>; 533 ranges; 534 535 gpio0: gpio0@ff750000 { 536 compatible = "rockchip,gpio-bank"; 537 reg = <0x0 0xff750000 0x0 0x100>; 538 clocks = <&cru PCLK_GPIO0>; 539 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; 540 541 gpio-controller; 542 #gpio-cells = <0x2>; 543 544 interrupt-controller; 545 #interrupt-cells = <0x2>; 546 }; 547 548 gpio1: gpio1@ff780000 { 549 compatible = "rockchip,gpio-bank"; 550 reg = <0x0 0xff780000 0x0 0x100>; 551 clocks = <&cru PCLK_GPIO1>; 552 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; 553 554 gpio-controller; 555 #gpio-cells = <0x2>; 556 557 interrupt-controller; 558 #interrupt-cells = <0x2>; 559 }; 560 561 gpio2: gpio2@ff790000 { 562 compatible = "rockchip,gpio-bank"; 563 reg = <0x0 0xff790000 0x0 0x100>; 564 clocks = <&cru PCLK_GPIO2>; 565 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; 566 567 gpio-controller; 568 #gpio-cells = <0x2>; 569 570 interrupt-controller; 571 #interrupt-cells = <0x2>; 572 }; 573 574 gpio3: gpio3@ff7a0000 { 575 compatible = "rockchip,gpio-bank"; 576 reg = <0x0 0xff7a0000 0x0 0x100>; 577 clocks = <&cru PCLK_GPIO3>; 578 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; 579 580 gpio-controller; 581 #gpio-cells = <0x2>; 582 583 interrupt-controller; 584 #interrupt-cells = <0x2>; 585 }; 586 587 pcfg_pull_up: pcfg-pull-up { 588 bias-pull-up; 589 }; 590 591 pcfg_pull_down: pcfg-pull-down { 592 bias-pull-down; 593 }; 594 595 pcfg_pull_none: pcfg-pull-none { 596 bias-disable; 597 }; 598 599 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 600 bias-disable; 601 drive-strength = <12>; 602 }; 603 604 emmc { 605 emmc_clk: emmc-clk { 606 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 607 }; 608 609 emmc_cmd: emmc-cmd { 610 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>; 611 }; 612 613 emmc_pwr: emmc-pwr { 614 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>; 615 }; 616 617 emmc_bus1: emmc-bus1 { 618 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>; 619 }; 620 621 emmc_bus4: emmc-bus4 { 622 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 623 <1 19 RK_FUNC_2 &pcfg_pull_up>, 624 <1 20 RK_FUNC_2 &pcfg_pull_up>, 625 <1 21 RK_FUNC_2 &pcfg_pull_up>; 626 }; 627 628 emmc_bus8: emmc-bus8 { 629 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 630 <1 19 RK_FUNC_2 &pcfg_pull_up>, 631 <1 20 RK_FUNC_2 &pcfg_pull_up>, 632 <1 21 RK_FUNC_2 &pcfg_pull_up>, 633 <1 22 RK_FUNC_2 &pcfg_pull_up>, 634 <1 23 RK_FUNC_2 &pcfg_pull_up>, 635 <1 24 RK_FUNC_2 &pcfg_pull_up>, 636 <1 25 RK_FUNC_2 &pcfg_pull_up>; 637 }; 638 }; 639 640 gmac { 641 rgmii_pins: rgmii-pins { 642 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 643 <3 24 RK_FUNC_1 &pcfg_pull_none>, 644 <3 19 RK_FUNC_1 &pcfg_pull_none>, 645 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 646 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 647 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>, 648 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>, 649 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>, 650 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 651 <3 15 RK_FUNC_1 &pcfg_pull_none>, 652 <3 16 RK_FUNC_1 &pcfg_pull_none>, 653 <3 17 RK_FUNC_1 &pcfg_pull_none>, 654 <3 18 RK_FUNC_1 &pcfg_pull_none>, 655 <3 25 RK_FUNC_1 &pcfg_pull_none>, 656 <3 20 RK_FUNC_1 &pcfg_pull_none>; 657 }; 658 659 rmii_pins: rmii-pins { 660 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 661 <3 24 RK_FUNC_1 &pcfg_pull_none>, 662 <3 19 RK_FUNC_1 &pcfg_pull_none>, 663 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 664 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 665 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 666 <3 15 RK_FUNC_1 &pcfg_pull_none>, 667 <3 16 RK_FUNC_1 &pcfg_pull_none>, 668 <3 20 RK_FUNC_1 &pcfg_pull_none>, 669 <3 21 RK_FUNC_1 &pcfg_pull_none>; 670 }; 671 }; 672 673 i2c0 { 674 i2c0_xfer: i2c0-xfer { 675 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 676 <0 7 RK_FUNC_1 &pcfg_pull_none>; 677 }; 678 }; 679 680 i2c1 { 681 i2c1_xfer: i2c1-xfer { 682 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>, 683 <2 22 RK_FUNC_1 &pcfg_pull_none>; 684 }; 685 }; 686 687 i2c2 { 688 i2c2_xfer: i2c2-xfer { 689 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>, 690 <3 31 RK_FUNC_2 &pcfg_pull_none>; 691 }; 692 }; 693 694 i2c3 { 695 i2c3_xfer: i2c3-xfer { 696 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>, 697 <1 17 RK_FUNC_1 &pcfg_pull_none>; 698 }; 699 }; 700 701 i2c4 { 702 i2c4_xfer: i2c4-xfer { 703 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>, 704 <3 25 RK_FUNC_2 &pcfg_pull_none>; 705 }; 706 }; 707 708 i2c5 { 709 i2c5_xfer: i2c5-xfer { 710 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>, 711 <3 27 RK_FUNC_2 &pcfg_pull_none>; 712 }; 713 }; 714 715 sdio0 { 716 sdio0_bus1: sdio0-bus1 { 717 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; 718 }; 719 720 sdio0_bus4: sdio0-bus4 { 721 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>, 722 <2 29 RK_FUNC_1 &pcfg_pull_up>, 723 <2 30 RK_FUNC_1 &pcfg_pull_up>, 724 <2 31 RK_FUNC_1 &pcfg_pull_up>; 725 }; 726 727 sdio0_cmd: sdio0-cmd { 728 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>; 729 }; 730 731 sdio0_clk: sdio0-clk { 732 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>; 733 }; 734 735 sdio0_cd: sdio0-cd { 736 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>; 737 }; 738 739 sdio0_wp: sdio0-wp { 740 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>; 741 }; 742 743 sdio0_pwr: sdio0-pwr { 744 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>; 745 }; 746 747 sdio0_bkpwr: sdio0-bkpwr { 748 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>; 749 }; 750 751 sdio0_int: sdio0-int { 752 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>; 753 }; 754 }; 755 756 sdmmc { 757 sdmmc_clk: sdmmc-clk { 758 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>; 759 }; 760 761 sdmmc_cmd: sdmmc-cmd { 762 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; 763 }; 764 765 sdmmc_cd: sdmcc-cd { 766 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; 767 }; 768 769 sdmmc_bus1: sdmmc-bus1 { 770 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>; 771 }; 772 773 sdmmc_bus4: sdmmc-bus4 { 774 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>, 775 <2 6 RK_FUNC_1 &pcfg_pull_up>, 776 <2 7 RK_FUNC_1 &pcfg_pull_up>, 777 <2 8 RK_FUNC_1 &pcfg_pull_up>; 778 }; 779 }; 780 781 spi0 { 782 spi0_clk: spi0-clk { 783 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>; 784 }; 785 spi0_cs0: spi0-cs0 { 786 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>; 787 }; 788 spi0_cs1: spi0-cs1 { 789 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>; 790 }; 791 spi0_tx: spi0-tx { 792 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>; 793 }; 794 spi0_rx: spi0-rx { 795 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>; 796 }; 797 }; 798 799 spi1 { 800 spi1_clk: spi1-clk { 801 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>; 802 }; 803 spi1_cs0: spi1-cs0 { 804 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>; 805 }; 806 spi1_cs1: spi1-cs1 { 807 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>; 808 }; 809 spi1_rx: spi1-rx { 810 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>; 811 }; 812 spi1_tx: spi1-tx { 813 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>; 814 }; 815 }; 816 817 spi2 { 818 spi2_clk: spi2-clk { 819 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>; 820 }; 821 spi2_cs0: spi2-cs0 { 822 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; 823 }; 824 spi2_rx: spi2-rx { 825 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>; 826 }; 827 spi2_tx: spi2-tx { 828 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; 829 }; 830 }; 831 832 uart0 { 833 uart0_xfer: uart0-xfer { 834 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>, 835 <2 25 RK_FUNC_1 &pcfg_pull_none>; 836 }; 837 838 uart0_cts: uart0-cts { 839 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>; 840 }; 841 842 uart0_rts: uart0-rts { 843 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>; 844 }; 845 }; 846 847 uart1 { 848 uart1_xfer: uart1-xfer { 849 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>, 850 <0 21 RK_FUNC_3 &pcfg_pull_none>; 851 }; 852 853 uart1_cts: uart1-cts { 854 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>; 855 }; 856 857 uart1_rts: uart1-rts { 858 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>; 859 }; 860 }; 861 862 uart2 { 863 uart2_xfer: uart2-xfer { 864 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>, 865 <2 5 RK_FUNC_2 &pcfg_pull_none>; 866 }; 867 /* no rts / cts for uart2 */ 868 }; 869 870 uart3 { 871 uart3_xfer: uart3-xfer { 872 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>, 873 <3 30 RK_FUNC_3 &pcfg_pull_none>; 874 }; 875 876 uart3_cts: uart3-cts { 877 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>; 878 }; 879 880 uart3_rts: uart3-rts { 881 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>; 882 }; 883 }; 884 885 uart4 { 886 uart4_xfer: uart4-xfer { 887 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>, 888 <0 26 RK_FUNC_3 &pcfg_pull_none>; 889 }; 890 891 uart4_cts: uart4-cts { 892 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>; 893 }; 894 895 uart4_rts: uart4-rts { 896 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>; 897 }; 898 }; 899 }; 900}; 901