1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 4 */ 5 6#include <dt-bindings/clock/rk3368-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/soc/rockchip,boot-mode.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3368"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 ethernet0 = &gmac; 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 i2c4 = &i2c4; 27 i2c5 = &i2c5; 28 mmc0 = &sdmmc; 29 mmc1 = &sdio0; 30 mmc2 = &emmc; 31 serial0 = &uart0; 32 serial1 = &uart1; 33 serial2 = &uart2; 34 serial3 = &uart3; 35 serial4 = &uart4; 36 spi0 = &spi0; 37 spi1 = &spi1; 38 spi2 = &spi2; 39 }; 40 41 cpus { 42 #address-cells = <0x2>; 43 #size-cells = <0x0>; 44 45 cpu-map { 46 cluster0 { 47 core0 { 48 cpu = <&cpu_b0>; 49 }; 50 core1 { 51 cpu = <&cpu_b1>; 52 }; 53 core2 { 54 cpu = <&cpu_b2>; 55 }; 56 core3 { 57 cpu = <&cpu_b3>; 58 }; 59 }; 60 61 cluster1 { 62 core0 { 63 cpu = <&cpu_l0>; 64 }; 65 core1 { 66 cpu = <&cpu_l1>; 67 }; 68 core2 { 69 cpu = <&cpu_l2>; 70 }; 71 core3 { 72 cpu = <&cpu_l3>; 73 }; 74 }; 75 }; 76 77 cpu_l0: cpu@0 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x0 0x0>; 81 enable-method = "psci"; 82 #cooling-cells = <2>; /* min followed by max */ 83 }; 84 85 cpu_l1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x0 0x1>; 89 enable-method = "psci"; 90 #cooling-cells = <2>; /* min followed by max */ 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 #cooling-cells = <2>; /* min followed by max */ 99 }; 100 101 cpu_l3: cpu@3 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x0 0x3>; 105 enable-method = "psci"; 106 #cooling-cells = <2>; /* min followed by max */ 107 }; 108 109 cpu_b0: cpu@100 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a53"; 112 reg = <0x0 0x100>; 113 enable-method = "psci"; 114 #cooling-cells = <2>; /* min followed by max */ 115 }; 116 117 cpu_b1: cpu@101 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a53"; 120 reg = <0x0 0x101>; 121 enable-method = "psci"; 122 #cooling-cells = <2>; /* min followed by max */ 123 }; 124 125 cpu_b2: cpu@102 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a53"; 128 reg = <0x0 0x102>; 129 enable-method = "psci"; 130 #cooling-cells = <2>; /* min followed by max */ 131 }; 132 133 cpu_b3: cpu@103 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a53"; 136 reg = <0x0 0x103>; 137 enable-method = "psci"; 138 #cooling-cells = <2>; /* min followed by max */ 139 }; 140 }; 141 142 arm-pmu { 143 compatible = "arm,armv8-pmuv3"; 144 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 152 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, 153 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, 154 <&cpu_b2>, <&cpu_b3>; 155 }; 156 157 psci { 158 compatible = "arm,psci-0.2"; 159 method = "smc"; 160 }; 161 162 timer { 163 compatible = "arm,armv8-timer"; 164 interrupts = <GIC_PPI 13 165 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 166 <GIC_PPI 14 167 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 168 <GIC_PPI 11 169 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 170 <GIC_PPI 10 171 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 172 }; 173 174 xin24m: oscillator { 175 compatible = "fixed-clock"; 176 clock-frequency = <24000000>; 177 clock-output-names = "xin24m"; 178 #clock-cells = <0>; 179 }; 180 181 sdmmc: mmc@ff0c0000 { 182 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 183 reg = <0x0 0xff0c0000 0x0 0x4000>; 184 max-frequency = <150000000>; 185 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 186 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 187 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 188 fifo-depth = <0x100>; 189 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 190 resets = <&cru SRST_MMC0>; 191 reset-names = "reset"; 192 status = "disabled"; 193 }; 194 195 sdio0: mmc@ff0d0000 { 196 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 197 reg = <0x0 0xff0d0000 0x0 0x4000>; 198 max-frequency = <150000000>; 199 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 200 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 201 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 202 fifo-depth = <0x100>; 203 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 204 resets = <&cru SRST_SDIO0>; 205 reset-names = "reset"; 206 status = "disabled"; 207 }; 208 209 emmc: mmc@ff0f0000 { 210 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 211 reg = <0x0 0xff0f0000 0x0 0x4000>; 212 max-frequency = <150000000>; 213 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 214 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 215 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 216 fifo-depth = <0x100>; 217 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 218 resets = <&cru SRST_EMMC>; 219 reset-names = "reset"; 220 status = "disabled"; 221 }; 222 223 saradc: saradc@ff100000 { 224 compatible = "rockchip,saradc"; 225 reg = <0x0 0xff100000 0x0 0x100>; 226 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 227 #io-channel-cells = <1>; 228 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 229 clock-names = "saradc", "apb_pclk"; 230 resets = <&cru SRST_SARADC>; 231 reset-names = "saradc-apb"; 232 status = "disabled"; 233 }; 234 235 spi0: spi@ff110000 { 236 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 237 reg = <0x0 0xff110000 0x0 0x1000>; 238 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 239 clock-names = "spiclk", "apb_pclk"; 240 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 status = "disabled"; 246 }; 247 248 spi1: spi@ff120000 { 249 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 250 reg = <0x0 0xff120000 0x0 0x1000>; 251 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 252 clock-names = "spiclk", "apb_pclk"; 253 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 status = "disabled"; 259 }; 260 261 spi2: spi@ff130000 { 262 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 263 reg = <0x0 0xff130000 0x0 0x1000>; 264 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 265 clock-names = "spiclk", "apb_pclk"; 266 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 status = "disabled"; 272 }; 273 274 i2c2: i2c@ff140000 { 275 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 276 reg = <0x0 0xff140000 0x0 0x1000>; 277 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 clock-names = "i2c"; 281 clocks = <&cru PCLK_I2C2>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&i2c2_xfer>; 284 status = "disabled"; 285 }; 286 287 i2c3: i2c@ff150000 { 288 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 289 reg = <0x0 0xff150000 0x0 0x1000>; 290 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 clock-names = "i2c"; 294 clocks = <&cru PCLK_I2C3>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&i2c3_xfer>; 297 status = "disabled"; 298 }; 299 300 i2c4: i2c@ff160000 { 301 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 302 reg = <0x0 0xff160000 0x0 0x1000>; 303 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 clock-names = "i2c"; 307 clocks = <&cru PCLK_I2C4>; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&i2c4_xfer>; 310 status = "disabled"; 311 }; 312 313 i2c5: i2c@ff170000 { 314 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 315 reg = <0x0 0xff170000 0x0 0x1000>; 316 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 clock-names = "i2c"; 320 clocks = <&cru PCLK_I2C5>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&i2c5_xfer>; 323 status = "disabled"; 324 }; 325 326 uart0: serial@ff180000 { 327 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 328 reg = <0x0 0xff180000 0x0 0x100>; 329 clock-frequency = <24000000>; 330 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 331 clock-names = "baudclk", "apb_pclk"; 332 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 333 reg-shift = <2>; 334 reg-io-width = <4>; 335 status = "disabled"; 336 }; 337 338 uart1: serial@ff190000 { 339 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 340 reg = <0x0 0xff190000 0x0 0x100>; 341 clock-frequency = <24000000>; 342 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 343 clock-names = "baudclk", "apb_pclk"; 344 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 345 reg-shift = <2>; 346 reg-io-width = <4>; 347 status = "disabled"; 348 }; 349 350 uart3: serial@ff1b0000 { 351 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 352 reg = <0x0 0xff1b0000 0x0 0x100>; 353 clock-frequency = <24000000>; 354 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 355 clock-names = "baudclk", "apb_pclk"; 356 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 357 reg-shift = <2>; 358 reg-io-width = <4>; 359 status = "disabled"; 360 }; 361 362 uart4: serial@ff1c0000 { 363 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 364 reg = <0x0 0xff1c0000 0x0 0x100>; 365 clock-frequency = <24000000>; 366 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 367 clock-names = "baudclk", "apb_pclk"; 368 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 369 reg-shift = <2>; 370 reg-io-width = <4>; 371 status = "disabled"; 372 }; 373 374 dmac_peri: dma-controller@ff250000 { 375 compatible = "arm,pl330", "arm,primecell"; 376 reg = <0x0 0xff250000 0x0 0x4000>; 377 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 379 #dma-cells = <1>; 380 arm,pl330-broken-no-flushp; 381 arm,pl330-periph-burst; 382 clocks = <&cru ACLK_DMAC_PERI>; 383 clock-names = "apb_pclk"; 384 }; 385 386 thermal-zones { 387 cpu_thermal: cpu-thermal { 388 polling-delay-passive = <100>; /* milliseconds */ 389 polling-delay = <5000>; /* milliseconds */ 390 391 thermal-sensors = <&tsadc 0>; 392 393 trips { 394 cpu_alert0: cpu_alert0 { 395 temperature = <75000>; /* millicelsius */ 396 hysteresis = <2000>; /* millicelsius */ 397 type = "passive"; 398 }; 399 cpu_alert1: cpu_alert1 { 400 temperature = <80000>; /* millicelsius */ 401 hysteresis = <2000>; /* millicelsius */ 402 type = "passive"; 403 }; 404 cpu_crit: cpu_crit { 405 temperature = <95000>; /* millicelsius */ 406 hysteresis = <2000>; /* millicelsius */ 407 type = "critical"; 408 }; 409 }; 410 411 cooling-maps { 412 map0 { 413 trip = <&cpu_alert0>; 414 cooling-device = 415 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 416 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 417 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 418 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 419 }; 420 map1 { 421 trip = <&cpu_alert1>; 422 cooling-device = 423 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 424 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 425 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 426 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 427 }; 428 }; 429 }; 430 431 gpu_thermal: gpu-thermal { 432 polling-delay-passive = <100>; /* milliseconds */ 433 polling-delay = <5000>; /* milliseconds */ 434 435 thermal-sensors = <&tsadc 1>; 436 437 trips { 438 gpu_alert0: gpu_alert0 { 439 temperature = <80000>; /* millicelsius */ 440 hysteresis = <2000>; /* millicelsius */ 441 type = "passive"; 442 }; 443 gpu_crit: gpu_crit { 444 temperature = <115000>; /* millicelsius */ 445 hysteresis = <2000>; /* millicelsius */ 446 type = "critical"; 447 }; 448 }; 449 450 cooling-maps { 451 map0 { 452 trip = <&gpu_alert0>; 453 cooling-device = 454 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 455 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 456 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 457 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 458 }; 459 }; 460 }; 461 }; 462 463 tsadc: tsadc@ff280000 { 464 compatible = "rockchip,rk3368-tsadc"; 465 reg = <0x0 0xff280000 0x0 0x100>; 466 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 468 clock-names = "tsadc", "apb_pclk"; 469 resets = <&cru SRST_TSADC>; 470 reset-names = "tsadc-apb"; 471 pinctrl-names = "init", "default", "sleep"; 472 pinctrl-0 = <&otp_pin>; 473 pinctrl-1 = <&otp_out>; 474 pinctrl-2 = <&otp_pin>; 475 #thermal-sensor-cells = <1>; 476 rockchip,hw-tshut-temp = <95000>; 477 status = "disabled"; 478 }; 479 480 gmac: ethernet@ff290000 { 481 compatible = "rockchip,rk3368-gmac"; 482 reg = <0x0 0xff290000 0x0 0x10000>; 483 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 484 interrupt-names = "macirq"; 485 rockchip,grf = <&grf>; 486 clocks = <&cru SCLK_MAC>, 487 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 488 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 489 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 490 clock-names = "stmmaceth", 491 "mac_clk_rx", "mac_clk_tx", 492 "clk_mac_ref", "clk_mac_refout", 493 "aclk_mac", "pclk_mac"; 494 status = "disabled"; 495 }; 496 497 usb_host0_ehci: usb@ff500000 { 498 compatible = "generic-ehci"; 499 reg = <0x0 0xff500000 0x0 0x100>; 500 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&cru HCLK_HOST0>; 502 status = "disabled"; 503 }; 504 505 usb_otg: usb@ff580000 { 506 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", 507 "snps,dwc2"; 508 reg = <0x0 0xff580000 0x0 0x40000>; 509 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&cru HCLK_OTG0>; 511 clock-names = "otg"; 512 dr_mode = "otg"; 513 g-np-tx-fifo-size = <16>; 514 g-rx-fifo-size = <275>; 515 g-tx-fifo-size = <256 128 128 64 64 32>; 516 status = "disabled"; 517 }; 518 519 dmac_bus: dma-controller@ff600000 { 520 compatible = "arm,pl330", "arm,primecell"; 521 reg = <0x0 0xff600000 0x0 0x4000>; 522 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 524 #dma-cells = <1>; 525 arm,pl330-broken-no-flushp; 526 arm,pl330-periph-burst; 527 clocks = <&cru ACLK_DMAC_BUS>; 528 clock-names = "apb_pclk"; 529 }; 530 531 i2c0: i2c@ff650000 { 532 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 533 reg = <0x0 0xff650000 0x0 0x1000>; 534 clocks = <&cru PCLK_I2C0>; 535 clock-names = "i2c"; 536 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 537 pinctrl-names = "default"; 538 pinctrl-0 = <&i2c0_xfer>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 status = "disabled"; 542 }; 543 544 i2c1: i2c@ff660000 { 545 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 546 reg = <0x0 0xff660000 0x0 0x1000>; 547 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 clock-names = "i2c"; 551 clocks = <&cru PCLK_I2C1>; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&i2c1_xfer>; 554 status = "disabled"; 555 }; 556 557 pwm0: pwm@ff680000 { 558 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 559 reg = <0x0 0xff680000 0x0 0x10>; 560 #pwm-cells = <3>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pwm0_pin>; 563 clocks = <&cru PCLK_PWM1>; 564 clock-names = "pwm"; 565 status = "disabled"; 566 }; 567 568 pwm1: pwm@ff680010 { 569 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 570 reg = <0x0 0xff680010 0x0 0x10>; 571 #pwm-cells = <3>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&pwm1_pin>; 574 clocks = <&cru PCLK_PWM1>; 575 clock-names = "pwm"; 576 status = "disabled"; 577 }; 578 579 pwm2: pwm@ff680020 { 580 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 581 reg = <0x0 0xff680020 0x0 0x10>; 582 #pwm-cells = <3>; 583 clocks = <&cru PCLK_PWM1>; 584 clock-names = "pwm"; 585 status = "disabled"; 586 }; 587 588 pwm3: pwm@ff680030 { 589 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 590 reg = <0x0 0xff680030 0x0 0x10>; 591 #pwm-cells = <3>; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&pwm3_pin>; 594 clocks = <&cru PCLK_PWM1>; 595 clock-names = "pwm"; 596 status = "disabled"; 597 }; 598 599 uart2: serial@ff690000 { 600 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 601 reg = <0x0 0xff690000 0x0 0x100>; 602 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 603 clock-names = "baudclk", "apb_pclk"; 604 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 605 pinctrl-names = "default"; 606 pinctrl-0 = <&uart2_xfer>; 607 reg-shift = <2>; 608 reg-io-width = <4>; 609 status = "disabled"; 610 }; 611 612 mbox: mbox@ff6b0000 { 613 compatible = "rockchip,rk3368-mailbox"; 614 reg = <0x0 0xff6b0000 0x0 0x1000>; 615 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&cru PCLK_MAILBOX>; 620 clock-names = "pclk_mailbox"; 621 #mbox-cells = <1>; 622 status = "disabled"; 623 }; 624 625 pmugrf: syscon@ff738000 { 626 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; 627 reg = <0x0 0xff738000 0x0 0x1000>; 628 629 pmu_io_domains: io-domains { 630 compatible = "rockchip,rk3368-pmu-io-voltage-domain"; 631 status = "disabled"; 632 }; 633 634 reboot-mode { 635 compatible = "syscon-reboot-mode"; 636 offset = <0x200>; 637 mode-normal = <BOOT_NORMAL>; 638 mode-recovery = <BOOT_RECOVERY>; 639 mode-bootloader = <BOOT_FASTBOOT>; 640 mode-loader = <BOOT_BL_DOWNLOAD>; 641 }; 642 }; 643 644 cru: clock-controller@ff760000 { 645 compatible = "rockchip,rk3368-cru"; 646 reg = <0x0 0xff760000 0x0 0x1000>; 647 rockchip,grf = <&grf>; 648 #clock-cells = <1>; 649 #reset-cells = <1>; 650 }; 651 652 grf: syscon@ff770000 { 653 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; 654 reg = <0x0 0xff770000 0x0 0x1000>; 655 656 io_domains: io-domains { 657 compatible = "rockchip,rk3368-io-voltage-domain"; 658 status = "disabled"; 659 }; 660 }; 661 662 wdt: watchdog@ff800000 { 663 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; 664 reg = <0x0 0xff800000 0x0 0x100>; 665 clocks = <&cru PCLK_WDT>; 666 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 667 status = "disabled"; 668 }; 669 670 timer@ff810000 { 671 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; 672 reg = <0x0 0xff810000 0x0 0x20>; 673 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 674 }; 675 676 spdif: spdif@ff880000 { 677 compatible = "rockchip,rk3368-spdif"; 678 reg = <0x0 0xff880000 0x0 0x1000>; 679 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 681 clock-names = "mclk", "hclk"; 682 dmas = <&dmac_bus 3>; 683 dma-names = "tx"; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&spdif_tx>; 686 status = "disabled"; 687 }; 688 689 i2s_2ch: i2s-2ch@ff890000 { 690 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; 691 reg = <0x0 0xff890000 0x0 0x1000>; 692 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 693 clock-names = "i2s_clk", "i2s_hclk"; 694 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; 695 dmas = <&dmac_bus 6>, <&dmac_bus 7>; 696 dma-names = "tx", "rx"; 697 status = "disabled"; 698 }; 699 700 i2s_8ch: i2s-8ch@ff898000 { 701 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; 702 reg = <0x0 0xff898000 0x0 0x1000>; 703 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 704 clock-names = "i2s_clk", "i2s_hclk"; 705 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; 706 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 707 dma-names = "tx", "rx"; 708 pinctrl-names = "default"; 709 pinctrl-0 = <&i2s_8ch_bus>; 710 status = "disabled"; 711 }; 712 713 iep_mmu: iommu@ff900800 { 714 compatible = "rockchip,iommu"; 715 reg = <0x0 0xff900800 0x0 0x100>; 716 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 717 interrupt-names = "iep_mmu"; 718 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 719 clock-names = "aclk", "iface"; 720 #iommu-cells = <0>; 721 status = "disabled"; 722 }; 723 724 isp_mmu: iommu@ff914000 { 725 compatible = "rockchip,iommu"; 726 reg = <0x0 0xff914000 0x0 0x100>, 727 <0x0 0xff915000 0x0 0x100>; 728 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 729 interrupt-names = "isp_mmu"; 730 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 731 clock-names = "aclk", "iface"; 732 #iommu-cells = <0>; 733 rockchip,disable-mmu-reset; 734 status = "disabled"; 735 }; 736 737 vop_mmu: iommu@ff930300 { 738 compatible = "rockchip,iommu"; 739 reg = <0x0 0xff930300 0x0 0x100>; 740 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 741 interrupt-names = "vop_mmu"; 742 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 743 clock-names = "aclk", "iface"; 744 #iommu-cells = <0>; 745 status = "disabled"; 746 }; 747 748 hevc_mmu: iommu@ff9a0440 { 749 compatible = "rockchip,iommu"; 750 reg = <0x0 0xff9a0440 0x0 0x40>, 751 <0x0 0xff9a0480 0x0 0x40>; 752 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 753 interrupt-names = "hevc_mmu"; 754 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; 755 clock-names = "aclk", "iface"; 756 #iommu-cells = <0>; 757 status = "disabled"; 758 }; 759 760 vpu_mmu: iommu@ff9a0800 { 761 compatible = "rockchip,iommu"; 762 reg = <0x0 0xff9a0800 0x0 0x100>; 763 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 765 interrupt-names = "vepu_mmu", "vdpu_mmu"; 766 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; 767 clock-names = "aclk", "iface"; 768 #iommu-cells = <0>; 769 status = "disabled"; 770 }; 771 772 efuse256: efuse@ffb00000 { 773 compatible = "rockchip,rk3368-efuse"; 774 reg = <0x0 0xffb00000 0x0 0x20>; 775 #address-cells = <1>; 776 #size-cells = <1>; 777 clocks = <&cru PCLK_EFUSE256>; 778 clock-names = "pclk_efuse"; 779 780 cpu_leakage: cpu-leakage@17 { 781 reg = <0x17 0x1>; 782 }; 783 temp_adjust: temp-adjust@1f { 784 reg = <0x1f 0x1>; 785 }; 786 }; 787 788 gic: interrupt-controller@ffb71000 { 789 compatible = "arm,gic-400"; 790 interrupt-controller; 791 #interrupt-cells = <3>; 792 #address-cells = <0>; 793 794 reg = <0x0 0xffb71000 0x0 0x1000>, 795 <0x0 0xffb72000 0x0 0x2000>, 796 <0x0 0xffb74000 0x0 0x2000>, 797 <0x0 0xffb76000 0x0 0x2000>; 798 interrupts = <GIC_PPI 9 799 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 800 }; 801 802 pinctrl: pinctrl { 803 compatible = "rockchip,rk3368-pinctrl"; 804 rockchip,grf = <&grf>; 805 rockchip,pmu = <&pmugrf>; 806 #address-cells = <0x2>; 807 #size-cells = <0x2>; 808 ranges; 809 810 gpio0: gpio0@ff750000 { 811 compatible = "rockchip,gpio-bank"; 812 reg = <0x0 0xff750000 0x0 0x100>; 813 clocks = <&cru PCLK_GPIO0>; 814 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; 815 816 gpio-controller; 817 #gpio-cells = <0x2>; 818 819 interrupt-controller; 820 #interrupt-cells = <0x2>; 821 }; 822 823 gpio1: gpio1@ff780000 { 824 compatible = "rockchip,gpio-bank"; 825 reg = <0x0 0xff780000 0x0 0x100>; 826 clocks = <&cru PCLK_GPIO1>; 827 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; 828 829 gpio-controller; 830 #gpio-cells = <0x2>; 831 832 interrupt-controller; 833 #interrupt-cells = <0x2>; 834 }; 835 836 gpio2: gpio2@ff790000 { 837 compatible = "rockchip,gpio-bank"; 838 reg = <0x0 0xff790000 0x0 0x100>; 839 clocks = <&cru PCLK_GPIO2>; 840 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; 841 842 gpio-controller; 843 #gpio-cells = <0x2>; 844 845 interrupt-controller; 846 #interrupt-cells = <0x2>; 847 }; 848 849 gpio3: gpio3@ff7a0000 { 850 compatible = "rockchip,gpio-bank"; 851 reg = <0x0 0xff7a0000 0x0 0x100>; 852 clocks = <&cru PCLK_GPIO3>; 853 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; 854 855 gpio-controller; 856 #gpio-cells = <0x2>; 857 858 interrupt-controller; 859 #interrupt-cells = <0x2>; 860 }; 861 862 pcfg_pull_up: pcfg-pull-up { 863 bias-pull-up; 864 }; 865 866 pcfg_pull_down: pcfg-pull-down { 867 bias-pull-down; 868 }; 869 870 pcfg_pull_none: pcfg-pull-none { 871 bias-disable; 872 }; 873 874 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 875 bias-disable; 876 drive-strength = <12>; 877 }; 878 879 emmc { 880 emmc_clk: emmc-clk { 881 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; 882 }; 883 884 emmc_cmd: emmc-cmd { 885 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; 886 }; 887 888 emmc_pwr: emmc-pwr { 889 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; 890 }; 891 892 emmc_bus1: emmc-bus1 { 893 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>; 894 }; 895 896 emmc_bus4: emmc-bus4 { 897 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 898 <1 RK_PC3 2 &pcfg_pull_up>, 899 <1 RK_PC4 2 &pcfg_pull_up>, 900 <1 RK_PC5 2 &pcfg_pull_up>; 901 }; 902 903 emmc_bus8: emmc-bus8 { 904 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 905 <1 RK_PC3 2 &pcfg_pull_up>, 906 <1 RK_PC4 2 &pcfg_pull_up>, 907 <1 RK_PC5 2 &pcfg_pull_up>, 908 <1 RK_PC6 2 &pcfg_pull_up>, 909 <1 RK_PC7 2 &pcfg_pull_up>, 910 <1 RK_PD0 2 &pcfg_pull_up>, 911 <1 RK_PD1 2 &pcfg_pull_up>; 912 }; 913 }; 914 915 gmac { 916 rgmii_pins: rgmii-pins { 917 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, 918 <3 RK_PD0 1 &pcfg_pull_none>, 919 <3 RK_PC3 1 &pcfg_pull_none>, 920 <3 RK_PB0 1 &pcfg_pull_none_12ma>, 921 <3 RK_PB1 1 &pcfg_pull_none_12ma>, 922 <3 RK_PB2 1 &pcfg_pull_none_12ma>, 923 <3 RK_PB6 1 &pcfg_pull_none_12ma>, 924 <3 RK_PD4 1 &pcfg_pull_none_12ma>, 925 <3 RK_PB5 1 &pcfg_pull_none_12ma>, 926 <3 RK_PB7 1 &pcfg_pull_none>, 927 <3 RK_PC0 1 &pcfg_pull_none>, 928 <3 RK_PC1 1 &pcfg_pull_none>, 929 <3 RK_PC2 1 &pcfg_pull_none>, 930 <3 RK_PD1 1 &pcfg_pull_none>, 931 <3 RK_PC4 1 &pcfg_pull_none>; 932 }; 933 934 rmii_pins: rmii-pins { 935 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, 936 <3 RK_PD0 1 &pcfg_pull_none>, 937 <3 RK_PC3 1 &pcfg_pull_none>, 938 <3 RK_PB0 1 &pcfg_pull_none_12ma>, 939 <3 RK_PB1 1 &pcfg_pull_none_12ma>, 940 <3 RK_PB5 1 &pcfg_pull_none_12ma>, 941 <3 RK_PB7 1 &pcfg_pull_none>, 942 <3 RK_PC0 1 &pcfg_pull_none>, 943 <3 RK_PC4 1 &pcfg_pull_none>, 944 <3 RK_PC5 1 &pcfg_pull_none>; 945 }; 946 }; 947 948 i2c0 { 949 i2c0_xfer: i2c0-xfer { 950 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 951 <0 RK_PA7 1 &pcfg_pull_none>; 952 }; 953 }; 954 955 i2c1 { 956 i2c1_xfer: i2c1-xfer { 957 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>, 958 <2 RK_PC6 1 &pcfg_pull_none>; 959 }; 960 }; 961 962 i2c2 { 963 i2c2_xfer: i2c2-xfer { 964 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>, 965 <3 RK_PD7 2 &pcfg_pull_none>; 966 }; 967 }; 968 969 i2c3 { 970 i2c3_xfer: i2c3-xfer { 971 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, 972 <1 RK_PC1 1 &pcfg_pull_none>; 973 }; 974 }; 975 976 i2c4 { 977 i2c4_xfer: i2c4-xfer { 978 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, 979 <3 RK_PD1 2 &pcfg_pull_none>; 980 }; 981 }; 982 983 i2c5 { 984 i2c5_xfer: i2c5-xfer { 985 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>, 986 <3 RK_PD3 2 &pcfg_pull_none>; 987 }; 988 }; 989 990 i2s { 991 i2s_8ch_bus: i2s-8ch-bus { 992 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 993 <2 RK_PB5 1 &pcfg_pull_none>, 994 <2 RK_PB6 1 &pcfg_pull_none>, 995 <2 RK_PB7 1 &pcfg_pull_none>, 996 <2 RK_PC0 1 &pcfg_pull_none>, 997 <2 RK_PC1 1 &pcfg_pull_none>, 998 <2 RK_PC2 1 &pcfg_pull_none>, 999 <2 RK_PC3 1 &pcfg_pull_none>, 1000 <2 RK_PC4 1 &pcfg_pull_none>; 1001 }; 1002 }; 1003 1004 pwm0 { 1005 pwm0_pin: pwm0-pin { 1006 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>; 1007 }; 1008 }; 1009 1010 pwm1 { 1011 pwm1_pin: pwm1-pin { 1012 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>; 1013 }; 1014 }; 1015 1016 pwm3 { 1017 pwm3_pin: pwm3-pin { 1018 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>; 1019 }; 1020 }; 1021 1022 sdio0 { 1023 sdio0_bus1: sdio0-bus1 { 1024 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>; 1025 }; 1026 1027 sdio0_bus4: sdio0-bus4 { 1028 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>, 1029 <2 RK_PD5 1 &pcfg_pull_up>, 1030 <2 RK_PD6 1 &pcfg_pull_up>, 1031 <2 RK_PD7 1 &pcfg_pull_up>; 1032 }; 1033 1034 sdio0_cmd: sdio0-cmd { 1035 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>; 1036 }; 1037 1038 sdio0_clk: sdio0-clk { 1039 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; 1040 }; 1041 1042 sdio0_cd: sdio0-cd { 1043 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>; 1044 }; 1045 1046 sdio0_wp: sdio0-wp { 1047 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>; 1048 }; 1049 1050 sdio0_pwr: sdio0-pwr { 1051 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>; 1052 }; 1053 1054 sdio0_bkpwr: sdio0-bkpwr { 1055 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>; 1056 }; 1057 1058 sdio0_int: sdio0-int { 1059 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>; 1060 }; 1061 }; 1062 1063 sdmmc { 1064 sdmmc_clk: sdmmc-clk { 1065 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 1066 }; 1067 1068 sdmmc_cmd: sdmmc-cmd { 1069 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1070 }; 1071 1072 sdmmc_cd: sdmmc-cd { 1073 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1074 }; 1075 1076 sdmmc_bus1: sdmmc-bus1 { 1077 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>; 1078 }; 1079 1080 sdmmc_bus4: sdmmc-bus4 { 1081 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>, 1082 <2 RK_PA6 1 &pcfg_pull_up>, 1083 <2 RK_PA7 1 &pcfg_pull_up>, 1084 <2 RK_PB0 1 &pcfg_pull_up>; 1085 }; 1086 }; 1087 1088 spdif { 1089 spdif_tx: spdif-tx { 1090 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1091 }; 1092 }; 1093 1094 spi0 { 1095 spi0_clk: spi0-clk { 1096 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>; 1097 }; 1098 spi0_cs0: spi0-cs0 { 1099 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>; 1100 }; 1101 spi0_cs1: spi0-cs1 { 1102 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>; 1103 }; 1104 spi0_tx: spi0-tx { 1105 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>; 1106 }; 1107 spi0_rx: spi0-rx { 1108 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>; 1109 }; 1110 }; 1111 1112 spi1 { 1113 spi1_clk: spi1-clk { 1114 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; 1115 }; 1116 spi1_cs0: spi1-cs0 { 1117 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>; 1118 }; 1119 spi1_cs1: spi1-cs1 { 1120 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>; 1121 }; 1122 spi1_rx: spi1-rx { 1123 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>; 1124 }; 1125 spi1_tx: spi1-tx { 1126 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>; 1127 }; 1128 }; 1129 1130 spi2 { 1131 spi2_clk: spi2-clk { 1132 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>; 1133 }; 1134 spi2_cs0: spi2-cs0 { 1135 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; 1136 }; 1137 spi2_rx: spi2-rx { 1138 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>; 1139 }; 1140 spi2_tx: spi2-tx { 1141 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; 1142 }; 1143 }; 1144 1145 tsadc { 1146 otp_pin: otp-pin { 1147 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 1148 }; 1149 1150 otp_out: otp-out { 1151 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1152 }; 1153 }; 1154 1155 uart0 { 1156 uart0_xfer: uart0-xfer { 1157 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>, 1158 <2 RK_PD1 1 &pcfg_pull_none>; 1159 }; 1160 1161 uart0_cts: uart0-cts { 1162 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; 1163 }; 1164 1165 uart0_rts: uart0-rts { 1166 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; 1167 }; 1168 }; 1169 1170 uart1 { 1171 uart1_xfer: uart1-xfer { 1172 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>, 1173 <0 RK_PC5 3 &pcfg_pull_none>; 1174 }; 1175 1176 uart1_cts: uart1-cts { 1177 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>; 1178 }; 1179 1180 uart1_rts: uart1-rts { 1181 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>; 1182 }; 1183 }; 1184 1185 uart2 { 1186 uart2_xfer: uart2-xfer { 1187 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>, 1188 <2 RK_PA5 2 &pcfg_pull_none>; 1189 }; 1190 /* no rts / cts for uart2 */ 1191 }; 1192 1193 uart3 { 1194 uart3_xfer: uart3-xfer { 1195 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>, 1196 <3 RK_PD6 3 &pcfg_pull_none>; 1197 }; 1198 1199 uart3_cts: uart3-cts { 1200 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>; 1201 }; 1202 1203 uart3_rts: uart3-rts { 1204 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>; 1205 }; 1206 }; 1207 1208 uart4 { 1209 uart4_xfer: uart4-xfer { 1210 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>, 1211 <0 RK_PD2 3 &pcfg_pull_none>; 1212 }; 1213 1214 uart4_cts: uart4-cts { 1215 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>; 1216 }; 1217 1218 uart4_rts: uart4-rts { 1219 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>; 1220 }; 1221 }; 1222 }; 1223}; 1224