1/* 2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3368-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/irq.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/soc/rockchip,boot-mode.h> 49#include <dt-bindings/thermal/thermal.h> 50 51/ { 52 compatible = "rockchip,rk3368"; 53 interrupt-parent = <&gic>; 54 #address-cells = <2>; 55 #size-cells = <2>; 56 57 aliases { 58 ethernet0 = &gmac; 59 i2c0 = &i2c0; 60 i2c1 = &i2c1; 61 i2c2 = &i2c2; 62 i2c3 = &i2c3; 63 i2c4 = &i2c4; 64 i2c5 = &i2c5; 65 serial0 = &uart0; 66 serial1 = &uart1; 67 serial2 = &uart2; 68 serial3 = &uart3; 69 serial4 = &uart4; 70 spi0 = &spi0; 71 spi1 = &spi1; 72 spi2 = &spi2; 73 }; 74 75 cpus { 76 #address-cells = <0x2>; 77 #size-cells = <0x0>; 78 79 cpu-map { 80 cluster0 { 81 core0 { 82 cpu = <&cpu_b0>; 83 }; 84 core1 { 85 cpu = <&cpu_b1>; 86 }; 87 core2 { 88 cpu = <&cpu_b2>; 89 }; 90 core3 { 91 cpu = <&cpu_b3>; 92 }; 93 }; 94 95 cluster1 { 96 core0 { 97 cpu = <&cpu_l0>; 98 }; 99 core1 { 100 cpu = <&cpu_l1>; 101 }; 102 core2 { 103 cpu = <&cpu_l2>; 104 }; 105 core3 { 106 cpu = <&cpu_l3>; 107 }; 108 }; 109 }; 110 111 cpu_l0: cpu@0 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a53", "arm,armv8"; 114 reg = <0x0 0x0>; 115 enable-method = "psci"; 116 clocks = <&cru ARMCLKL>; 117 operating-points-v2 = <&cluster0_opp>; 118 #cooling-cells = <2>; /* min followed by max */ 119 }; 120 121 cpu_l1: cpu@1 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a53", "arm,armv8"; 124 reg = <0x0 0x1>; 125 enable-method = "psci"; 126 clocks = <&cru ARMCLKL>; 127 operating-points-v2 = <&cluster0_opp>; 128 }; 129 130 cpu_l2: cpu@2 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a53", "arm,armv8"; 133 reg = <0x0 0x2>; 134 enable-method = "psci"; 135 clocks = <&cru ARMCLKL>; 136 operating-points-v2 = <&cluster0_opp>; 137 }; 138 139 cpu_l3: cpu@3 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-a53", "arm,armv8"; 142 reg = <0x0 0x3>; 143 enable-method = "psci"; 144 clocks = <&cru ARMCLKL>; 145 operating-points-v2 = <&cluster0_opp>; 146 }; 147 148 cpu_b0: cpu@100 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a53", "arm,armv8"; 151 reg = <0x0 0x100>; 152 enable-method = "psci"; 153 clocks = <&cru ARMCLKB>; 154 operating-points-v2 = <&cluster1_opp>; 155 #cooling-cells = <2>; /* min followed by max */ 156 }; 157 158 cpu_b1: cpu@101 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a53", "arm,armv8"; 161 reg = <0x0 0x101>; 162 enable-method = "psci"; 163 clocks = <&cru ARMCLKB>; 164 operating-points-v2 = <&cluster1_opp>; 165 }; 166 167 cpu_b2: cpu@102 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a53", "arm,armv8"; 170 reg = <0x0 0x102>; 171 enable-method = "psci"; 172 clocks = <&cru ARMCLKB>; 173 operating-points-v2 = <&cluster1_opp>; 174 }; 175 176 cpu_b3: cpu@103 { 177 device_type = "cpu"; 178 compatible = "arm,cortex-a53", "arm,armv8"; 179 reg = <0x0 0x103>; 180 enable-method = "psci"; 181 clocks = <&cru ARMCLKB>; 182 operating-points-v2 = <&cluster1_opp>; 183 }; 184 }; 185 186 cluster0_opp: opp-table0 { 187 compatible = "operating-points-v2"; 188 opp-shared; 189 190 opp00 { 191 opp-hz = /bits/ 64 <312000000>; 192 opp-microvolt = <950000>; 193 clock-latency-ns = <40000>; 194 }; 195 opp01 { 196 opp-hz = /bits/ 64 <408000000>; 197 opp-microvolt = <950000>; 198 }; 199 opp02 { 200 opp-hz = /bits/ 64 <600000000>; 201 opp-microvolt = <950000>; 202 }; 203 opp03 { 204 opp-hz = /bits/ 64 <816000000>; 205 opp-microvolt = <1025000>; 206 }; 207 opp04 { 208 opp-hz = /bits/ 64 <1008000000>; 209 opp-microvolt = <1125000>; 210 }; 211 }; 212 213 cluster1_opp: opp-table1 { 214 compatible = "operating-points-v2"; 215 opp-shared; 216 217 opp00 { 218 opp-hz = /bits/ 64 <312000000>; 219 opp-microvolt = <950000>; 220 clock-latency-ns = <40000>; 221 }; 222 opp01 { 223 opp-hz = /bits/ 64 <408000000>; 224 opp-microvolt = <950000>; 225 }; 226 opp02 { 227 opp-hz = /bits/ 64 <600000000>; 228 opp-microvolt = <950000>; 229 }; 230 opp03 { 231 opp-hz = /bits/ 64 <816000000>; 232 opp-microvolt = <975000>; 233 }; 234 opp04 { 235 opp-hz = /bits/ 64 <1008000000>; 236 opp-microvolt = <1050000>; 237 }; 238 }; 239 240 amba { 241 compatible = "simple-bus"; 242 #address-cells = <2>; 243 #size-cells = <2>; 244 ranges; 245 246 dmac_peri: dma-controller@ff250000 { 247 compatible = "arm,pl330", "arm,primecell"; 248 reg = <0x0 0xff250000 0x0 0x4000>; 249 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 251 #dma-cells = <1>; 252 arm,pl330-broken-no-flushp; 253 clocks = <&cru ACLK_DMAC_PERI>; 254 clock-names = "apb_pclk"; 255 }; 256 257 dmac_bus: dma-controller@ff600000 { 258 compatible = "arm,pl330", "arm,primecell"; 259 reg = <0x0 0xff600000 0x0 0x4000>; 260 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 262 #dma-cells = <1>; 263 arm,pl330-broken-no-flushp; 264 clocks = <&cru ACLK_DMAC_BUS>; 265 clock-names = "apb_pclk"; 266 }; 267 }; 268 269 arm-pmu { 270 compatible = "arm,armv8-pmuv3"; 271 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 279 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, 280 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, 281 <&cpu_b2>, <&cpu_b3>; 282 }; 283 284 psci { 285 compatible = "arm,psci-0.2"; 286 method = "smc"; 287 }; 288 289 timer { 290 compatible = "arm,armv8-timer"; 291 interrupts = <GIC_PPI 13 292 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 293 <GIC_PPI 14 294 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 295 <GIC_PPI 11 296 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 297 <GIC_PPI 10 298 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 299 }; 300 301 xin24m: oscillator { 302 compatible = "fixed-clock"; 303 clock-frequency = <24000000>; 304 clock-output-names = "xin24m"; 305 #clock-cells = <0>; 306 }; 307 308 sdmmc: dwmmc@ff0c0000 { 309 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 310 reg = <0x0 0xff0c0000 0x0 0x4000>; 311 max-frequency = <150000000>; 312 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 313 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 314 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 315 fifo-depth = <0x100>; 316 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 317 resets = <&cru SRST_MMC0>; 318 reset-names = "reset"; 319 status = "disabled"; 320 }; 321 322 sdio0: dwmmc@ff0d0000 { 323 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 324 reg = <0x0 0xff0d0000 0x0 0x4000>; 325 max-frequency = <150000000>; 326 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 327 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 328 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; 329 fifo-depth = <0x100>; 330 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 331 resets = <&cru SRST_SDIO0>; 332 reset-names = "reset"; 333 status = "disabled"; 334 }; 335 336 emmc: dwmmc@ff0f0000 { 337 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 338 reg = <0x0 0xff0f0000 0x0 0x4000>; 339 max-frequency = <150000000>; 340 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 341 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 342 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 343 fifo-depth = <0x100>; 344 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 345 resets = <&cru SRST_EMMC>; 346 reset-names = "reset"; 347 status = "disabled"; 348 }; 349 350 saradc: saradc@ff100000 { 351 compatible = "rockchip,saradc"; 352 reg = <0x0 0xff100000 0x0 0x100>; 353 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 354 #io-channel-cells = <1>; 355 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 356 clock-names = "saradc", "apb_pclk"; 357 resets = <&cru SRST_SARADC>; 358 reset-names = "saradc-apb"; 359 status = "disabled"; 360 }; 361 362 spi0: spi@ff110000 { 363 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 364 reg = <0x0 0xff110000 0x0 0x1000>; 365 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 366 clock-names = "spiclk", "apb_pclk"; 367 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 status = "disabled"; 373 }; 374 375 spi1: spi@ff120000 { 376 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 377 reg = <0x0 0xff120000 0x0 0x1000>; 378 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 379 clock-names = "spiclk", "apb_pclk"; 380 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 381 pinctrl-names = "default"; 382 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 status = "disabled"; 386 }; 387 388 spi2: spi@ff130000 { 389 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 390 reg = <0x0 0xff130000 0x0 0x1000>; 391 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 392 clock-names = "spiclk", "apb_pclk"; 393 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 status = "disabled"; 399 }; 400 401 i2c2: i2c@ff140000 { 402 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 403 reg = <0x0 0xff140000 0x0 0x1000>; 404 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 clock-names = "i2c"; 408 clocks = <&cru PCLK_I2C2>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&i2c2_xfer>; 411 status = "disabled"; 412 }; 413 414 i2c3: i2c@ff150000 { 415 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 416 reg = <0x0 0xff150000 0x0 0x1000>; 417 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 clock-names = "i2c"; 421 clocks = <&cru PCLK_I2C3>; 422 pinctrl-names = "default"; 423 pinctrl-0 = <&i2c3_xfer>; 424 status = "disabled"; 425 }; 426 427 i2c4: i2c@ff160000 { 428 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 429 reg = <0x0 0xff160000 0x0 0x1000>; 430 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 clock-names = "i2c"; 434 clocks = <&cru PCLK_I2C4>; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&i2c4_xfer>; 437 status = "disabled"; 438 }; 439 440 i2c5: i2c@ff170000 { 441 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 442 reg = <0x0 0xff170000 0x0 0x1000>; 443 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 clock-names = "i2c"; 447 clocks = <&cru PCLK_I2C5>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&i2c5_xfer>; 450 status = "disabled"; 451 }; 452 453 uart0: serial@ff180000 { 454 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 455 reg = <0x0 0xff180000 0x0 0x100>; 456 clock-frequency = <24000000>; 457 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 458 clock-names = "baudclk", "apb_pclk"; 459 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 460 reg-shift = <2>; 461 reg-io-width = <4>; 462 status = "disabled"; 463 }; 464 465 uart1: serial@ff190000 { 466 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 467 reg = <0x0 0xff190000 0x0 0x100>; 468 clock-frequency = <24000000>; 469 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 470 clock-names = "baudclk", "apb_pclk"; 471 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 472 reg-shift = <2>; 473 reg-io-width = <4>; 474 status = "disabled"; 475 }; 476 477 uart3: serial@ff1b0000 { 478 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 479 reg = <0x0 0xff1b0000 0x0 0x100>; 480 clock-frequency = <24000000>; 481 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 482 clock-names = "baudclk", "apb_pclk"; 483 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 484 reg-shift = <2>; 485 reg-io-width = <4>; 486 status = "disabled"; 487 }; 488 489 uart4: serial@ff1c0000 { 490 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 491 reg = <0x0 0xff1c0000 0x0 0x100>; 492 clock-frequency = <24000000>; 493 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 494 clock-names = "baudclk", "apb_pclk"; 495 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 496 reg-shift = <2>; 497 reg-io-width = <4>; 498 status = "disabled"; 499 }; 500 501 thermal-zones { 502 cpu { 503 polling-delay-passive = <100>; /* milliseconds */ 504 polling-delay = <5000>; /* milliseconds */ 505 506 thermal-sensors = <&tsadc 0>; 507 508 trips { 509 cpu_alert0: cpu_alert0 { 510 temperature = <75000>; /* millicelsius */ 511 hysteresis = <2000>; /* millicelsius */ 512 type = "passive"; 513 }; 514 cpu_alert1: cpu_alert1 { 515 temperature = <80000>; /* millicelsius */ 516 hysteresis = <2000>; /* millicelsius */ 517 type = "passive"; 518 }; 519 cpu_crit: cpu_crit { 520 temperature = <95000>; /* millicelsius */ 521 hysteresis = <2000>; /* millicelsius */ 522 type = "critical"; 523 }; 524 }; 525 526 cooling-maps { 527 map0 { 528 trip = <&cpu_alert0>; 529 cooling-device = 530 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 531 }; 532 map1 { 533 trip = <&cpu_alert1>; 534 cooling-device = 535 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 536 }; 537 }; 538 }; 539 540 gpu { 541 polling-delay-passive = <100>; /* milliseconds */ 542 polling-delay = <5000>; /* milliseconds */ 543 544 thermal-sensors = <&tsadc 1>; 545 546 trips { 547 gpu_alert0: gpu_alert0 { 548 temperature = <80000>; /* millicelsius */ 549 hysteresis = <2000>; /* millicelsius */ 550 type = "passive"; 551 }; 552 gpu_crit: gpu_crit { 553 temperature = <115000>; /* millicelsius */ 554 hysteresis = <2000>; /* millicelsius */ 555 type = "critical"; 556 }; 557 }; 558 559 cooling-maps { 560 map0 { 561 trip = <&gpu_alert0>; 562 cooling-device = 563 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 564 }; 565 }; 566 }; 567 }; 568 569 tsadc: tsadc@ff280000 { 570 compatible = "rockchip,rk3368-tsadc"; 571 reg = <0x0 0xff280000 0x0 0x100>; 572 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 574 clock-names = "tsadc", "apb_pclk"; 575 resets = <&cru SRST_TSADC>; 576 reset-names = "tsadc-apb"; 577 pinctrl-names = "init", "default", "sleep"; 578 pinctrl-0 = <&otp_gpio>; 579 pinctrl-1 = <&otp_out>; 580 pinctrl-2 = <&otp_gpio>; 581 #thermal-sensor-cells = <1>; 582 rockchip,hw-tshut-temp = <95000>; 583 status = "disabled"; 584 }; 585 586 gmac: ethernet@ff290000 { 587 compatible = "rockchip,rk3368-gmac"; 588 reg = <0x0 0xff290000 0x0 0x10000>; 589 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 590 interrupt-names = "macirq"; 591 rockchip,grf = <&grf>; 592 clocks = <&cru SCLK_MAC>, 593 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 594 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 595 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 596 clock-names = "stmmaceth", 597 "mac_clk_rx", "mac_clk_tx", 598 "clk_mac_ref", "clk_mac_refout", 599 "aclk_mac", "pclk_mac"; 600 status = "disabled"; 601 }; 602 603 usb_host0_ehci: usb@ff500000 { 604 compatible = "generic-ehci"; 605 reg = <0x0 0xff500000 0x0 0x100>; 606 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&cru HCLK_HOST0>; 608 clock-names = "usbhost"; 609 status = "disabled"; 610 }; 611 612 usb_otg: usb@ff580000 { 613 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", 614 "snps,dwc2"; 615 reg = <0x0 0xff580000 0x0 0x40000>; 616 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&cru HCLK_OTG0>; 618 clock-names = "otg"; 619 dr_mode = "otg"; 620 g-np-tx-fifo-size = <16>; 621 g-rx-fifo-size = <275>; 622 g-tx-fifo-size = <256 128 128 64 64 32>; 623 status = "disabled"; 624 }; 625 626 i2c0: i2c@ff650000 { 627 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 628 reg = <0x0 0xff650000 0x0 0x1000>; 629 clocks = <&cru PCLK_I2C0>; 630 clock-names = "i2c"; 631 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&i2c0_xfer>; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 status = "disabled"; 637 }; 638 639 i2c1: i2c@ff660000 { 640 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 641 reg = <0x0 0xff660000 0x0 0x1000>; 642 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 clock-names = "i2c"; 646 clocks = <&cru PCLK_I2C1>; 647 pinctrl-names = "default"; 648 pinctrl-0 = <&i2c1_xfer>; 649 status = "disabled"; 650 }; 651 652 pwm0: pwm@ff680000 { 653 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 654 reg = <0x0 0xff680000 0x0 0x10>; 655 #pwm-cells = <3>; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&pwm0_pin>; 658 clocks = <&cru PCLK_PWM1>; 659 clock-names = "pwm"; 660 status = "disabled"; 661 }; 662 663 pwm1: pwm@ff680010 { 664 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 665 reg = <0x0 0xff680010 0x0 0x10>; 666 #pwm-cells = <3>; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pwm1_pin>; 669 clocks = <&cru PCLK_PWM1>; 670 clock-names = "pwm"; 671 status = "disabled"; 672 }; 673 674 pwm2: pwm@ff680020 { 675 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 676 reg = <0x0 0xff680020 0x0 0x10>; 677 #pwm-cells = <3>; 678 clocks = <&cru PCLK_PWM1>; 679 clock-names = "pwm"; 680 status = "disabled"; 681 }; 682 683 pwm3: pwm@ff680030 { 684 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 685 reg = <0x0 0xff680030 0x0 0x10>; 686 #pwm-cells = <3>; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&pwm3_pin>; 689 clocks = <&cru PCLK_PWM1>; 690 clock-names = "pwm"; 691 status = "disabled"; 692 }; 693 694 uart2: serial@ff690000 { 695 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 696 reg = <0x0 0xff690000 0x0 0x100>; 697 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 698 clock-names = "baudclk", "apb_pclk"; 699 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&uart2_xfer>; 702 reg-shift = <2>; 703 reg-io-width = <4>; 704 status = "disabled"; 705 }; 706 707 mbox: mbox@ff6b0000 { 708 compatible = "rockchip,rk3368-mailbox"; 709 reg = <0x0 0xff6b0000 0x0 0x1000>; 710 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&cru PCLK_MAILBOX>; 715 clock-names = "pclk_mailbox"; 716 #mbox-cells = <1>; 717 status = "disabled"; 718 }; 719 720 pmugrf: syscon@ff738000 { 721 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; 722 reg = <0x0 0xff738000 0x0 0x1000>; 723 724 pmu_io_domains: io-domains { 725 compatible = "rockchip,rk3368-pmu-io-voltage-domain"; 726 status = "disabled"; 727 }; 728 729 reboot-mode { 730 compatible = "syscon-reboot-mode"; 731 offset = <0x200>; 732 mode-normal = <BOOT_NORMAL>; 733 mode-recovery = <BOOT_RECOVERY>; 734 mode-bootloader = <BOOT_FASTBOOT>; 735 mode-loader = <BOOT_BL_DOWNLOAD>; 736 }; 737 }; 738 739 cru: clock-controller@ff760000 { 740 compatible = "rockchip,rk3368-cru"; 741 reg = <0x0 0xff760000 0x0 0x1000>; 742 rockchip,grf = <&grf>; 743 #clock-cells = <1>; 744 #reset-cells = <1>; 745 }; 746 747 grf: syscon@ff770000 { 748 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; 749 reg = <0x0 0xff770000 0x0 0x1000>; 750 751 io_domains: io-domains { 752 compatible = "rockchip,rk3368-io-voltage-domain"; 753 status = "disabled"; 754 }; 755 }; 756 757 wdt: watchdog@ff800000 { 758 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; 759 reg = <0x0 0xff800000 0x0 0x100>; 760 clocks = <&cru PCLK_WDT>; 761 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 762 status = "disabled"; 763 }; 764 765 timer@ff810000 { 766 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; 767 reg = <0x0 0xff810000 0x0 0x20>; 768 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 769 }; 770 771 spdif: spdif@ff880000 { 772 compatible = "rockchip,rk3368-spdif"; 773 reg = <0x0 0xff880000 0x0 0x1000>; 774 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 776 clock-names = "mclk", "hclk"; 777 dmas = <&dmac_bus 3>; 778 dma-names = "tx"; 779 pinctrl-names = "default"; 780 pinctrl-0 = <&spdif_tx>; 781 status = "disabled"; 782 }; 783 784 i2s_2ch: i2s-2ch@ff890000 { 785 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; 786 reg = <0x0 0xff890000 0x0 0x1000>; 787 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 788 clock-names = "i2s_clk", "i2s_hclk"; 789 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; 790 dmas = <&dmac_bus 6>, <&dmac_bus 7>; 791 dma-names = "tx", "rx"; 792 status = "disabled"; 793 }; 794 795 i2s_8ch: i2s-8ch@ff898000 { 796 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; 797 reg = <0x0 0xff898000 0x0 0x1000>; 798 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 799 clock-names = "i2s_clk", "i2s_hclk"; 800 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; 801 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 802 dma-names = "tx", "rx"; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&i2s_8ch_bus>; 805 status = "disabled"; 806 }; 807 808 iep_mmu: iommu@ff900800 { 809 compatible = "rockchip,iommu"; 810 reg = <0x0 0xff900800 0x0 0x100>; 811 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 812 interrupt-names = "iep_mmu"; 813 #iommu-cells = <0>; 814 status = "disabled"; 815 }; 816 817 isp_mmu: iommu@ff914000 { 818 compatible = "rockchip,iommu"; 819 reg = <0x0 0xff914000 0x0 0x100>, 820 <0x0 0xff915000 0x0 0x100>; 821 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 822 interrupt-names = "isp_mmu"; 823 #iommu-cells = <0>; 824 rockchip,disable-mmu-reset; 825 status = "disabled"; 826 }; 827 828 vop_mmu: iommu@ff930300 { 829 compatible = "rockchip,iommu"; 830 reg = <0x0 0xff930300 0x0 0x100>; 831 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 832 interrupt-names = "vop_mmu"; 833 #iommu-cells = <0>; 834 status = "disabled"; 835 }; 836 837 hevc_mmu: iommu@ff9a0440 { 838 compatible = "rockchip,iommu"; 839 reg = <0x0 0xff9a0440 0x0 0x40>, 840 <0x0 0xff9a0480 0x0 0x40>; 841 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 842 interrupt-names = "hevc_mmu"; 843 #iommu-cells = <0>; 844 status = "disabled"; 845 }; 846 847 vpu_mmu: iommu@ff9a0800 { 848 compatible = "rockchip,iommu"; 849 reg = <0x0 0xff9a0800 0x0 0x100>; 850 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 852 interrupt-names = "vepu_mmu", "vdpu_mmu"; 853 #iommu-cells = <0>; 854 status = "disabled"; 855 }; 856 857 gic: interrupt-controller@ffb71000 { 858 compatible = "arm,gic-400"; 859 interrupt-controller; 860 #interrupt-cells = <3>; 861 #address-cells = <0>; 862 863 reg = <0x0 0xffb71000 0x0 0x1000>, 864 <0x0 0xffb72000 0x0 0x2000>, 865 <0x0 0xffb74000 0x0 0x2000>, 866 <0x0 0xffb76000 0x0 0x2000>; 867 interrupts = <GIC_PPI 9 868 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 869 }; 870 871 pinctrl: pinctrl { 872 compatible = "rockchip,rk3368-pinctrl"; 873 rockchip,grf = <&grf>; 874 rockchip,pmu = <&pmugrf>; 875 #address-cells = <0x2>; 876 #size-cells = <0x2>; 877 ranges; 878 879 gpio0: gpio0@ff750000 { 880 compatible = "rockchip,gpio-bank"; 881 reg = <0x0 0xff750000 0x0 0x100>; 882 clocks = <&cru PCLK_GPIO0>; 883 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; 884 885 gpio-controller; 886 #gpio-cells = <0x2>; 887 888 interrupt-controller; 889 #interrupt-cells = <0x2>; 890 }; 891 892 gpio1: gpio1@ff780000 { 893 compatible = "rockchip,gpio-bank"; 894 reg = <0x0 0xff780000 0x0 0x100>; 895 clocks = <&cru PCLK_GPIO1>; 896 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; 897 898 gpio-controller; 899 #gpio-cells = <0x2>; 900 901 interrupt-controller; 902 #interrupt-cells = <0x2>; 903 }; 904 905 gpio2: gpio2@ff790000 { 906 compatible = "rockchip,gpio-bank"; 907 reg = <0x0 0xff790000 0x0 0x100>; 908 clocks = <&cru PCLK_GPIO2>; 909 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; 910 911 gpio-controller; 912 #gpio-cells = <0x2>; 913 914 interrupt-controller; 915 #interrupt-cells = <0x2>; 916 }; 917 918 gpio3: gpio3@ff7a0000 { 919 compatible = "rockchip,gpio-bank"; 920 reg = <0x0 0xff7a0000 0x0 0x100>; 921 clocks = <&cru PCLK_GPIO3>; 922 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; 923 924 gpio-controller; 925 #gpio-cells = <0x2>; 926 927 interrupt-controller; 928 #interrupt-cells = <0x2>; 929 }; 930 931 pcfg_pull_up: pcfg-pull-up { 932 bias-pull-up; 933 }; 934 935 pcfg_pull_down: pcfg-pull-down { 936 bias-pull-down; 937 }; 938 939 pcfg_pull_none: pcfg-pull-none { 940 bias-disable; 941 }; 942 943 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 944 bias-disable; 945 drive-strength = <12>; 946 }; 947 948 emmc { 949 emmc_clk: emmc-clk { 950 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 951 }; 952 953 emmc_cmd: emmc-cmd { 954 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>; 955 }; 956 957 emmc_pwr: emmc-pwr { 958 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>; 959 }; 960 961 emmc_bus1: emmc-bus1 { 962 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>; 963 }; 964 965 emmc_bus4: emmc-bus4 { 966 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 967 <1 19 RK_FUNC_2 &pcfg_pull_up>, 968 <1 20 RK_FUNC_2 &pcfg_pull_up>, 969 <1 21 RK_FUNC_2 &pcfg_pull_up>; 970 }; 971 972 emmc_bus8: emmc-bus8 { 973 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 974 <1 19 RK_FUNC_2 &pcfg_pull_up>, 975 <1 20 RK_FUNC_2 &pcfg_pull_up>, 976 <1 21 RK_FUNC_2 &pcfg_pull_up>, 977 <1 22 RK_FUNC_2 &pcfg_pull_up>, 978 <1 23 RK_FUNC_2 &pcfg_pull_up>, 979 <1 24 RK_FUNC_2 &pcfg_pull_up>, 980 <1 25 RK_FUNC_2 &pcfg_pull_up>; 981 }; 982 }; 983 984 gmac { 985 rgmii_pins: rgmii-pins { 986 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 987 <3 24 RK_FUNC_1 &pcfg_pull_none>, 988 <3 19 RK_FUNC_1 &pcfg_pull_none>, 989 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 990 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 991 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>, 992 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>, 993 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>, 994 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 995 <3 15 RK_FUNC_1 &pcfg_pull_none>, 996 <3 16 RK_FUNC_1 &pcfg_pull_none>, 997 <3 17 RK_FUNC_1 &pcfg_pull_none>, 998 <3 18 RK_FUNC_1 &pcfg_pull_none>, 999 <3 25 RK_FUNC_1 &pcfg_pull_none>, 1000 <3 20 RK_FUNC_1 &pcfg_pull_none>; 1001 }; 1002 1003 rmii_pins: rmii-pins { 1004 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 1005 <3 24 RK_FUNC_1 &pcfg_pull_none>, 1006 <3 19 RK_FUNC_1 &pcfg_pull_none>, 1007 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 1008 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 1009 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 1010 <3 15 RK_FUNC_1 &pcfg_pull_none>, 1011 <3 16 RK_FUNC_1 &pcfg_pull_none>, 1012 <3 20 RK_FUNC_1 &pcfg_pull_none>, 1013 <3 21 RK_FUNC_1 &pcfg_pull_none>; 1014 }; 1015 }; 1016 1017 i2c0 { 1018 i2c0_xfer: i2c0-xfer { 1019 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 1020 <0 7 RK_FUNC_1 &pcfg_pull_none>; 1021 }; 1022 }; 1023 1024 i2c1 { 1025 i2c1_xfer: i2c1-xfer { 1026 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>, 1027 <2 22 RK_FUNC_1 &pcfg_pull_none>; 1028 }; 1029 }; 1030 1031 i2c2 { 1032 i2c2_xfer: i2c2-xfer { 1033 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>, 1034 <3 31 RK_FUNC_2 &pcfg_pull_none>; 1035 }; 1036 }; 1037 1038 i2c3 { 1039 i2c3_xfer: i2c3-xfer { 1040 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>, 1041 <1 17 RK_FUNC_1 &pcfg_pull_none>; 1042 }; 1043 }; 1044 1045 i2c4 { 1046 i2c4_xfer: i2c4-xfer { 1047 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>, 1048 <3 25 RK_FUNC_2 &pcfg_pull_none>; 1049 }; 1050 }; 1051 1052 i2c5 { 1053 i2c5_xfer: i2c5-xfer { 1054 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>, 1055 <3 27 RK_FUNC_2 &pcfg_pull_none>; 1056 }; 1057 }; 1058 1059 i2s { 1060 i2s_8ch_bus: i2s-8ch-bus { 1061 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>, 1062 <2 13 RK_FUNC_1 &pcfg_pull_none>, 1063 <2 14 RK_FUNC_1 &pcfg_pull_none>, 1064 <2 15 RK_FUNC_1 &pcfg_pull_none>, 1065 <2 16 RK_FUNC_1 &pcfg_pull_none>, 1066 <2 17 RK_FUNC_1 &pcfg_pull_none>, 1067 <2 18 RK_FUNC_1 &pcfg_pull_none>, 1068 <2 19 RK_FUNC_1 &pcfg_pull_none>, 1069 <2 20 RK_FUNC_1 &pcfg_pull_none>; 1070 }; 1071 }; 1072 1073 pwm0 { 1074 pwm0_pin: pwm0-pin { 1075 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; 1076 }; 1077 }; 1078 1079 pwm1 { 1080 pwm1_pin: pwm1-pin { 1081 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; 1082 }; 1083 }; 1084 1085 pwm3 { 1086 pwm3_pin: pwm3-pin { 1087 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; 1088 }; 1089 }; 1090 1091 sdio0 { 1092 sdio0_bus1: sdio0-bus1 { 1093 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; 1094 }; 1095 1096 sdio0_bus4: sdio0-bus4 { 1097 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>, 1098 <2 29 RK_FUNC_1 &pcfg_pull_up>, 1099 <2 30 RK_FUNC_1 &pcfg_pull_up>, 1100 <2 31 RK_FUNC_1 &pcfg_pull_up>; 1101 }; 1102 1103 sdio0_cmd: sdio0-cmd { 1104 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>; 1105 }; 1106 1107 sdio0_clk: sdio0-clk { 1108 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>; 1109 }; 1110 1111 sdio0_cd: sdio0-cd { 1112 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>; 1113 }; 1114 1115 sdio0_wp: sdio0-wp { 1116 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>; 1117 }; 1118 1119 sdio0_pwr: sdio0-pwr { 1120 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>; 1121 }; 1122 1123 sdio0_bkpwr: sdio0-bkpwr { 1124 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>; 1125 }; 1126 1127 sdio0_int: sdio0-int { 1128 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>; 1129 }; 1130 }; 1131 1132 sdmmc { 1133 sdmmc_clk: sdmmc-clk { 1134 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>; 1135 }; 1136 1137 sdmmc_cmd: sdmmc-cmd { 1138 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; 1139 }; 1140 1141 sdmmc_cd: sdmmc-cd { 1142 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; 1143 }; 1144 1145 sdmmc_bus1: sdmmc-bus1 { 1146 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>; 1147 }; 1148 1149 sdmmc_bus4: sdmmc-bus4 { 1150 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>, 1151 <2 6 RK_FUNC_1 &pcfg_pull_up>, 1152 <2 7 RK_FUNC_1 &pcfg_pull_up>, 1153 <2 8 RK_FUNC_1 &pcfg_pull_up>; 1154 }; 1155 }; 1156 1157 spdif { 1158 spdif_tx: spdif-tx { 1159 rockchip,pins = <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 1160 }; 1161 }; 1162 1163 spi0 { 1164 spi0_clk: spi0-clk { 1165 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>; 1166 }; 1167 spi0_cs0: spi0-cs0 { 1168 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>; 1169 }; 1170 spi0_cs1: spi0-cs1 { 1171 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>; 1172 }; 1173 spi0_tx: spi0-tx { 1174 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>; 1175 }; 1176 spi0_rx: spi0-rx { 1177 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>; 1178 }; 1179 }; 1180 1181 spi1 { 1182 spi1_clk: spi1-clk { 1183 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>; 1184 }; 1185 spi1_cs0: spi1-cs0 { 1186 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>; 1187 }; 1188 spi1_cs1: spi1-cs1 { 1189 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>; 1190 }; 1191 spi1_rx: spi1-rx { 1192 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>; 1193 }; 1194 spi1_tx: spi1-tx { 1195 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>; 1196 }; 1197 }; 1198 1199 spi2 { 1200 spi2_clk: spi2-clk { 1201 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>; 1202 }; 1203 spi2_cs0: spi2-cs0 { 1204 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; 1205 }; 1206 spi2_rx: spi2-rx { 1207 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>; 1208 }; 1209 spi2_tx: spi2-tx { 1210 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; 1211 }; 1212 }; 1213 1214 tsadc { 1215 otp_gpio: otp-gpio { 1216 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; 1217 }; 1218 1219 otp_out: otp-out { 1220 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>; 1221 }; 1222 }; 1223 1224 uart0 { 1225 uart0_xfer: uart0-xfer { 1226 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>, 1227 <2 25 RK_FUNC_1 &pcfg_pull_none>; 1228 }; 1229 1230 uart0_cts: uart0-cts { 1231 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>; 1232 }; 1233 1234 uart0_rts: uart0-rts { 1235 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>; 1236 }; 1237 }; 1238 1239 uart1 { 1240 uart1_xfer: uart1-xfer { 1241 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>, 1242 <0 21 RK_FUNC_3 &pcfg_pull_none>; 1243 }; 1244 1245 uart1_cts: uart1-cts { 1246 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>; 1247 }; 1248 1249 uart1_rts: uart1-rts { 1250 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>; 1251 }; 1252 }; 1253 1254 uart2 { 1255 uart2_xfer: uart2-xfer { 1256 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>, 1257 <2 5 RK_FUNC_2 &pcfg_pull_none>; 1258 }; 1259 /* no rts / cts for uart2 */ 1260 }; 1261 1262 uart3 { 1263 uart3_xfer: uart3-xfer { 1264 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>, 1265 <3 30 RK_FUNC_3 &pcfg_pull_none>; 1266 }; 1267 1268 uart3_cts: uart3-cts { 1269 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>; 1270 }; 1271 1272 uart3_rts: uart3-rts { 1273 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>; 1274 }; 1275 }; 1276 1277 uart4 { 1278 uart4_xfer: uart4-xfer { 1279 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>, 1280 <0 26 RK_FUNC_3 &pcfg_pull_none>; 1281 }; 1282 1283 uart4_cts: uart4-cts { 1284 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>; 1285 }; 1286 1287 uart4_rts: uart4-rts { 1288 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>; 1289 }; 1290 }; 1291 }; 1292}; 1293