1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 cpu-idle-states = <&CPU_SLEEP>; 45 dynamic-power-coefficient = <120>; 46 enable-method = "psci"; 47 next-level-cache = <&l2>; 48 operating-points-v2 = <&cpu0_opp_table>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x0 0x1>; 55 clocks = <&cru ARMCLK>; 56 #cooling-cells = <2>; 57 cpu-idle-states = <&CPU_SLEEP>; 58 dynamic-power-coefficient = <120>; 59 enable-method = "psci"; 60 next-level-cache = <&l2>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0 0x2>; 68 clocks = <&cru ARMCLK>; 69 #cooling-cells = <2>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 dynamic-power-coefficient = <120>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 }; 76 77 cpu3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x0 0x3>; 81 clocks = <&cru ARMCLK>; 82 #cooling-cells = <2>; 83 cpu-idle-states = <&CPU_SLEEP>; 84 dynamic-power-coefficient = <120>; 85 enable-method = "psci"; 86 next-level-cache = <&l2>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 }; 102 103 l2: l2-cache0 { 104 compatible = "cache"; 105 cache-level = <2>; 106 }; 107 }; 108 109 cpu0_opp_table: opp-table-0 { 110 compatible = "operating-points-v2"; 111 opp-shared; 112 113 opp-408000000 { 114 opp-hz = /bits/ 64 <408000000>; 115 opp-microvolt = <950000>; 116 clock-latency-ns = <40000>; 117 opp-suspend; 118 }; 119 opp-600000000 { 120 opp-hz = /bits/ 64 <600000000>; 121 opp-microvolt = <950000>; 122 clock-latency-ns = <40000>; 123 }; 124 opp-816000000 { 125 opp-hz = /bits/ 64 <816000000>; 126 opp-microvolt = <1000000>; 127 clock-latency-ns = <40000>; 128 }; 129 opp-1008000000 { 130 opp-hz = /bits/ 64 <1008000000>; 131 opp-microvolt = <1100000>; 132 clock-latency-ns = <40000>; 133 }; 134 opp-1200000000 { 135 opp-hz = /bits/ 64 <1200000000>; 136 opp-microvolt = <1225000>; 137 clock-latency-ns = <40000>; 138 }; 139 opp-1296000000 { 140 opp-hz = /bits/ 64 <1296000000>; 141 opp-microvolt = <1300000>; 142 clock-latency-ns = <40000>; 143 }; 144 }; 145 146 analog_sound: analog-sound { 147 compatible = "simple-audio-card"; 148 simple-audio-card,format = "i2s"; 149 simple-audio-card,mclk-fs = <256>; 150 simple-audio-card,name = "Analog"; 151 status = "disabled"; 152 153 simple-audio-card,cpu { 154 sound-dai = <&i2s1>; 155 }; 156 157 simple-audio-card,codec { 158 sound-dai = <&codec>; 159 }; 160 }; 161 162 arm-pmu { 163 compatible = "arm,cortex-a53-pmu"; 164 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 168 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 169 }; 170 171 display_subsystem: display-subsystem { 172 compatible = "rockchip,display-subsystem"; 173 ports = <&vop_out>; 174 }; 175 176 hdmi_sound: hdmi-sound { 177 compatible = "simple-audio-card"; 178 simple-audio-card,format = "i2s"; 179 simple-audio-card,mclk-fs = <128>; 180 simple-audio-card,name = "HDMI"; 181 status = "disabled"; 182 183 simple-audio-card,cpu { 184 sound-dai = <&i2s0>; 185 }; 186 187 simple-audio-card,codec { 188 sound-dai = <&hdmi>; 189 }; 190 }; 191 192 psci { 193 compatible = "arm,psci-1.0", "arm,psci-0.2"; 194 method = "smc"; 195 }; 196 197 timer { 198 compatible = "arm,armv8-timer"; 199 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 200 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 201 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 202 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 203 }; 204 205 xin24m: xin24m { 206 compatible = "fixed-clock"; 207 #clock-cells = <0>; 208 clock-frequency = <24000000>; 209 clock-output-names = "xin24m"; 210 }; 211 212 i2s0: i2s@ff000000 { 213 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 214 reg = <0x0 0xff000000 0x0 0x1000>; 215 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 217 clock-names = "i2s_clk", "i2s_hclk"; 218 dmas = <&dmac 11>, <&dmac 12>; 219 dma-names = "tx", "rx"; 220 #sound-dai-cells = <0>; 221 status = "disabled"; 222 }; 223 224 i2s1: i2s@ff010000 { 225 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 226 reg = <0x0 0xff010000 0x0 0x1000>; 227 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 229 clock-names = "i2s_clk", "i2s_hclk"; 230 dmas = <&dmac 14>, <&dmac 15>; 231 dma-names = "tx", "rx"; 232 #sound-dai-cells = <0>; 233 status = "disabled"; 234 }; 235 236 i2s2: i2s@ff020000 { 237 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 238 reg = <0x0 0xff020000 0x0 0x1000>; 239 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 241 clock-names = "i2s_clk", "i2s_hclk"; 242 dmas = <&dmac 0>, <&dmac 1>; 243 dma-names = "tx", "rx"; 244 #sound-dai-cells = <0>; 245 status = "disabled"; 246 }; 247 248 spdif: spdif@ff030000 { 249 compatible = "rockchip,rk3328-spdif"; 250 reg = <0x0 0xff030000 0x0 0x1000>; 251 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 253 clock-names = "mclk", "hclk"; 254 dmas = <&dmac 10>; 255 dma-names = "tx"; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&spdifm2_tx>; 258 #sound-dai-cells = <0>; 259 status = "disabled"; 260 }; 261 262 pdm: pdm@ff040000 { 263 compatible = "rockchip,pdm"; 264 reg = <0x0 0xff040000 0x0 0x1000>; 265 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 266 clock-names = "pdm_clk", "pdm_hclk"; 267 dmas = <&dmac 16>; 268 dma-names = "rx"; 269 pinctrl-names = "default", "sleep"; 270 pinctrl-0 = <&pdmm0_clk 271 &pdmm0_sdi0 272 &pdmm0_sdi1 273 &pdmm0_sdi2 274 &pdmm0_sdi3>; 275 pinctrl-1 = <&pdmm0_clk_sleep 276 &pdmm0_sdi0_sleep 277 &pdmm0_sdi1_sleep 278 &pdmm0_sdi2_sleep 279 &pdmm0_sdi3_sleep>; 280 status = "disabled"; 281 }; 282 283 grf: syscon@ff100000 { 284 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 285 reg = <0x0 0xff100000 0x0 0x1000>; 286 287 io_domains: io-domains { 288 compatible = "rockchip,rk3328-io-voltage-domain"; 289 status = "disabled"; 290 }; 291 292 grf_gpio: gpio { 293 compatible = "rockchip,rk3328-grf-gpio"; 294 gpio-controller; 295 #gpio-cells = <2>; 296 }; 297 298 power: power-controller { 299 compatible = "rockchip,rk3328-power-controller"; 300 #power-domain-cells = <1>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 304 power-domain@RK3328_PD_HEVC { 305 reg = <RK3328_PD_HEVC>; 306 #power-domain-cells = <0>; 307 }; 308 power-domain@RK3328_PD_VIDEO { 309 reg = <RK3328_PD_VIDEO>; 310 clocks = <&cru ACLK_RKVDEC>, 311 <&cru HCLK_RKVDEC>, 312 <&cru SCLK_VDEC_CABAC>, 313 <&cru SCLK_VDEC_CORE>; 314 #power-domain-cells = <0>; 315 }; 316 power-domain@RK3328_PD_VPU { 317 reg = <RK3328_PD_VPU>; 318 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 319 #power-domain-cells = <0>; 320 }; 321 }; 322 323 reboot-mode { 324 compatible = "syscon-reboot-mode"; 325 offset = <0x5c8>; 326 mode-normal = <BOOT_NORMAL>; 327 mode-recovery = <BOOT_RECOVERY>; 328 mode-bootloader = <BOOT_FASTBOOT>; 329 mode-loader = <BOOT_BL_DOWNLOAD>; 330 }; 331 }; 332 333 uart0: serial@ff110000 { 334 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 335 reg = <0x0 0xff110000 0x0 0x100>; 336 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 338 clock-names = "baudclk", "apb_pclk"; 339 dmas = <&dmac 2>, <&dmac 3>; 340 dma-names = "tx", "rx"; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 343 reg-io-width = <4>; 344 reg-shift = <2>; 345 status = "disabled"; 346 }; 347 348 uart1: serial@ff120000 { 349 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 350 reg = <0x0 0xff120000 0x0 0x100>; 351 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 353 clock-names = "baudclk", "apb_pclk"; 354 dmas = <&dmac 4>, <&dmac 5>; 355 dma-names = "tx", "rx"; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 358 reg-io-width = <4>; 359 reg-shift = <2>; 360 status = "disabled"; 361 }; 362 363 uart2: serial@ff130000 { 364 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 365 reg = <0x0 0xff130000 0x0 0x100>; 366 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 368 clock-names = "baudclk", "apb_pclk"; 369 dmas = <&dmac 6>, <&dmac 7>; 370 dma-names = "tx", "rx"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&uart2m1_xfer>; 373 reg-io-width = <4>; 374 reg-shift = <2>; 375 status = "disabled"; 376 }; 377 378 i2c0: i2c@ff150000 { 379 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 380 reg = <0x0 0xff150000 0x0 0x1000>; 381 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 385 clock-names = "i2c", "pclk"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&i2c0_xfer>; 388 status = "disabled"; 389 }; 390 391 i2c1: i2c@ff160000 { 392 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 393 reg = <0x0 0xff160000 0x0 0x1000>; 394 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 398 clock-names = "i2c", "pclk"; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&i2c1_xfer>; 401 status = "disabled"; 402 }; 403 404 i2c2: i2c@ff170000 { 405 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 406 reg = <0x0 0xff170000 0x0 0x1000>; 407 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 411 clock-names = "i2c", "pclk"; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&i2c2_xfer>; 414 status = "disabled"; 415 }; 416 417 i2c3: i2c@ff180000 { 418 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 419 reg = <0x0 0xff180000 0x0 0x1000>; 420 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 424 clock-names = "i2c", "pclk"; 425 pinctrl-names = "default"; 426 pinctrl-0 = <&i2c3_xfer>; 427 status = "disabled"; 428 }; 429 430 spi0: spi@ff190000 { 431 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 432 reg = <0x0 0xff190000 0x0 0x1000>; 433 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 437 clock-names = "spiclk", "apb_pclk"; 438 dmas = <&dmac 8>, <&dmac 9>; 439 dma-names = "tx", "rx"; 440 pinctrl-names = "default"; 441 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 442 status = "disabled"; 443 }; 444 445 wdt: watchdog@ff1a0000 { 446 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 447 reg = <0x0 0xff1a0000 0x0 0x100>; 448 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cru PCLK_WDT>; 450 }; 451 452 pwm0: pwm@ff1b0000 { 453 compatible = "rockchip,rk3328-pwm"; 454 reg = <0x0 0xff1b0000 0x0 0x10>; 455 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 456 clock-names = "pwm", "pclk"; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&pwm0_pin>; 459 #pwm-cells = <3>; 460 status = "disabled"; 461 }; 462 463 pwm1: pwm@ff1b0010 { 464 compatible = "rockchip,rk3328-pwm"; 465 reg = <0x0 0xff1b0010 0x0 0x10>; 466 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 467 clock-names = "pwm", "pclk"; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pwm1_pin>; 470 #pwm-cells = <3>; 471 status = "disabled"; 472 }; 473 474 pwm2: pwm@ff1b0020 { 475 compatible = "rockchip,rk3328-pwm"; 476 reg = <0x0 0xff1b0020 0x0 0x10>; 477 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 478 clock-names = "pwm", "pclk"; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pwm2_pin>; 481 #pwm-cells = <3>; 482 status = "disabled"; 483 }; 484 485 pwm3: pwm@ff1b0030 { 486 compatible = "rockchip,rk3328-pwm"; 487 reg = <0x0 0xff1b0030 0x0 0x10>; 488 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 490 clock-names = "pwm", "pclk"; 491 pinctrl-names = "default"; 492 pinctrl-0 = <&pwmir_pin>; 493 #pwm-cells = <3>; 494 status = "disabled"; 495 }; 496 497 dmac: dma-controller@ff1f0000 { 498 compatible = "arm,pl330", "arm,primecell"; 499 reg = <0x0 0xff1f0000 0x0 0x4000>; 500 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 502 arm,pl330-periph-burst; 503 clocks = <&cru ACLK_DMAC>; 504 clock-names = "apb_pclk"; 505 #dma-cells = <1>; 506 }; 507 508 thermal-zones { 509 soc_thermal: soc-thermal { 510 polling-delay-passive = <20>; 511 polling-delay = <1000>; 512 sustainable-power = <1000>; 513 514 thermal-sensors = <&tsadc 0>; 515 516 trips { 517 threshold: trip-point0 { 518 temperature = <70000>; 519 hysteresis = <2000>; 520 type = "passive"; 521 }; 522 target: trip-point1 { 523 temperature = <85000>; 524 hysteresis = <2000>; 525 type = "passive"; 526 }; 527 soc_crit: soc-crit { 528 temperature = <95000>; 529 hysteresis = <2000>; 530 type = "critical"; 531 }; 532 }; 533 534 cooling-maps { 535 map0 { 536 trip = <&target>; 537 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 538 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 539 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 540 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 541 contribution = <4096>; 542 }; 543 }; 544 }; 545 546 }; 547 548 tsadc: tsadc@ff250000 { 549 compatible = "rockchip,rk3328-tsadc"; 550 reg = <0x0 0xff250000 0x0 0x100>; 551 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 552 assigned-clocks = <&cru SCLK_TSADC>; 553 assigned-clock-rates = <50000>; 554 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 555 clock-names = "tsadc", "apb_pclk"; 556 pinctrl-names = "init", "default", "sleep"; 557 pinctrl-0 = <&otp_pin>; 558 pinctrl-1 = <&otp_out>; 559 pinctrl-2 = <&otp_pin>; 560 resets = <&cru SRST_TSADC>; 561 reset-names = "tsadc-apb"; 562 rockchip,grf = <&grf>; 563 rockchip,hw-tshut-temp = <100000>; 564 #thermal-sensor-cells = <1>; 565 status = "disabled"; 566 }; 567 568 efuse: efuse@ff260000 { 569 compatible = "rockchip,rk3328-efuse"; 570 reg = <0x0 0xff260000 0x0 0x50>; 571 #address-cells = <1>; 572 #size-cells = <1>; 573 clocks = <&cru SCLK_EFUSE>; 574 clock-names = "pclk_efuse"; 575 rockchip,efuse-size = <0x20>; 576 577 /* Data cells */ 578 efuse_id: id@7 { 579 reg = <0x07 0x10>; 580 }; 581 cpu_leakage: cpu-leakage@17 { 582 reg = <0x17 0x1>; 583 }; 584 logic_leakage: logic-leakage@19 { 585 reg = <0x19 0x1>; 586 }; 587 efuse_cpu_version: cpu-version@1a { 588 reg = <0x1a 0x1>; 589 bits = <3 3>; 590 }; 591 }; 592 593 saradc: adc@ff280000 { 594 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 595 reg = <0x0 0xff280000 0x0 0x100>; 596 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 597 #io-channel-cells = <1>; 598 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 599 clock-names = "saradc", "apb_pclk"; 600 resets = <&cru SRST_SARADC_P>; 601 reset-names = "saradc-apb"; 602 status = "disabled"; 603 }; 604 605 gpu: gpu@ff300000 { 606 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 607 reg = <0x0 0xff300000 0x0 0x30000>; 608 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 615 interrupt-names = "gp", 616 "gpmmu", 617 "pp", 618 "pp0", 619 "ppmmu0", 620 "pp1", 621 "ppmmu1"; 622 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 623 clock-names = "bus", "core"; 624 resets = <&cru SRST_GPU_A>; 625 }; 626 627 h265e_mmu: iommu@ff330200 { 628 compatible = "rockchip,iommu"; 629 reg = <0x0 0xff330200 0 0x100>; 630 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 632 clock-names = "aclk", "iface"; 633 #iommu-cells = <0>; 634 status = "disabled"; 635 }; 636 637 vepu_mmu: iommu@ff340800 { 638 compatible = "rockchip,iommu"; 639 reg = <0x0 0xff340800 0x0 0x40>; 640 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 642 clock-names = "aclk", "iface"; 643 #iommu-cells = <0>; 644 status = "disabled"; 645 }; 646 647 vpu: video-codec@ff350000 { 648 compatible = "rockchip,rk3328-vpu"; 649 reg = <0x0 0xff350000 0x0 0x800>; 650 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-names = "vdpu"; 652 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 653 clock-names = "aclk", "hclk"; 654 iommus = <&vpu_mmu>; 655 power-domains = <&power RK3328_PD_VPU>; 656 }; 657 658 vpu_mmu: iommu@ff350800 { 659 compatible = "rockchip,iommu"; 660 reg = <0x0 0xff350800 0x0 0x40>; 661 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 663 clock-names = "aclk", "iface"; 664 #iommu-cells = <0>; 665 power-domains = <&power RK3328_PD_VPU>; 666 }; 667 668 vdec: video-codec@ff360000 { 669 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; 670 reg = <0x0 0xff360000 0x0 0x400>; 671 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 673 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 674 clock-names = "axi", "ahb", "cabac", "core"; 675 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, 676 <&cru SCLK_VDEC_CORE>; 677 assigned-clock-rates = <400000000>, <400000000>, <300000000>; 678 iommus = <&vdec_mmu>; 679 power-domains = <&power RK3328_PD_VIDEO>; 680 }; 681 682 vdec_mmu: iommu@ff360480 { 683 compatible = "rockchip,iommu"; 684 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 685 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 687 clock-names = "aclk", "iface"; 688 #iommu-cells = <0>; 689 power-domains = <&power RK3328_PD_VIDEO>; 690 }; 691 692 vop: vop@ff370000 { 693 compatible = "rockchip,rk3328-vop"; 694 reg = <0x0 0xff370000 0x0 0x3efc>; 695 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 697 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 698 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 699 reset-names = "axi", "ahb", "dclk"; 700 iommus = <&vop_mmu>; 701 status = "disabled"; 702 703 vop_out: port { 704 #address-cells = <1>; 705 #size-cells = <0>; 706 707 vop_out_hdmi: endpoint@0 { 708 reg = <0>; 709 remote-endpoint = <&hdmi_in_vop>; 710 }; 711 }; 712 }; 713 714 vop_mmu: iommu@ff373f00 { 715 compatible = "rockchip,iommu"; 716 reg = <0x0 0xff373f00 0x0 0x100>; 717 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 719 clock-names = "aclk", "iface"; 720 #iommu-cells = <0>; 721 status = "disabled"; 722 }; 723 724 hdmi: hdmi@ff3c0000 { 725 compatible = "rockchip,rk3328-dw-hdmi"; 726 reg = <0x0 0xff3c0000 0x0 0x20000>; 727 reg-io-width = <4>; 728 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&cru PCLK_HDMI>, 731 <&cru SCLK_HDMI_SFC>, 732 <&cru SCLK_RTC32K>; 733 clock-names = "iahb", 734 "isfr", 735 "cec"; 736 phys = <&hdmiphy>; 737 phy-names = "hdmi"; 738 pinctrl-names = "default"; 739 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 740 rockchip,grf = <&grf>; 741 #sound-dai-cells = <0>; 742 status = "disabled"; 743 744 ports { 745 hdmi_in: port { 746 hdmi_in_vop: endpoint { 747 remote-endpoint = <&vop_out_hdmi>; 748 }; 749 }; 750 }; 751 }; 752 753 codec: codec@ff410000 { 754 compatible = "rockchip,rk3328-codec"; 755 reg = <0x0 0xff410000 0x0 0x1000>; 756 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 757 clock-names = "pclk", "mclk"; 758 rockchip,grf = <&grf>; 759 #sound-dai-cells = <0>; 760 status = "disabled"; 761 }; 762 763 hdmiphy: phy@ff430000 { 764 compatible = "rockchip,rk3328-hdmi-phy"; 765 reg = <0x0 0xff430000 0x0 0x10000>; 766 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 768 clock-names = "sysclk", "refoclk", "refpclk"; 769 clock-output-names = "hdmi_phy"; 770 #clock-cells = <0>; 771 nvmem-cells = <&efuse_cpu_version>; 772 nvmem-cell-names = "cpu-version"; 773 #phy-cells = <0>; 774 status = "disabled"; 775 }; 776 777 cru: clock-controller@ff440000 { 778 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 779 reg = <0x0 0xff440000 0x0 0x1000>; 780 rockchip,grf = <&grf>; 781 #clock-cells = <1>; 782 #reset-cells = <1>; 783 assigned-clocks = 784 /* 785 * CPLL should run at 1200, but that is to high for 786 * the initial dividers of most of its children. 787 * We need set cpll child clk div first, 788 * and then set the cpll frequency. 789 */ 790 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 791 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 792 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 793 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 794 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 795 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 796 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 797 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 798 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 799 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 800 <&cru SCLK_WIFI>, <&cru ARMCLK>, 801 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 802 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 803 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 804 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 805 <&cru SCLK_RTC32K>; 806 assigned-clock-parents = 807 <&cru HDMIPHY>, <&cru PLL_APLL>, 808 <&cru PLL_GPLL>, <&xin24m>, 809 <&xin24m>, <&xin24m>; 810 assigned-clock-rates = 811 <0>, <61440000>, 812 <0>, <24000000>, 813 <24000000>, <24000000>, 814 <15000000>, <15000000>, 815 <100000000>, <100000000>, 816 <100000000>, <100000000>, 817 <50000000>, <100000000>, 818 <100000000>, <100000000>, 819 <50000000>, <50000000>, 820 <50000000>, <50000000>, 821 <24000000>, <600000000>, 822 <491520000>, <1200000000>, 823 <150000000>, <75000000>, 824 <75000000>, <150000000>, 825 <75000000>, <75000000>, 826 <32768>; 827 }; 828 829 usb2phy_grf: syscon@ff450000 { 830 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 831 "simple-mfd"; 832 reg = <0x0 0xff450000 0x0 0x10000>; 833 #address-cells = <1>; 834 #size-cells = <1>; 835 836 u2phy: usb2phy@100 { 837 compatible = "rockchip,rk3328-usb2phy"; 838 reg = <0x100 0x10>; 839 clocks = <&xin24m>; 840 clock-names = "phyclk"; 841 clock-output-names = "usb480m_phy"; 842 #clock-cells = <0>; 843 assigned-clocks = <&cru USB480M>; 844 assigned-clock-parents = <&u2phy>; 845 status = "disabled"; 846 847 u2phy_otg: otg-port { 848 #phy-cells = <0>; 849 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 852 interrupt-names = "otg-bvalid", "otg-id", 853 "linestate"; 854 status = "disabled"; 855 }; 856 857 u2phy_host: host-port { 858 #phy-cells = <0>; 859 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 860 interrupt-names = "linestate"; 861 status = "disabled"; 862 }; 863 }; 864 }; 865 866 sdmmc: mmc@ff500000 { 867 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 868 reg = <0x0 0xff500000 0x0 0x4000>; 869 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 871 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 872 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 873 fifo-depth = <0x100>; 874 max-frequency = <150000000>; 875 status = "disabled"; 876 }; 877 878 sdio: mmc@ff510000 { 879 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 880 reg = <0x0 0xff510000 0x0 0x4000>; 881 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 883 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 884 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 885 fifo-depth = <0x100>; 886 max-frequency = <150000000>; 887 status = "disabled"; 888 }; 889 890 emmc: mmc@ff520000 { 891 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 892 reg = <0x0 0xff520000 0x0 0x4000>; 893 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 895 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 896 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 897 fifo-depth = <0x100>; 898 max-frequency = <150000000>; 899 status = "disabled"; 900 }; 901 902 gmac2io: ethernet@ff540000 { 903 compatible = "rockchip,rk3328-gmac"; 904 reg = <0x0 0xff540000 0x0 0x10000>; 905 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 906 interrupt-names = "macirq"; 907 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 908 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 909 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 910 <&cru PCLK_MAC2IO>; 911 clock-names = "stmmaceth", "mac_clk_rx", 912 "mac_clk_tx", "clk_mac_ref", 913 "clk_mac_refout", "aclk_mac", 914 "pclk_mac"; 915 resets = <&cru SRST_GMAC2IO_A>; 916 reset-names = "stmmaceth"; 917 rockchip,grf = <&grf>; 918 snps,txpbl = <0x4>; 919 status = "disabled"; 920 }; 921 922 gmac2phy: ethernet@ff550000 { 923 compatible = "rockchip,rk3328-gmac"; 924 reg = <0x0 0xff550000 0x0 0x10000>; 925 rockchip,grf = <&grf>; 926 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 927 interrupt-names = "macirq"; 928 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 929 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 930 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 931 <&cru SCLK_MAC2PHY_OUT>; 932 clock-names = "stmmaceth", "mac_clk_rx", 933 "mac_clk_tx", "clk_mac_ref", 934 "aclk_mac", "pclk_mac", 935 "clk_macphy"; 936 resets = <&cru SRST_GMAC2PHY_A>; 937 reset-names = "stmmaceth"; 938 phy-mode = "rmii"; 939 phy-handle = <&phy>; 940 snps,txpbl = <0x4>; 941 clock_in_out = "output"; 942 status = "disabled"; 943 944 mdio { 945 compatible = "snps,dwmac-mdio"; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 949 phy: ethernet-phy@0 { 950 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 951 reg = <0>; 952 clocks = <&cru SCLK_MAC2PHY_OUT>; 953 resets = <&cru SRST_MACPHY>; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 956 phy-is-integrated; 957 }; 958 }; 959 }; 960 961 usb20_otg: usb@ff580000 { 962 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 963 "snps,dwc2"; 964 reg = <0x0 0xff580000 0x0 0x40000>; 965 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&cru HCLK_OTG>; 967 clock-names = "otg"; 968 dr_mode = "otg"; 969 g-np-tx-fifo-size = <16>; 970 g-rx-fifo-size = <280>; 971 g-tx-fifo-size = <256 128 128 64 32 16>; 972 phys = <&u2phy_otg>; 973 phy-names = "usb2-phy"; 974 status = "disabled"; 975 }; 976 977 usb_host0_ehci: usb@ff5c0000 { 978 compatible = "generic-ehci"; 979 reg = <0x0 0xff5c0000 0x0 0x10000>; 980 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&cru HCLK_HOST0>, <&u2phy>; 982 phys = <&u2phy_host>; 983 phy-names = "usb"; 984 status = "disabled"; 985 }; 986 987 usb_host0_ohci: usb@ff5d0000 { 988 compatible = "generic-ohci"; 989 reg = <0x0 0xff5d0000 0x0 0x10000>; 990 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&cru HCLK_HOST0>, <&u2phy>; 992 phys = <&u2phy_host>; 993 phy-names = "usb"; 994 status = "disabled"; 995 }; 996 997 usbdrd3: usb@ff600000 { 998 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 999 reg = <0x0 0xff600000 0x0 0x100000>; 1000 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 1002 <&cru ACLK_USB3OTG>; 1003 clock-names = "ref_clk", "suspend_clk", 1004 "bus_clk"; 1005 dr_mode = "otg"; 1006 phy_type = "utmi_wide"; 1007 snps,dis-del-phy-power-chg-quirk; 1008 snps,dis_enblslpm_quirk; 1009 snps,dis-tx-ipgap-linecheck-quirk; 1010 snps,dis-u2-freeclk-exists-quirk; 1011 snps,dis_u2_susphy_quirk; 1012 snps,dis_u3_susphy_quirk; 1013 status = "disabled"; 1014 }; 1015 1016 gic: interrupt-controller@ff811000 { 1017 compatible = "arm,gic-400"; 1018 #interrupt-cells = <3>; 1019 #address-cells = <0>; 1020 interrupt-controller; 1021 reg = <0x0 0xff811000 0 0x1000>, 1022 <0x0 0xff812000 0 0x2000>, 1023 <0x0 0xff814000 0 0x2000>, 1024 <0x0 0xff816000 0 0x2000>; 1025 interrupts = <GIC_PPI 9 1026 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1027 }; 1028 1029 crypto: crypto@ff060000 { 1030 compatible = "rockchip,rk3328-crypto"; 1031 reg = <0x0 0xff060000 0x0 0x4000>; 1032 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, 1034 <&cru SCLK_CRYPTO>; 1035 clock-names = "hclk_master", "hclk_slave", "sclk"; 1036 resets = <&cru SRST_CRYPTO>; 1037 reset-names = "crypto-rst"; 1038 }; 1039 1040 pinctrl: pinctrl { 1041 compatible = "rockchip,rk3328-pinctrl"; 1042 rockchip,grf = <&grf>; 1043 #address-cells = <2>; 1044 #size-cells = <2>; 1045 ranges; 1046 1047 gpio0: gpio@ff210000 { 1048 compatible = "rockchip,gpio-bank"; 1049 reg = <0x0 0xff210000 0x0 0x100>; 1050 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&cru PCLK_GPIO0>; 1052 1053 gpio-controller; 1054 #gpio-cells = <2>; 1055 1056 interrupt-controller; 1057 #interrupt-cells = <2>; 1058 }; 1059 1060 gpio1: gpio@ff220000 { 1061 compatible = "rockchip,gpio-bank"; 1062 reg = <0x0 0xff220000 0x0 0x100>; 1063 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&cru PCLK_GPIO1>; 1065 1066 gpio-controller; 1067 #gpio-cells = <2>; 1068 1069 interrupt-controller; 1070 #interrupt-cells = <2>; 1071 }; 1072 1073 gpio2: gpio@ff230000 { 1074 compatible = "rockchip,gpio-bank"; 1075 reg = <0x0 0xff230000 0x0 0x100>; 1076 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1077 clocks = <&cru PCLK_GPIO2>; 1078 1079 gpio-controller; 1080 #gpio-cells = <2>; 1081 1082 interrupt-controller; 1083 #interrupt-cells = <2>; 1084 }; 1085 1086 gpio3: gpio@ff240000 { 1087 compatible = "rockchip,gpio-bank"; 1088 reg = <0x0 0xff240000 0x0 0x100>; 1089 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&cru PCLK_GPIO3>; 1091 1092 gpio-controller; 1093 #gpio-cells = <2>; 1094 1095 interrupt-controller; 1096 #interrupt-cells = <2>; 1097 }; 1098 1099 pcfg_pull_up: pcfg-pull-up { 1100 bias-pull-up; 1101 }; 1102 1103 pcfg_pull_down: pcfg-pull-down { 1104 bias-pull-down; 1105 }; 1106 1107 pcfg_pull_none: pcfg-pull-none { 1108 bias-disable; 1109 }; 1110 1111 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1112 bias-disable; 1113 drive-strength = <2>; 1114 }; 1115 1116 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1117 bias-pull-up; 1118 drive-strength = <2>; 1119 }; 1120 1121 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1122 bias-pull-up; 1123 drive-strength = <4>; 1124 }; 1125 1126 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1127 bias-disable; 1128 drive-strength = <4>; 1129 }; 1130 1131 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1132 bias-pull-down; 1133 drive-strength = <4>; 1134 }; 1135 1136 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1137 bias-disable; 1138 drive-strength = <8>; 1139 }; 1140 1141 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1142 bias-pull-up; 1143 drive-strength = <8>; 1144 }; 1145 1146 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1147 bias-disable; 1148 drive-strength = <12>; 1149 }; 1150 1151 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1152 bias-pull-up; 1153 drive-strength = <12>; 1154 }; 1155 1156 pcfg_output_high: pcfg-output-high { 1157 output-high; 1158 }; 1159 1160 pcfg_output_low: pcfg-output-low { 1161 output-low; 1162 }; 1163 1164 pcfg_input_high: pcfg-input-high { 1165 bias-pull-up; 1166 input-enable; 1167 }; 1168 1169 pcfg_input: pcfg-input { 1170 input-enable; 1171 }; 1172 1173 i2c0 { 1174 i2c0_xfer: i2c0-xfer { 1175 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1176 <2 RK_PD1 1 &pcfg_pull_none>; 1177 }; 1178 }; 1179 1180 i2c1 { 1181 i2c1_xfer: i2c1-xfer { 1182 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1183 <2 RK_PA5 2 &pcfg_pull_none>; 1184 }; 1185 }; 1186 1187 i2c2 { 1188 i2c2_xfer: i2c2-xfer { 1189 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1190 <2 RK_PB6 1 &pcfg_pull_none>; 1191 }; 1192 }; 1193 1194 i2c3 { 1195 i2c3_xfer: i2c3-xfer { 1196 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1197 <0 RK_PA6 2 &pcfg_pull_none>; 1198 }; 1199 i2c3_pins: i2c3-pins { 1200 rockchip,pins = 1201 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1202 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1203 }; 1204 }; 1205 1206 hdmi_i2c { 1207 hdmii2c_xfer: hdmii2c-xfer { 1208 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1209 <0 RK_PA6 1 &pcfg_pull_none>; 1210 }; 1211 }; 1212 1213 pdm-0 { 1214 pdmm0_clk: pdmm0-clk { 1215 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1216 }; 1217 1218 pdmm0_fsync: pdmm0-fsync { 1219 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1220 }; 1221 1222 pdmm0_sdi0: pdmm0-sdi0 { 1223 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1224 }; 1225 1226 pdmm0_sdi1: pdmm0-sdi1 { 1227 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1228 }; 1229 1230 pdmm0_sdi2: pdmm0-sdi2 { 1231 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1232 }; 1233 1234 pdmm0_sdi3: pdmm0-sdi3 { 1235 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1236 }; 1237 1238 pdmm0_clk_sleep: pdmm0-clk-sleep { 1239 rockchip,pins = 1240 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1241 }; 1242 1243 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1244 rockchip,pins = 1245 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1246 }; 1247 1248 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1249 rockchip,pins = 1250 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1251 }; 1252 1253 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1254 rockchip,pins = 1255 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1256 }; 1257 1258 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1259 rockchip,pins = 1260 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1261 }; 1262 1263 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1264 rockchip,pins = 1265 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1266 }; 1267 }; 1268 1269 tsadc { 1270 otp_pin: otp-pin { 1271 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1272 }; 1273 1274 otp_out: otp-out { 1275 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1276 }; 1277 }; 1278 1279 uart0 { 1280 uart0_xfer: uart0-xfer { 1281 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1282 <1 RK_PB0 1 &pcfg_pull_up>; 1283 }; 1284 1285 uart0_cts: uart0-cts { 1286 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1287 }; 1288 1289 uart0_rts: uart0-rts { 1290 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1291 }; 1292 1293 uart0_rts_pin: uart0-rts-pin { 1294 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1295 }; 1296 }; 1297 1298 uart1 { 1299 uart1_xfer: uart1-xfer { 1300 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1301 <3 RK_PA6 4 &pcfg_pull_up>; 1302 }; 1303 1304 uart1_cts: uart1-cts { 1305 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1306 }; 1307 1308 uart1_rts: uart1-rts { 1309 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1310 }; 1311 1312 uart1_rts_pin: uart1-rts-pin { 1313 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1314 }; 1315 }; 1316 1317 uart2-0 { 1318 uart2m0_xfer: uart2m0-xfer { 1319 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1320 <1 RK_PA1 2 &pcfg_pull_up>; 1321 }; 1322 }; 1323 1324 uart2-1 { 1325 uart2m1_xfer: uart2m1-xfer { 1326 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1327 <2 RK_PA1 1 &pcfg_pull_up>; 1328 }; 1329 }; 1330 1331 spi0-0 { 1332 spi0m0_clk: spi0m0-clk { 1333 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1334 }; 1335 1336 spi0m0_cs0: spi0m0-cs0 { 1337 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1338 }; 1339 1340 spi0m0_tx: spi0m0-tx { 1341 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1342 }; 1343 1344 spi0m0_rx: spi0m0-rx { 1345 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1346 }; 1347 1348 spi0m0_cs1: spi0m0-cs1 { 1349 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1350 }; 1351 }; 1352 1353 spi0-1 { 1354 spi0m1_clk: spi0m1-clk { 1355 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1356 }; 1357 1358 spi0m1_cs0: spi0m1-cs0 { 1359 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1360 }; 1361 1362 spi0m1_tx: spi0m1-tx { 1363 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1364 }; 1365 1366 spi0m1_rx: spi0m1-rx { 1367 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1368 }; 1369 1370 spi0m1_cs1: spi0m1-cs1 { 1371 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1372 }; 1373 }; 1374 1375 spi0-2 { 1376 spi0m2_clk: spi0m2-clk { 1377 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1378 }; 1379 1380 spi0m2_cs0: spi0m2-cs0 { 1381 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1382 }; 1383 1384 spi0m2_tx: spi0m2-tx { 1385 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1386 }; 1387 1388 spi0m2_rx: spi0m2-rx { 1389 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1390 }; 1391 }; 1392 1393 i2s1 { 1394 i2s1_mclk: i2s1-mclk { 1395 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1396 }; 1397 1398 i2s1_sclk: i2s1-sclk { 1399 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1400 }; 1401 1402 i2s1_lrckrx: i2s1-lrckrx { 1403 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1404 }; 1405 1406 i2s1_lrcktx: i2s1-lrcktx { 1407 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1408 }; 1409 1410 i2s1_sdi: i2s1-sdi { 1411 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1412 }; 1413 1414 i2s1_sdo: i2s1-sdo { 1415 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1416 }; 1417 1418 i2s1_sdio1: i2s1-sdio1 { 1419 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1420 }; 1421 1422 i2s1_sdio2: i2s1-sdio2 { 1423 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1424 }; 1425 1426 i2s1_sdio3: i2s1-sdio3 { 1427 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1428 }; 1429 1430 i2s1_sleep: i2s1-sleep { 1431 rockchip,pins = 1432 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1433 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1434 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1435 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1436 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1437 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1438 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1439 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1440 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1441 }; 1442 }; 1443 1444 i2s2-0 { 1445 i2s2m0_mclk: i2s2m0-mclk { 1446 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1447 }; 1448 1449 i2s2m0_sclk: i2s2m0-sclk { 1450 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1451 }; 1452 1453 i2s2m0_lrckrx: i2s2m0-lrckrx { 1454 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1455 }; 1456 1457 i2s2m0_lrcktx: i2s2m0-lrcktx { 1458 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1459 }; 1460 1461 i2s2m0_sdi: i2s2m0-sdi { 1462 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1463 }; 1464 1465 i2s2m0_sdo: i2s2m0-sdo { 1466 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1467 }; 1468 1469 i2s2m0_sleep: i2s2m0-sleep { 1470 rockchip,pins = 1471 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1472 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1473 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1474 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1475 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1476 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1477 }; 1478 }; 1479 1480 i2s2-1 { 1481 i2s2m1_mclk: i2s2m1-mclk { 1482 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1483 }; 1484 1485 i2s2m1_sclk: i2s2m1-sclk { 1486 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1487 }; 1488 1489 i2s2m1_lrckrx: i2sm1-lrckrx { 1490 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1491 }; 1492 1493 i2s2m1_lrcktx: i2s2m1-lrcktx { 1494 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1495 }; 1496 1497 i2s2m1_sdi: i2s2m1-sdi { 1498 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1499 }; 1500 1501 i2s2m1_sdo: i2s2m1-sdo { 1502 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1503 }; 1504 1505 i2s2m1_sleep: i2s2m1-sleep { 1506 rockchip,pins = 1507 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1508 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1509 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1510 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1511 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1512 }; 1513 }; 1514 1515 spdif-0 { 1516 spdifm0_tx: spdifm0-tx { 1517 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1518 }; 1519 }; 1520 1521 spdif-1 { 1522 spdifm1_tx: spdifm1-tx { 1523 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1524 }; 1525 }; 1526 1527 spdif-2 { 1528 spdifm2_tx: spdifm2-tx { 1529 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1530 }; 1531 }; 1532 1533 sdmmc0-0 { 1534 sdmmc0m0_pwren: sdmmc0m0-pwren { 1535 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1536 }; 1537 1538 sdmmc0m0_pin: sdmmc0m0-pin { 1539 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1540 }; 1541 }; 1542 1543 sdmmc0-1 { 1544 sdmmc0m1_pwren: sdmmc0m1-pwren { 1545 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1546 }; 1547 1548 sdmmc0m1_pin: sdmmc0m1-pin { 1549 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1550 }; 1551 }; 1552 1553 sdmmc0 { 1554 sdmmc0_clk: sdmmc0-clk { 1555 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1556 }; 1557 1558 sdmmc0_cmd: sdmmc0-cmd { 1559 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1560 }; 1561 1562 sdmmc0_dectn: sdmmc0-dectn { 1563 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1564 }; 1565 1566 sdmmc0_wrprt: sdmmc0-wrprt { 1567 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1568 }; 1569 1570 sdmmc0_bus1: sdmmc0-bus1 { 1571 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1572 }; 1573 1574 sdmmc0_bus4: sdmmc0-bus4 { 1575 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1576 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1577 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1578 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1579 }; 1580 1581 sdmmc0_pins: sdmmc0-pins { 1582 rockchip,pins = 1583 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1584 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1585 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1586 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1587 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1588 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1589 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1590 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1591 }; 1592 }; 1593 1594 sdmmc0ext { 1595 sdmmc0ext_clk: sdmmc0ext-clk { 1596 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1597 }; 1598 1599 sdmmc0ext_cmd: sdmmc0ext-cmd { 1600 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1601 }; 1602 1603 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1604 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1605 }; 1606 1607 sdmmc0ext_dectn: sdmmc0ext-dectn { 1608 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1609 }; 1610 1611 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1612 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1613 }; 1614 1615 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1616 rockchip,pins = 1617 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1618 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1619 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1620 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1621 }; 1622 1623 sdmmc0ext_pins: sdmmc0ext-pins { 1624 rockchip,pins = 1625 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1626 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1627 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1628 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1629 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1630 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1631 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1632 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1633 }; 1634 }; 1635 1636 sdmmc1 { 1637 sdmmc1_clk: sdmmc1-clk { 1638 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1639 }; 1640 1641 sdmmc1_cmd: sdmmc1-cmd { 1642 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1643 }; 1644 1645 sdmmc1_pwren: sdmmc1-pwren { 1646 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1647 }; 1648 1649 sdmmc1_wrprt: sdmmc1-wrprt { 1650 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1651 }; 1652 1653 sdmmc1_dectn: sdmmc1-dectn { 1654 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1655 }; 1656 1657 sdmmc1_bus1: sdmmc1-bus1 { 1658 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1659 }; 1660 1661 sdmmc1_bus4: sdmmc1-bus4 { 1662 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1663 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1664 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1665 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1666 }; 1667 1668 sdmmc1_pins: sdmmc1-pins { 1669 rockchip,pins = 1670 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1671 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1672 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1673 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1674 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1675 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1676 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1677 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1678 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1679 }; 1680 }; 1681 1682 emmc { 1683 emmc_clk: emmc-clk { 1684 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1685 }; 1686 1687 emmc_cmd: emmc-cmd { 1688 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1689 }; 1690 1691 emmc_pwren: emmc-pwren { 1692 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1693 }; 1694 1695 emmc_rstnout: emmc-rstnout { 1696 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1697 }; 1698 1699 emmc_bus1: emmc-bus1 { 1700 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1701 }; 1702 1703 emmc_bus4: emmc-bus4 { 1704 rockchip,pins = 1705 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1706 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1707 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1708 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1709 }; 1710 1711 emmc_bus8: emmc-bus8 { 1712 rockchip,pins = 1713 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1714 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1715 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1716 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1717 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1718 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1719 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1720 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1721 }; 1722 }; 1723 1724 pwm0 { 1725 pwm0_pin: pwm0-pin { 1726 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1727 }; 1728 }; 1729 1730 pwm1 { 1731 pwm1_pin: pwm1-pin { 1732 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1733 }; 1734 }; 1735 1736 pwm2 { 1737 pwm2_pin: pwm2-pin { 1738 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1739 }; 1740 }; 1741 1742 pwmir { 1743 pwmir_pin: pwmir-pin { 1744 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1745 }; 1746 }; 1747 1748 gmac-1 { 1749 rgmiim1_pins: rgmiim1-pins { 1750 rockchip,pins = 1751 /* mac_txclk */ 1752 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1753 /* mac_rxclk */ 1754 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1755 /* mac_mdio */ 1756 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1757 /* mac_txen */ 1758 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1759 /* mac_clk */ 1760 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1761 /* mac_rxdv */ 1762 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1763 /* mac_mdc */ 1764 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1765 /* mac_rxd1 */ 1766 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1767 /* mac_rxd0 */ 1768 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1769 /* mac_txd1 */ 1770 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1771 /* mac_txd0 */ 1772 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1773 /* mac_rxd3 */ 1774 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1775 /* mac_rxd2 */ 1776 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1777 /* mac_txd3 */ 1778 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1779 /* mac_txd2 */ 1780 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1781 1782 /* mac_txclk */ 1783 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1784 /* mac_txen */ 1785 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1786 /* mac_clk */ 1787 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1788 /* mac_txd1 */ 1789 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1790 /* mac_txd0 */ 1791 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1792 /* mac_txd3 */ 1793 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1794 /* mac_txd2 */ 1795 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1796 }; 1797 1798 rmiim1_pins: rmiim1-pins { 1799 rockchip,pins = 1800 /* mac_mdio */ 1801 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1802 /* mac_txen */ 1803 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1804 /* mac_clk */ 1805 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1806 /* mac_rxer */ 1807 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1808 /* mac_rxdv */ 1809 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1810 /* mac_mdc */ 1811 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1812 /* mac_rxd1 */ 1813 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1814 /* mac_rxd0 */ 1815 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1816 /* mac_txd1 */ 1817 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1818 /* mac_txd0 */ 1819 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1820 1821 /* mac_mdio */ 1822 <0 RK_PB3 1 &pcfg_pull_none>, 1823 /* mac_txen */ 1824 <0 RK_PB4 1 &pcfg_pull_none>, 1825 /* mac_clk */ 1826 <0 RK_PD0 1 &pcfg_pull_none>, 1827 /* mac_mdc */ 1828 <0 RK_PC3 1 &pcfg_pull_none>, 1829 /* mac_txd1 */ 1830 <0 RK_PC0 1 &pcfg_pull_none>, 1831 /* mac_txd0 */ 1832 <0 RK_PC1 1 &pcfg_pull_none>; 1833 }; 1834 }; 1835 1836 gmac2phy { 1837 fephyled_speed10: fephyled-speed10 { 1838 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1839 }; 1840 1841 fephyled_duplex: fephyled-duplex { 1842 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1843 }; 1844 1845 fephyled_rxm1: fephyled-rxm1 { 1846 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1847 }; 1848 1849 fephyled_txm1: fephyled-txm1 { 1850 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1851 }; 1852 1853 fephyled_linkm1: fephyled-linkm1 { 1854 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1855 }; 1856 }; 1857 1858 tsadc_pin { 1859 tsadc_int: tsadc-int { 1860 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1861 }; 1862 tsadc_pin: tsadc-pin { 1863 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1864 }; 1865 }; 1866 1867 hdmi_pin { 1868 hdmi_cec: hdmi-cec { 1869 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1870 }; 1871 1872 hdmi_hpd: hdmi-hpd { 1873 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1874 }; 1875 }; 1876 1877 cif-0 { 1878 dvp_d2d9_m0:dvp-d2d9-m0 { 1879 rockchip,pins = 1880 /* cif_d0 */ 1881 <3 RK_PA4 2 &pcfg_pull_none>, 1882 /* cif_d1 */ 1883 <3 RK_PA5 2 &pcfg_pull_none>, 1884 /* cif_d2 */ 1885 <3 RK_PA6 2 &pcfg_pull_none>, 1886 /* cif_d3 */ 1887 <3 RK_PA7 2 &pcfg_pull_none>, 1888 /* cif_d4 */ 1889 <3 RK_PB0 2 &pcfg_pull_none>, 1890 /* cif_d5m0 */ 1891 <3 RK_PB1 2 &pcfg_pull_none>, 1892 /* cif_d6m0 */ 1893 <3 RK_PB2 2 &pcfg_pull_none>, 1894 /* cif_d7m0 */ 1895 <3 RK_PB3 2 &pcfg_pull_none>, 1896 /* cif_href */ 1897 <3 RK_PA1 2 &pcfg_pull_none>, 1898 /* cif_vsync */ 1899 <3 RK_PA0 2 &pcfg_pull_none>, 1900 /* cif_clkoutm0 */ 1901 <3 RK_PA3 2 &pcfg_pull_none>, 1902 /* cif_clkin */ 1903 <3 RK_PA2 2 &pcfg_pull_none>; 1904 }; 1905 }; 1906 1907 cif-1 { 1908 dvp_d2d9_m1:dvp-d2d9-m1 { 1909 rockchip,pins = 1910 /* cif_d0 */ 1911 <3 RK_PA4 2 &pcfg_pull_none>, 1912 /* cif_d1 */ 1913 <3 RK_PA5 2 &pcfg_pull_none>, 1914 /* cif_d2 */ 1915 <3 RK_PA6 2 &pcfg_pull_none>, 1916 /* cif_d3 */ 1917 <3 RK_PA7 2 &pcfg_pull_none>, 1918 /* cif_d4 */ 1919 <3 RK_PB0 2 &pcfg_pull_none>, 1920 /* cif_d5m1 */ 1921 <2 RK_PC0 4 &pcfg_pull_none>, 1922 /* cif_d6m1 */ 1923 <2 RK_PC1 4 &pcfg_pull_none>, 1924 /* cif_d7m1 */ 1925 <2 RK_PC2 4 &pcfg_pull_none>, 1926 /* cif_href */ 1927 <3 RK_PA1 2 &pcfg_pull_none>, 1928 /* cif_vsync */ 1929 <3 RK_PA0 2 &pcfg_pull_none>, 1930 /* cif_clkoutm1 */ 1931 <2 RK_PB7 4 &pcfg_pull_none>, 1932 /* cif_clkin */ 1933 <3 RK_PA2 2 &pcfg_pull_none>; 1934 }; 1935 }; 1936 }; 1937}; 1938