1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 cpu-idle-states = <&CPU_SLEEP>; 45 dynamic-power-coefficient = <120>; 46 enable-method = "psci"; 47 next-level-cache = <&l2>; 48 operating-points-v2 = <&cpu0_opp_table>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x0 0x1>; 55 clocks = <&cru ARMCLK>; 56 #cooling-cells = <2>; 57 cpu-idle-states = <&CPU_SLEEP>; 58 dynamic-power-coefficient = <120>; 59 enable-method = "psci"; 60 next-level-cache = <&l2>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0 0x2>; 68 clocks = <&cru ARMCLK>; 69 #cooling-cells = <2>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 dynamic-power-coefficient = <120>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 }; 76 77 cpu3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x0 0x3>; 81 clocks = <&cru ARMCLK>; 82 #cooling-cells = <2>; 83 cpu-idle-states = <&CPU_SLEEP>; 84 dynamic-power-coefficient = <120>; 85 enable-method = "psci"; 86 next-level-cache = <&l2>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 }; 102 103 l2: l2-cache0 { 104 compatible = "cache"; 105 }; 106 }; 107 108 cpu0_opp_table: opp_table0 { 109 compatible = "operating-points-v2"; 110 opp-shared; 111 112 opp-408000000 { 113 opp-hz = /bits/ 64 <408000000>; 114 opp-microvolt = <950000>; 115 clock-latency-ns = <40000>; 116 opp-suspend; 117 }; 118 opp-600000000 { 119 opp-hz = /bits/ 64 <600000000>; 120 opp-microvolt = <950000>; 121 clock-latency-ns = <40000>; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1000000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1100000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1225000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1300000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 analog_sound: analog-sound { 146 compatible = "simple-audio-card"; 147 simple-audio-card,format = "i2s"; 148 simple-audio-card,mclk-fs = <256>; 149 simple-audio-card,name = "Analog"; 150 status = "disabled"; 151 152 simple-audio-card,cpu { 153 sound-dai = <&i2s1>; 154 }; 155 156 simple-audio-card,codec { 157 sound-dai = <&codec>; 158 }; 159 }; 160 161 arm-pmu { 162 compatible = "arm,cortex-a53-pmu"; 163 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 167 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 168 }; 169 170 display_subsystem: display-subsystem { 171 compatible = "rockchip,display-subsystem"; 172 ports = <&vop_out>; 173 }; 174 175 hdmi_sound: hdmi-sound { 176 compatible = "simple-audio-card"; 177 simple-audio-card,format = "i2s"; 178 simple-audio-card,mclk-fs = <128>; 179 simple-audio-card,name = "HDMI"; 180 status = "disabled"; 181 182 simple-audio-card,cpu { 183 sound-dai = <&i2s0>; 184 }; 185 186 simple-audio-card,codec { 187 sound-dai = <&hdmi>; 188 }; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0", "arm,psci-0.2"; 193 method = "smc"; 194 }; 195 196 timer { 197 compatible = "arm,armv8-timer"; 198 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 199 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 200 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 201 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 202 }; 203 204 xin24m: xin24m { 205 compatible = "fixed-clock"; 206 #clock-cells = <0>; 207 clock-frequency = <24000000>; 208 clock-output-names = "xin24m"; 209 }; 210 211 i2s0: i2s@ff000000 { 212 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 213 reg = <0x0 0xff000000 0x0 0x1000>; 214 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 216 clock-names = "i2s_clk", "i2s_hclk"; 217 dmas = <&dmac 11>, <&dmac 12>; 218 dma-names = "tx", "rx"; 219 #sound-dai-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2s1: i2s@ff010000 { 224 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 225 reg = <0x0 0xff010000 0x0 0x1000>; 226 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 228 clock-names = "i2s_clk", "i2s_hclk"; 229 dmas = <&dmac 14>, <&dmac 15>; 230 dma-names = "tx", "rx"; 231 #sound-dai-cells = <0>; 232 status = "disabled"; 233 }; 234 235 i2s2: i2s@ff020000 { 236 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 237 reg = <0x0 0xff020000 0x0 0x1000>; 238 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 240 clock-names = "i2s_clk", "i2s_hclk"; 241 dmas = <&dmac 0>, <&dmac 1>; 242 dma-names = "tx", "rx"; 243 #sound-dai-cells = <0>; 244 status = "disabled"; 245 }; 246 247 spdif: spdif@ff030000 { 248 compatible = "rockchip,rk3328-spdif"; 249 reg = <0x0 0xff030000 0x0 0x1000>; 250 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 252 clock-names = "mclk", "hclk"; 253 dmas = <&dmac 10>; 254 dma-names = "tx"; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&spdifm2_tx>; 257 #sound-dai-cells = <0>; 258 status = "disabled"; 259 }; 260 261 pdm: pdm@ff040000 { 262 compatible = "rockchip,pdm"; 263 reg = <0x0 0xff040000 0x0 0x1000>; 264 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 265 clock-names = "pdm_clk", "pdm_hclk"; 266 dmas = <&dmac 16>; 267 dma-names = "rx"; 268 pinctrl-names = "default", "sleep"; 269 pinctrl-0 = <&pdmm0_clk 270 &pdmm0_sdi0 271 &pdmm0_sdi1 272 &pdmm0_sdi2 273 &pdmm0_sdi3>; 274 pinctrl-1 = <&pdmm0_clk_sleep 275 &pdmm0_sdi0_sleep 276 &pdmm0_sdi1_sleep 277 &pdmm0_sdi2_sleep 278 &pdmm0_sdi3_sleep>; 279 status = "disabled"; 280 }; 281 282 grf: syscon@ff100000 { 283 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 284 reg = <0x0 0xff100000 0x0 0x1000>; 285 286 io_domains: io-domains { 287 compatible = "rockchip,rk3328-io-voltage-domain"; 288 status = "disabled"; 289 }; 290 291 grf_gpio: grf-gpio { 292 compatible = "rockchip,rk3328-grf-gpio"; 293 gpio-controller; 294 #gpio-cells = <2>; 295 }; 296 297 power: power-controller { 298 compatible = "rockchip,rk3328-power-controller"; 299 #power-domain-cells = <1>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 303 pd_hevc@RK3328_PD_HEVC { 304 reg = <RK3328_PD_HEVC>; 305 }; 306 pd_video@RK3328_PD_VIDEO { 307 reg = <RK3328_PD_VIDEO>; 308 }; 309 pd_vpu@RK3328_PD_VPU { 310 reg = <RK3328_PD_VPU>; 311 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 312 }; 313 }; 314 315 reboot-mode { 316 compatible = "syscon-reboot-mode"; 317 offset = <0x5c8>; 318 mode-normal = <BOOT_NORMAL>; 319 mode-recovery = <BOOT_RECOVERY>; 320 mode-bootloader = <BOOT_FASTBOOT>; 321 mode-loader = <BOOT_BL_DOWNLOAD>; 322 }; 323 }; 324 325 uart0: serial@ff110000 { 326 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 327 reg = <0x0 0xff110000 0x0 0x100>; 328 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 330 clock-names = "baudclk", "apb_pclk"; 331 dmas = <&dmac 2>, <&dmac 3>; 332 dma-names = "tx", "rx"; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 335 reg-io-width = <4>; 336 reg-shift = <2>; 337 status = "disabled"; 338 }; 339 340 uart1: serial@ff120000 { 341 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 342 reg = <0x0 0xff120000 0x0 0x100>; 343 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 345 clock-names = "baudclk", "apb_pclk"; 346 dmas = <&dmac 4>, <&dmac 5>; 347 dma-names = "tx", "rx"; 348 pinctrl-names = "default"; 349 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 350 reg-io-width = <4>; 351 reg-shift = <2>; 352 status = "disabled"; 353 }; 354 355 uart2: serial@ff130000 { 356 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 357 reg = <0x0 0xff130000 0x0 0x100>; 358 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 360 clock-names = "baudclk", "apb_pclk"; 361 dmas = <&dmac 6>, <&dmac 7>; 362 dma-names = "tx", "rx"; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&uart2m1_xfer>; 365 reg-io-width = <4>; 366 reg-shift = <2>; 367 status = "disabled"; 368 }; 369 370 i2c0: i2c@ff150000 { 371 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 372 reg = <0x0 0xff150000 0x0 0x1000>; 373 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 377 clock-names = "i2c", "pclk"; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&i2c0_xfer>; 380 status = "disabled"; 381 }; 382 383 i2c1: i2c@ff160000 { 384 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 385 reg = <0x0 0xff160000 0x0 0x1000>; 386 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 390 clock-names = "i2c", "pclk"; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&i2c1_xfer>; 393 status = "disabled"; 394 }; 395 396 i2c2: i2c@ff170000 { 397 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 398 reg = <0x0 0xff170000 0x0 0x1000>; 399 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 403 clock-names = "i2c", "pclk"; 404 pinctrl-names = "default"; 405 pinctrl-0 = <&i2c2_xfer>; 406 status = "disabled"; 407 }; 408 409 i2c3: i2c@ff180000 { 410 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 411 reg = <0x0 0xff180000 0x0 0x1000>; 412 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 416 clock-names = "i2c", "pclk"; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&i2c3_xfer>; 419 status = "disabled"; 420 }; 421 422 spi0: spi@ff190000 { 423 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 424 reg = <0x0 0xff190000 0x0 0x1000>; 425 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 429 clock-names = "spiclk", "apb_pclk"; 430 dmas = <&dmac 8>, <&dmac 9>; 431 dma-names = "tx", "rx"; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 434 status = "disabled"; 435 }; 436 437 wdt: watchdog@ff1a0000 { 438 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 439 reg = <0x0 0xff1a0000 0x0 0x100>; 440 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&cru PCLK_WDT>; 442 }; 443 444 pwm0: pwm@ff1b0000 { 445 compatible = "rockchip,rk3328-pwm"; 446 reg = <0x0 0xff1b0000 0x0 0x10>; 447 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 448 clock-names = "pwm", "pclk"; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pwm0_pin>; 451 #pwm-cells = <3>; 452 status = "disabled"; 453 }; 454 455 pwm1: pwm@ff1b0010 { 456 compatible = "rockchip,rk3328-pwm"; 457 reg = <0x0 0xff1b0010 0x0 0x10>; 458 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 459 clock-names = "pwm", "pclk"; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&pwm1_pin>; 462 #pwm-cells = <3>; 463 status = "disabled"; 464 }; 465 466 pwm2: pwm@ff1b0020 { 467 compatible = "rockchip,rk3328-pwm"; 468 reg = <0x0 0xff1b0020 0x0 0x10>; 469 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 470 clock-names = "pwm", "pclk"; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&pwm2_pin>; 473 #pwm-cells = <3>; 474 status = "disabled"; 475 }; 476 477 pwm3: pwm@ff1b0030 { 478 compatible = "rockchip,rk3328-pwm"; 479 reg = <0x0 0xff1b0030 0x0 0x10>; 480 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 482 clock-names = "pwm", "pclk"; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&pwmir_pin>; 485 #pwm-cells = <3>; 486 status = "disabled"; 487 }; 488 489 dmac: dmac@ff1f0000 { 490 compatible = "arm,pl330", "arm,primecell"; 491 reg = <0x0 0xff1f0000 0x0 0x4000>; 492 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 494 arm,pl330-periph-burst; 495 clocks = <&cru ACLK_DMAC>; 496 clock-names = "apb_pclk"; 497 #dma-cells = <1>; 498 }; 499 500 thermal-zones { 501 soc_thermal: soc-thermal { 502 polling-delay-passive = <20>; 503 polling-delay = <1000>; 504 sustainable-power = <1000>; 505 506 thermal-sensors = <&tsadc 0>; 507 508 trips { 509 threshold: trip-point0 { 510 temperature = <70000>; 511 hysteresis = <2000>; 512 type = "passive"; 513 }; 514 target: trip-point1 { 515 temperature = <85000>; 516 hysteresis = <2000>; 517 type = "passive"; 518 }; 519 soc_crit: soc-crit { 520 temperature = <95000>; 521 hysteresis = <2000>; 522 type = "critical"; 523 }; 524 }; 525 526 cooling-maps { 527 map0 { 528 trip = <&target>; 529 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 530 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 531 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 532 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 533 contribution = <4096>; 534 }; 535 }; 536 }; 537 538 }; 539 540 tsadc: tsadc@ff250000 { 541 compatible = "rockchip,rk3328-tsadc"; 542 reg = <0x0 0xff250000 0x0 0x100>; 543 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 544 assigned-clocks = <&cru SCLK_TSADC>; 545 assigned-clock-rates = <50000>; 546 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 547 clock-names = "tsadc", "apb_pclk"; 548 pinctrl-names = "init", "default", "sleep"; 549 pinctrl-0 = <&otp_pin>; 550 pinctrl-1 = <&otp_out>; 551 pinctrl-2 = <&otp_pin>; 552 resets = <&cru SRST_TSADC>; 553 reset-names = "tsadc-apb"; 554 rockchip,grf = <&grf>; 555 rockchip,hw-tshut-temp = <100000>; 556 #thermal-sensor-cells = <1>; 557 status = "disabled"; 558 }; 559 560 efuse: efuse@ff260000 { 561 compatible = "rockchip,rk3328-efuse"; 562 reg = <0x0 0xff260000 0x0 0x50>; 563 #address-cells = <1>; 564 #size-cells = <1>; 565 clocks = <&cru SCLK_EFUSE>; 566 clock-names = "pclk_efuse"; 567 rockchip,efuse-size = <0x20>; 568 569 /* Data cells */ 570 efuse_id: id@7 { 571 reg = <0x07 0x10>; 572 }; 573 cpu_leakage: cpu-leakage@17 { 574 reg = <0x17 0x1>; 575 }; 576 logic_leakage: logic-leakage@19 { 577 reg = <0x19 0x1>; 578 }; 579 efuse_cpu_version: cpu-version@1a { 580 reg = <0x1a 0x1>; 581 bits = <3 3>; 582 }; 583 }; 584 585 saradc: adc@ff280000 { 586 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 587 reg = <0x0 0xff280000 0x0 0x100>; 588 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 589 #io-channel-cells = <1>; 590 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 591 clock-names = "saradc", "apb_pclk"; 592 resets = <&cru SRST_SARADC_P>; 593 reset-names = "saradc-apb"; 594 status = "disabled"; 595 }; 596 597 gpu: gpu@ff300000 { 598 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 599 reg = <0x0 0xff300000 0x0 0x40000>; 600 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 607 interrupt-names = "gp", 608 "gpmmu", 609 "pp", 610 "pp0", 611 "ppmmu0", 612 "pp1", 613 "ppmmu1"; 614 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 615 clock-names = "bus", "core"; 616 resets = <&cru SRST_GPU_A>; 617 }; 618 619 h265e_mmu: iommu@ff330200 { 620 compatible = "rockchip,iommu"; 621 reg = <0x0 0xff330200 0 0x100>; 622 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 623 interrupt-names = "h265e_mmu"; 624 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 625 clock-names = "aclk", "iface"; 626 #iommu-cells = <0>; 627 status = "disabled"; 628 }; 629 630 vepu_mmu: iommu@ff340800 { 631 compatible = "rockchip,iommu"; 632 reg = <0x0 0xff340800 0x0 0x40>; 633 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 634 interrupt-names = "vepu_mmu"; 635 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 636 clock-names = "aclk", "iface"; 637 #iommu-cells = <0>; 638 status = "disabled"; 639 }; 640 641 vpu: video-codec@ff350000 { 642 compatible = "rockchip,rk3328-vpu"; 643 reg = <0x0 0xff350000 0x0 0x800>; 644 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 645 interrupt-names = "vdpu"; 646 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 647 clock-names = "aclk", "hclk"; 648 iommus = <&vpu_mmu>; 649 power-domains = <&power RK3328_PD_VPU>; 650 }; 651 652 vpu_mmu: iommu@ff350800 { 653 compatible = "rockchip,iommu"; 654 reg = <0x0 0xff350800 0x0 0x40>; 655 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 656 interrupt-names = "vpu_mmu"; 657 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 658 clock-names = "aclk", "iface"; 659 #iommu-cells = <0>; 660 power-domains = <&power RK3328_PD_VPU>; 661 }; 662 663 rkvdec_mmu: iommu@ff360480 { 664 compatible = "rockchip,iommu"; 665 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 666 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 667 interrupt-names = "rkvdec_mmu"; 668 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 669 clock-names = "aclk", "iface"; 670 #iommu-cells = <0>; 671 status = "disabled"; 672 }; 673 674 vop: vop@ff370000 { 675 compatible = "rockchip,rk3328-vop"; 676 reg = <0x0 0xff370000 0x0 0x3efc>; 677 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 679 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 680 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 681 reset-names = "axi", "ahb", "dclk"; 682 iommus = <&vop_mmu>; 683 status = "disabled"; 684 685 vop_out: port { 686 #address-cells = <1>; 687 #size-cells = <0>; 688 689 vop_out_hdmi: endpoint@0 { 690 reg = <0>; 691 remote-endpoint = <&hdmi_in_vop>; 692 }; 693 }; 694 }; 695 696 vop_mmu: iommu@ff373f00 { 697 compatible = "rockchip,iommu"; 698 reg = <0x0 0xff373f00 0x0 0x100>; 699 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 700 interrupt-names = "vop_mmu"; 701 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 702 clock-names = "aclk", "iface"; 703 #iommu-cells = <0>; 704 status = "disabled"; 705 }; 706 707 hdmi: hdmi@ff3c0000 { 708 compatible = "rockchip,rk3328-dw-hdmi"; 709 reg = <0x0 0xff3c0000 0x0 0x20000>; 710 reg-io-width = <4>; 711 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&cru PCLK_HDMI>, 714 <&cru SCLK_HDMI_SFC>, 715 <&cru SCLK_RTC32K>; 716 clock-names = "iahb", 717 "isfr", 718 "cec"; 719 phys = <&hdmiphy>; 720 phy-names = "hdmi"; 721 pinctrl-names = "default"; 722 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 723 rockchip,grf = <&grf>; 724 #sound-dai-cells = <0>; 725 status = "disabled"; 726 727 ports { 728 hdmi_in: port { 729 hdmi_in_vop: endpoint { 730 remote-endpoint = <&vop_out_hdmi>; 731 }; 732 }; 733 }; 734 }; 735 736 codec: codec@ff410000 { 737 compatible = "rockchip,rk3328-codec"; 738 reg = <0x0 0xff410000 0x0 0x1000>; 739 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 740 clock-names = "pclk", "mclk"; 741 rockchip,grf = <&grf>; 742 #sound-dai-cells = <0>; 743 status = "disabled"; 744 }; 745 746 hdmiphy: phy@ff430000 { 747 compatible = "rockchip,rk3328-hdmi-phy"; 748 reg = <0x0 0xff430000 0x0 0x10000>; 749 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 751 clock-names = "sysclk", "refoclk", "refpclk"; 752 clock-output-names = "hdmi_phy"; 753 #clock-cells = <0>; 754 nvmem-cells = <&efuse_cpu_version>; 755 nvmem-cell-names = "cpu-version"; 756 #phy-cells = <0>; 757 status = "disabled"; 758 }; 759 760 cru: clock-controller@ff440000 { 761 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 762 reg = <0x0 0xff440000 0x0 0x1000>; 763 rockchip,grf = <&grf>; 764 #clock-cells = <1>; 765 #reset-cells = <1>; 766 assigned-clocks = 767 /* 768 * CPLL should run at 1200, but that is to high for 769 * the initial dividers of most of its children. 770 * We need set cpll child clk div first, 771 * and then set the cpll frequency. 772 */ 773 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 774 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 775 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 776 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 777 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 778 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 779 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 780 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 781 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 782 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 783 <&cru SCLK_WIFI>, <&cru ARMCLK>, 784 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 785 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 786 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 787 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 788 <&cru SCLK_RTC32K>; 789 assigned-clock-parents = 790 <&cru HDMIPHY>, <&cru PLL_APLL>, 791 <&cru PLL_GPLL>, <&xin24m>, 792 <&xin24m>, <&xin24m>; 793 assigned-clock-rates = 794 <0>, <61440000>, 795 <0>, <24000000>, 796 <24000000>, <24000000>, 797 <15000000>, <15000000>, 798 <100000000>, <100000000>, 799 <100000000>, <100000000>, 800 <50000000>, <100000000>, 801 <100000000>, <100000000>, 802 <50000000>, <50000000>, 803 <50000000>, <50000000>, 804 <24000000>, <600000000>, 805 <491520000>, <1200000000>, 806 <150000000>, <75000000>, 807 <75000000>, <150000000>, 808 <75000000>, <75000000>, 809 <32768>; 810 }; 811 812 usb2phy_grf: syscon@ff450000 { 813 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 814 "simple-mfd"; 815 reg = <0x0 0xff450000 0x0 0x10000>; 816 #address-cells = <1>; 817 #size-cells = <1>; 818 819 u2phy: usb2-phy@100 { 820 compatible = "rockchip,rk3328-usb2phy"; 821 reg = <0x100 0x10>; 822 clocks = <&xin24m>; 823 clock-names = "phyclk"; 824 clock-output-names = "usb480m_phy"; 825 #clock-cells = <0>; 826 assigned-clocks = <&cru USB480M>; 827 assigned-clock-parents = <&u2phy>; 828 status = "disabled"; 829 830 u2phy_otg: otg-port { 831 #phy-cells = <0>; 832 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 835 interrupt-names = "otg-bvalid", "otg-id", 836 "linestate"; 837 status = "disabled"; 838 }; 839 840 u2phy_host: host-port { 841 #phy-cells = <0>; 842 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 843 interrupt-names = "linestate"; 844 status = "disabled"; 845 }; 846 }; 847 }; 848 849 sdmmc: mmc@ff500000 { 850 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 851 reg = <0x0 0xff500000 0x0 0x4000>; 852 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 854 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 855 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 856 fifo-depth = <0x100>; 857 max-frequency = <150000000>; 858 status = "disabled"; 859 }; 860 861 sdio: mmc@ff510000 { 862 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 863 reg = <0x0 0xff510000 0x0 0x4000>; 864 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 866 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 867 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 868 fifo-depth = <0x100>; 869 max-frequency = <150000000>; 870 status = "disabled"; 871 }; 872 873 emmc: mmc@ff520000 { 874 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 875 reg = <0x0 0xff520000 0x0 0x4000>; 876 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 878 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 879 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 880 fifo-depth = <0x100>; 881 max-frequency = <150000000>; 882 status = "disabled"; 883 }; 884 885 gmac2io: ethernet@ff540000 { 886 compatible = "rockchip,rk3328-gmac"; 887 reg = <0x0 0xff540000 0x0 0x10000>; 888 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 889 interrupt-names = "macirq"; 890 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 891 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 892 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 893 <&cru PCLK_MAC2IO>; 894 clock-names = "stmmaceth", "mac_clk_rx", 895 "mac_clk_tx", "clk_mac_ref", 896 "clk_mac_refout", "aclk_mac", 897 "pclk_mac"; 898 resets = <&cru SRST_GMAC2IO_A>; 899 reset-names = "stmmaceth"; 900 rockchip,grf = <&grf>; 901 snps,txpbl = <0x4>; 902 status = "disabled"; 903 }; 904 905 gmac2phy: ethernet@ff550000 { 906 compatible = "rockchip,rk3328-gmac"; 907 reg = <0x0 0xff550000 0x0 0x10000>; 908 rockchip,grf = <&grf>; 909 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 910 interrupt-names = "macirq"; 911 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 912 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 913 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 914 <&cru SCLK_MAC2PHY_OUT>; 915 clock-names = "stmmaceth", "mac_clk_rx", 916 "mac_clk_tx", "clk_mac_ref", 917 "aclk_mac", "pclk_mac", 918 "clk_macphy"; 919 resets = <&cru SRST_GMAC2PHY_A>; 920 reset-names = "stmmaceth"; 921 phy-mode = "rmii"; 922 phy-handle = <&phy>; 923 snps,txpbl = <0x4>; 924 clock_in_out = "output"; 925 status = "disabled"; 926 927 mdio { 928 compatible = "snps,dwmac-mdio"; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 932 phy: ethernet-phy@0 { 933 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 934 reg = <0>; 935 clocks = <&cru SCLK_MAC2PHY_OUT>; 936 resets = <&cru SRST_MACPHY>; 937 pinctrl-names = "default"; 938 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 939 phy-is-integrated; 940 }; 941 }; 942 }; 943 944 usb20_otg: usb@ff580000 { 945 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 946 "snps,dwc2"; 947 reg = <0x0 0xff580000 0x0 0x40000>; 948 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 949 clocks = <&cru HCLK_OTG>; 950 clock-names = "otg"; 951 dr_mode = "otg"; 952 g-np-tx-fifo-size = <16>; 953 g-rx-fifo-size = <280>; 954 g-tx-fifo-size = <256 128 128 64 32 16>; 955 phys = <&u2phy_otg>; 956 phy-names = "usb2-phy"; 957 status = "disabled"; 958 }; 959 960 usb_host0_ehci: usb@ff5c0000 { 961 compatible = "generic-ehci"; 962 reg = <0x0 0xff5c0000 0x0 0x10000>; 963 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&cru HCLK_HOST0>, <&u2phy>; 965 phys = <&u2phy_host>; 966 phy-names = "usb"; 967 status = "disabled"; 968 }; 969 970 usb_host0_ohci: usb@ff5d0000 { 971 compatible = "generic-ohci"; 972 reg = <0x0 0xff5d0000 0x0 0x10000>; 973 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&cru HCLK_HOST0>, <&u2phy>; 975 phys = <&u2phy_host>; 976 phy-names = "usb"; 977 status = "disabled"; 978 }; 979 980 usbdrd3: usb@ff600000 { 981 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 982 reg = <0x0 0xff600000 0x0 0x100000>; 983 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 985 <&cru ACLK_USB3OTG>; 986 clock-names = "ref_clk", "suspend_clk", 987 "bus_clk"; 988 dr_mode = "otg"; 989 phy_type = "utmi_wide"; 990 snps,dis-del-phy-power-chg-quirk; 991 snps,dis_enblslpm_quirk; 992 snps,dis-tx-ipgap-linecheck-quirk; 993 snps,dis-u2-freeclk-exists-quirk; 994 snps,dis_u2_susphy_quirk; 995 snps,dis_u3_susphy_quirk; 996 status = "disabled"; 997 }; 998 999 gic: interrupt-controller@ff811000 { 1000 compatible = "arm,gic-400"; 1001 #interrupt-cells = <3>; 1002 #address-cells = <0>; 1003 interrupt-controller; 1004 reg = <0x0 0xff811000 0 0x1000>, 1005 <0x0 0xff812000 0 0x2000>, 1006 <0x0 0xff814000 0 0x2000>, 1007 <0x0 0xff816000 0 0x2000>; 1008 interrupts = <GIC_PPI 9 1009 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1010 }; 1011 1012 pinctrl: pinctrl { 1013 compatible = "rockchip,rk3328-pinctrl"; 1014 rockchip,grf = <&grf>; 1015 #address-cells = <2>; 1016 #size-cells = <2>; 1017 ranges; 1018 1019 gpio0: gpio0@ff210000 { 1020 compatible = "rockchip,gpio-bank"; 1021 reg = <0x0 0xff210000 0x0 0x100>; 1022 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&cru PCLK_GPIO0>; 1024 1025 gpio-controller; 1026 #gpio-cells = <2>; 1027 1028 interrupt-controller; 1029 #interrupt-cells = <2>; 1030 }; 1031 1032 gpio1: gpio1@ff220000 { 1033 compatible = "rockchip,gpio-bank"; 1034 reg = <0x0 0xff220000 0x0 0x100>; 1035 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&cru PCLK_GPIO1>; 1037 1038 gpio-controller; 1039 #gpio-cells = <2>; 1040 1041 interrupt-controller; 1042 #interrupt-cells = <2>; 1043 }; 1044 1045 gpio2: gpio2@ff230000 { 1046 compatible = "rockchip,gpio-bank"; 1047 reg = <0x0 0xff230000 0x0 0x100>; 1048 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&cru PCLK_GPIO2>; 1050 1051 gpio-controller; 1052 #gpio-cells = <2>; 1053 1054 interrupt-controller; 1055 #interrupt-cells = <2>; 1056 }; 1057 1058 gpio3: gpio3@ff240000 { 1059 compatible = "rockchip,gpio-bank"; 1060 reg = <0x0 0xff240000 0x0 0x100>; 1061 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&cru PCLK_GPIO3>; 1063 1064 gpio-controller; 1065 #gpio-cells = <2>; 1066 1067 interrupt-controller; 1068 #interrupt-cells = <2>; 1069 }; 1070 1071 pcfg_pull_up: pcfg-pull-up { 1072 bias-pull-up; 1073 }; 1074 1075 pcfg_pull_down: pcfg-pull-down { 1076 bias-pull-down; 1077 }; 1078 1079 pcfg_pull_none: pcfg-pull-none { 1080 bias-disable; 1081 }; 1082 1083 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1084 bias-disable; 1085 drive-strength = <2>; 1086 }; 1087 1088 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1089 bias-pull-up; 1090 drive-strength = <2>; 1091 }; 1092 1093 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1094 bias-pull-up; 1095 drive-strength = <4>; 1096 }; 1097 1098 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1099 bias-disable; 1100 drive-strength = <4>; 1101 }; 1102 1103 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1104 bias-pull-down; 1105 drive-strength = <4>; 1106 }; 1107 1108 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1109 bias-disable; 1110 drive-strength = <8>; 1111 }; 1112 1113 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1114 bias-pull-up; 1115 drive-strength = <8>; 1116 }; 1117 1118 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1119 bias-disable; 1120 drive-strength = <12>; 1121 }; 1122 1123 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1124 bias-pull-up; 1125 drive-strength = <12>; 1126 }; 1127 1128 pcfg_output_high: pcfg-output-high { 1129 output-high; 1130 }; 1131 1132 pcfg_output_low: pcfg-output-low { 1133 output-low; 1134 }; 1135 1136 pcfg_input_high: pcfg-input-high { 1137 bias-pull-up; 1138 input-enable; 1139 }; 1140 1141 pcfg_input: pcfg-input { 1142 input-enable; 1143 }; 1144 1145 i2c0 { 1146 i2c0_xfer: i2c0-xfer { 1147 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1148 <2 RK_PD1 1 &pcfg_pull_none>; 1149 }; 1150 }; 1151 1152 i2c1 { 1153 i2c1_xfer: i2c1-xfer { 1154 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1155 <2 RK_PA5 2 &pcfg_pull_none>; 1156 }; 1157 }; 1158 1159 i2c2 { 1160 i2c2_xfer: i2c2-xfer { 1161 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1162 <2 RK_PB6 1 &pcfg_pull_none>; 1163 }; 1164 }; 1165 1166 i2c3 { 1167 i2c3_xfer: i2c3-xfer { 1168 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1169 <0 RK_PA6 2 &pcfg_pull_none>; 1170 }; 1171 i2c3_pins: i2c3-pins { 1172 rockchip,pins = 1173 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1174 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1175 }; 1176 }; 1177 1178 hdmi_i2c { 1179 hdmii2c_xfer: hdmii2c-xfer { 1180 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1181 <0 RK_PA6 1 &pcfg_pull_none>; 1182 }; 1183 }; 1184 1185 pdm-0 { 1186 pdmm0_clk: pdmm0-clk { 1187 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1188 }; 1189 1190 pdmm0_fsync: pdmm0-fsync { 1191 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1192 }; 1193 1194 pdmm0_sdi0: pdmm0-sdi0 { 1195 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1196 }; 1197 1198 pdmm0_sdi1: pdmm0-sdi1 { 1199 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1200 }; 1201 1202 pdmm0_sdi2: pdmm0-sdi2 { 1203 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1204 }; 1205 1206 pdmm0_sdi3: pdmm0-sdi3 { 1207 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1208 }; 1209 1210 pdmm0_clk_sleep: pdmm0-clk-sleep { 1211 rockchip,pins = 1212 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1213 }; 1214 1215 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1216 rockchip,pins = 1217 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1218 }; 1219 1220 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1221 rockchip,pins = 1222 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1223 }; 1224 1225 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1226 rockchip,pins = 1227 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1228 }; 1229 1230 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1231 rockchip,pins = 1232 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1233 }; 1234 1235 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1236 rockchip,pins = 1237 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1238 }; 1239 }; 1240 1241 tsadc { 1242 otp_pin: otp-pin { 1243 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1244 }; 1245 1246 otp_out: otp-out { 1247 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1248 }; 1249 }; 1250 1251 uart0 { 1252 uart0_xfer: uart0-xfer { 1253 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1254 <1 RK_PB0 1 &pcfg_pull_up>; 1255 }; 1256 1257 uart0_cts: uart0-cts { 1258 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1259 }; 1260 1261 uart0_rts: uart0-rts { 1262 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1263 }; 1264 1265 uart0_rts_pin: uart0-rts-pin { 1266 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1267 }; 1268 }; 1269 1270 uart1 { 1271 uart1_xfer: uart1-xfer { 1272 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1273 <3 RK_PA6 4 &pcfg_pull_up>; 1274 }; 1275 1276 uart1_cts: uart1-cts { 1277 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1278 }; 1279 1280 uart1_rts: uart1-rts { 1281 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1282 }; 1283 1284 uart1_rts_pin: uart1-rts-pin { 1285 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1286 }; 1287 }; 1288 1289 uart2-0 { 1290 uart2m0_xfer: uart2m0-xfer { 1291 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1292 <1 RK_PA1 2 &pcfg_pull_up>; 1293 }; 1294 }; 1295 1296 uart2-1 { 1297 uart2m1_xfer: uart2m1-xfer { 1298 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1299 <2 RK_PA1 1 &pcfg_pull_up>; 1300 }; 1301 }; 1302 1303 spi0-0 { 1304 spi0m0_clk: spi0m0-clk { 1305 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1306 }; 1307 1308 spi0m0_cs0: spi0m0-cs0 { 1309 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1310 }; 1311 1312 spi0m0_tx: spi0m0-tx { 1313 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1314 }; 1315 1316 spi0m0_rx: spi0m0-rx { 1317 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1318 }; 1319 1320 spi0m0_cs1: spi0m0-cs1 { 1321 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1322 }; 1323 }; 1324 1325 spi0-1 { 1326 spi0m1_clk: spi0m1-clk { 1327 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1328 }; 1329 1330 spi0m1_cs0: spi0m1-cs0 { 1331 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1332 }; 1333 1334 spi0m1_tx: spi0m1-tx { 1335 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1336 }; 1337 1338 spi0m1_rx: spi0m1-rx { 1339 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1340 }; 1341 1342 spi0m1_cs1: spi0m1-cs1 { 1343 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1344 }; 1345 }; 1346 1347 spi0-2 { 1348 spi0m2_clk: spi0m2-clk { 1349 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1350 }; 1351 1352 spi0m2_cs0: spi0m2-cs0 { 1353 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1354 }; 1355 1356 spi0m2_tx: spi0m2-tx { 1357 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1358 }; 1359 1360 spi0m2_rx: spi0m2-rx { 1361 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1362 }; 1363 }; 1364 1365 i2s1 { 1366 i2s1_mclk: i2s1-mclk { 1367 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1368 }; 1369 1370 i2s1_sclk: i2s1-sclk { 1371 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1372 }; 1373 1374 i2s1_lrckrx: i2s1-lrckrx { 1375 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1376 }; 1377 1378 i2s1_lrcktx: i2s1-lrcktx { 1379 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1380 }; 1381 1382 i2s1_sdi: i2s1-sdi { 1383 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1384 }; 1385 1386 i2s1_sdo: i2s1-sdo { 1387 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1388 }; 1389 1390 i2s1_sdio1: i2s1-sdio1 { 1391 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1392 }; 1393 1394 i2s1_sdio2: i2s1-sdio2 { 1395 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1396 }; 1397 1398 i2s1_sdio3: i2s1-sdio3 { 1399 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1400 }; 1401 1402 i2s1_sleep: i2s1-sleep { 1403 rockchip,pins = 1404 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1405 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1406 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1407 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1408 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1409 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1410 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1411 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1412 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1413 }; 1414 }; 1415 1416 i2s2-0 { 1417 i2s2m0_mclk: i2s2m0-mclk { 1418 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1419 }; 1420 1421 i2s2m0_sclk: i2s2m0-sclk { 1422 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1423 }; 1424 1425 i2s2m0_lrckrx: i2s2m0-lrckrx { 1426 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1427 }; 1428 1429 i2s2m0_lrcktx: i2s2m0-lrcktx { 1430 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1431 }; 1432 1433 i2s2m0_sdi: i2s2m0-sdi { 1434 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1435 }; 1436 1437 i2s2m0_sdo: i2s2m0-sdo { 1438 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1439 }; 1440 1441 i2s2m0_sleep: i2s2m0-sleep { 1442 rockchip,pins = 1443 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1444 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1445 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1446 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1447 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1448 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1449 }; 1450 }; 1451 1452 i2s2-1 { 1453 i2s2m1_mclk: i2s2m1-mclk { 1454 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1455 }; 1456 1457 i2s2m1_sclk: i2s2m1-sclk { 1458 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1459 }; 1460 1461 i2s2m1_lrckrx: i2sm1-lrckrx { 1462 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1463 }; 1464 1465 i2s2m1_lrcktx: i2s2m1-lrcktx { 1466 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1467 }; 1468 1469 i2s2m1_sdi: i2s2m1-sdi { 1470 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1471 }; 1472 1473 i2s2m1_sdo: i2s2m1-sdo { 1474 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1475 }; 1476 1477 i2s2m1_sleep: i2s2m1-sleep { 1478 rockchip,pins = 1479 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1480 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1481 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1482 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1483 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1484 }; 1485 }; 1486 1487 spdif-0 { 1488 spdifm0_tx: spdifm0-tx { 1489 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1490 }; 1491 }; 1492 1493 spdif-1 { 1494 spdifm1_tx: spdifm1-tx { 1495 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1496 }; 1497 }; 1498 1499 spdif-2 { 1500 spdifm2_tx: spdifm2-tx { 1501 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1502 }; 1503 }; 1504 1505 sdmmc0-0 { 1506 sdmmc0m0_pwren: sdmmc0m0-pwren { 1507 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1508 }; 1509 1510 sdmmc0m0_pin: sdmmc0m0-pin { 1511 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1512 }; 1513 }; 1514 1515 sdmmc0-1 { 1516 sdmmc0m1_pwren: sdmmc0m1-pwren { 1517 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1518 }; 1519 1520 sdmmc0m1_pin: sdmmc0m1-pin { 1521 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1522 }; 1523 }; 1524 1525 sdmmc0 { 1526 sdmmc0_clk: sdmmc0-clk { 1527 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1528 }; 1529 1530 sdmmc0_cmd: sdmmc0-cmd { 1531 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1532 }; 1533 1534 sdmmc0_dectn: sdmmc0-dectn { 1535 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1536 }; 1537 1538 sdmmc0_wrprt: sdmmc0-wrprt { 1539 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1540 }; 1541 1542 sdmmc0_bus1: sdmmc0-bus1 { 1543 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1544 }; 1545 1546 sdmmc0_bus4: sdmmc0-bus4 { 1547 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1548 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1549 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1550 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1551 }; 1552 1553 sdmmc0_pins: sdmmc0-pins { 1554 rockchip,pins = 1555 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1556 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1557 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1558 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1559 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1560 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1561 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1562 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1563 }; 1564 }; 1565 1566 sdmmc0ext { 1567 sdmmc0ext_clk: sdmmc0ext-clk { 1568 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1569 }; 1570 1571 sdmmc0ext_cmd: sdmmc0ext-cmd { 1572 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1573 }; 1574 1575 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1576 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1577 }; 1578 1579 sdmmc0ext_dectn: sdmmc0ext-dectn { 1580 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1581 }; 1582 1583 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1584 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1585 }; 1586 1587 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1588 rockchip,pins = 1589 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1590 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1591 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1592 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1593 }; 1594 1595 sdmmc0ext_pins: sdmmc0ext-pins { 1596 rockchip,pins = 1597 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1598 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1599 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1600 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1601 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1602 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1603 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1604 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1605 }; 1606 }; 1607 1608 sdmmc1 { 1609 sdmmc1_clk: sdmmc1-clk { 1610 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1611 }; 1612 1613 sdmmc1_cmd: sdmmc1-cmd { 1614 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1615 }; 1616 1617 sdmmc1_pwren: sdmmc1-pwren { 1618 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1619 }; 1620 1621 sdmmc1_wrprt: sdmmc1-wrprt { 1622 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1623 }; 1624 1625 sdmmc1_dectn: sdmmc1-dectn { 1626 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1627 }; 1628 1629 sdmmc1_bus1: sdmmc1-bus1 { 1630 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1631 }; 1632 1633 sdmmc1_bus4: sdmmc1-bus4 { 1634 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1635 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1636 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1637 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1638 }; 1639 1640 sdmmc1_pins: sdmmc1-pins { 1641 rockchip,pins = 1642 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1643 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1644 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1645 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1646 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1647 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1648 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1649 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1650 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1651 }; 1652 }; 1653 1654 emmc { 1655 emmc_clk: emmc-clk { 1656 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1657 }; 1658 1659 emmc_cmd: emmc-cmd { 1660 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1661 }; 1662 1663 emmc_pwren: emmc-pwren { 1664 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1665 }; 1666 1667 emmc_rstnout: emmc-rstnout { 1668 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1669 }; 1670 1671 emmc_bus1: emmc-bus1 { 1672 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1673 }; 1674 1675 emmc_bus4: emmc-bus4 { 1676 rockchip,pins = 1677 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1678 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1679 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1680 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1681 }; 1682 1683 emmc_bus8: emmc-bus8 { 1684 rockchip,pins = 1685 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1686 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1687 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1688 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1689 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1690 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1691 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1692 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1693 }; 1694 }; 1695 1696 pwm0 { 1697 pwm0_pin: pwm0-pin { 1698 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1699 }; 1700 }; 1701 1702 pwm1 { 1703 pwm1_pin: pwm1-pin { 1704 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1705 }; 1706 }; 1707 1708 pwm2 { 1709 pwm2_pin: pwm2-pin { 1710 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1711 }; 1712 }; 1713 1714 pwmir { 1715 pwmir_pin: pwmir-pin { 1716 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1717 }; 1718 }; 1719 1720 gmac-1 { 1721 rgmiim1_pins: rgmiim1-pins { 1722 rockchip,pins = 1723 /* mac_txclk */ 1724 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1725 /* mac_rxclk */ 1726 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1727 /* mac_mdio */ 1728 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1729 /* mac_txen */ 1730 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1731 /* mac_clk */ 1732 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1733 /* mac_rxdv */ 1734 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1735 /* mac_mdc */ 1736 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1737 /* mac_rxd1 */ 1738 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1739 /* mac_rxd0 */ 1740 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1741 /* mac_txd1 */ 1742 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1743 /* mac_txd0 */ 1744 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1745 /* mac_rxd3 */ 1746 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1747 /* mac_rxd2 */ 1748 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1749 /* mac_txd3 */ 1750 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1751 /* mac_txd2 */ 1752 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1753 1754 /* mac_txclk */ 1755 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1756 /* mac_txen */ 1757 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1758 /* mac_clk */ 1759 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1760 /* mac_txd1 */ 1761 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1762 /* mac_txd0 */ 1763 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1764 /* mac_txd3 */ 1765 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1766 /* mac_txd2 */ 1767 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1768 }; 1769 1770 rmiim1_pins: rmiim1-pins { 1771 rockchip,pins = 1772 /* mac_mdio */ 1773 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1774 /* mac_txen */ 1775 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1776 /* mac_clk */ 1777 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1778 /* mac_rxer */ 1779 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1780 /* mac_rxdv */ 1781 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1782 /* mac_mdc */ 1783 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1784 /* mac_rxd1 */ 1785 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1786 /* mac_rxd0 */ 1787 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1788 /* mac_txd1 */ 1789 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1790 /* mac_txd0 */ 1791 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1792 1793 /* mac_mdio */ 1794 <0 RK_PB3 1 &pcfg_pull_none>, 1795 /* mac_txen */ 1796 <0 RK_PB4 1 &pcfg_pull_none>, 1797 /* mac_clk */ 1798 <0 RK_PD0 1 &pcfg_pull_none>, 1799 /* mac_mdc */ 1800 <0 RK_PC3 1 &pcfg_pull_none>, 1801 /* mac_txd1 */ 1802 <0 RK_PC0 1 &pcfg_pull_none>, 1803 /* mac_txd0 */ 1804 <0 RK_PC1 1 &pcfg_pull_none>; 1805 }; 1806 }; 1807 1808 gmac2phy { 1809 fephyled_speed10: fephyled-speed10 { 1810 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1811 }; 1812 1813 fephyled_duplex: fephyled-duplex { 1814 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1815 }; 1816 1817 fephyled_rxm1: fephyled-rxm1 { 1818 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1819 }; 1820 1821 fephyled_txm1: fephyled-txm1 { 1822 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1823 }; 1824 1825 fephyled_linkm1: fephyled-linkm1 { 1826 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1827 }; 1828 }; 1829 1830 tsadc_pin { 1831 tsadc_int: tsadc-int { 1832 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1833 }; 1834 tsadc_pin: tsadc-pin { 1835 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1836 }; 1837 }; 1838 1839 hdmi_pin { 1840 hdmi_cec: hdmi-cec { 1841 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1842 }; 1843 1844 hdmi_hpd: hdmi-hpd { 1845 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1846 }; 1847 }; 1848 1849 cif-0 { 1850 dvp_d2d9_m0:dvp-d2d9-m0 { 1851 rockchip,pins = 1852 /* cif_d0 */ 1853 <3 RK_PA4 2 &pcfg_pull_none>, 1854 /* cif_d1 */ 1855 <3 RK_PA5 2 &pcfg_pull_none>, 1856 /* cif_d2 */ 1857 <3 RK_PA6 2 &pcfg_pull_none>, 1858 /* cif_d3 */ 1859 <3 RK_PA7 2 &pcfg_pull_none>, 1860 /* cif_d4 */ 1861 <3 RK_PB0 2 &pcfg_pull_none>, 1862 /* cif_d5m0 */ 1863 <3 RK_PB1 2 &pcfg_pull_none>, 1864 /* cif_d6m0 */ 1865 <3 RK_PB2 2 &pcfg_pull_none>, 1866 /* cif_d7m0 */ 1867 <3 RK_PB3 2 &pcfg_pull_none>, 1868 /* cif_href */ 1869 <3 RK_PA1 2 &pcfg_pull_none>, 1870 /* cif_vsync */ 1871 <3 RK_PA0 2 &pcfg_pull_none>, 1872 /* cif_clkoutm0 */ 1873 <3 RK_PA3 2 &pcfg_pull_none>, 1874 /* cif_clkin */ 1875 <3 RK_PA2 2 &pcfg_pull_none>; 1876 }; 1877 }; 1878 1879 cif-1 { 1880 dvp_d2d9_m1:dvp-d2d9-m1 { 1881 rockchip,pins = 1882 /* cif_d0 */ 1883 <3 RK_PA4 2 &pcfg_pull_none>, 1884 /* cif_d1 */ 1885 <3 RK_PA5 2 &pcfg_pull_none>, 1886 /* cif_d2 */ 1887 <3 RK_PA6 2 &pcfg_pull_none>, 1888 /* cif_d3 */ 1889 <3 RK_PA7 2 &pcfg_pull_none>, 1890 /* cif_d4 */ 1891 <3 RK_PB0 2 &pcfg_pull_none>, 1892 /* cif_d5m1 */ 1893 <2 RK_PC0 4 &pcfg_pull_none>, 1894 /* cif_d6m1 */ 1895 <2 RK_PC1 4 &pcfg_pull_none>, 1896 /* cif_d7m1 */ 1897 <2 RK_PC2 4 &pcfg_pull_none>, 1898 /* cif_href */ 1899 <3 RK_PA1 2 &pcfg_pull_none>, 1900 /* cif_vsync */ 1901 <3 RK_PA0 2 &pcfg_pull_none>, 1902 /* cif_clkoutm1 */ 1903 <2 RK_PB7 4 &pcfg_pull_none>, 1904 /* cif_clkin */ 1905 <3 RK_PA2 2 &pcfg_pull_none>; 1906 }; 1907 }; 1908 }; 1909}; 1910