1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 cpu-idle-states = <&CPU_SLEEP>; 45 dynamic-power-coefficient = <120>; 46 enable-method = "psci"; 47 next-level-cache = <&l2>; 48 operating-points-v2 = <&cpu0_opp_table>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x0 0x1>; 55 clocks = <&cru ARMCLK>; 56 #cooling-cells = <2>; 57 cpu-idle-states = <&CPU_SLEEP>; 58 dynamic-power-coefficient = <120>; 59 enable-method = "psci"; 60 next-level-cache = <&l2>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0 0x2>; 68 clocks = <&cru ARMCLK>; 69 #cooling-cells = <2>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 dynamic-power-coefficient = <120>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 }; 76 77 cpu3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x0 0x3>; 81 clocks = <&cru ARMCLK>; 82 #cooling-cells = <2>; 83 cpu-idle-states = <&CPU_SLEEP>; 84 dynamic-power-coefficient = <120>; 85 enable-method = "psci"; 86 next-level-cache = <&l2>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 }; 102 103 l2: l2-cache0 { 104 compatible = "cache"; 105 }; 106 }; 107 108 cpu0_opp_table: opp_table0 { 109 compatible = "operating-points-v2"; 110 opp-shared; 111 112 opp-408000000 { 113 opp-hz = /bits/ 64 <408000000>; 114 opp-microvolt = <950000>; 115 clock-latency-ns = <40000>; 116 opp-suspend; 117 }; 118 opp-600000000 { 119 opp-hz = /bits/ 64 <600000000>; 120 opp-microvolt = <950000>; 121 clock-latency-ns = <40000>; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1000000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1100000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1225000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1300000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 amba: bus { 146 compatible = "simple-bus"; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 151 dmac: dmac@ff1f0000 { 152 compatible = "arm,pl330", "arm,primecell"; 153 reg = <0x0 0xff1f0000 0x0 0x4000>; 154 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&cru ACLK_DMAC>; 157 clock-names = "apb_pclk"; 158 #dma-cells = <1>; 159 }; 160 }; 161 162 analog_sound: analog-sound { 163 compatible = "simple-audio-card"; 164 simple-audio-card,format = "i2s"; 165 simple-audio-card,mclk-fs = <256>; 166 simple-audio-card,name = "Analog"; 167 status = "disabled"; 168 169 simple-audio-card,cpu { 170 sound-dai = <&i2s1>; 171 }; 172 173 simple-audio-card,codec { 174 sound-dai = <&codec>; 175 }; 176 }; 177 178 arm-pmu { 179 compatible = "arm,cortex-a53-pmu"; 180 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 185 }; 186 187 display_subsystem: display-subsystem { 188 compatible = "rockchip,display-subsystem"; 189 ports = <&vop_out>; 190 }; 191 192 hdmi_sound: hdmi-sound { 193 compatible = "simple-audio-card"; 194 simple-audio-card,format = "i2s"; 195 simple-audio-card,mclk-fs = <128>; 196 simple-audio-card,name = "HDMI"; 197 status = "disabled"; 198 199 simple-audio-card,cpu { 200 sound-dai = <&i2s0>; 201 }; 202 203 simple-audio-card,codec { 204 sound-dai = <&hdmi>; 205 }; 206 }; 207 208 psci { 209 compatible = "arm,psci-1.0", "arm,psci-0.2"; 210 method = "smc"; 211 }; 212 213 timer { 214 compatible = "arm,armv8-timer"; 215 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 216 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 218 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 219 }; 220 221 xin24m: xin24m { 222 compatible = "fixed-clock"; 223 #clock-cells = <0>; 224 clock-frequency = <24000000>; 225 clock-output-names = "xin24m"; 226 }; 227 228 i2s0: i2s@ff000000 { 229 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 230 reg = <0x0 0xff000000 0x0 0x1000>; 231 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 233 clock-names = "i2s_clk", "i2s_hclk"; 234 dmas = <&dmac 11>, <&dmac 12>; 235 dma-names = "tx", "rx"; 236 #sound-dai-cells = <0>; 237 status = "disabled"; 238 }; 239 240 i2s1: i2s@ff010000 { 241 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 242 reg = <0x0 0xff010000 0x0 0x1000>; 243 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 245 clock-names = "i2s_clk", "i2s_hclk"; 246 dmas = <&dmac 14>, <&dmac 15>; 247 dma-names = "tx", "rx"; 248 #sound-dai-cells = <0>; 249 status = "disabled"; 250 }; 251 252 i2s2: i2s@ff020000 { 253 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 254 reg = <0x0 0xff020000 0x0 0x1000>; 255 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 257 clock-names = "i2s_clk", "i2s_hclk"; 258 dmas = <&dmac 0>, <&dmac 1>; 259 dma-names = "tx", "rx"; 260 #sound-dai-cells = <0>; 261 status = "disabled"; 262 }; 263 264 spdif: spdif@ff030000 { 265 compatible = "rockchip,rk3328-spdif"; 266 reg = <0x0 0xff030000 0x0 0x1000>; 267 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 269 clock-names = "mclk", "hclk"; 270 dmas = <&dmac 10>; 271 dma-names = "tx"; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&spdifm2_tx>; 274 #sound-dai-cells = <0>; 275 status = "disabled"; 276 }; 277 278 pdm: pdm@ff040000 { 279 compatible = "rockchip,pdm"; 280 reg = <0x0 0xff040000 0x0 0x1000>; 281 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 282 clock-names = "pdm_clk", "pdm_hclk"; 283 dmas = <&dmac 16>; 284 dma-names = "rx"; 285 pinctrl-names = "default", "sleep"; 286 pinctrl-0 = <&pdmm0_clk 287 &pdmm0_sdi0 288 &pdmm0_sdi1 289 &pdmm0_sdi2 290 &pdmm0_sdi3>; 291 pinctrl-1 = <&pdmm0_clk_sleep 292 &pdmm0_sdi0_sleep 293 &pdmm0_sdi1_sleep 294 &pdmm0_sdi2_sleep 295 &pdmm0_sdi3_sleep>; 296 status = "disabled"; 297 }; 298 299 grf: syscon@ff100000 { 300 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 301 reg = <0x0 0xff100000 0x0 0x1000>; 302 303 io_domains: io-domains { 304 compatible = "rockchip,rk3328-io-voltage-domain"; 305 status = "disabled"; 306 }; 307 308 grf_gpio: grf-gpio { 309 compatible = "rockchip,rk3328-grf-gpio"; 310 gpio-controller; 311 #gpio-cells = <2>; 312 }; 313 314 power: power-controller { 315 compatible = "rockchip,rk3328-power-controller"; 316 #power-domain-cells = <1>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 320 pd_hevc@RK3328_PD_HEVC { 321 reg = <RK3328_PD_HEVC>; 322 }; 323 pd_video@RK3328_PD_VIDEO { 324 reg = <RK3328_PD_VIDEO>; 325 }; 326 pd_vpu@RK3328_PD_VPU { 327 reg = <RK3328_PD_VPU>; 328 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 329 }; 330 }; 331 332 reboot-mode { 333 compatible = "syscon-reboot-mode"; 334 offset = <0x5c8>; 335 mode-normal = <BOOT_NORMAL>; 336 mode-recovery = <BOOT_RECOVERY>; 337 mode-bootloader = <BOOT_FASTBOOT>; 338 mode-loader = <BOOT_BL_DOWNLOAD>; 339 }; 340 }; 341 342 uart0: serial@ff110000 { 343 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 344 reg = <0x0 0xff110000 0x0 0x100>; 345 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 347 clock-names = "baudclk", "apb_pclk"; 348 dmas = <&dmac 2>, <&dmac 3>; 349 dma-names = "tx", "rx"; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 352 reg-io-width = <4>; 353 reg-shift = <2>; 354 status = "disabled"; 355 }; 356 357 uart1: serial@ff120000 { 358 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 359 reg = <0x0 0xff120000 0x0 0x100>; 360 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 362 clock-names = "baudclk", "apb_pclk"; 363 dmas = <&dmac 4>, <&dmac 5>; 364 dma-names = "tx", "rx"; 365 pinctrl-names = "default"; 366 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 367 reg-io-width = <4>; 368 reg-shift = <2>; 369 status = "disabled"; 370 }; 371 372 uart2: serial@ff130000 { 373 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 374 reg = <0x0 0xff130000 0x0 0x100>; 375 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 377 clock-names = "baudclk", "apb_pclk"; 378 dmas = <&dmac 6>, <&dmac 7>; 379 dma-names = "tx", "rx"; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&uart2m1_xfer>; 382 reg-io-width = <4>; 383 reg-shift = <2>; 384 status = "disabled"; 385 }; 386 387 i2c0: i2c@ff150000 { 388 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 389 reg = <0x0 0xff150000 0x0 0x1000>; 390 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 394 clock-names = "i2c", "pclk"; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&i2c0_xfer>; 397 status = "disabled"; 398 }; 399 400 i2c1: i2c@ff160000 { 401 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 402 reg = <0x0 0xff160000 0x0 0x1000>; 403 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 407 clock-names = "i2c", "pclk"; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&i2c1_xfer>; 410 status = "disabled"; 411 }; 412 413 i2c2: i2c@ff170000 { 414 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 415 reg = <0x0 0xff170000 0x0 0x1000>; 416 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 420 clock-names = "i2c", "pclk"; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&i2c2_xfer>; 423 status = "disabled"; 424 }; 425 426 i2c3: i2c@ff180000 { 427 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 428 reg = <0x0 0xff180000 0x0 0x1000>; 429 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 433 clock-names = "i2c", "pclk"; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&i2c3_xfer>; 436 status = "disabled"; 437 }; 438 439 spi0: spi@ff190000 { 440 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 441 reg = <0x0 0xff190000 0x0 0x1000>; 442 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 446 clock-names = "spiclk", "apb_pclk"; 447 dmas = <&dmac 8>, <&dmac 9>; 448 dma-names = "tx", "rx"; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 451 status = "disabled"; 452 }; 453 454 wdt: watchdog@ff1a0000 { 455 compatible = "snps,dw-wdt"; 456 reg = <0x0 0xff1a0000 0x0 0x100>; 457 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&cru PCLK_WDT>; 459 }; 460 461 pwm0: pwm@ff1b0000 { 462 compatible = "rockchip,rk3328-pwm"; 463 reg = <0x0 0xff1b0000 0x0 0x10>; 464 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 465 clock-names = "pwm", "pclk"; 466 pinctrl-names = "default"; 467 pinctrl-0 = <&pwm0_pin>; 468 #pwm-cells = <3>; 469 status = "disabled"; 470 }; 471 472 pwm1: pwm@ff1b0010 { 473 compatible = "rockchip,rk3328-pwm"; 474 reg = <0x0 0xff1b0010 0x0 0x10>; 475 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 476 clock-names = "pwm", "pclk"; 477 pinctrl-names = "default"; 478 pinctrl-0 = <&pwm1_pin>; 479 #pwm-cells = <3>; 480 status = "disabled"; 481 }; 482 483 pwm2: pwm@ff1b0020 { 484 compatible = "rockchip,rk3328-pwm"; 485 reg = <0x0 0xff1b0020 0x0 0x10>; 486 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 487 clock-names = "pwm", "pclk"; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pwm2_pin>; 490 #pwm-cells = <3>; 491 status = "disabled"; 492 }; 493 494 pwm3: pwm@ff1b0030 { 495 compatible = "rockchip,rk3328-pwm"; 496 reg = <0x0 0xff1b0030 0x0 0x10>; 497 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 499 clock-names = "pwm", "pclk"; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&pwmir_pin>; 502 #pwm-cells = <3>; 503 status = "disabled"; 504 }; 505 506 thermal-zones { 507 soc_thermal: soc-thermal { 508 polling-delay-passive = <20>; 509 polling-delay = <1000>; 510 sustainable-power = <1000>; 511 512 thermal-sensors = <&tsadc 0>; 513 514 trips { 515 threshold: trip-point0 { 516 temperature = <70000>; 517 hysteresis = <2000>; 518 type = "passive"; 519 }; 520 target: trip-point1 { 521 temperature = <85000>; 522 hysteresis = <2000>; 523 type = "passive"; 524 }; 525 soc_crit: soc-crit { 526 temperature = <95000>; 527 hysteresis = <2000>; 528 type = "critical"; 529 }; 530 }; 531 532 cooling-maps { 533 map0 { 534 trip = <&target>; 535 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 536 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 537 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 538 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 539 contribution = <4096>; 540 }; 541 }; 542 }; 543 544 }; 545 546 tsadc: tsadc@ff250000 { 547 compatible = "rockchip,rk3328-tsadc"; 548 reg = <0x0 0xff250000 0x0 0x100>; 549 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 550 assigned-clocks = <&cru SCLK_TSADC>; 551 assigned-clock-rates = <50000>; 552 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 553 clock-names = "tsadc", "apb_pclk"; 554 pinctrl-names = "init", "default", "sleep"; 555 pinctrl-0 = <&otp_gpio>; 556 pinctrl-1 = <&otp_out>; 557 pinctrl-2 = <&otp_gpio>; 558 resets = <&cru SRST_TSADC>; 559 reset-names = "tsadc-apb"; 560 rockchip,grf = <&grf>; 561 rockchip,hw-tshut-temp = <100000>; 562 #thermal-sensor-cells = <1>; 563 status = "disabled"; 564 }; 565 566 efuse: efuse@ff260000 { 567 compatible = "rockchip,rk3328-efuse"; 568 reg = <0x0 0xff260000 0x0 0x50>; 569 #address-cells = <1>; 570 #size-cells = <1>; 571 clocks = <&cru SCLK_EFUSE>; 572 clock-names = "pclk_efuse"; 573 rockchip,efuse-size = <0x20>; 574 575 /* Data cells */ 576 efuse_id: id@7 { 577 reg = <0x07 0x10>; 578 }; 579 cpu_leakage: cpu-leakage@17 { 580 reg = <0x17 0x1>; 581 }; 582 logic_leakage: logic-leakage@19 { 583 reg = <0x19 0x1>; 584 }; 585 efuse_cpu_version: cpu-version@1a { 586 reg = <0x1a 0x1>; 587 bits = <3 3>; 588 }; 589 }; 590 591 saradc: adc@ff280000 { 592 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 593 reg = <0x0 0xff280000 0x0 0x100>; 594 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 595 #io-channel-cells = <1>; 596 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 597 clock-names = "saradc", "apb_pclk"; 598 resets = <&cru SRST_SARADC_P>; 599 reset-names = "saradc-apb"; 600 status = "disabled"; 601 }; 602 603 gpu: gpu@ff300000 { 604 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 605 reg = <0x0 0xff300000 0x0 0x40000>; 606 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 613 interrupt-names = "gp", 614 "gpmmu", 615 "pp", 616 "pp0", 617 "ppmmu0", 618 "pp1", 619 "ppmmu1"; 620 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 621 clock-names = "bus", "core"; 622 resets = <&cru SRST_GPU_A>; 623 }; 624 625 h265e_mmu: iommu@ff330200 { 626 compatible = "rockchip,iommu"; 627 reg = <0x0 0xff330200 0 0x100>; 628 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 629 interrupt-names = "h265e_mmu"; 630 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 631 clock-names = "aclk", "iface"; 632 #iommu-cells = <0>; 633 status = "disabled"; 634 }; 635 636 vepu_mmu: iommu@ff340800 { 637 compatible = "rockchip,iommu"; 638 reg = <0x0 0xff340800 0x0 0x40>; 639 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 640 interrupt-names = "vepu_mmu"; 641 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 642 clock-names = "aclk", "iface"; 643 #iommu-cells = <0>; 644 status = "disabled"; 645 }; 646 647 vpu: video-codec@ff350000 { 648 compatible = "rockchip,rk3328-vpu"; 649 reg = <0x0 0xff350000 0x0 0x800>; 650 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-names = "vdpu"; 652 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 653 clock-names = "aclk", "hclk"; 654 iommus = <&vpu_mmu>; 655 power-domains = <&power RK3328_PD_VPU>; 656 }; 657 658 vpu_mmu: iommu@ff350800 { 659 compatible = "rockchip,iommu"; 660 reg = <0x0 0xff350800 0x0 0x40>; 661 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 662 interrupt-names = "vpu_mmu"; 663 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 664 clock-names = "aclk", "iface"; 665 #iommu-cells = <0>; 666 power-domains = <&power RK3328_PD_VPU>; 667 }; 668 669 rkvdec_mmu: iommu@ff360480 { 670 compatible = "rockchip,iommu"; 671 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 672 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 673 interrupt-names = "rkvdec_mmu"; 674 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 675 clock-names = "aclk", "iface"; 676 #iommu-cells = <0>; 677 status = "disabled"; 678 }; 679 680 vop: vop@ff370000 { 681 compatible = "rockchip,rk3328-vop"; 682 reg = <0x0 0xff370000 0x0 0x3efc>; 683 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 685 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 686 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 687 reset-names = "axi", "ahb", "dclk"; 688 iommus = <&vop_mmu>; 689 status = "disabled"; 690 691 vop_out: port { 692 #address-cells = <1>; 693 #size-cells = <0>; 694 695 vop_out_hdmi: endpoint@0 { 696 reg = <0>; 697 remote-endpoint = <&hdmi_in_vop>; 698 }; 699 }; 700 }; 701 702 vop_mmu: iommu@ff373f00 { 703 compatible = "rockchip,iommu"; 704 reg = <0x0 0xff373f00 0x0 0x100>; 705 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 706 interrupt-names = "vop_mmu"; 707 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 708 clock-names = "aclk", "iface"; 709 #iommu-cells = <0>; 710 status = "disabled"; 711 }; 712 713 hdmi: hdmi@ff3c0000 { 714 compatible = "rockchip,rk3328-dw-hdmi"; 715 reg = <0x0 0xff3c0000 0x0 0x20000>; 716 reg-io-width = <4>; 717 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cru PCLK_HDMI>, 720 <&cru SCLK_HDMI_SFC>, 721 <&cru SCLK_RTC32K>; 722 clock-names = "iahb", 723 "isfr", 724 "cec"; 725 phys = <&hdmiphy>; 726 phy-names = "hdmi"; 727 pinctrl-names = "default"; 728 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 729 rockchip,grf = <&grf>; 730 #sound-dai-cells = <0>; 731 status = "disabled"; 732 733 ports { 734 hdmi_in: port { 735 hdmi_in_vop: endpoint { 736 remote-endpoint = <&vop_out_hdmi>; 737 }; 738 }; 739 }; 740 }; 741 742 codec: codec@ff410000 { 743 compatible = "rockchip,rk3328-codec"; 744 reg = <0x0 0xff410000 0x0 0x1000>; 745 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 746 clock-names = "pclk", "mclk"; 747 rockchip,grf = <&grf>; 748 #sound-dai-cells = <0>; 749 status = "disabled"; 750 }; 751 752 hdmiphy: phy@ff430000 { 753 compatible = "rockchip,rk3328-hdmi-phy"; 754 reg = <0x0 0xff430000 0x0 0x10000>; 755 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 757 clock-names = "sysclk", "refoclk", "refpclk"; 758 clock-output-names = "hdmi_phy"; 759 #clock-cells = <0>; 760 nvmem-cells = <&efuse_cpu_version>; 761 nvmem-cell-names = "cpu-version"; 762 #phy-cells = <0>; 763 status = "disabled"; 764 }; 765 766 cru: clock-controller@ff440000 { 767 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 768 reg = <0x0 0xff440000 0x0 0x1000>; 769 rockchip,grf = <&grf>; 770 #clock-cells = <1>; 771 #reset-cells = <1>; 772 assigned-clocks = 773 /* 774 * CPLL should run at 1200, but that is to high for 775 * the initial dividers of most of its children. 776 * We need set cpll child clk div first, 777 * and then set the cpll frequency. 778 */ 779 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 780 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 781 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 782 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 783 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 784 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 785 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 786 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 787 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 788 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 789 <&cru SCLK_WIFI>, <&cru ARMCLK>, 790 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 791 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 792 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 793 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 794 <&cru SCLK_RTC32K>; 795 assigned-clock-parents = 796 <&cru HDMIPHY>, <&cru PLL_APLL>, 797 <&cru PLL_GPLL>, <&xin24m>, 798 <&xin24m>, <&xin24m>; 799 assigned-clock-rates = 800 <0>, <61440000>, 801 <0>, <24000000>, 802 <24000000>, <24000000>, 803 <15000000>, <15000000>, 804 <100000000>, <100000000>, 805 <100000000>, <100000000>, 806 <50000000>, <100000000>, 807 <100000000>, <100000000>, 808 <50000000>, <50000000>, 809 <50000000>, <50000000>, 810 <24000000>, <600000000>, 811 <491520000>, <1200000000>, 812 <150000000>, <75000000>, 813 <75000000>, <150000000>, 814 <75000000>, <75000000>, 815 <32768>; 816 }; 817 818 usb2phy_grf: syscon@ff450000 { 819 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 820 "simple-mfd"; 821 reg = <0x0 0xff450000 0x0 0x10000>; 822 #address-cells = <1>; 823 #size-cells = <1>; 824 825 u2phy: usb2-phy@100 { 826 compatible = "rockchip,rk3328-usb2phy"; 827 reg = <0x100 0x10>; 828 clocks = <&xin24m>; 829 clock-names = "phyclk"; 830 clock-output-names = "usb480m_phy"; 831 #clock-cells = <0>; 832 assigned-clocks = <&cru USB480M>; 833 assigned-clock-parents = <&u2phy>; 834 status = "disabled"; 835 836 u2phy_otg: otg-port { 837 #phy-cells = <0>; 838 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 841 interrupt-names = "otg-bvalid", "otg-id", 842 "linestate"; 843 status = "disabled"; 844 }; 845 846 u2phy_host: host-port { 847 #phy-cells = <0>; 848 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 849 interrupt-names = "linestate"; 850 status = "disabled"; 851 }; 852 }; 853 }; 854 855 sdmmc: mmc@ff500000 { 856 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 857 reg = <0x0 0xff500000 0x0 0x4000>; 858 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 860 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 861 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 862 fifo-depth = <0x100>; 863 max-frequency = <150000000>; 864 status = "disabled"; 865 }; 866 867 sdio: mmc@ff510000 { 868 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 869 reg = <0x0 0xff510000 0x0 0x4000>; 870 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 872 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 873 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 874 fifo-depth = <0x100>; 875 max-frequency = <150000000>; 876 status = "disabled"; 877 }; 878 879 emmc: mmc@ff520000 { 880 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 881 reg = <0x0 0xff520000 0x0 0x4000>; 882 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 884 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 885 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 886 fifo-depth = <0x100>; 887 max-frequency = <150000000>; 888 status = "disabled"; 889 }; 890 891 gmac2io: ethernet@ff540000 { 892 compatible = "rockchip,rk3328-gmac"; 893 reg = <0x0 0xff540000 0x0 0x10000>; 894 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 895 interrupt-names = "macirq"; 896 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 897 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 898 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 899 <&cru PCLK_MAC2IO>; 900 clock-names = "stmmaceth", "mac_clk_rx", 901 "mac_clk_tx", "clk_mac_ref", 902 "clk_mac_refout", "aclk_mac", 903 "pclk_mac"; 904 resets = <&cru SRST_GMAC2IO_A>; 905 reset-names = "stmmaceth"; 906 rockchip,grf = <&grf>; 907 snps,txpbl = <0x4>; 908 status = "disabled"; 909 }; 910 911 gmac2phy: ethernet@ff550000 { 912 compatible = "rockchip,rk3328-gmac"; 913 reg = <0x0 0xff550000 0x0 0x10000>; 914 rockchip,grf = <&grf>; 915 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 916 interrupt-names = "macirq"; 917 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 918 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 919 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 920 <&cru SCLK_MAC2PHY_OUT>; 921 clock-names = "stmmaceth", "mac_clk_rx", 922 "mac_clk_tx", "clk_mac_ref", 923 "aclk_mac", "pclk_mac", 924 "clk_macphy"; 925 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; 926 reset-names = "stmmaceth", "mac-phy"; 927 phy-mode = "rmii"; 928 phy-handle = <&phy>; 929 snps,txpbl = <0x4>; 930 status = "disabled"; 931 932 mdio { 933 compatible = "snps,dwmac-mdio"; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 937 phy: ethernet-phy@0 { 938 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 939 reg = <0>; 940 clocks = <&cru SCLK_MAC2PHY_OUT>; 941 resets = <&cru SRST_MACPHY>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 944 phy-is-integrated; 945 }; 946 }; 947 }; 948 949 usb20_otg: usb@ff580000 { 950 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 951 "snps,dwc2"; 952 reg = <0x0 0xff580000 0x0 0x40000>; 953 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&cru HCLK_OTG>; 955 clock-names = "otg"; 956 dr_mode = "otg"; 957 g-np-tx-fifo-size = <16>; 958 g-rx-fifo-size = <280>; 959 g-tx-fifo-size = <256 128 128 64 32 16>; 960 phys = <&u2phy_otg>; 961 phy-names = "usb2-phy"; 962 status = "disabled"; 963 }; 964 965 usb_host0_ehci: usb@ff5c0000 { 966 compatible = "generic-ehci"; 967 reg = <0x0 0xff5c0000 0x0 0x10000>; 968 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&cru HCLK_HOST0>, <&u2phy>; 970 phys = <&u2phy_host>; 971 phy-names = "usb"; 972 status = "disabled"; 973 }; 974 975 usb_host0_ohci: usb@ff5d0000 { 976 compatible = "generic-ohci"; 977 reg = <0x0 0xff5d0000 0x0 0x10000>; 978 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&cru HCLK_HOST0>, <&u2phy>; 980 phys = <&u2phy_host>; 981 phy-names = "usb"; 982 status = "disabled"; 983 }; 984 985 gic: interrupt-controller@ff811000 { 986 compatible = "arm,gic-400"; 987 #interrupt-cells = <3>; 988 #address-cells = <0>; 989 interrupt-controller; 990 reg = <0x0 0xff811000 0 0x1000>, 991 <0x0 0xff812000 0 0x2000>, 992 <0x0 0xff814000 0 0x2000>, 993 <0x0 0xff816000 0 0x2000>; 994 interrupts = <GIC_PPI 9 995 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 996 }; 997 998 pinctrl: pinctrl { 999 compatible = "rockchip,rk3328-pinctrl"; 1000 rockchip,grf = <&grf>; 1001 #address-cells = <2>; 1002 #size-cells = <2>; 1003 ranges; 1004 1005 gpio0: gpio0@ff210000 { 1006 compatible = "rockchip,gpio-bank"; 1007 reg = <0x0 0xff210000 0x0 0x100>; 1008 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&cru PCLK_GPIO0>; 1010 1011 gpio-controller; 1012 #gpio-cells = <2>; 1013 1014 interrupt-controller; 1015 #interrupt-cells = <2>; 1016 }; 1017 1018 gpio1: gpio1@ff220000 { 1019 compatible = "rockchip,gpio-bank"; 1020 reg = <0x0 0xff220000 0x0 0x100>; 1021 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&cru PCLK_GPIO1>; 1023 1024 gpio-controller; 1025 #gpio-cells = <2>; 1026 1027 interrupt-controller; 1028 #interrupt-cells = <2>; 1029 }; 1030 1031 gpio2: gpio2@ff230000 { 1032 compatible = "rockchip,gpio-bank"; 1033 reg = <0x0 0xff230000 0x0 0x100>; 1034 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&cru PCLK_GPIO2>; 1036 1037 gpio-controller; 1038 #gpio-cells = <2>; 1039 1040 interrupt-controller; 1041 #interrupt-cells = <2>; 1042 }; 1043 1044 gpio3: gpio3@ff240000 { 1045 compatible = "rockchip,gpio-bank"; 1046 reg = <0x0 0xff240000 0x0 0x100>; 1047 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&cru PCLK_GPIO3>; 1049 1050 gpio-controller; 1051 #gpio-cells = <2>; 1052 1053 interrupt-controller; 1054 #interrupt-cells = <2>; 1055 }; 1056 1057 pcfg_pull_up: pcfg-pull-up { 1058 bias-pull-up; 1059 }; 1060 1061 pcfg_pull_down: pcfg-pull-down { 1062 bias-pull-down; 1063 }; 1064 1065 pcfg_pull_none: pcfg-pull-none { 1066 bias-disable; 1067 }; 1068 1069 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1070 bias-disable; 1071 drive-strength = <2>; 1072 }; 1073 1074 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1075 bias-pull-up; 1076 drive-strength = <2>; 1077 }; 1078 1079 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1080 bias-pull-up; 1081 drive-strength = <4>; 1082 }; 1083 1084 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1085 bias-disable; 1086 drive-strength = <4>; 1087 }; 1088 1089 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1090 bias-pull-down; 1091 drive-strength = <4>; 1092 }; 1093 1094 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1095 bias-disable; 1096 drive-strength = <8>; 1097 }; 1098 1099 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1100 bias-pull-up; 1101 drive-strength = <8>; 1102 }; 1103 1104 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1105 bias-disable; 1106 drive-strength = <12>; 1107 }; 1108 1109 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1110 bias-pull-up; 1111 drive-strength = <12>; 1112 }; 1113 1114 pcfg_output_high: pcfg-output-high { 1115 output-high; 1116 }; 1117 1118 pcfg_output_low: pcfg-output-low { 1119 output-low; 1120 }; 1121 1122 pcfg_input_high: pcfg-input-high { 1123 bias-pull-up; 1124 input-enable; 1125 }; 1126 1127 pcfg_input: pcfg-input { 1128 input-enable; 1129 }; 1130 1131 i2c0 { 1132 i2c0_xfer: i2c0-xfer { 1133 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1134 <2 RK_PD1 1 &pcfg_pull_none>; 1135 }; 1136 }; 1137 1138 i2c1 { 1139 i2c1_xfer: i2c1-xfer { 1140 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1141 <2 RK_PA5 2 &pcfg_pull_none>; 1142 }; 1143 }; 1144 1145 i2c2 { 1146 i2c2_xfer: i2c2-xfer { 1147 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1148 <2 RK_PB6 1 &pcfg_pull_none>; 1149 }; 1150 }; 1151 1152 i2c3 { 1153 i2c3_xfer: i2c3-xfer { 1154 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1155 <0 RK_PA6 2 &pcfg_pull_none>; 1156 }; 1157 i2c3_gpio: i2c3-gpio { 1158 rockchip,pins = 1159 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1160 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1161 }; 1162 }; 1163 1164 hdmi_i2c { 1165 hdmii2c_xfer: hdmii2c-xfer { 1166 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1167 <0 RK_PA6 1 &pcfg_pull_none>; 1168 }; 1169 }; 1170 1171 pdm-0 { 1172 pdmm0_clk: pdmm0-clk { 1173 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1174 }; 1175 1176 pdmm0_fsync: pdmm0-fsync { 1177 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1178 }; 1179 1180 pdmm0_sdi0: pdmm0-sdi0 { 1181 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1182 }; 1183 1184 pdmm0_sdi1: pdmm0-sdi1 { 1185 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1186 }; 1187 1188 pdmm0_sdi2: pdmm0-sdi2 { 1189 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1190 }; 1191 1192 pdmm0_sdi3: pdmm0-sdi3 { 1193 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1194 }; 1195 1196 pdmm0_clk_sleep: pdmm0-clk-sleep { 1197 rockchip,pins = 1198 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1199 }; 1200 1201 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1202 rockchip,pins = 1203 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1204 }; 1205 1206 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1207 rockchip,pins = 1208 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1209 }; 1210 1211 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1212 rockchip,pins = 1213 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1214 }; 1215 1216 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1217 rockchip,pins = 1218 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1219 }; 1220 1221 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1222 rockchip,pins = 1223 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1224 }; 1225 }; 1226 1227 tsadc { 1228 otp_gpio: otp-gpio { 1229 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1230 }; 1231 1232 otp_out: otp-out { 1233 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1234 }; 1235 }; 1236 1237 uart0 { 1238 uart0_xfer: uart0-xfer { 1239 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, 1240 <1 RK_PB0 1 &pcfg_pull_none>; 1241 }; 1242 1243 uart0_cts: uart0-cts { 1244 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1245 }; 1246 1247 uart0_rts: uart0-rts { 1248 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1249 }; 1250 1251 uart0_rts_gpio: uart0-rts-gpio { 1252 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1253 }; 1254 }; 1255 1256 uart1 { 1257 uart1_xfer: uart1-xfer { 1258 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, 1259 <3 RK_PA6 4 &pcfg_pull_none>; 1260 }; 1261 1262 uart1_cts: uart1-cts { 1263 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1264 }; 1265 1266 uart1_rts: uart1-rts { 1267 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1268 }; 1269 1270 uart1_rts_gpio: uart1-rts-gpio { 1271 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1272 }; 1273 }; 1274 1275 uart2-0 { 1276 uart2m0_xfer: uart2m0-xfer { 1277 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, 1278 <1 RK_PA1 2 &pcfg_pull_none>; 1279 }; 1280 }; 1281 1282 uart2-1 { 1283 uart2m1_xfer: uart2m1-xfer { 1284 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, 1285 <2 RK_PA1 1 &pcfg_pull_none>; 1286 }; 1287 }; 1288 1289 spi0-0 { 1290 spi0m0_clk: spi0m0-clk { 1291 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1292 }; 1293 1294 spi0m0_cs0: spi0m0-cs0 { 1295 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1296 }; 1297 1298 spi0m0_tx: spi0m0-tx { 1299 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1300 }; 1301 1302 spi0m0_rx: spi0m0-rx { 1303 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1304 }; 1305 1306 spi0m0_cs1: spi0m0-cs1 { 1307 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1308 }; 1309 }; 1310 1311 spi0-1 { 1312 spi0m1_clk: spi0m1-clk { 1313 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1314 }; 1315 1316 spi0m1_cs0: spi0m1-cs0 { 1317 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1318 }; 1319 1320 spi0m1_tx: spi0m1-tx { 1321 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1322 }; 1323 1324 spi0m1_rx: spi0m1-rx { 1325 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1326 }; 1327 1328 spi0m1_cs1: spi0m1-cs1 { 1329 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1330 }; 1331 }; 1332 1333 spi0-2 { 1334 spi0m2_clk: spi0m2-clk { 1335 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1336 }; 1337 1338 spi0m2_cs0: spi0m2-cs0 { 1339 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1340 }; 1341 1342 spi0m2_tx: spi0m2-tx { 1343 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1344 }; 1345 1346 spi0m2_rx: spi0m2-rx { 1347 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1348 }; 1349 }; 1350 1351 i2s1 { 1352 i2s1_mclk: i2s1-mclk { 1353 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1354 }; 1355 1356 i2s1_sclk: i2s1-sclk { 1357 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1358 }; 1359 1360 i2s1_lrckrx: i2s1-lrckrx { 1361 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1362 }; 1363 1364 i2s1_lrcktx: i2s1-lrcktx { 1365 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1366 }; 1367 1368 i2s1_sdi: i2s1-sdi { 1369 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1370 }; 1371 1372 i2s1_sdo: i2s1-sdo { 1373 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1374 }; 1375 1376 i2s1_sdio1: i2s1-sdio1 { 1377 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1378 }; 1379 1380 i2s1_sdio2: i2s1-sdio2 { 1381 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1382 }; 1383 1384 i2s1_sdio3: i2s1-sdio3 { 1385 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1386 }; 1387 1388 i2s1_sleep: i2s1-sleep { 1389 rockchip,pins = 1390 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1391 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1392 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1393 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1394 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1395 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1396 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1397 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1398 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1399 }; 1400 }; 1401 1402 i2s2-0 { 1403 i2s2m0_mclk: i2s2m0-mclk { 1404 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1405 }; 1406 1407 i2s2m0_sclk: i2s2m0-sclk { 1408 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1409 }; 1410 1411 i2s2m0_lrckrx: i2s2m0-lrckrx { 1412 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1413 }; 1414 1415 i2s2m0_lrcktx: i2s2m0-lrcktx { 1416 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1417 }; 1418 1419 i2s2m0_sdi: i2s2m0-sdi { 1420 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1421 }; 1422 1423 i2s2m0_sdo: i2s2m0-sdo { 1424 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1425 }; 1426 1427 i2s2m0_sleep: i2s2m0-sleep { 1428 rockchip,pins = 1429 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1430 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1431 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1432 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1433 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1434 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1435 }; 1436 }; 1437 1438 i2s2-1 { 1439 i2s2m1_mclk: i2s2m1-mclk { 1440 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1441 }; 1442 1443 i2s2m1_sclk: i2s2m1-sclk { 1444 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1445 }; 1446 1447 i2s2m1_lrckrx: i2sm1-lrckrx { 1448 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1449 }; 1450 1451 i2s2m1_lrcktx: i2s2m1-lrcktx { 1452 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1453 }; 1454 1455 i2s2m1_sdi: i2s2m1-sdi { 1456 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1457 }; 1458 1459 i2s2m1_sdo: i2s2m1-sdo { 1460 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1461 }; 1462 1463 i2s2m1_sleep: i2s2m1-sleep { 1464 rockchip,pins = 1465 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1466 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1467 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1468 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1469 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1470 }; 1471 }; 1472 1473 spdif-0 { 1474 spdifm0_tx: spdifm0-tx { 1475 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1476 }; 1477 }; 1478 1479 spdif-1 { 1480 spdifm1_tx: spdifm1-tx { 1481 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1482 }; 1483 }; 1484 1485 spdif-2 { 1486 spdifm2_tx: spdifm2-tx { 1487 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1488 }; 1489 }; 1490 1491 sdmmc0-0 { 1492 sdmmc0m0_pwren: sdmmc0m0-pwren { 1493 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1494 }; 1495 1496 sdmmc0m0_gpio: sdmmc0m0-gpio { 1497 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1498 }; 1499 }; 1500 1501 sdmmc0-1 { 1502 sdmmc0m1_pwren: sdmmc0m1-pwren { 1503 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1504 }; 1505 1506 sdmmc0m1_gpio: sdmmc0m1-gpio { 1507 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1508 }; 1509 }; 1510 1511 sdmmc0 { 1512 sdmmc0_clk: sdmmc0-clk { 1513 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1514 }; 1515 1516 sdmmc0_cmd: sdmmc0-cmd { 1517 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1518 }; 1519 1520 sdmmc0_dectn: sdmmc0-dectn { 1521 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1522 }; 1523 1524 sdmmc0_wrprt: sdmmc0-wrprt { 1525 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1526 }; 1527 1528 sdmmc0_bus1: sdmmc0-bus1 { 1529 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1530 }; 1531 1532 sdmmc0_bus4: sdmmc0-bus4 { 1533 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1534 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1535 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1536 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1537 }; 1538 1539 sdmmc0_gpio: sdmmc0-gpio { 1540 rockchip,pins = 1541 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1542 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1543 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1544 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1545 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1546 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1547 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1548 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1549 }; 1550 }; 1551 1552 sdmmc0ext { 1553 sdmmc0ext_clk: sdmmc0ext-clk { 1554 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1555 }; 1556 1557 sdmmc0ext_cmd: sdmmc0ext-cmd { 1558 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1559 }; 1560 1561 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1562 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1563 }; 1564 1565 sdmmc0ext_dectn: sdmmc0ext-dectn { 1566 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1567 }; 1568 1569 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1570 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1571 }; 1572 1573 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1574 rockchip,pins = 1575 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1576 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1577 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1578 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1579 }; 1580 1581 sdmmc0ext_gpio: sdmmc0ext-gpio { 1582 rockchip,pins = 1583 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1584 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1585 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1586 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1587 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1588 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1589 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1590 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1591 }; 1592 }; 1593 1594 sdmmc1 { 1595 sdmmc1_clk: sdmmc1-clk { 1596 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1597 }; 1598 1599 sdmmc1_cmd: sdmmc1-cmd { 1600 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1601 }; 1602 1603 sdmmc1_pwren: sdmmc1-pwren { 1604 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1605 }; 1606 1607 sdmmc1_wrprt: sdmmc1-wrprt { 1608 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1609 }; 1610 1611 sdmmc1_dectn: sdmmc1-dectn { 1612 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1613 }; 1614 1615 sdmmc1_bus1: sdmmc1-bus1 { 1616 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1617 }; 1618 1619 sdmmc1_bus4: sdmmc1-bus4 { 1620 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1621 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1622 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1623 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1624 }; 1625 1626 sdmmc1_gpio: sdmmc1-gpio { 1627 rockchip,pins = 1628 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1629 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1630 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1631 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1632 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1633 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1634 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1635 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1636 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1637 }; 1638 }; 1639 1640 emmc { 1641 emmc_clk: emmc-clk { 1642 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1643 }; 1644 1645 emmc_cmd: emmc-cmd { 1646 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1647 }; 1648 1649 emmc_pwren: emmc-pwren { 1650 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1651 }; 1652 1653 emmc_rstnout: emmc-rstnout { 1654 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1655 }; 1656 1657 emmc_bus1: emmc-bus1 { 1658 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1659 }; 1660 1661 emmc_bus4: emmc-bus4 { 1662 rockchip,pins = 1663 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1664 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1665 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1666 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1667 }; 1668 1669 emmc_bus8: emmc-bus8 { 1670 rockchip,pins = 1671 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1672 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1673 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1674 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1675 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1676 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1677 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1678 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1679 }; 1680 }; 1681 1682 pwm0 { 1683 pwm0_pin: pwm0-pin { 1684 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1685 }; 1686 }; 1687 1688 pwm1 { 1689 pwm1_pin: pwm1-pin { 1690 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1691 }; 1692 }; 1693 1694 pwm2 { 1695 pwm2_pin: pwm2-pin { 1696 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1697 }; 1698 }; 1699 1700 pwmir { 1701 pwmir_pin: pwmir-pin { 1702 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1703 }; 1704 }; 1705 1706 gmac-1 { 1707 rgmiim1_pins: rgmiim1-pins { 1708 rockchip,pins = 1709 /* mac_txclk */ 1710 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1711 /* mac_rxclk */ 1712 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1713 /* mac_mdio */ 1714 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1715 /* mac_txen */ 1716 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1717 /* mac_clk */ 1718 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1719 /* mac_rxdv */ 1720 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1721 /* mac_mdc */ 1722 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1723 /* mac_rxd1 */ 1724 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1725 /* mac_rxd0 */ 1726 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1727 /* mac_txd1 */ 1728 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1729 /* mac_txd0 */ 1730 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1731 /* mac_rxd3 */ 1732 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1733 /* mac_rxd2 */ 1734 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1735 /* mac_txd3 */ 1736 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1737 /* mac_txd2 */ 1738 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1739 1740 /* mac_txclk */ 1741 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1742 /* mac_txen */ 1743 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1744 /* mac_clk */ 1745 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1746 /* mac_txd1 */ 1747 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1748 /* mac_txd0 */ 1749 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1750 /* mac_txd3 */ 1751 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1752 /* mac_txd2 */ 1753 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1754 }; 1755 1756 rmiim1_pins: rmiim1-pins { 1757 rockchip,pins = 1758 /* mac_mdio */ 1759 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1760 /* mac_txen */ 1761 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1762 /* mac_clk */ 1763 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1764 /* mac_rxer */ 1765 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1766 /* mac_rxdv */ 1767 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1768 /* mac_mdc */ 1769 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1770 /* mac_rxd1 */ 1771 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1772 /* mac_rxd0 */ 1773 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1774 /* mac_txd1 */ 1775 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1776 /* mac_txd0 */ 1777 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1778 1779 /* mac_mdio */ 1780 <0 RK_PB3 1 &pcfg_pull_none>, 1781 /* mac_txen */ 1782 <0 RK_PB4 1 &pcfg_pull_none>, 1783 /* mac_clk */ 1784 <0 RK_PD0 1 &pcfg_pull_none>, 1785 /* mac_mdc */ 1786 <0 RK_PC3 1 &pcfg_pull_none>, 1787 /* mac_txd1 */ 1788 <0 RK_PC0 1 &pcfg_pull_none>, 1789 /* mac_txd0 */ 1790 <0 RK_PC1 1 &pcfg_pull_none>; 1791 }; 1792 }; 1793 1794 gmac2phy { 1795 fephyled_speed10: fephyled-speed10 { 1796 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1797 }; 1798 1799 fephyled_duplex: fephyled-duplex { 1800 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1801 }; 1802 1803 fephyled_rxm1: fephyled-rxm1 { 1804 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1805 }; 1806 1807 fephyled_txm1: fephyled-txm1 { 1808 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1809 }; 1810 1811 fephyled_linkm1: fephyled-linkm1 { 1812 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1813 }; 1814 }; 1815 1816 tsadc_pin { 1817 tsadc_int: tsadc-int { 1818 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1819 }; 1820 tsadc_gpio: tsadc-gpio { 1821 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1822 }; 1823 }; 1824 1825 hdmi_pin { 1826 hdmi_cec: hdmi-cec { 1827 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1828 }; 1829 1830 hdmi_hpd: hdmi-hpd { 1831 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1832 }; 1833 }; 1834 1835 cif-0 { 1836 dvp_d2d9_m0:dvp-d2d9-m0 { 1837 rockchip,pins = 1838 /* cif_d0 */ 1839 <3 RK_PA4 2 &pcfg_pull_none>, 1840 /* cif_d1 */ 1841 <3 RK_PA5 2 &pcfg_pull_none>, 1842 /* cif_d2 */ 1843 <3 RK_PA6 2 &pcfg_pull_none>, 1844 /* cif_d3 */ 1845 <3 RK_PA7 2 &pcfg_pull_none>, 1846 /* cif_d4 */ 1847 <3 RK_PB0 2 &pcfg_pull_none>, 1848 /* cif_d5m0 */ 1849 <3 RK_PB1 2 &pcfg_pull_none>, 1850 /* cif_d6m0 */ 1851 <3 RK_PB2 2 &pcfg_pull_none>, 1852 /* cif_d7m0 */ 1853 <3 RK_PB3 2 &pcfg_pull_none>, 1854 /* cif_href */ 1855 <3 RK_PA1 2 &pcfg_pull_none>, 1856 /* cif_vsync */ 1857 <3 RK_PA0 2 &pcfg_pull_none>, 1858 /* cif_clkoutm0 */ 1859 <3 RK_PA3 2 &pcfg_pull_none>, 1860 /* cif_clkin */ 1861 <3 RK_PA2 2 &pcfg_pull_none>; 1862 }; 1863 }; 1864 1865 cif-1 { 1866 dvp_d2d9_m1:dvp-d2d9-m1 { 1867 rockchip,pins = 1868 /* cif_d0 */ 1869 <3 RK_PA4 2 &pcfg_pull_none>, 1870 /* cif_d1 */ 1871 <3 RK_PA5 2 &pcfg_pull_none>, 1872 /* cif_d2 */ 1873 <3 RK_PA6 2 &pcfg_pull_none>, 1874 /* cif_d3 */ 1875 <3 RK_PA7 2 &pcfg_pull_none>, 1876 /* cif_d4 */ 1877 <3 RK_PB0 2 &pcfg_pull_none>, 1878 /* cif_d5m1 */ 1879 <2 RK_PC0 4 &pcfg_pull_none>, 1880 /* cif_d6m1 */ 1881 <2 RK_PC1 4 &pcfg_pull_none>, 1882 /* cif_d7m1 */ 1883 <2 RK_PC2 4 &pcfg_pull_none>, 1884 /* cif_href */ 1885 <3 RK_PA1 2 &pcfg_pull_none>, 1886 /* cif_vsync */ 1887 <3 RK_PA0 2 &pcfg_pull_none>, 1888 /* cif_clkoutm1 */ 1889 <2 RK_PB7 4 &pcfg_pull_none>, 1890 /* cif_clkin */ 1891 <3 RK_PA2 2 &pcfg_pull_none>; 1892 }; 1893 }; 1894 }; 1895}; 1896