1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 dynamic-power-coefficient = <120>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 operating-points-v2 = <&cpu0_opp_table>; 48 }; 49 50 cpu1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x1>; 54 clocks = <&cru ARMCLK>; 55 #cooling-cells = <2>; 56 dynamic-power-coefficient = <120>; 57 enable-method = "psci"; 58 next-level-cache = <&l2>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 }; 61 62 cpu2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53"; 65 reg = <0x0 0x2>; 66 clocks = <&cru ARMCLK>; 67 #cooling-cells = <2>; 68 dynamic-power-coefficient = <120>; 69 enable-method = "psci"; 70 next-level-cache = <&l2>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x0 0x3>; 78 clocks = <&cru ARMCLK>; 79 #cooling-cells = <2>; 80 dynamic-power-coefficient = <120>; 81 enable-method = "psci"; 82 next-level-cache = <&l2>; 83 operating-points-v2 = <&cpu0_opp_table>; 84 }; 85 86 l2: l2-cache0 { 87 compatible = "cache"; 88 }; 89 }; 90 91 cpu0_opp_table: opp_table0 { 92 compatible = "operating-points-v2"; 93 opp-shared; 94 95 opp-408000000 { 96 opp-hz = /bits/ 64 <408000000>; 97 opp-microvolt = <950000>; 98 clock-latency-ns = <40000>; 99 opp-suspend; 100 }; 101 opp-600000000 { 102 opp-hz = /bits/ 64 <600000000>; 103 opp-microvolt = <950000>; 104 clock-latency-ns = <40000>; 105 }; 106 opp-816000000 { 107 opp-hz = /bits/ 64 <816000000>; 108 opp-microvolt = <1000000>; 109 clock-latency-ns = <40000>; 110 }; 111 opp-1008000000 { 112 opp-hz = /bits/ 64 <1008000000>; 113 opp-microvolt = <1100000>; 114 clock-latency-ns = <40000>; 115 }; 116 opp-1200000000 { 117 opp-hz = /bits/ 64 <1200000000>; 118 opp-microvolt = <1225000>; 119 clock-latency-ns = <40000>; 120 }; 121 opp-1296000000 { 122 opp-hz = /bits/ 64 <1296000000>; 123 opp-microvolt = <1300000>; 124 clock-latency-ns = <40000>; 125 }; 126 }; 127 128 amba { 129 compatible = "simple-bus"; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 134 dmac: dmac@ff1f0000 { 135 compatible = "arm,pl330", "arm,primecell"; 136 reg = <0x0 0xff1f0000 0x0 0x4000>; 137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&cru ACLK_DMAC>; 140 clock-names = "apb_pclk"; 141 #dma-cells = <1>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vop_out>; 157 }; 158 159 psci { 160 compatible = "arm,psci-1.0", "arm,psci-0.2"; 161 method = "smc"; 162 }; 163 164 timer { 165 compatible = "arm,armv8-timer"; 166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 170 }; 171 172 xin24m: xin24m { 173 compatible = "fixed-clock"; 174 #clock-cells = <0>; 175 clock-frequency = <24000000>; 176 clock-output-names = "xin24m"; 177 }; 178 179 i2s0: i2s@ff000000 { 180 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 181 reg = <0x0 0xff000000 0x0 0x1000>; 182 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 184 clock-names = "i2s_clk", "i2s_hclk"; 185 dmas = <&dmac 11>, <&dmac 12>; 186 dma-names = "tx", "rx"; 187 #sound-dai-cells = <0>; 188 status = "disabled"; 189 }; 190 191 i2s1: i2s@ff010000 { 192 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 193 reg = <0x0 0xff010000 0x0 0x1000>; 194 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 196 clock-names = "i2s_clk", "i2s_hclk"; 197 dmas = <&dmac 14>, <&dmac 15>; 198 dma-names = "tx", "rx"; 199 #sound-dai-cells = <0>; 200 status = "disabled"; 201 }; 202 203 i2s2: i2s@ff020000 { 204 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 205 reg = <0x0 0xff020000 0x0 0x1000>; 206 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 208 clock-names = "i2s_clk", "i2s_hclk"; 209 dmas = <&dmac 0>, <&dmac 1>; 210 dma-names = "tx", "rx"; 211 #sound-dai-cells = <0>; 212 status = "disabled"; 213 }; 214 215 spdif: spdif@ff030000 { 216 compatible = "rockchip,rk3328-spdif"; 217 reg = <0x0 0xff030000 0x0 0x1000>; 218 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 220 clock-names = "mclk", "hclk"; 221 dmas = <&dmac 10>; 222 dma-names = "tx"; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&spdifm2_tx>; 225 #sound-dai-cells = <0>; 226 status = "disabled"; 227 }; 228 229 pdm: pdm@ff040000 { 230 compatible = "rockchip,pdm"; 231 reg = <0x0 0xff040000 0x0 0x1000>; 232 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 233 clock-names = "pdm_clk", "pdm_hclk"; 234 dmas = <&dmac 16>; 235 dma-names = "rx"; 236 pinctrl-names = "default", "sleep"; 237 pinctrl-0 = <&pdmm0_clk 238 &pdmm0_sdi0 239 &pdmm0_sdi1 240 &pdmm0_sdi2 241 &pdmm0_sdi3>; 242 pinctrl-1 = <&pdmm0_clk_sleep 243 &pdmm0_sdi0_sleep 244 &pdmm0_sdi1_sleep 245 &pdmm0_sdi2_sleep 246 &pdmm0_sdi3_sleep>; 247 status = "disabled"; 248 }; 249 250 grf: syscon@ff100000 { 251 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 252 reg = <0x0 0xff100000 0x0 0x1000>; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 256 io_domains: io-domains { 257 compatible = "rockchip,rk3328-io-voltage-domain"; 258 status = "disabled"; 259 }; 260 261 grf_gpio: grf-gpio { 262 compatible = "rockchip,rk3328-grf-gpio"; 263 gpio-controller; 264 #gpio-cells = <2>; 265 }; 266 267 power: power-controller { 268 compatible = "rockchip,rk3328-power-controller"; 269 #power-domain-cells = <1>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 pd_hevc@RK3328_PD_HEVC { 274 reg = <RK3328_PD_HEVC>; 275 }; 276 pd_video@RK3328_PD_VIDEO { 277 reg = <RK3328_PD_VIDEO>; 278 }; 279 pd_vpu@RK3328_PD_VPU { 280 reg = <RK3328_PD_VPU>; 281 }; 282 }; 283 284 reboot-mode { 285 compatible = "syscon-reboot-mode"; 286 offset = <0x5c8>; 287 mode-normal = <BOOT_NORMAL>; 288 mode-recovery = <BOOT_RECOVERY>; 289 mode-bootloader = <BOOT_FASTBOOT>; 290 mode-loader = <BOOT_BL_DOWNLOAD>; 291 }; 292 }; 293 294 uart0: serial@ff110000 { 295 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 296 reg = <0x0 0xff110000 0x0 0x100>; 297 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 299 clock-names = "baudclk", "apb_pclk"; 300 dmas = <&dmac 2>, <&dmac 3>; 301 dma-names = "tx", "rx"; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 304 reg-io-width = <4>; 305 reg-shift = <2>; 306 status = "disabled"; 307 }; 308 309 uart1: serial@ff120000 { 310 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 311 reg = <0x0 0xff120000 0x0 0x100>; 312 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 314 clock-names = "baudclk", "apb_pclk"; 315 dmas = <&dmac 4>, <&dmac 5>; 316 dma-names = "tx", "rx"; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 319 reg-io-width = <4>; 320 reg-shift = <2>; 321 status = "disabled"; 322 }; 323 324 uart2: serial@ff130000 { 325 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 326 reg = <0x0 0xff130000 0x0 0x100>; 327 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 329 clock-names = "baudclk", "apb_pclk"; 330 dmas = <&dmac 6>, <&dmac 7>; 331 dma-names = "tx", "rx"; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&uart2m1_xfer>; 334 reg-io-width = <4>; 335 reg-shift = <2>; 336 status = "disabled"; 337 }; 338 339 i2c0: i2c@ff150000 { 340 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 341 reg = <0x0 0xff150000 0x0 0x1000>; 342 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 346 clock-names = "i2c", "pclk"; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&i2c0_xfer>; 349 status = "disabled"; 350 }; 351 352 i2c1: i2c@ff160000 { 353 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 354 reg = <0x0 0xff160000 0x0 0x1000>; 355 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 359 clock-names = "i2c", "pclk"; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&i2c1_xfer>; 362 status = "disabled"; 363 }; 364 365 i2c2: i2c@ff170000 { 366 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 367 reg = <0x0 0xff170000 0x0 0x1000>; 368 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 372 clock-names = "i2c", "pclk"; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&i2c2_xfer>; 375 status = "disabled"; 376 }; 377 378 i2c3: i2c@ff180000 { 379 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 380 reg = <0x0 0xff180000 0x0 0x1000>; 381 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 385 clock-names = "i2c", "pclk"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&i2c3_xfer>; 388 status = "disabled"; 389 }; 390 391 spi0: spi@ff190000 { 392 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 393 reg = <0x0 0xff190000 0x0 0x1000>; 394 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 398 clock-names = "spiclk", "apb_pclk"; 399 dmas = <&dmac 8>, <&dmac 9>; 400 dma-names = "tx", "rx"; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 403 status = "disabled"; 404 }; 405 406 wdt: watchdog@ff1a0000 { 407 compatible = "snps,dw-wdt"; 408 reg = <0x0 0xff1a0000 0x0 0x100>; 409 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 410 }; 411 412 pwm0: pwm@ff1b0000 { 413 compatible = "rockchip,rk3328-pwm"; 414 reg = <0x0 0xff1b0000 0x0 0x10>; 415 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 416 clock-names = "pwm", "pclk"; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&pwm0_pin>; 419 #pwm-cells = <3>; 420 status = "disabled"; 421 }; 422 423 pwm1: pwm@ff1b0010 { 424 compatible = "rockchip,rk3328-pwm"; 425 reg = <0x0 0xff1b0010 0x0 0x10>; 426 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 427 clock-names = "pwm", "pclk"; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&pwm1_pin>; 430 #pwm-cells = <3>; 431 status = "disabled"; 432 }; 433 434 pwm2: pwm@ff1b0020 { 435 compatible = "rockchip,rk3328-pwm"; 436 reg = <0x0 0xff1b0020 0x0 0x10>; 437 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 438 clock-names = "pwm", "pclk"; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&pwm2_pin>; 441 #pwm-cells = <3>; 442 status = "disabled"; 443 }; 444 445 pwm3: pwm@ff1b0030 { 446 compatible = "rockchip,rk3328-pwm"; 447 reg = <0x0 0xff1b0030 0x0 0x10>; 448 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 450 clock-names = "pwm", "pclk"; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pwmir_pin>; 453 #pwm-cells = <3>; 454 status = "disabled"; 455 }; 456 457 thermal-zones { 458 soc_thermal: soc-thermal { 459 polling-delay-passive = <20>; 460 polling-delay = <1000>; 461 sustainable-power = <1000>; 462 463 thermal-sensors = <&tsadc 0>; 464 465 trips { 466 threshold: trip-point0 { 467 temperature = <70000>; 468 hysteresis = <2000>; 469 type = "passive"; 470 }; 471 target: trip-point1 { 472 temperature = <85000>; 473 hysteresis = <2000>; 474 type = "passive"; 475 }; 476 soc_crit: soc-crit { 477 temperature = <95000>; 478 hysteresis = <2000>; 479 type = "critical"; 480 }; 481 }; 482 483 cooling-maps { 484 map0 { 485 trip = <&target>; 486 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 487 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 488 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 489 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 490 contribution = <4096>; 491 }; 492 }; 493 }; 494 495 }; 496 497 tsadc: tsadc@ff250000 { 498 compatible = "rockchip,rk3328-tsadc"; 499 reg = <0x0 0xff250000 0x0 0x100>; 500 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 501 assigned-clocks = <&cru SCLK_TSADC>; 502 assigned-clock-rates = <50000>; 503 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 504 clock-names = "tsadc", "apb_pclk"; 505 pinctrl-names = "init", "default", "sleep"; 506 pinctrl-0 = <&otp_gpio>; 507 pinctrl-1 = <&otp_out>; 508 pinctrl-2 = <&otp_gpio>; 509 resets = <&cru SRST_TSADC>; 510 reset-names = "tsadc-apb"; 511 rockchip,grf = <&grf>; 512 rockchip,hw-tshut-temp = <100000>; 513 #thermal-sensor-cells = <1>; 514 status = "disabled"; 515 }; 516 517 efuse: efuse@ff260000 { 518 compatible = "rockchip,rk3328-efuse"; 519 reg = <0x0 0xff260000 0x0 0x50>; 520 #address-cells = <1>; 521 #size-cells = <1>; 522 clocks = <&cru SCLK_EFUSE>; 523 clock-names = "pclk_efuse"; 524 rockchip,efuse-size = <0x20>; 525 526 /* Data cells */ 527 efuse_id: id@7 { 528 reg = <0x07 0x10>; 529 }; 530 cpu_leakage: cpu-leakage@17 { 531 reg = <0x17 0x1>; 532 }; 533 logic_leakage: logic-leakage@19 { 534 reg = <0x19 0x1>; 535 }; 536 efuse_cpu_version: cpu-version@1a { 537 reg = <0x1a 0x1>; 538 bits = <3 3>; 539 }; 540 }; 541 542 saradc: adc@ff280000 { 543 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 544 reg = <0x0 0xff280000 0x0 0x100>; 545 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 546 #io-channel-cells = <1>; 547 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 548 clock-names = "saradc", "apb_pclk"; 549 resets = <&cru SRST_SARADC_P>; 550 reset-names = "saradc-apb"; 551 status = "disabled"; 552 }; 553 554 gpu: gpu@ff300000 { 555 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 556 reg = <0x0 0xff300000 0x0 0x40000>; 557 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 564 interrupt-names = "gp", 565 "gpmmu", 566 "pp", 567 "pp0", 568 "ppmmu0", 569 "pp1", 570 "ppmmu1"; 571 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 572 clock-names = "bus", "core"; 573 resets = <&cru SRST_GPU_A>; 574 }; 575 576 h265e_mmu: iommu@ff330200 { 577 compatible = "rockchip,iommu"; 578 reg = <0x0 0xff330200 0 0x100>; 579 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 580 interrupt-names = "h265e_mmu"; 581 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 582 clock-names = "aclk", "iface"; 583 #iommu-cells = <0>; 584 status = "disabled"; 585 }; 586 587 vepu_mmu: iommu@ff340800 { 588 compatible = "rockchip,iommu"; 589 reg = <0x0 0xff340800 0x0 0x40>; 590 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 591 interrupt-names = "vepu_mmu"; 592 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 593 clock-names = "aclk", "iface"; 594 #iommu-cells = <0>; 595 status = "disabled"; 596 }; 597 598 vpu_mmu: iommu@ff350800 { 599 compatible = "rockchip,iommu"; 600 reg = <0x0 0xff350800 0x0 0x40>; 601 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 602 interrupt-names = "vpu_mmu"; 603 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 604 clock-names = "aclk", "iface"; 605 #iommu-cells = <0>; 606 status = "disabled"; 607 }; 608 609 rkvdec_mmu: iommu@ff360480 { 610 compatible = "rockchip,iommu"; 611 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 612 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 613 interrupt-names = "rkvdec_mmu"; 614 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 615 clock-names = "aclk", "iface"; 616 #iommu-cells = <0>; 617 status = "disabled"; 618 }; 619 620 vop: vop@ff370000 { 621 compatible = "rockchip,rk3328-vop"; 622 reg = <0x0 0xff370000 0x0 0x3efc>; 623 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 625 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 626 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 627 reset-names = "axi", "ahb", "dclk"; 628 iommus = <&vop_mmu>; 629 status = "disabled"; 630 631 vop_out: port { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 635 vop_out_hdmi: endpoint@0 { 636 reg = <0>; 637 remote-endpoint = <&hdmi_in_vop>; 638 }; 639 }; 640 }; 641 642 vop_mmu: iommu@ff373f00 { 643 compatible = "rockchip,iommu"; 644 reg = <0x0 0xff373f00 0x0 0x100>; 645 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 646 interrupt-names = "vop_mmu"; 647 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 648 clock-names = "aclk", "iface"; 649 #iommu-cells = <0>; 650 status = "disabled"; 651 }; 652 653 hdmi: hdmi@ff3c0000 { 654 compatible = "rockchip,rk3328-dw-hdmi"; 655 reg = <0x0 0xff3c0000 0x0 0x20000>; 656 reg-io-width = <4>; 657 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&cru PCLK_HDMI>, 660 <&cru SCLK_HDMI_SFC>; 661 clock-names = "iahb", 662 "isfr"; 663 phys = <&hdmiphy>; 664 phy-names = "hdmi"; 665 pinctrl-names = "default"; 666 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 667 rockchip,grf = <&grf>; 668 status = "disabled"; 669 670 ports { 671 hdmi_in: port { 672 hdmi_in_vop: endpoint { 673 remote-endpoint = <&vop_out_hdmi>; 674 }; 675 }; 676 }; 677 }; 678 679 codec: codec@ff410000 { 680 compatible = "rockchip,rk3328-codec"; 681 reg = <0x0 0xff410000 0x0 0x1000>; 682 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 683 clock-names = "pclk", "mclk"; 684 rockchip,grf = <&grf>; 685 #sound-dai-cells = <0>; 686 status = "disabled"; 687 }; 688 689 hdmiphy: phy@ff430000 { 690 compatible = "rockchip,rk3328-hdmi-phy"; 691 reg = <0x0 0xff430000 0x0 0x10000>; 692 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 694 clock-names = "sysclk", "refoclk", "refpclk"; 695 clock-output-names = "hdmi_phy"; 696 #clock-cells = <0>; 697 nvmem-cells = <&efuse_cpu_version>; 698 nvmem-cell-names = "cpu-version"; 699 #phy-cells = <0>; 700 status = "disabled"; 701 }; 702 703 cru: clock-controller@ff440000 { 704 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 705 reg = <0x0 0xff440000 0x0 0x1000>; 706 rockchip,grf = <&grf>; 707 #clock-cells = <1>; 708 #reset-cells = <1>; 709 assigned-clocks = 710 /* 711 * CPLL should run at 1200, but that is to high for 712 * the initial dividers of most of its children. 713 * We need set cpll child clk div first, 714 * and then set the cpll frequency. 715 */ 716 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 717 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 718 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 719 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 720 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 721 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 722 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 723 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 724 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 725 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 726 <&cru SCLK_WIFI>, <&cru ARMCLK>, 727 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 728 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 729 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 730 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 731 <&cru SCLK_RTC32K>; 732 assigned-clock-parents = 733 <&cru HDMIPHY>, <&cru PLL_APLL>, 734 <&cru PLL_GPLL>, <&xin24m>, 735 <&xin24m>, <&xin24m>; 736 assigned-clock-rates = 737 <0>, <61440000>, 738 <0>, <24000000>, 739 <24000000>, <24000000>, 740 <15000000>, <15000000>, 741 <100000000>, <100000000>, 742 <100000000>, <100000000>, 743 <50000000>, <100000000>, 744 <100000000>, <100000000>, 745 <50000000>, <50000000>, 746 <50000000>, <50000000>, 747 <24000000>, <600000000>, 748 <491520000>, <1200000000>, 749 <150000000>, <75000000>, 750 <75000000>, <150000000>, 751 <75000000>, <75000000>, 752 <32768>; 753 }; 754 755 usb2phy_grf: syscon@ff450000 { 756 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 757 "simple-mfd"; 758 reg = <0x0 0xff450000 0x0 0x10000>; 759 #address-cells = <1>; 760 #size-cells = <1>; 761 762 u2phy: usb2-phy@100 { 763 compatible = "rockchip,rk3328-usb2phy"; 764 reg = <0x100 0x10>; 765 clocks = <&xin24m>; 766 clock-names = "phyclk"; 767 clock-output-names = "usb480m_phy"; 768 #clock-cells = <0>; 769 assigned-clocks = <&cru USB480M>; 770 assigned-clock-parents = <&u2phy>; 771 status = "disabled"; 772 773 u2phy_otg: otg-port { 774 #phy-cells = <0>; 775 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 778 interrupt-names = "otg-bvalid", "otg-id", 779 "linestate"; 780 status = "disabled"; 781 }; 782 783 u2phy_host: host-port { 784 #phy-cells = <0>; 785 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 786 interrupt-names = "linestate"; 787 status = "disabled"; 788 }; 789 }; 790 }; 791 792 sdmmc: dwmmc@ff500000 { 793 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 794 reg = <0x0 0xff500000 0x0 0x4000>; 795 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 797 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 798 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 799 fifo-depth = <0x100>; 800 status = "disabled"; 801 }; 802 803 sdio: dwmmc@ff510000 { 804 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 805 reg = <0x0 0xff510000 0x0 0x4000>; 806 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 808 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 809 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 810 fifo-depth = <0x100>; 811 status = "disabled"; 812 }; 813 814 emmc: dwmmc@ff520000 { 815 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 816 reg = <0x0 0xff520000 0x0 0x4000>; 817 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 819 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 820 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 821 fifo-depth = <0x100>; 822 status = "disabled"; 823 }; 824 825 gmac2io: ethernet@ff540000 { 826 compatible = "rockchip,rk3328-gmac"; 827 reg = <0x0 0xff540000 0x0 0x10000>; 828 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 829 interrupt-names = "macirq"; 830 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 831 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 832 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 833 <&cru PCLK_MAC2IO>; 834 clock-names = "stmmaceth", "mac_clk_rx", 835 "mac_clk_tx", "clk_mac_ref", 836 "clk_mac_refout", "aclk_mac", 837 "pclk_mac"; 838 resets = <&cru SRST_GMAC2IO_A>; 839 reset-names = "stmmaceth"; 840 rockchip,grf = <&grf>; 841 status = "disabled"; 842 }; 843 844 gmac2phy: ethernet@ff550000 { 845 compatible = "rockchip,rk3328-gmac"; 846 reg = <0x0 0xff550000 0x0 0x10000>; 847 rockchip,grf = <&grf>; 848 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 849 interrupt-names = "macirq"; 850 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 851 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 852 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 853 <&cru SCLK_MAC2PHY_OUT>; 854 clock-names = "stmmaceth", "mac_clk_rx", 855 "mac_clk_tx", "clk_mac_ref", 856 "aclk_mac", "pclk_mac", 857 "clk_macphy"; 858 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; 859 reset-names = "stmmaceth", "mac-phy"; 860 phy-mode = "rmii"; 861 phy-handle = <&phy>; 862 status = "disabled"; 863 864 mdio { 865 compatible = "snps,dwmac-mdio"; 866 #address-cells = <1>; 867 #size-cells = <0>; 868 869 phy: phy@0 { 870 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 871 reg = <0>; 872 clocks = <&cru SCLK_MAC2PHY_OUT>; 873 resets = <&cru SRST_MACPHY>; 874 pinctrl-names = "default"; 875 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 876 phy-is-integrated; 877 }; 878 }; 879 }; 880 881 usb20_otg: usb@ff580000 { 882 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 883 "snps,dwc2"; 884 reg = <0x0 0xff580000 0x0 0x40000>; 885 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&cru HCLK_OTG>; 887 clock-names = "otg"; 888 dr_mode = "otg"; 889 g-np-tx-fifo-size = <16>; 890 g-rx-fifo-size = <280>; 891 g-tx-fifo-size = <256 128 128 64 32 16>; 892 g-use-dma; 893 phys = <&u2phy_otg>; 894 phy-names = "usb2-phy"; 895 status = "disabled"; 896 }; 897 898 usb_host0_ehci: usb@ff5c0000 { 899 compatible = "generic-ehci"; 900 reg = <0x0 0xff5c0000 0x0 0x10000>; 901 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&cru HCLK_HOST0>, <&u2phy>; 903 clock-names = "usbhost", "utmi"; 904 phys = <&u2phy_host>; 905 phy-names = "usb"; 906 status = "disabled"; 907 }; 908 909 usb_host0_ohci: usb@ff5d0000 { 910 compatible = "generic-ohci"; 911 reg = <0x0 0xff5d0000 0x0 0x10000>; 912 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&cru HCLK_HOST0>, <&u2phy>; 914 clock-names = "usbhost", "utmi"; 915 phys = <&u2phy_host>; 916 phy-names = "usb"; 917 status = "disabled"; 918 }; 919 920 gic: interrupt-controller@ff811000 { 921 compatible = "arm,gic-400"; 922 #interrupt-cells = <3>; 923 #address-cells = <0>; 924 interrupt-controller; 925 reg = <0x0 0xff811000 0 0x1000>, 926 <0x0 0xff812000 0 0x2000>, 927 <0x0 0xff814000 0 0x2000>, 928 <0x0 0xff816000 0 0x2000>; 929 interrupts = <GIC_PPI 9 930 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 931 }; 932 933 pinctrl: pinctrl { 934 compatible = "rockchip,rk3328-pinctrl"; 935 rockchip,grf = <&grf>; 936 #address-cells = <2>; 937 #size-cells = <2>; 938 ranges; 939 940 gpio0: gpio0@ff210000 { 941 compatible = "rockchip,gpio-bank"; 942 reg = <0x0 0xff210000 0x0 0x100>; 943 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&cru PCLK_GPIO0>; 945 946 gpio-controller; 947 #gpio-cells = <2>; 948 949 interrupt-controller; 950 #interrupt-cells = <2>; 951 }; 952 953 gpio1: gpio1@ff220000 { 954 compatible = "rockchip,gpio-bank"; 955 reg = <0x0 0xff220000 0x0 0x100>; 956 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&cru PCLK_GPIO1>; 958 959 gpio-controller; 960 #gpio-cells = <2>; 961 962 interrupt-controller; 963 #interrupt-cells = <2>; 964 }; 965 966 gpio2: gpio2@ff230000 { 967 compatible = "rockchip,gpio-bank"; 968 reg = <0x0 0xff230000 0x0 0x100>; 969 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&cru PCLK_GPIO2>; 971 972 gpio-controller; 973 #gpio-cells = <2>; 974 975 interrupt-controller; 976 #interrupt-cells = <2>; 977 }; 978 979 gpio3: gpio3@ff240000 { 980 compatible = "rockchip,gpio-bank"; 981 reg = <0x0 0xff240000 0x0 0x100>; 982 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&cru PCLK_GPIO3>; 984 985 gpio-controller; 986 #gpio-cells = <2>; 987 988 interrupt-controller; 989 #interrupt-cells = <2>; 990 }; 991 992 pcfg_pull_up: pcfg-pull-up { 993 bias-pull-up; 994 }; 995 996 pcfg_pull_down: pcfg-pull-down { 997 bias-pull-down; 998 }; 999 1000 pcfg_pull_none: pcfg-pull-none { 1001 bias-disable; 1002 }; 1003 1004 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1005 bias-disable; 1006 drive-strength = <2>; 1007 }; 1008 1009 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1010 bias-pull-up; 1011 drive-strength = <2>; 1012 }; 1013 1014 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1015 bias-pull-up; 1016 drive-strength = <4>; 1017 }; 1018 1019 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1020 bias-disable; 1021 drive-strength = <4>; 1022 }; 1023 1024 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1025 bias-pull-down; 1026 drive-strength = <4>; 1027 }; 1028 1029 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1030 bias-disable; 1031 drive-strength = <8>; 1032 }; 1033 1034 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1035 bias-pull-up; 1036 drive-strength = <8>; 1037 }; 1038 1039 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1040 bias-disable; 1041 drive-strength = <12>; 1042 }; 1043 1044 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1045 bias-pull-up; 1046 drive-strength = <12>; 1047 }; 1048 1049 pcfg_output_high: pcfg-output-high { 1050 output-high; 1051 }; 1052 1053 pcfg_output_low: pcfg-output-low { 1054 output-low; 1055 }; 1056 1057 pcfg_input_high: pcfg-input-high { 1058 bias-pull-up; 1059 input-enable; 1060 }; 1061 1062 pcfg_input: pcfg-input { 1063 input-enable; 1064 }; 1065 1066 i2c0 { 1067 i2c0_xfer: i2c0-xfer { 1068 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1069 <2 RK_PD1 1 &pcfg_pull_none>; 1070 }; 1071 }; 1072 1073 i2c1 { 1074 i2c1_xfer: i2c1-xfer { 1075 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1076 <2 RK_PA5 2 &pcfg_pull_none>; 1077 }; 1078 }; 1079 1080 i2c2 { 1081 i2c2_xfer: i2c2-xfer { 1082 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1083 <2 RK_PB6 1 &pcfg_pull_none>; 1084 }; 1085 }; 1086 1087 i2c3 { 1088 i2c3_xfer: i2c3-xfer { 1089 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1090 <0 RK_PA6 2 &pcfg_pull_none>; 1091 }; 1092 i2c3_gpio: i2c3-gpio { 1093 rockchip,pins = 1094 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1095 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1096 }; 1097 }; 1098 1099 hdmi_i2c { 1100 hdmii2c_xfer: hdmii2c-xfer { 1101 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1102 <0 RK_PA6 1 &pcfg_pull_none>; 1103 }; 1104 }; 1105 1106 pdm-0 { 1107 pdmm0_clk: pdmm0-clk { 1108 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1109 }; 1110 1111 pdmm0_fsync: pdmm0-fsync { 1112 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1113 }; 1114 1115 pdmm0_sdi0: pdmm0-sdi0 { 1116 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1117 }; 1118 1119 pdmm0_sdi1: pdmm0-sdi1 { 1120 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1121 }; 1122 1123 pdmm0_sdi2: pdmm0-sdi2 { 1124 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1125 }; 1126 1127 pdmm0_sdi3: pdmm0-sdi3 { 1128 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1129 }; 1130 1131 pdmm0_clk_sleep: pdmm0-clk-sleep { 1132 rockchip,pins = 1133 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1134 }; 1135 1136 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1137 rockchip,pins = 1138 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1139 }; 1140 1141 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1142 rockchip,pins = 1143 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1144 }; 1145 1146 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1147 rockchip,pins = 1148 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1149 }; 1150 1151 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1152 rockchip,pins = 1153 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1154 }; 1155 1156 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1157 rockchip,pins = 1158 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1159 }; 1160 }; 1161 1162 tsadc { 1163 otp_gpio: otp-gpio { 1164 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1165 }; 1166 1167 otp_out: otp-out { 1168 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1169 }; 1170 }; 1171 1172 uart0 { 1173 uart0_xfer: uart0-xfer { 1174 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, 1175 <1 RK_PB0 1 &pcfg_pull_none>; 1176 }; 1177 1178 uart0_cts: uart0-cts { 1179 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1180 }; 1181 1182 uart0_rts: uart0-rts { 1183 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1184 }; 1185 1186 uart0_rts_gpio: uart0-rts-gpio { 1187 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1188 }; 1189 }; 1190 1191 uart1 { 1192 uart1_xfer: uart1-xfer { 1193 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, 1194 <3 RK_PA6 4 &pcfg_pull_none>; 1195 }; 1196 1197 uart1_cts: uart1-cts { 1198 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1199 }; 1200 1201 uart1_rts: uart1-rts { 1202 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1203 }; 1204 1205 uart1_rts_gpio: uart1-rts-gpio { 1206 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1207 }; 1208 }; 1209 1210 uart2-0 { 1211 uart2m0_xfer: uart2m0-xfer { 1212 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, 1213 <1 RK_PA1 2 &pcfg_pull_none>; 1214 }; 1215 }; 1216 1217 uart2-1 { 1218 uart2m1_xfer: uart2m1-xfer { 1219 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, 1220 <2 RK_PA1 1 &pcfg_pull_none>; 1221 }; 1222 }; 1223 1224 spi0-0 { 1225 spi0m0_clk: spi0m0-clk { 1226 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1227 }; 1228 1229 spi0m0_cs0: spi0m0-cs0 { 1230 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1231 }; 1232 1233 spi0m0_tx: spi0m0-tx { 1234 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1235 }; 1236 1237 spi0m0_rx: spi0m0-rx { 1238 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1239 }; 1240 1241 spi0m0_cs1: spi0m0-cs1 { 1242 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1243 }; 1244 }; 1245 1246 spi0-1 { 1247 spi0m1_clk: spi0m1-clk { 1248 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1249 }; 1250 1251 spi0m1_cs0: spi0m1-cs0 { 1252 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1253 }; 1254 1255 spi0m1_tx: spi0m1-tx { 1256 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1257 }; 1258 1259 spi0m1_rx: spi0m1-rx { 1260 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1261 }; 1262 1263 spi0m1_cs1: spi0m1-cs1 { 1264 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1265 }; 1266 }; 1267 1268 spi0-2 { 1269 spi0m2_clk: spi0m2-clk { 1270 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1271 }; 1272 1273 spi0m2_cs0: spi0m2-cs0 { 1274 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1275 }; 1276 1277 spi0m2_tx: spi0m2-tx { 1278 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1279 }; 1280 1281 spi0m2_rx: spi0m2-rx { 1282 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1283 }; 1284 }; 1285 1286 i2s1 { 1287 i2s1_mclk: i2s1-mclk { 1288 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1289 }; 1290 1291 i2s1_sclk: i2s1-sclk { 1292 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1293 }; 1294 1295 i2s1_lrckrx: i2s1-lrckrx { 1296 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1297 }; 1298 1299 i2s1_lrcktx: i2s1-lrcktx { 1300 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1301 }; 1302 1303 i2s1_sdi: i2s1-sdi { 1304 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1305 }; 1306 1307 i2s1_sdo: i2s1-sdo { 1308 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1309 }; 1310 1311 i2s1_sdio1: i2s1-sdio1 { 1312 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1313 }; 1314 1315 i2s1_sdio2: i2s1-sdio2 { 1316 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1317 }; 1318 1319 i2s1_sdio3: i2s1-sdio3 { 1320 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1321 }; 1322 1323 i2s1_sleep: i2s1-sleep { 1324 rockchip,pins = 1325 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1326 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1327 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1328 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1329 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1330 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1331 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1332 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1333 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1334 }; 1335 }; 1336 1337 i2s2-0 { 1338 i2s2m0_mclk: i2s2m0-mclk { 1339 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1340 }; 1341 1342 i2s2m0_sclk: i2s2m0-sclk { 1343 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1344 }; 1345 1346 i2s2m0_lrckrx: i2s2m0-lrckrx { 1347 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1348 }; 1349 1350 i2s2m0_lrcktx: i2s2m0-lrcktx { 1351 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1352 }; 1353 1354 i2s2m0_sdi: i2s2m0-sdi { 1355 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1356 }; 1357 1358 i2s2m0_sdo: i2s2m0-sdo { 1359 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1360 }; 1361 1362 i2s2m0_sleep: i2s2m0-sleep { 1363 rockchip,pins = 1364 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1365 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1366 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1367 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1368 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1369 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1370 }; 1371 }; 1372 1373 i2s2-1 { 1374 i2s2m1_mclk: i2s2m1-mclk { 1375 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1376 }; 1377 1378 i2s2m1_sclk: i2s2m1-sclk { 1379 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1380 }; 1381 1382 i2s2m1_lrckrx: i2sm1-lrckrx { 1383 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1384 }; 1385 1386 i2s2m1_lrcktx: i2s2m1-lrcktx { 1387 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1388 }; 1389 1390 i2s2m1_sdi: i2s2m1-sdi { 1391 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1392 }; 1393 1394 i2s2m1_sdo: i2s2m1-sdo { 1395 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1396 }; 1397 1398 i2s2m1_sleep: i2s2m1-sleep { 1399 rockchip,pins = 1400 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1401 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1402 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1403 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1404 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1405 }; 1406 }; 1407 1408 spdif-0 { 1409 spdifm0_tx: spdifm0-tx { 1410 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1411 }; 1412 }; 1413 1414 spdif-1 { 1415 spdifm1_tx: spdifm1-tx { 1416 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1417 }; 1418 }; 1419 1420 spdif-2 { 1421 spdifm2_tx: spdifm2-tx { 1422 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1423 }; 1424 }; 1425 1426 sdmmc0-0 { 1427 sdmmc0m0_pwren: sdmmc0m0-pwren { 1428 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1429 }; 1430 1431 sdmmc0m0_gpio: sdmmc0m0-gpio { 1432 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1433 }; 1434 }; 1435 1436 sdmmc0-1 { 1437 sdmmc0m1_pwren: sdmmc0m1-pwren { 1438 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1439 }; 1440 1441 sdmmc0m1_gpio: sdmmc0m1-gpio { 1442 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1443 }; 1444 }; 1445 1446 sdmmc0 { 1447 sdmmc0_clk: sdmmc0-clk { 1448 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>; 1449 }; 1450 1451 sdmmc0_cmd: sdmmc0-cmd { 1452 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>; 1453 }; 1454 1455 sdmmc0_dectn: sdmmc0-dectn { 1456 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1457 }; 1458 1459 sdmmc0_wrprt: sdmmc0-wrprt { 1460 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1461 }; 1462 1463 sdmmc0_bus1: sdmmc0-bus1 { 1464 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>; 1465 }; 1466 1467 sdmmc0_bus4: sdmmc0-bus4 { 1468 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>, 1469 <1 RK_PA1 1 &pcfg_pull_up_4ma>, 1470 <1 RK_PA2 1 &pcfg_pull_up_4ma>, 1471 <1 RK_PA3 1 &pcfg_pull_up_4ma>; 1472 }; 1473 1474 sdmmc0_gpio: sdmmc0-gpio { 1475 rockchip,pins = 1476 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1477 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1478 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1479 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1480 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1481 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1482 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1483 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1484 }; 1485 }; 1486 1487 sdmmc0ext { 1488 sdmmc0ext_clk: sdmmc0ext-clk { 1489 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1490 }; 1491 1492 sdmmc0ext_cmd: sdmmc0ext-cmd { 1493 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1494 }; 1495 1496 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1497 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1498 }; 1499 1500 sdmmc0ext_dectn: sdmmc0ext-dectn { 1501 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1502 }; 1503 1504 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1505 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1506 }; 1507 1508 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1509 rockchip,pins = 1510 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1511 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1512 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1513 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1514 }; 1515 1516 sdmmc0ext_gpio: sdmmc0ext-gpio { 1517 rockchip,pins = 1518 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1519 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1520 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1521 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1522 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1523 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1524 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1525 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1526 }; 1527 }; 1528 1529 sdmmc1 { 1530 sdmmc1_clk: sdmmc1-clk { 1531 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1532 }; 1533 1534 sdmmc1_cmd: sdmmc1-cmd { 1535 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1536 }; 1537 1538 sdmmc1_pwren: sdmmc1-pwren { 1539 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1540 }; 1541 1542 sdmmc1_wrprt: sdmmc1-wrprt { 1543 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1544 }; 1545 1546 sdmmc1_dectn: sdmmc1-dectn { 1547 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1548 }; 1549 1550 sdmmc1_bus1: sdmmc1-bus1 { 1551 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1552 }; 1553 1554 sdmmc1_bus4: sdmmc1-bus4 { 1555 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1556 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1557 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1558 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1559 }; 1560 1561 sdmmc1_gpio: sdmmc1-gpio { 1562 rockchip,pins = 1563 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1564 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1565 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1566 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1567 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1568 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1569 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1570 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1571 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1572 }; 1573 }; 1574 1575 emmc { 1576 emmc_clk: emmc-clk { 1577 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1578 }; 1579 1580 emmc_cmd: emmc-cmd { 1581 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1582 }; 1583 1584 emmc_pwren: emmc-pwren { 1585 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1586 }; 1587 1588 emmc_rstnout: emmc-rstnout { 1589 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1590 }; 1591 1592 emmc_bus1: emmc-bus1 { 1593 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1594 }; 1595 1596 emmc_bus4: emmc-bus4 { 1597 rockchip,pins = 1598 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1599 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1600 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1601 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1602 }; 1603 1604 emmc_bus8: emmc-bus8 { 1605 rockchip,pins = 1606 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1607 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1608 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1609 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1610 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1611 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1612 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1613 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1614 }; 1615 }; 1616 1617 pwm0 { 1618 pwm0_pin: pwm0-pin { 1619 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1620 }; 1621 }; 1622 1623 pwm1 { 1624 pwm1_pin: pwm1-pin { 1625 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1626 }; 1627 }; 1628 1629 pwm2 { 1630 pwm2_pin: pwm2-pin { 1631 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1632 }; 1633 }; 1634 1635 pwmir { 1636 pwmir_pin: pwmir-pin { 1637 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1638 }; 1639 }; 1640 1641 gmac-1 { 1642 rgmiim1_pins: rgmiim1-pins { 1643 rockchip,pins = 1644 /* mac_txclk */ 1645 <1 RK_PB4 2 &pcfg_pull_none_12ma>, 1646 /* mac_rxclk */ 1647 <1 RK_PB5 2 &pcfg_pull_none_2ma>, 1648 /* mac_mdio */ 1649 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1650 /* mac_txen */ 1651 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1652 /* mac_clk */ 1653 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1654 /* mac_rxdv */ 1655 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1656 /* mac_mdc */ 1657 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1658 /* mac_rxd1 */ 1659 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1660 /* mac_rxd0 */ 1661 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1662 /* mac_txd1 */ 1663 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1664 /* mac_txd0 */ 1665 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1666 /* mac_rxd3 */ 1667 <1 RK_PB6 2 &pcfg_pull_none_2ma>, 1668 /* mac_rxd2 */ 1669 <1 RK_PB7 2 &pcfg_pull_none_2ma>, 1670 /* mac_txd3 */ 1671 <1 RK_PC0 2 &pcfg_pull_none_12ma>, 1672 /* mac_txd2 */ 1673 <1 RK_PC1 2 &pcfg_pull_none_12ma>, 1674 1675 /* mac_txclk */ 1676 <0 RK_PB0 1 &pcfg_pull_none>, 1677 /* mac_txen */ 1678 <0 RK_PB4 1 &pcfg_pull_none>, 1679 /* mac_clk */ 1680 <0 RK_PD0 1 &pcfg_pull_none>, 1681 /* mac_txd1 */ 1682 <0 RK_PC0 1 &pcfg_pull_none>, 1683 /* mac_txd0 */ 1684 <0 RK_PC1 1 &pcfg_pull_none>, 1685 /* mac_txd3 */ 1686 <0 RK_PC7 1 &pcfg_pull_none>, 1687 /* mac_txd2 */ 1688 <0 RK_PC6 1 &pcfg_pull_none>; 1689 }; 1690 1691 rmiim1_pins: rmiim1-pins { 1692 rockchip,pins = 1693 /* mac_mdio */ 1694 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1695 /* mac_txen */ 1696 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1697 /* mac_clk */ 1698 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1699 /* mac_rxer */ 1700 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1701 /* mac_rxdv */ 1702 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1703 /* mac_mdc */ 1704 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1705 /* mac_rxd1 */ 1706 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1707 /* mac_rxd0 */ 1708 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1709 /* mac_txd1 */ 1710 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1711 /* mac_txd0 */ 1712 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1713 1714 /* mac_mdio */ 1715 <0 RK_PB3 1 &pcfg_pull_none>, 1716 /* mac_txen */ 1717 <0 RK_PB4 1 &pcfg_pull_none>, 1718 /* mac_clk */ 1719 <0 RK_PD0 1 &pcfg_pull_none>, 1720 /* mac_mdc */ 1721 <0 RK_PC3 1 &pcfg_pull_none>, 1722 /* mac_txd1 */ 1723 <0 RK_PC0 1 &pcfg_pull_none>, 1724 /* mac_txd0 */ 1725 <0 RK_PC1 1 &pcfg_pull_none>; 1726 }; 1727 }; 1728 1729 gmac2phy { 1730 fephyled_speed100: fephyled-speed100 { 1731 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 1732 }; 1733 1734 fephyled_speed10: fephyled-speed10 { 1735 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1736 }; 1737 1738 fephyled_duplex: fephyled-duplex { 1739 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1740 }; 1741 1742 fephyled_rxm0: fephyled-rxm0 { 1743 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>; 1744 }; 1745 1746 fephyled_txm0: fephyled-txm0 { 1747 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>; 1748 }; 1749 1750 fephyled_linkm0: fephyled-linkm0 { 1751 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1752 }; 1753 1754 fephyled_rxm1: fephyled-rxm1 { 1755 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1756 }; 1757 1758 fephyled_txm1: fephyled-txm1 { 1759 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1760 }; 1761 1762 fephyled_linkm1: fephyled-linkm1 { 1763 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1764 }; 1765 }; 1766 1767 tsadc_pin { 1768 tsadc_int: tsadc-int { 1769 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1770 }; 1771 tsadc_gpio: tsadc-gpio { 1772 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1773 }; 1774 }; 1775 1776 hdmi_pin { 1777 hdmi_cec: hdmi-cec { 1778 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1779 }; 1780 1781 hdmi_hpd: hdmi-hpd { 1782 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1783 }; 1784 }; 1785 1786 cif-0 { 1787 dvp_d2d9_m0:dvp-d2d9-m0 { 1788 rockchip,pins = 1789 /* cif_d0 */ 1790 <3 RK_PA4 2 &pcfg_pull_none>, 1791 /* cif_d1 */ 1792 <3 RK_PA5 2 &pcfg_pull_none>, 1793 /* cif_d2 */ 1794 <3 RK_PA6 2 &pcfg_pull_none>, 1795 /* cif_d3 */ 1796 <3 RK_PA7 2 &pcfg_pull_none>, 1797 /* cif_d4 */ 1798 <3 RK_PB0 2 &pcfg_pull_none>, 1799 /* cif_d5m0 */ 1800 <3 RK_PB1 2 &pcfg_pull_none>, 1801 /* cif_d6m0 */ 1802 <3 RK_PB2 2 &pcfg_pull_none>, 1803 /* cif_d7m0 */ 1804 <3 RK_PB3 2 &pcfg_pull_none>, 1805 /* cif_href */ 1806 <3 RK_PA1 2 &pcfg_pull_none>, 1807 /* cif_vsync */ 1808 <3 RK_PA0 2 &pcfg_pull_none>, 1809 /* cif_clkoutm0 */ 1810 <3 RK_PA3 2 &pcfg_pull_none>, 1811 /* cif_clkin */ 1812 <3 RK_PA2 2 &pcfg_pull_none>; 1813 }; 1814 }; 1815 1816 cif-1 { 1817 dvp_d2d9_m1:dvp-d2d9-m1 { 1818 rockchip,pins = 1819 /* cif_d0 */ 1820 <3 RK_PA4 2 &pcfg_pull_none>, 1821 /* cif_d1 */ 1822 <3 RK_PA5 2 &pcfg_pull_none>, 1823 /* cif_d2 */ 1824 <3 RK_PA6 2 &pcfg_pull_none>, 1825 /* cif_d3 */ 1826 <3 RK_PA7 2 &pcfg_pull_none>, 1827 /* cif_d4 */ 1828 <3 RK_PB0 2 &pcfg_pull_none>, 1829 /* cif_d5m1 */ 1830 <2 RK_PC0 4 &pcfg_pull_none>, 1831 /* cif_d6m1 */ 1832 <2 RK_PC1 4 &pcfg_pull_none>, 1833 /* cif_d7m1 */ 1834 <2 RK_PC2 4 &pcfg_pull_none>, 1835 /* cif_href */ 1836 <3 RK_PA1 2 &pcfg_pull_none>, 1837 /* cif_vsync */ 1838 <3 RK_PA0 2 &pcfg_pull_none>, 1839 /* cif_clkoutm1 */ 1840 <2 RK_PB7 4 &pcfg_pull_none>, 1841 /* cif_clkin */ 1842 <3 RK_PA2 2 &pcfg_pull_none>; 1843 }; 1844 }; 1845 }; 1846}; 1847