1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53", "arm,armv8"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 dynamic-power-coefficient = <120>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 operating-points-v2 = <&cpu0_opp_table>; 48 }; 49 50 cpu1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53", "arm,armv8"; 53 reg = <0x0 0x1>; 54 clocks = <&cru ARMCLK>; 55 #cooling-cells = <2>; 56 dynamic-power-coefficient = <120>; 57 enable-method = "psci"; 58 next-level-cache = <&l2>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 }; 61 62 cpu2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53", "arm,armv8"; 65 reg = <0x0 0x2>; 66 clocks = <&cru ARMCLK>; 67 #cooling-cells = <2>; 68 dynamic-power-coefficient = <120>; 69 enable-method = "psci"; 70 next-level-cache = <&l2>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53", "arm,armv8"; 77 reg = <0x0 0x3>; 78 clocks = <&cru ARMCLK>; 79 #cooling-cells = <2>; 80 dynamic-power-coefficient = <120>; 81 enable-method = "psci"; 82 next-level-cache = <&l2>; 83 operating-points-v2 = <&cpu0_opp_table>; 84 }; 85 86 l2: l2-cache0 { 87 compatible = "cache"; 88 }; 89 }; 90 91 cpu0_opp_table: opp_table0 { 92 compatible = "operating-points-v2"; 93 opp-shared; 94 95 opp-408000000 { 96 opp-hz = /bits/ 64 <408000000>; 97 opp-microvolt = <950000>; 98 clock-latency-ns = <40000>; 99 opp-suspend; 100 }; 101 opp-600000000 { 102 opp-hz = /bits/ 64 <600000000>; 103 opp-microvolt = <950000>; 104 clock-latency-ns = <40000>; 105 }; 106 opp-816000000 { 107 opp-hz = /bits/ 64 <816000000>; 108 opp-microvolt = <1000000>; 109 clock-latency-ns = <40000>; 110 }; 111 opp-1008000000 { 112 opp-hz = /bits/ 64 <1008000000>; 113 opp-microvolt = <1100000>; 114 clock-latency-ns = <40000>; 115 }; 116 opp-1200000000 { 117 opp-hz = /bits/ 64 <1200000000>; 118 opp-microvolt = <1225000>; 119 clock-latency-ns = <40000>; 120 }; 121 opp-1296000000 { 122 opp-hz = /bits/ 64 <1296000000>; 123 opp-microvolt = <1300000>; 124 clock-latency-ns = <40000>; 125 }; 126 }; 127 128 amba { 129 compatible = "simple-bus"; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 134 dmac: dmac@ff1f0000 { 135 compatible = "arm,pl330", "arm,primecell"; 136 reg = <0x0 0xff1f0000 0x0 0x4000>; 137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&cru ACLK_DMAC>; 140 clock-names = "apb_pclk"; 141 #dma-cells = <1>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 psci { 155 compatible = "arm,psci-1.0", "arm,psci-0.2"; 156 method = "smc"; 157 }; 158 159 timer { 160 compatible = "arm,armv8-timer"; 161 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 162 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 163 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 164 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 165 }; 166 167 xin24m: xin24m { 168 compatible = "fixed-clock"; 169 #clock-cells = <0>; 170 clock-frequency = <24000000>; 171 clock-output-names = "xin24m"; 172 }; 173 174 i2s0: i2s@ff000000 { 175 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 176 reg = <0x0 0xff000000 0x0 0x1000>; 177 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 179 clock-names = "i2s_clk", "i2s_hclk"; 180 dmas = <&dmac 11>, <&dmac 12>; 181 dma-names = "tx", "rx"; 182 status = "disabled"; 183 }; 184 185 i2s1: i2s@ff010000 { 186 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 187 reg = <0x0 0xff010000 0x0 0x1000>; 188 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 190 clock-names = "i2s_clk", "i2s_hclk"; 191 dmas = <&dmac 14>, <&dmac 15>; 192 dma-names = "tx", "rx"; 193 status = "disabled"; 194 }; 195 196 i2s2: i2s@ff020000 { 197 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 198 reg = <0x0 0xff020000 0x0 0x1000>; 199 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 201 clock-names = "i2s_clk", "i2s_hclk"; 202 dmas = <&dmac 0>, <&dmac 1>; 203 dma-names = "tx", "rx"; 204 status = "disabled"; 205 }; 206 207 spdif: spdif@ff030000 { 208 compatible = "rockchip,rk3328-spdif"; 209 reg = <0x0 0xff030000 0x0 0x1000>; 210 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 212 clock-names = "mclk", "hclk"; 213 dmas = <&dmac 10>; 214 dma-names = "tx"; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&spdifm2_tx>; 217 status = "disabled"; 218 }; 219 220 pdm: pdm@ff040000 { 221 compatible = "rockchip,pdm"; 222 reg = <0x0 0xff040000 0x0 0x1000>; 223 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 224 clock-names = "pdm_clk", "pdm_hclk"; 225 dmas = <&dmac 16>; 226 dma-names = "rx"; 227 pinctrl-names = "default", "sleep"; 228 pinctrl-0 = <&pdmm0_clk 229 &pdmm0_sdi0 230 &pdmm0_sdi1 231 &pdmm0_sdi2 232 &pdmm0_sdi3>; 233 pinctrl-1 = <&pdmm0_clk_sleep 234 &pdmm0_sdi0_sleep 235 &pdmm0_sdi1_sleep 236 &pdmm0_sdi2_sleep 237 &pdmm0_sdi3_sleep>; 238 status = "disabled"; 239 }; 240 241 grf: syscon@ff100000 { 242 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 243 reg = <0x0 0xff100000 0x0 0x1000>; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 247 io_domains: io-domains { 248 compatible = "rockchip,rk3328-io-voltage-domain"; 249 status = "disabled"; 250 }; 251 252 power: power-controller { 253 compatible = "rockchip,rk3328-power-controller"; 254 #power-domain-cells = <1>; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 258 pd_hevc@RK3328_PD_HEVC { 259 reg = <RK3328_PD_HEVC>; 260 }; 261 pd_video@RK3328_PD_VIDEO { 262 reg = <RK3328_PD_VIDEO>; 263 }; 264 pd_vpu@RK3328_PD_VPU { 265 reg = <RK3328_PD_VPU>; 266 }; 267 }; 268 269 reboot-mode { 270 compatible = "syscon-reboot-mode"; 271 offset = <0x5c8>; 272 mode-normal = <BOOT_NORMAL>; 273 mode-recovery = <BOOT_RECOVERY>; 274 mode-bootloader = <BOOT_FASTBOOT>; 275 mode-loader = <BOOT_BL_DOWNLOAD>; 276 }; 277 278 }; 279 280 uart0: serial@ff110000 { 281 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 282 reg = <0x0 0xff110000 0x0 0x100>; 283 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 285 clock-names = "baudclk", "apb_pclk"; 286 dmas = <&dmac 2>, <&dmac 3>; 287 dma-names = "tx", "rx"; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 290 reg-io-width = <4>; 291 reg-shift = <2>; 292 status = "disabled"; 293 }; 294 295 uart1: serial@ff120000 { 296 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 297 reg = <0x0 0xff120000 0x0 0x100>; 298 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 300 clock-names = "baudclk", "apb_pclk"; 301 dmas = <&dmac 4>, <&dmac 5>; 302 dma-names = "tx", "rx"; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 305 reg-io-width = <4>; 306 reg-shift = <2>; 307 status = "disabled"; 308 }; 309 310 uart2: serial@ff130000 { 311 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 312 reg = <0x0 0xff130000 0x0 0x100>; 313 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 315 clock-names = "baudclk", "apb_pclk"; 316 dmas = <&dmac 6>, <&dmac 7>; 317 dma-names = "tx", "rx"; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&uart2m1_xfer>; 320 reg-io-width = <4>; 321 reg-shift = <2>; 322 status = "disabled"; 323 }; 324 325 i2c0: i2c@ff150000 { 326 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 327 reg = <0x0 0xff150000 0x0 0x1000>; 328 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 332 clock-names = "i2c", "pclk"; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&i2c0_xfer>; 335 status = "disabled"; 336 }; 337 338 i2c1: i2c@ff160000 { 339 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 340 reg = <0x0 0xff160000 0x0 0x1000>; 341 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 345 clock-names = "i2c", "pclk"; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&i2c1_xfer>; 348 status = "disabled"; 349 }; 350 351 i2c2: i2c@ff170000 { 352 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 353 reg = <0x0 0xff170000 0x0 0x1000>; 354 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 358 clock-names = "i2c", "pclk"; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&i2c2_xfer>; 361 status = "disabled"; 362 }; 363 364 i2c3: i2c@ff180000 { 365 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 366 reg = <0x0 0xff180000 0x0 0x1000>; 367 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 371 clock-names = "i2c", "pclk"; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&i2c3_xfer>; 374 status = "disabled"; 375 }; 376 377 spi0: spi@ff190000 { 378 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 379 reg = <0x0 0xff190000 0x0 0x1000>; 380 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 384 clock-names = "spiclk", "apb_pclk"; 385 dmas = <&dmac 8>, <&dmac 9>; 386 dma-names = "tx", "rx"; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 389 status = "disabled"; 390 }; 391 392 wdt: watchdog@ff1a0000 { 393 compatible = "snps,dw-wdt"; 394 reg = <0x0 0xff1a0000 0x0 0x100>; 395 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 396 }; 397 398 pwm0: pwm@ff1b0000 { 399 compatible = "rockchip,rk3328-pwm"; 400 reg = <0x0 0xff1b0000 0x0 0x10>; 401 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 402 clock-names = "pwm", "pclk"; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&pwm0_pin>; 405 #pwm-cells = <3>; 406 status = "disabled"; 407 }; 408 409 pwm1: pwm@ff1b0010 { 410 compatible = "rockchip,rk3328-pwm"; 411 reg = <0x0 0xff1b0010 0x0 0x10>; 412 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 413 clock-names = "pwm", "pclk"; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&pwm1_pin>; 416 #pwm-cells = <3>; 417 status = "disabled"; 418 }; 419 420 pwm2: pwm@ff1b0020 { 421 compatible = "rockchip,rk3328-pwm"; 422 reg = <0x0 0xff1b0020 0x0 0x10>; 423 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 424 clock-names = "pwm", "pclk"; 425 pinctrl-names = "default"; 426 pinctrl-0 = <&pwm2_pin>; 427 #pwm-cells = <3>; 428 status = "disabled"; 429 }; 430 431 pwm3: pwm@ff1b0030 { 432 compatible = "rockchip,rk3328-pwm"; 433 reg = <0x0 0xff1b0030 0x0 0x10>; 434 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 436 clock-names = "pwm", "pclk"; 437 pinctrl-names = "default"; 438 pinctrl-0 = <&pwmir_pin>; 439 #pwm-cells = <3>; 440 status = "disabled"; 441 }; 442 443 thermal-zones { 444 soc_thermal: soc-thermal { 445 polling-delay-passive = <20>; 446 polling-delay = <1000>; 447 sustainable-power = <1000>; 448 449 thermal-sensors = <&tsadc 0>; 450 451 trips { 452 threshold: trip-point0 { 453 temperature = <70000>; 454 hysteresis = <2000>; 455 type = "passive"; 456 }; 457 target: trip-point1 { 458 temperature = <85000>; 459 hysteresis = <2000>; 460 type = "passive"; 461 }; 462 soc_crit: soc-crit { 463 temperature = <95000>; 464 hysteresis = <2000>; 465 type = "critical"; 466 }; 467 }; 468 469 cooling-maps { 470 map0 { 471 trip = <&target>; 472 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 473 contribution = <4096>; 474 }; 475 }; 476 }; 477 478 }; 479 480 tsadc: tsadc@ff250000 { 481 compatible = "rockchip,rk3328-tsadc"; 482 reg = <0x0 0xff250000 0x0 0x100>; 483 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 484 assigned-clocks = <&cru SCLK_TSADC>; 485 assigned-clock-rates = <50000>; 486 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 487 clock-names = "tsadc", "apb_pclk"; 488 pinctrl-names = "init", "default", "sleep"; 489 pinctrl-0 = <&otp_gpio>; 490 pinctrl-1 = <&otp_out>; 491 pinctrl-2 = <&otp_gpio>; 492 resets = <&cru SRST_TSADC>; 493 reset-names = "tsadc-apb"; 494 rockchip,grf = <&grf>; 495 rockchip,hw-tshut-temp = <100000>; 496 #thermal-sensor-cells = <1>; 497 status = "disabled"; 498 }; 499 500 efuse: efuse@ff260000 { 501 compatible = "rockchip,rk3328-efuse"; 502 reg = <0x0 0xff260000 0x0 0x50>; 503 #address-cells = <1>; 504 #size-cells = <1>; 505 clocks = <&cru SCLK_EFUSE>; 506 clock-names = "pclk_efuse"; 507 rockchip,efuse-size = <0x20>; 508 509 /* Data cells */ 510 efuse_id: id@7 { 511 reg = <0x07 0x10>; 512 }; 513 cpu_leakage: cpu-leakage@17 { 514 reg = <0x17 0x1>; 515 }; 516 logic_leakage: logic-leakage@19 { 517 reg = <0x19 0x1>; 518 }; 519 efuse_cpu_version: cpu-version@1a { 520 reg = <0x1a 0x1>; 521 bits = <3 3>; 522 }; 523 }; 524 525 saradc: adc@ff280000 { 526 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 527 reg = <0x0 0xff280000 0x0 0x100>; 528 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 529 #io-channel-cells = <1>; 530 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 531 clock-names = "saradc", "apb_pclk"; 532 resets = <&cru SRST_SARADC_P>; 533 reset-names = "saradc-apb"; 534 status = "disabled"; 535 }; 536 537 gpu: gpu@ff300000 { 538 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 539 reg = <0x0 0xff300000 0x0 0x40000>; 540 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 547 interrupt-names = "gp", 548 "gpmmu", 549 "pp", 550 "pp0", 551 "ppmmu0", 552 "pp1", 553 "ppmmu1"; 554 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 555 clock-names = "bus", "core"; 556 resets = <&cru SRST_GPU_A>; 557 }; 558 559 h265e_mmu: iommu@ff330200 { 560 compatible = "rockchip,iommu"; 561 reg = <0x0 0xff330200 0 0x100>; 562 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 563 interrupt-names = "h265e_mmu"; 564 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 565 clock-names = "aclk", "iface"; 566 #iommu-cells = <0>; 567 status = "disabled"; 568 }; 569 570 vepu_mmu: iommu@ff340800 { 571 compatible = "rockchip,iommu"; 572 reg = <0x0 0xff340800 0x0 0x40>; 573 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "vepu_mmu"; 575 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 576 clock-names = "aclk", "iface"; 577 #iommu-cells = <0>; 578 status = "disabled"; 579 }; 580 581 vpu_mmu: iommu@ff350800 { 582 compatible = "rockchip,iommu"; 583 reg = <0x0 0xff350800 0x0 0x40>; 584 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 585 interrupt-names = "vpu_mmu"; 586 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 587 clock-names = "aclk", "iface"; 588 #iommu-cells = <0>; 589 status = "disabled"; 590 }; 591 592 rkvdec_mmu: iommu@ff360480 { 593 compatible = "rockchip,iommu"; 594 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 595 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 596 interrupt-names = "rkvdec_mmu"; 597 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 598 clock-names = "aclk", "iface"; 599 #iommu-cells = <0>; 600 status = "disabled"; 601 }; 602 603 vop_mmu: iommu@ff373f00 { 604 compatible = "rockchip,iommu"; 605 reg = <0x0 0xff373f00 0x0 0x100>; 606 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 607 interrupt-names = "vop_mmu"; 608 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 609 clock-names = "aclk", "iface"; 610 #iommu-cells = <0>; 611 status = "disabled"; 612 }; 613 614 cru: clock-controller@ff440000 { 615 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 616 reg = <0x0 0xff440000 0x0 0x1000>; 617 rockchip,grf = <&grf>; 618 #clock-cells = <1>; 619 #reset-cells = <1>; 620 assigned-clocks = 621 /* 622 * CPLL should run at 1200, but that is to high for 623 * the initial dividers of most of its children. 624 * We need set cpll child clk div first, 625 * and then set the cpll frequency. 626 */ 627 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 628 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 629 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 630 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 631 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 632 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 633 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 634 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 635 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 636 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 637 <&cru SCLK_WIFI>, <&cru ARMCLK>, 638 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 639 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 640 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 641 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 642 <&cru SCLK_RTC32K>; 643 assigned-clock-parents = 644 <&cru HDMIPHY>, <&cru PLL_APLL>, 645 <&cru PLL_GPLL>, <&xin24m>, 646 <&xin24m>, <&xin24m>; 647 assigned-clock-rates = 648 <0>, <61440000>, 649 <0>, <24000000>, 650 <24000000>, <24000000>, 651 <15000000>, <15000000>, 652 <100000000>, <100000000>, 653 <100000000>, <100000000>, 654 <50000000>, <100000000>, 655 <100000000>, <100000000>, 656 <50000000>, <50000000>, 657 <50000000>, <50000000>, 658 <24000000>, <600000000>, 659 <491520000>, <1200000000>, 660 <150000000>, <75000000>, 661 <75000000>, <150000000>, 662 <75000000>, <75000000>, 663 <32768>; 664 }; 665 666 usb2phy_grf: syscon@ff450000 { 667 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 668 "simple-mfd"; 669 reg = <0x0 0xff450000 0x0 0x10000>; 670 #address-cells = <1>; 671 #size-cells = <1>; 672 673 u2phy: usb2-phy@100 { 674 compatible = "rockchip,rk3328-usb2phy"; 675 reg = <0x100 0x10>; 676 clocks = <&xin24m>; 677 clock-names = "phyclk"; 678 clock-output-names = "usb480m_phy"; 679 #clock-cells = <0>; 680 assigned-clocks = <&cru USB480M>; 681 assigned-clock-parents = <&u2phy>; 682 status = "disabled"; 683 684 u2phy_otg: otg-port { 685 #phy-cells = <0>; 686 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 689 interrupt-names = "otg-bvalid", "otg-id", 690 "linestate"; 691 status = "disabled"; 692 }; 693 694 u2phy_host: host-port { 695 #phy-cells = <0>; 696 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 697 interrupt-names = "linestate"; 698 status = "disabled"; 699 }; 700 }; 701 }; 702 703 sdmmc: dwmmc@ff500000 { 704 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 705 reg = <0x0 0xff500000 0x0 0x4000>; 706 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 708 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 709 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 710 fifo-depth = <0x100>; 711 status = "disabled"; 712 }; 713 714 sdio: dwmmc@ff510000 { 715 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 716 reg = <0x0 0xff510000 0x0 0x4000>; 717 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 719 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 720 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 721 fifo-depth = <0x100>; 722 status = "disabled"; 723 }; 724 725 emmc: dwmmc@ff520000 { 726 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 727 reg = <0x0 0xff520000 0x0 0x4000>; 728 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 730 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 731 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 732 fifo-depth = <0x100>; 733 status = "disabled"; 734 }; 735 736 gmac2io: ethernet@ff540000 { 737 compatible = "rockchip,rk3328-gmac"; 738 reg = <0x0 0xff540000 0x0 0x10000>; 739 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 740 interrupt-names = "macirq"; 741 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 742 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 743 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 744 <&cru PCLK_MAC2IO>; 745 clock-names = "stmmaceth", "mac_clk_rx", 746 "mac_clk_tx", "clk_mac_ref", 747 "clk_mac_refout", "aclk_mac", 748 "pclk_mac"; 749 resets = <&cru SRST_GMAC2IO_A>; 750 reset-names = "stmmaceth"; 751 rockchip,grf = <&grf>; 752 status = "disabled"; 753 }; 754 755 gmac2phy: ethernet@ff550000 { 756 compatible = "rockchip,rk3328-gmac"; 757 reg = <0x0 0xff550000 0x0 0x10000>; 758 rockchip,grf = <&grf>; 759 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 760 interrupt-names = "macirq"; 761 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 762 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 763 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 764 <&cru SCLK_MAC2PHY_OUT>; 765 clock-names = "stmmaceth", "mac_clk_rx", 766 "mac_clk_tx", "clk_mac_ref", 767 "aclk_mac", "pclk_mac", 768 "clk_macphy"; 769 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; 770 reset-names = "stmmaceth", "mac-phy"; 771 phy-mode = "rmii"; 772 phy-handle = <&phy>; 773 status = "disabled"; 774 775 mdio { 776 compatible = "snps,dwmac-mdio"; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 780 phy: phy@0 { 781 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 782 reg = <0>; 783 clocks = <&cru SCLK_MAC2PHY_OUT>; 784 resets = <&cru SRST_MACPHY>; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 787 phy-is-integrated; 788 }; 789 }; 790 }; 791 792 usb20_otg: usb@ff580000 { 793 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 794 "snps,dwc2"; 795 reg = <0x0 0xff580000 0x0 0x40000>; 796 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cru HCLK_OTG>; 798 clock-names = "otg"; 799 dr_mode = "otg"; 800 g-np-tx-fifo-size = <16>; 801 g-rx-fifo-size = <280>; 802 g-tx-fifo-size = <256 128 128 64 32 16>; 803 g-use-dma; 804 phys = <&u2phy_otg>; 805 phy-names = "usb2-phy"; 806 status = "disabled"; 807 }; 808 809 usb_host0_ehci: usb@ff5c0000 { 810 compatible = "generic-ehci"; 811 reg = <0x0 0xff5c0000 0x0 0x10000>; 812 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&cru HCLK_HOST0>, <&u2phy>; 814 clock-names = "usbhost", "utmi"; 815 phys = <&u2phy_host>; 816 phy-names = "usb"; 817 status = "disabled"; 818 }; 819 820 usb_host0_ohci: usb@ff5d0000 { 821 compatible = "generic-ohci"; 822 reg = <0x0 0xff5d0000 0x0 0x10000>; 823 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&cru HCLK_HOST0>, <&u2phy>; 825 clock-names = "usbhost", "utmi"; 826 phys = <&u2phy_host>; 827 phy-names = "usb"; 828 status = "disabled"; 829 }; 830 831 gic: interrupt-controller@ff811000 { 832 compatible = "arm,gic-400"; 833 #interrupt-cells = <3>; 834 #address-cells = <0>; 835 interrupt-controller; 836 reg = <0x0 0xff811000 0 0x1000>, 837 <0x0 0xff812000 0 0x2000>, 838 <0x0 0xff814000 0 0x2000>, 839 <0x0 0xff816000 0 0x2000>; 840 interrupts = <GIC_PPI 9 841 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 842 }; 843 844 pinctrl: pinctrl { 845 compatible = "rockchip,rk3328-pinctrl"; 846 rockchip,grf = <&grf>; 847 #address-cells = <2>; 848 #size-cells = <2>; 849 ranges; 850 851 gpio0: gpio0@ff210000 { 852 compatible = "rockchip,gpio-bank"; 853 reg = <0x0 0xff210000 0x0 0x100>; 854 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&cru PCLK_GPIO0>; 856 857 gpio-controller; 858 #gpio-cells = <2>; 859 860 interrupt-controller; 861 #interrupt-cells = <2>; 862 }; 863 864 gpio1: gpio1@ff220000 { 865 compatible = "rockchip,gpio-bank"; 866 reg = <0x0 0xff220000 0x0 0x100>; 867 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cru PCLK_GPIO1>; 869 870 gpio-controller; 871 #gpio-cells = <2>; 872 873 interrupt-controller; 874 #interrupt-cells = <2>; 875 }; 876 877 gpio2: gpio2@ff230000 { 878 compatible = "rockchip,gpio-bank"; 879 reg = <0x0 0xff230000 0x0 0x100>; 880 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&cru PCLK_GPIO2>; 882 883 gpio-controller; 884 #gpio-cells = <2>; 885 886 interrupt-controller; 887 #interrupt-cells = <2>; 888 }; 889 890 gpio3: gpio3@ff240000 { 891 compatible = "rockchip,gpio-bank"; 892 reg = <0x0 0xff240000 0x0 0x100>; 893 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&cru PCLK_GPIO3>; 895 896 gpio-controller; 897 #gpio-cells = <2>; 898 899 interrupt-controller; 900 #interrupt-cells = <2>; 901 }; 902 903 pcfg_pull_up: pcfg-pull-up { 904 bias-pull-up; 905 }; 906 907 pcfg_pull_down: pcfg-pull-down { 908 bias-pull-down; 909 }; 910 911 pcfg_pull_none: pcfg-pull-none { 912 bias-disable; 913 }; 914 915 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 916 bias-disable; 917 drive-strength = <2>; 918 }; 919 920 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 921 bias-pull-up; 922 drive-strength = <2>; 923 }; 924 925 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 926 bias-pull-up; 927 drive-strength = <4>; 928 }; 929 930 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 931 bias-disable; 932 drive-strength = <4>; 933 }; 934 935 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 936 bias-pull-down; 937 drive-strength = <4>; 938 }; 939 940 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 941 bias-disable; 942 drive-strength = <8>; 943 }; 944 945 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 946 bias-pull-up; 947 drive-strength = <8>; 948 }; 949 950 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 951 bias-disable; 952 drive-strength = <12>; 953 }; 954 955 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 956 bias-pull-up; 957 drive-strength = <12>; 958 }; 959 960 pcfg_output_high: pcfg-output-high { 961 output-high; 962 }; 963 964 pcfg_output_low: pcfg-output-low { 965 output-low; 966 }; 967 968 pcfg_input_high: pcfg-input-high { 969 bias-pull-up; 970 input-enable; 971 }; 972 973 pcfg_input: pcfg-input { 974 input-enable; 975 }; 976 977 i2c0 { 978 i2c0_xfer: i2c0-xfer { 979 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 980 <2 RK_PD1 1 &pcfg_pull_none>; 981 }; 982 }; 983 984 i2c1 { 985 i2c1_xfer: i2c1-xfer { 986 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 987 <2 RK_PA5 2 &pcfg_pull_none>; 988 }; 989 }; 990 991 i2c2 { 992 i2c2_xfer: i2c2-xfer { 993 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 994 <2 RK_PB6 1 &pcfg_pull_none>; 995 }; 996 }; 997 998 i2c3 { 999 i2c3_xfer: i2c3-xfer { 1000 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1001 <0 RK_PA6 2 &pcfg_pull_none>; 1002 }; 1003 i2c3_gpio: i2c3-gpio { 1004 rockchip,pins = 1005 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1006 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1007 }; 1008 }; 1009 1010 hdmi_i2c { 1011 hdmii2c_xfer: hdmii2c-xfer { 1012 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1013 <0 RK_PA6 1 &pcfg_pull_none>; 1014 }; 1015 }; 1016 1017 pdm-0 { 1018 pdmm0_clk: pdmm0-clk { 1019 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1020 }; 1021 1022 pdmm0_fsync: pdmm0-fsync { 1023 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1024 }; 1025 1026 pdmm0_sdi0: pdmm0-sdi0 { 1027 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1028 }; 1029 1030 pdmm0_sdi1: pdmm0-sdi1 { 1031 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1032 }; 1033 1034 pdmm0_sdi2: pdmm0-sdi2 { 1035 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1036 }; 1037 1038 pdmm0_sdi3: pdmm0-sdi3 { 1039 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1040 }; 1041 1042 pdmm0_clk_sleep: pdmm0-clk-sleep { 1043 rockchip,pins = 1044 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1045 }; 1046 1047 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1048 rockchip,pins = 1049 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1050 }; 1051 1052 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1053 rockchip,pins = 1054 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1055 }; 1056 1057 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1058 rockchip,pins = 1059 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1060 }; 1061 1062 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1063 rockchip,pins = 1064 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1065 }; 1066 1067 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1068 rockchip,pins = 1069 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1070 }; 1071 }; 1072 1073 tsadc { 1074 otp_gpio: otp-gpio { 1075 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1076 }; 1077 1078 otp_out: otp-out { 1079 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1080 }; 1081 }; 1082 1083 uart0 { 1084 uart0_xfer: uart0-xfer { 1085 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, 1086 <1 RK_PB0 1 &pcfg_pull_none>; 1087 }; 1088 1089 uart0_cts: uart0-cts { 1090 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1091 }; 1092 1093 uart0_rts: uart0-rts { 1094 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1095 }; 1096 1097 uart0_rts_gpio: uart0-rts-gpio { 1098 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1099 }; 1100 }; 1101 1102 uart1 { 1103 uart1_xfer: uart1-xfer { 1104 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, 1105 <3 RK_PA6 4 &pcfg_pull_none>; 1106 }; 1107 1108 uart1_cts: uart1-cts { 1109 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1110 }; 1111 1112 uart1_rts: uart1-rts { 1113 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1114 }; 1115 1116 uart1_rts_gpio: uart1-rts-gpio { 1117 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1118 }; 1119 }; 1120 1121 uart2-0 { 1122 uart2m0_xfer: uart2m0-xfer { 1123 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, 1124 <1 RK_PA1 2 &pcfg_pull_none>; 1125 }; 1126 }; 1127 1128 uart2-1 { 1129 uart2m1_xfer: uart2m1-xfer { 1130 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, 1131 <2 RK_PA1 1 &pcfg_pull_none>; 1132 }; 1133 }; 1134 1135 spi0-0 { 1136 spi0m0_clk: spi0m0-clk { 1137 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1138 }; 1139 1140 spi0m0_cs0: spi0m0-cs0 { 1141 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1142 }; 1143 1144 spi0m0_tx: spi0m0-tx { 1145 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1146 }; 1147 1148 spi0m0_rx: spi0m0-rx { 1149 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1150 }; 1151 1152 spi0m0_cs1: spi0m0-cs1 { 1153 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1154 }; 1155 }; 1156 1157 spi0-1 { 1158 spi0m1_clk: spi0m1-clk { 1159 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1160 }; 1161 1162 spi0m1_cs0: spi0m1-cs0 { 1163 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1164 }; 1165 1166 spi0m1_tx: spi0m1-tx { 1167 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1168 }; 1169 1170 spi0m1_rx: spi0m1-rx { 1171 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1172 }; 1173 1174 spi0m1_cs1: spi0m1-cs1 { 1175 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1176 }; 1177 }; 1178 1179 spi0-2 { 1180 spi0m2_clk: spi0m2-clk { 1181 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1182 }; 1183 1184 spi0m2_cs0: spi0m2-cs0 { 1185 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1186 }; 1187 1188 spi0m2_tx: spi0m2-tx { 1189 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1190 }; 1191 1192 spi0m2_rx: spi0m2-rx { 1193 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1194 }; 1195 }; 1196 1197 i2s1 { 1198 i2s1_mclk: i2s1-mclk { 1199 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1200 }; 1201 1202 i2s1_sclk: i2s1-sclk { 1203 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1204 }; 1205 1206 i2s1_lrckrx: i2s1-lrckrx { 1207 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1208 }; 1209 1210 i2s1_lrcktx: i2s1-lrcktx { 1211 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1212 }; 1213 1214 i2s1_sdi: i2s1-sdi { 1215 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1216 }; 1217 1218 i2s1_sdo: i2s1-sdo { 1219 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1220 }; 1221 1222 i2s1_sdio1: i2s1-sdio1 { 1223 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1224 }; 1225 1226 i2s1_sdio2: i2s1-sdio2 { 1227 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1228 }; 1229 1230 i2s1_sdio3: i2s1-sdio3 { 1231 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1232 }; 1233 1234 i2s1_sleep: i2s1-sleep { 1235 rockchip,pins = 1236 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1237 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1238 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1239 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1240 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1241 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1242 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1243 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1244 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1245 }; 1246 }; 1247 1248 i2s2-0 { 1249 i2s2m0_mclk: i2s2m0-mclk { 1250 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1251 }; 1252 1253 i2s2m0_sclk: i2s2m0-sclk { 1254 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1255 }; 1256 1257 i2s2m0_lrckrx: i2s2m0-lrckrx { 1258 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1259 }; 1260 1261 i2s2m0_lrcktx: i2s2m0-lrcktx { 1262 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1263 }; 1264 1265 i2s2m0_sdi: i2s2m0-sdi { 1266 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1267 }; 1268 1269 i2s2m0_sdo: i2s2m0-sdo { 1270 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1271 }; 1272 1273 i2s2m0_sleep: i2s2m0-sleep { 1274 rockchip,pins = 1275 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1276 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1277 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1278 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1279 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1280 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1281 }; 1282 }; 1283 1284 i2s2-1 { 1285 i2s2m1_mclk: i2s2m1-mclk { 1286 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1287 }; 1288 1289 i2s2m1_sclk: i2s2m1-sclk { 1290 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1291 }; 1292 1293 i2s2m1_lrckrx: i2sm1-lrckrx { 1294 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1295 }; 1296 1297 i2s2m1_lrcktx: i2s2m1-lrcktx { 1298 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1299 }; 1300 1301 i2s2m1_sdi: i2s2m1-sdi { 1302 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1303 }; 1304 1305 i2s2m1_sdo: i2s2m1-sdo { 1306 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1307 }; 1308 1309 i2s2m1_sleep: i2s2m1-sleep { 1310 rockchip,pins = 1311 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1312 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1313 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1314 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1315 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1316 }; 1317 }; 1318 1319 spdif-0 { 1320 spdifm0_tx: spdifm0-tx { 1321 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1322 }; 1323 }; 1324 1325 spdif-1 { 1326 spdifm1_tx: spdifm1-tx { 1327 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1328 }; 1329 }; 1330 1331 spdif-2 { 1332 spdifm2_tx: spdifm2-tx { 1333 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1334 }; 1335 }; 1336 1337 sdmmc0-0 { 1338 sdmmc0m0_pwren: sdmmc0m0-pwren { 1339 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1340 }; 1341 1342 sdmmc0m0_gpio: sdmmc0m0-gpio { 1343 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1344 }; 1345 }; 1346 1347 sdmmc0-1 { 1348 sdmmc0m1_pwren: sdmmc0m1-pwren { 1349 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1350 }; 1351 1352 sdmmc0m1_gpio: sdmmc0m1-gpio { 1353 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1354 }; 1355 }; 1356 1357 sdmmc0 { 1358 sdmmc0_clk: sdmmc0-clk { 1359 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>; 1360 }; 1361 1362 sdmmc0_cmd: sdmmc0-cmd { 1363 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>; 1364 }; 1365 1366 sdmmc0_dectn: sdmmc0-dectn { 1367 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1368 }; 1369 1370 sdmmc0_wrprt: sdmmc0-wrprt { 1371 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1372 }; 1373 1374 sdmmc0_bus1: sdmmc0-bus1 { 1375 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>; 1376 }; 1377 1378 sdmmc0_bus4: sdmmc0-bus4 { 1379 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>, 1380 <1 RK_PA1 1 &pcfg_pull_up_4ma>, 1381 <1 RK_PA2 1 &pcfg_pull_up_4ma>, 1382 <1 RK_PA3 1 &pcfg_pull_up_4ma>; 1383 }; 1384 1385 sdmmc0_gpio: sdmmc0-gpio { 1386 rockchip,pins = 1387 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1388 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1389 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1390 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1391 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1392 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1393 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1394 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1395 }; 1396 }; 1397 1398 sdmmc0ext { 1399 sdmmc0ext_clk: sdmmc0ext-clk { 1400 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1401 }; 1402 1403 sdmmc0ext_cmd: sdmmc0ext-cmd { 1404 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1405 }; 1406 1407 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1408 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1409 }; 1410 1411 sdmmc0ext_dectn: sdmmc0ext-dectn { 1412 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1413 }; 1414 1415 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1416 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1417 }; 1418 1419 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1420 rockchip,pins = 1421 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1422 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1423 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1424 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1425 }; 1426 1427 sdmmc0ext_gpio: sdmmc0ext-gpio { 1428 rockchip,pins = 1429 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1430 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1431 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1432 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1433 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1434 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1435 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1436 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1437 }; 1438 }; 1439 1440 sdmmc1 { 1441 sdmmc1_clk: sdmmc1-clk { 1442 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1443 }; 1444 1445 sdmmc1_cmd: sdmmc1-cmd { 1446 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1447 }; 1448 1449 sdmmc1_pwren: sdmmc1-pwren { 1450 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1451 }; 1452 1453 sdmmc1_wrprt: sdmmc1-wrprt { 1454 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1455 }; 1456 1457 sdmmc1_dectn: sdmmc1-dectn { 1458 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1459 }; 1460 1461 sdmmc1_bus1: sdmmc1-bus1 { 1462 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1463 }; 1464 1465 sdmmc1_bus4: sdmmc1-bus4 { 1466 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1467 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1468 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1469 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1470 }; 1471 1472 sdmmc1_gpio: sdmmc1-gpio { 1473 rockchip,pins = 1474 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1475 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1476 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1477 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1478 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1479 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1480 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1481 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1482 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1483 }; 1484 }; 1485 1486 emmc { 1487 emmc_clk: emmc-clk { 1488 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1489 }; 1490 1491 emmc_cmd: emmc-cmd { 1492 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1493 }; 1494 1495 emmc_pwren: emmc-pwren { 1496 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1497 }; 1498 1499 emmc_rstnout: emmc-rstnout { 1500 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1501 }; 1502 1503 emmc_bus1: emmc-bus1 { 1504 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1505 }; 1506 1507 emmc_bus4: emmc-bus4 { 1508 rockchip,pins = 1509 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1510 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1511 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1512 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1513 }; 1514 1515 emmc_bus8: emmc-bus8 { 1516 rockchip,pins = 1517 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1518 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1519 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1520 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1521 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1522 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1523 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1524 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1525 }; 1526 }; 1527 1528 pwm0 { 1529 pwm0_pin: pwm0-pin { 1530 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1531 }; 1532 }; 1533 1534 pwm1 { 1535 pwm1_pin: pwm1-pin { 1536 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1537 }; 1538 }; 1539 1540 pwm2 { 1541 pwm2_pin: pwm2-pin { 1542 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1543 }; 1544 }; 1545 1546 pwmir { 1547 pwmir_pin: pwmir-pin { 1548 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1549 }; 1550 }; 1551 1552 gmac-1 { 1553 rgmiim1_pins: rgmiim1-pins { 1554 rockchip,pins = 1555 /* mac_txclk */ 1556 <1 RK_PB4 2 &pcfg_pull_none_12ma>, 1557 /* mac_rxclk */ 1558 <1 RK_PB5 2 &pcfg_pull_none_2ma>, 1559 /* mac_mdio */ 1560 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1561 /* mac_txen */ 1562 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1563 /* mac_clk */ 1564 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1565 /* mac_rxdv */ 1566 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1567 /* mac_mdc */ 1568 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1569 /* mac_rxd1 */ 1570 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1571 /* mac_rxd0 */ 1572 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1573 /* mac_txd1 */ 1574 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1575 /* mac_txd0 */ 1576 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1577 /* mac_rxd3 */ 1578 <1 RK_PB6 2 &pcfg_pull_none_2ma>, 1579 /* mac_rxd2 */ 1580 <1 RK_PB7 2 &pcfg_pull_none_2ma>, 1581 /* mac_txd3 */ 1582 <1 RK_PC0 2 &pcfg_pull_none_12ma>, 1583 /* mac_txd2 */ 1584 <1 RK_PC1 2 &pcfg_pull_none_12ma>, 1585 1586 /* mac_txclk */ 1587 <0 RK_PB0 1 &pcfg_pull_none>, 1588 /* mac_txen */ 1589 <0 RK_PB4 1 &pcfg_pull_none>, 1590 /* mac_clk */ 1591 <0 RK_PD0 1 &pcfg_pull_none>, 1592 /* mac_txd1 */ 1593 <0 RK_PC0 1 &pcfg_pull_none>, 1594 /* mac_txd0 */ 1595 <0 RK_PC1 1 &pcfg_pull_none>, 1596 /* mac_txd3 */ 1597 <0 RK_PC7 1 &pcfg_pull_none>, 1598 /* mac_txd2 */ 1599 <0 RK_PC6 1 &pcfg_pull_none>; 1600 }; 1601 1602 rmiim1_pins: rmiim1-pins { 1603 rockchip,pins = 1604 /* mac_mdio */ 1605 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1606 /* mac_txen */ 1607 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1608 /* mac_clk */ 1609 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1610 /* mac_rxer */ 1611 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1612 /* mac_rxdv */ 1613 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1614 /* mac_mdc */ 1615 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1616 /* mac_rxd1 */ 1617 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1618 /* mac_rxd0 */ 1619 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1620 /* mac_txd1 */ 1621 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1622 /* mac_txd0 */ 1623 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1624 1625 /* mac_mdio */ 1626 <0 RK_PB3 1 &pcfg_pull_none>, 1627 /* mac_txen */ 1628 <0 RK_PB4 1 &pcfg_pull_none>, 1629 /* mac_clk */ 1630 <0 RK_PD0 1 &pcfg_pull_none>, 1631 /* mac_mdc */ 1632 <0 RK_PC3 1 &pcfg_pull_none>, 1633 /* mac_txd1 */ 1634 <0 RK_PC0 1 &pcfg_pull_none>, 1635 /* mac_txd0 */ 1636 <0 RK_PC1 1 &pcfg_pull_none>; 1637 }; 1638 }; 1639 1640 gmac2phy { 1641 fephyled_speed100: fephyled-speed100 { 1642 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 1643 }; 1644 1645 fephyled_speed10: fephyled-speed10 { 1646 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1647 }; 1648 1649 fephyled_duplex: fephyled-duplex { 1650 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1651 }; 1652 1653 fephyled_rxm0: fephyled-rxm0 { 1654 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>; 1655 }; 1656 1657 fephyled_txm0: fephyled-txm0 { 1658 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>; 1659 }; 1660 1661 fephyled_linkm0: fephyled-linkm0 { 1662 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1663 }; 1664 1665 fephyled_rxm1: fephyled-rxm1 { 1666 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1667 }; 1668 1669 fephyled_txm1: fephyled-txm1 { 1670 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1671 }; 1672 1673 fephyled_linkm1: fephyled-linkm1 { 1674 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1675 }; 1676 }; 1677 1678 tsadc_pin { 1679 tsadc_int: tsadc-int { 1680 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1681 }; 1682 tsadc_gpio: tsadc-gpio { 1683 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1684 }; 1685 }; 1686 1687 hdmi_pin { 1688 hdmi_cec: hdmi-cec { 1689 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1690 }; 1691 1692 hdmi_hpd: hdmi-hpd { 1693 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1694 }; 1695 }; 1696 1697 cif-0 { 1698 dvp_d2d9_m0:dvp-d2d9-m0 { 1699 rockchip,pins = 1700 /* cif_d0 */ 1701 <3 RK_PA4 2 &pcfg_pull_none>, 1702 /* cif_d1 */ 1703 <3 RK_PA5 2 &pcfg_pull_none>, 1704 /* cif_d2 */ 1705 <3 RK_PA6 2 &pcfg_pull_none>, 1706 /* cif_d3 */ 1707 <3 RK_PA7 2 &pcfg_pull_none>, 1708 /* cif_d4 */ 1709 <3 RK_PB0 2 &pcfg_pull_none>, 1710 /* cif_d5m0 */ 1711 <3 RK_PB1 2 &pcfg_pull_none>, 1712 /* cif_d6m0 */ 1713 <3 RK_PB2 2 &pcfg_pull_none>, 1714 /* cif_d7m0 */ 1715 <3 RK_PB3 2 &pcfg_pull_none>, 1716 /* cif_href */ 1717 <3 RK_PA1 2 &pcfg_pull_none>, 1718 /* cif_vsync */ 1719 <3 RK_PA0 2 &pcfg_pull_none>, 1720 /* cif_clkoutm0 */ 1721 <3 RK_PA3 2 &pcfg_pull_none>, 1722 /* cif_clkin */ 1723 <3 RK_PA2 2 &pcfg_pull_none>; 1724 }; 1725 }; 1726 1727 cif-1 { 1728 dvp_d2d9_m1:dvp-d2d9-m1 { 1729 rockchip,pins = 1730 /* cif_d0 */ 1731 <3 RK_PA4 2 &pcfg_pull_none>, 1732 /* cif_d1 */ 1733 <3 RK_PA5 2 &pcfg_pull_none>, 1734 /* cif_d2 */ 1735 <3 RK_PA6 2 &pcfg_pull_none>, 1736 /* cif_d3 */ 1737 <3 RK_PA7 2 &pcfg_pull_none>, 1738 /* cif_d4 */ 1739 <3 RK_PB0 2 &pcfg_pull_none>, 1740 /* cif_d5m1 */ 1741 <2 RK_PC0 4 &pcfg_pull_none>, 1742 /* cif_d6m1 */ 1743 <2 RK_PC1 4 &pcfg_pull_none>, 1744 /* cif_d7m1 */ 1745 <2 RK_PC2 4 &pcfg_pull_none>, 1746 /* cif_href */ 1747 <3 RK_PA1 2 &pcfg_pull_none>, 1748 /* cif_vsync */ 1749 <3 RK_PA0 2 &pcfg_pull_none>, 1750 /* cif_clkoutm1 */ 1751 <2 RK_PB7 4 &pcfg_pull_none>, 1752 /* cif_clkin */ 1753 <3 RK_PA2 2 &pcfg_pull_none>; 1754 }; 1755 }; 1756 }; 1757}; 1758