1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 cpu-idle-states = <&CPU_SLEEP>; 45 dynamic-power-coefficient = <120>; 46 enable-method = "psci"; 47 next-level-cache = <&l2>; 48 operating-points-v2 = <&cpu0_opp_table>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x0 0x1>; 55 clocks = <&cru ARMCLK>; 56 #cooling-cells = <2>; 57 cpu-idle-states = <&CPU_SLEEP>; 58 dynamic-power-coefficient = <120>; 59 enable-method = "psci"; 60 next-level-cache = <&l2>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0 0x2>; 68 clocks = <&cru ARMCLK>; 69 #cooling-cells = <2>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 dynamic-power-coefficient = <120>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 }; 76 77 cpu3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x0 0x3>; 81 clocks = <&cru ARMCLK>; 82 #cooling-cells = <2>; 83 cpu-idle-states = <&CPU_SLEEP>; 84 dynamic-power-coefficient = <120>; 85 enable-method = "psci"; 86 next-level-cache = <&l2>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 }; 102 103 l2: l2-cache0 { 104 compatible = "cache"; 105 }; 106 }; 107 108 cpu0_opp_table: opp-table-0 { 109 compatible = "operating-points-v2"; 110 opp-shared; 111 112 opp-408000000 { 113 opp-hz = /bits/ 64 <408000000>; 114 opp-microvolt = <950000>; 115 clock-latency-ns = <40000>; 116 opp-suspend; 117 }; 118 opp-600000000 { 119 opp-hz = /bits/ 64 <600000000>; 120 opp-microvolt = <950000>; 121 clock-latency-ns = <40000>; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1000000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1100000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1225000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1300000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 analog_sound: analog-sound { 146 compatible = "simple-audio-card"; 147 simple-audio-card,format = "i2s"; 148 simple-audio-card,mclk-fs = <256>; 149 simple-audio-card,name = "Analog"; 150 status = "disabled"; 151 152 simple-audio-card,cpu { 153 sound-dai = <&i2s1>; 154 }; 155 156 simple-audio-card,codec { 157 sound-dai = <&codec>; 158 }; 159 }; 160 161 arm-pmu { 162 compatible = "arm,cortex-a53-pmu"; 163 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 167 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 168 }; 169 170 display_subsystem: display-subsystem { 171 compatible = "rockchip,display-subsystem"; 172 ports = <&vop_out>; 173 }; 174 175 hdmi_sound: hdmi-sound { 176 compatible = "simple-audio-card"; 177 simple-audio-card,format = "i2s"; 178 simple-audio-card,mclk-fs = <128>; 179 simple-audio-card,name = "HDMI"; 180 status = "disabled"; 181 182 simple-audio-card,cpu { 183 sound-dai = <&i2s0>; 184 }; 185 186 simple-audio-card,codec { 187 sound-dai = <&hdmi>; 188 }; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0", "arm,psci-0.2"; 193 method = "smc"; 194 }; 195 196 timer { 197 compatible = "arm,armv8-timer"; 198 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 199 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 200 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 201 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 202 }; 203 204 xin24m: xin24m { 205 compatible = "fixed-clock"; 206 #clock-cells = <0>; 207 clock-frequency = <24000000>; 208 clock-output-names = "xin24m"; 209 }; 210 211 i2s0: i2s@ff000000 { 212 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 213 reg = <0x0 0xff000000 0x0 0x1000>; 214 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 216 clock-names = "i2s_clk", "i2s_hclk"; 217 dmas = <&dmac 11>, <&dmac 12>; 218 dma-names = "tx", "rx"; 219 #sound-dai-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2s1: i2s@ff010000 { 224 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 225 reg = <0x0 0xff010000 0x0 0x1000>; 226 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 228 clock-names = "i2s_clk", "i2s_hclk"; 229 dmas = <&dmac 14>, <&dmac 15>; 230 dma-names = "tx", "rx"; 231 #sound-dai-cells = <0>; 232 status = "disabled"; 233 }; 234 235 i2s2: i2s@ff020000 { 236 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 237 reg = <0x0 0xff020000 0x0 0x1000>; 238 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 240 clock-names = "i2s_clk", "i2s_hclk"; 241 dmas = <&dmac 0>, <&dmac 1>; 242 dma-names = "tx", "rx"; 243 #sound-dai-cells = <0>; 244 status = "disabled"; 245 }; 246 247 spdif: spdif@ff030000 { 248 compatible = "rockchip,rk3328-spdif"; 249 reg = <0x0 0xff030000 0x0 0x1000>; 250 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 252 clock-names = "mclk", "hclk"; 253 dmas = <&dmac 10>; 254 dma-names = "tx"; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&spdifm2_tx>; 257 #sound-dai-cells = <0>; 258 status = "disabled"; 259 }; 260 261 pdm: pdm@ff040000 { 262 compatible = "rockchip,pdm"; 263 reg = <0x0 0xff040000 0x0 0x1000>; 264 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 265 clock-names = "pdm_clk", "pdm_hclk"; 266 dmas = <&dmac 16>; 267 dma-names = "rx"; 268 pinctrl-names = "default", "sleep"; 269 pinctrl-0 = <&pdmm0_clk 270 &pdmm0_sdi0 271 &pdmm0_sdi1 272 &pdmm0_sdi2 273 &pdmm0_sdi3>; 274 pinctrl-1 = <&pdmm0_clk_sleep 275 &pdmm0_sdi0_sleep 276 &pdmm0_sdi1_sleep 277 &pdmm0_sdi2_sleep 278 &pdmm0_sdi3_sleep>; 279 status = "disabled"; 280 }; 281 282 grf: syscon@ff100000 { 283 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 284 reg = <0x0 0xff100000 0x0 0x1000>; 285 286 io_domains: io-domains { 287 compatible = "rockchip,rk3328-io-voltage-domain"; 288 status = "disabled"; 289 }; 290 291 grf_gpio: gpio { 292 compatible = "rockchip,rk3328-grf-gpio"; 293 gpio-controller; 294 #gpio-cells = <2>; 295 }; 296 297 power: power-controller { 298 compatible = "rockchip,rk3328-power-controller"; 299 #power-domain-cells = <1>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 303 power-domain@RK3328_PD_HEVC { 304 reg = <RK3328_PD_HEVC>; 305 #power-domain-cells = <0>; 306 }; 307 power-domain@RK3328_PD_VIDEO { 308 reg = <RK3328_PD_VIDEO>; 309 #power-domain-cells = <0>; 310 }; 311 power-domain@RK3328_PD_VPU { 312 reg = <RK3328_PD_VPU>; 313 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 314 #power-domain-cells = <0>; 315 }; 316 }; 317 318 reboot-mode { 319 compatible = "syscon-reboot-mode"; 320 offset = <0x5c8>; 321 mode-normal = <BOOT_NORMAL>; 322 mode-recovery = <BOOT_RECOVERY>; 323 mode-bootloader = <BOOT_FASTBOOT>; 324 mode-loader = <BOOT_BL_DOWNLOAD>; 325 }; 326 }; 327 328 uart0: serial@ff110000 { 329 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 330 reg = <0x0 0xff110000 0x0 0x100>; 331 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 333 clock-names = "baudclk", "apb_pclk"; 334 dmas = <&dmac 2>, <&dmac 3>; 335 dma-names = "tx", "rx"; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 338 reg-io-width = <4>; 339 reg-shift = <2>; 340 status = "disabled"; 341 }; 342 343 uart1: serial@ff120000 { 344 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 345 reg = <0x0 0xff120000 0x0 0x100>; 346 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 348 clock-names = "baudclk", "apb_pclk"; 349 dmas = <&dmac 4>, <&dmac 5>; 350 dma-names = "tx", "rx"; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 353 reg-io-width = <4>; 354 reg-shift = <2>; 355 status = "disabled"; 356 }; 357 358 uart2: serial@ff130000 { 359 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 360 reg = <0x0 0xff130000 0x0 0x100>; 361 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 363 clock-names = "baudclk", "apb_pclk"; 364 dmas = <&dmac 6>, <&dmac 7>; 365 dma-names = "tx", "rx"; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&uart2m1_xfer>; 368 reg-io-width = <4>; 369 reg-shift = <2>; 370 status = "disabled"; 371 }; 372 373 i2c0: i2c@ff150000 { 374 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 375 reg = <0x0 0xff150000 0x0 0x1000>; 376 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 380 clock-names = "i2c", "pclk"; 381 pinctrl-names = "default"; 382 pinctrl-0 = <&i2c0_xfer>; 383 status = "disabled"; 384 }; 385 386 i2c1: i2c@ff160000 { 387 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 388 reg = <0x0 0xff160000 0x0 0x1000>; 389 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 393 clock-names = "i2c", "pclk"; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&i2c1_xfer>; 396 status = "disabled"; 397 }; 398 399 i2c2: i2c@ff170000 { 400 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 401 reg = <0x0 0xff170000 0x0 0x1000>; 402 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 406 clock-names = "i2c", "pclk"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&i2c2_xfer>; 409 status = "disabled"; 410 }; 411 412 i2c3: i2c@ff180000 { 413 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 414 reg = <0x0 0xff180000 0x0 0x1000>; 415 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 419 clock-names = "i2c", "pclk"; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&i2c3_xfer>; 422 status = "disabled"; 423 }; 424 425 spi0: spi@ff190000 { 426 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 427 reg = <0x0 0xff190000 0x0 0x1000>; 428 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 432 clock-names = "spiclk", "apb_pclk"; 433 dmas = <&dmac 8>, <&dmac 9>; 434 dma-names = "tx", "rx"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 437 status = "disabled"; 438 }; 439 440 wdt: watchdog@ff1a0000 { 441 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 442 reg = <0x0 0xff1a0000 0x0 0x100>; 443 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&cru PCLK_WDT>; 445 }; 446 447 pwm0: pwm@ff1b0000 { 448 compatible = "rockchip,rk3328-pwm"; 449 reg = <0x0 0xff1b0000 0x0 0x10>; 450 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 451 clock-names = "pwm", "pclk"; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&pwm0_pin>; 454 #pwm-cells = <3>; 455 status = "disabled"; 456 }; 457 458 pwm1: pwm@ff1b0010 { 459 compatible = "rockchip,rk3328-pwm"; 460 reg = <0x0 0xff1b0010 0x0 0x10>; 461 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 462 clock-names = "pwm", "pclk"; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pwm1_pin>; 465 #pwm-cells = <3>; 466 status = "disabled"; 467 }; 468 469 pwm2: pwm@ff1b0020 { 470 compatible = "rockchip,rk3328-pwm"; 471 reg = <0x0 0xff1b0020 0x0 0x10>; 472 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 473 clock-names = "pwm", "pclk"; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&pwm2_pin>; 476 #pwm-cells = <3>; 477 status = "disabled"; 478 }; 479 480 pwm3: pwm@ff1b0030 { 481 compatible = "rockchip,rk3328-pwm"; 482 reg = <0x0 0xff1b0030 0x0 0x10>; 483 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 485 clock-names = "pwm", "pclk"; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&pwmir_pin>; 488 #pwm-cells = <3>; 489 status = "disabled"; 490 }; 491 492 dmac: dmac@ff1f0000 { 493 compatible = "arm,pl330", "arm,primecell"; 494 reg = <0x0 0xff1f0000 0x0 0x4000>; 495 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 497 arm,pl330-periph-burst; 498 clocks = <&cru ACLK_DMAC>; 499 clock-names = "apb_pclk"; 500 #dma-cells = <1>; 501 }; 502 503 thermal-zones { 504 soc_thermal: soc-thermal { 505 polling-delay-passive = <20>; 506 polling-delay = <1000>; 507 sustainable-power = <1000>; 508 509 thermal-sensors = <&tsadc 0>; 510 511 trips { 512 threshold: trip-point0 { 513 temperature = <70000>; 514 hysteresis = <2000>; 515 type = "passive"; 516 }; 517 target: trip-point1 { 518 temperature = <85000>; 519 hysteresis = <2000>; 520 type = "passive"; 521 }; 522 soc_crit: soc-crit { 523 temperature = <95000>; 524 hysteresis = <2000>; 525 type = "critical"; 526 }; 527 }; 528 529 cooling-maps { 530 map0 { 531 trip = <&target>; 532 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 533 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 534 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 535 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 536 contribution = <4096>; 537 }; 538 }; 539 }; 540 541 }; 542 543 tsadc: tsadc@ff250000 { 544 compatible = "rockchip,rk3328-tsadc"; 545 reg = <0x0 0xff250000 0x0 0x100>; 546 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 547 assigned-clocks = <&cru SCLK_TSADC>; 548 assigned-clock-rates = <50000>; 549 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 550 clock-names = "tsadc", "apb_pclk"; 551 pinctrl-names = "init", "default", "sleep"; 552 pinctrl-0 = <&otp_pin>; 553 pinctrl-1 = <&otp_out>; 554 pinctrl-2 = <&otp_pin>; 555 resets = <&cru SRST_TSADC>; 556 reset-names = "tsadc-apb"; 557 rockchip,grf = <&grf>; 558 rockchip,hw-tshut-temp = <100000>; 559 #thermal-sensor-cells = <1>; 560 status = "disabled"; 561 }; 562 563 efuse: efuse@ff260000 { 564 compatible = "rockchip,rk3328-efuse"; 565 reg = <0x0 0xff260000 0x0 0x50>; 566 #address-cells = <1>; 567 #size-cells = <1>; 568 clocks = <&cru SCLK_EFUSE>; 569 clock-names = "pclk_efuse"; 570 rockchip,efuse-size = <0x20>; 571 572 /* Data cells */ 573 efuse_id: id@7 { 574 reg = <0x07 0x10>; 575 }; 576 cpu_leakage: cpu-leakage@17 { 577 reg = <0x17 0x1>; 578 }; 579 logic_leakage: logic-leakage@19 { 580 reg = <0x19 0x1>; 581 }; 582 efuse_cpu_version: cpu-version@1a { 583 reg = <0x1a 0x1>; 584 bits = <3 3>; 585 }; 586 }; 587 588 saradc: adc@ff280000 { 589 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 590 reg = <0x0 0xff280000 0x0 0x100>; 591 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 592 #io-channel-cells = <1>; 593 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 594 clock-names = "saradc", "apb_pclk"; 595 resets = <&cru SRST_SARADC_P>; 596 reset-names = "saradc-apb"; 597 status = "disabled"; 598 }; 599 600 gpu: gpu@ff300000 { 601 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 602 reg = <0x0 0xff300000 0x0 0x30000>; 603 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 610 interrupt-names = "gp", 611 "gpmmu", 612 "pp", 613 "pp0", 614 "ppmmu0", 615 "pp1", 616 "ppmmu1"; 617 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 618 clock-names = "bus", "core"; 619 resets = <&cru SRST_GPU_A>; 620 }; 621 622 h265e_mmu: iommu@ff330200 { 623 compatible = "rockchip,iommu"; 624 reg = <0x0 0xff330200 0 0x100>; 625 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 627 clock-names = "aclk", "iface"; 628 #iommu-cells = <0>; 629 status = "disabled"; 630 }; 631 632 vepu_mmu: iommu@ff340800 { 633 compatible = "rockchip,iommu"; 634 reg = <0x0 0xff340800 0x0 0x40>; 635 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 637 clock-names = "aclk", "iface"; 638 #iommu-cells = <0>; 639 status = "disabled"; 640 }; 641 642 vpu: video-codec@ff350000 { 643 compatible = "rockchip,rk3328-vpu"; 644 reg = <0x0 0xff350000 0x0 0x800>; 645 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 646 interrupt-names = "vdpu"; 647 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 648 clock-names = "aclk", "hclk"; 649 iommus = <&vpu_mmu>; 650 power-domains = <&power RK3328_PD_VPU>; 651 }; 652 653 vpu_mmu: iommu@ff350800 { 654 compatible = "rockchip,iommu"; 655 reg = <0x0 0xff350800 0x0 0x40>; 656 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 658 clock-names = "aclk", "iface"; 659 #iommu-cells = <0>; 660 power-domains = <&power RK3328_PD_VPU>; 661 }; 662 663 rkvdec_mmu: iommu@ff360480 { 664 compatible = "rockchip,iommu"; 665 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 666 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 668 clock-names = "aclk", "iface"; 669 #iommu-cells = <0>; 670 status = "disabled"; 671 }; 672 673 vop: vop@ff370000 { 674 compatible = "rockchip,rk3328-vop"; 675 reg = <0x0 0xff370000 0x0 0x3efc>; 676 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 678 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 679 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 680 reset-names = "axi", "ahb", "dclk"; 681 iommus = <&vop_mmu>; 682 status = "disabled"; 683 684 vop_out: port { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 688 vop_out_hdmi: endpoint@0 { 689 reg = <0>; 690 remote-endpoint = <&hdmi_in_vop>; 691 }; 692 }; 693 }; 694 695 vop_mmu: iommu@ff373f00 { 696 compatible = "rockchip,iommu"; 697 reg = <0x0 0xff373f00 0x0 0x100>; 698 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 700 clock-names = "aclk", "iface"; 701 #iommu-cells = <0>; 702 status = "disabled"; 703 }; 704 705 hdmi: hdmi@ff3c0000 { 706 compatible = "rockchip,rk3328-dw-hdmi"; 707 reg = <0x0 0xff3c0000 0x0 0x20000>; 708 reg-io-width = <4>; 709 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&cru PCLK_HDMI>, 712 <&cru SCLK_HDMI_SFC>, 713 <&cru SCLK_RTC32K>; 714 clock-names = "iahb", 715 "isfr", 716 "cec"; 717 phys = <&hdmiphy>; 718 phy-names = "hdmi"; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 721 rockchip,grf = <&grf>; 722 #sound-dai-cells = <0>; 723 status = "disabled"; 724 725 ports { 726 hdmi_in: port { 727 hdmi_in_vop: endpoint { 728 remote-endpoint = <&vop_out_hdmi>; 729 }; 730 }; 731 }; 732 }; 733 734 codec: codec@ff410000 { 735 compatible = "rockchip,rk3328-codec"; 736 reg = <0x0 0xff410000 0x0 0x1000>; 737 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 738 clock-names = "pclk", "mclk"; 739 rockchip,grf = <&grf>; 740 #sound-dai-cells = <0>; 741 status = "disabled"; 742 }; 743 744 hdmiphy: phy@ff430000 { 745 compatible = "rockchip,rk3328-hdmi-phy"; 746 reg = <0x0 0xff430000 0x0 0x10000>; 747 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 749 clock-names = "sysclk", "refoclk", "refpclk"; 750 clock-output-names = "hdmi_phy"; 751 #clock-cells = <0>; 752 nvmem-cells = <&efuse_cpu_version>; 753 nvmem-cell-names = "cpu-version"; 754 #phy-cells = <0>; 755 status = "disabled"; 756 }; 757 758 cru: clock-controller@ff440000 { 759 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 760 reg = <0x0 0xff440000 0x0 0x1000>; 761 rockchip,grf = <&grf>; 762 #clock-cells = <1>; 763 #reset-cells = <1>; 764 assigned-clocks = 765 /* 766 * CPLL should run at 1200, but that is to high for 767 * the initial dividers of most of its children. 768 * We need set cpll child clk div first, 769 * and then set the cpll frequency. 770 */ 771 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 772 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 773 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 774 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 775 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 776 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 777 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 778 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 779 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 780 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 781 <&cru SCLK_WIFI>, <&cru ARMCLK>, 782 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 783 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 784 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 785 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 786 <&cru SCLK_RTC32K>; 787 assigned-clock-parents = 788 <&cru HDMIPHY>, <&cru PLL_APLL>, 789 <&cru PLL_GPLL>, <&xin24m>, 790 <&xin24m>, <&xin24m>; 791 assigned-clock-rates = 792 <0>, <61440000>, 793 <0>, <24000000>, 794 <24000000>, <24000000>, 795 <15000000>, <15000000>, 796 <100000000>, <100000000>, 797 <100000000>, <100000000>, 798 <50000000>, <100000000>, 799 <100000000>, <100000000>, 800 <50000000>, <50000000>, 801 <50000000>, <50000000>, 802 <24000000>, <600000000>, 803 <491520000>, <1200000000>, 804 <150000000>, <75000000>, 805 <75000000>, <150000000>, 806 <75000000>, <75000000>, 807 <32768>; 808 }; 809 810 usb2phy_grf: syscon@ff450000 { 811 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 812 "simple-mfd"; 813 reg = <0x0 0xff450000 0x0 0x10000>; 814 #address-cells = <1>; 815 #size-cells = <1>; 816 817 u2phy: usb2phy@100 { 818 compatible = "rockchip,rk3328-usb2phy"; 819 reg = <0x100 0x10>; 820 clocks = <&xin24m>; 821 clock-names = "phyclk"; 822 clock-output-names = "usb480m_phy"; 823 #clock-cells = <0>; 824 assigned-clocks = <&cru USB480M>; 825 assigned-clock-parents = <&u2phy>; 826 status = "disabled"; 827 828 u2phy_otg: otg-port { 829 #phy-cells = <0>; 830 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 833 interrupt-names = "otg-bvalid", "otg-id", 834 "linestate"; 835 status = "disabled"; 836 }; 837 838 u2phy_host: host-port { 839 #phy-cells = <0>; 840 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 841 interrupt-names = "linestate"; 842 status = "disabled"; 843 }; 844 }; 845 }; 846 847 sdmmc: mmc@ff500000 { 848 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 849 reg = <0x0 0xff500000 0x0 0x4000>; 850 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 852 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 853 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 854 fifo-depth = <0x100>; 855 max-frequency = <150000000>; 856 status = "disabled"; 857 }; 858 859 sdio: mmc@ff510000 { 860 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 861 reg = <0x0 0xff510000 0x0 0x4000>; 862 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 864 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 865 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 866 fifo-depth = <0x100>; 867 max-frequency = <150000000>; 868 status = "disabled"; 869 }; 870 871 emmc: mmc@ff520000 { 872 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 873 reg = <0x0 0xff520000 0x0 0x4000>; 874 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 876 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 877 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 878 fifo-depth = <0x100>; 879 max-frequency = <150000000>; 880 status = "disabled"; 881 }; 882 883 gmac2io: ethernet@ff540000 { 884 compatible = "rockchip,rk3328-gmac"; 885 reg = <0x0 0xff540000 0x0 0x10000>; 886 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 887 interrupt-names = "macirq"; 888 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 889 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 890 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 891 <&cru PCLK_MAC2IO>; 892 clock-names = "stmmaceth", "mac_clk_rx", 893 "mac_clk_tx", "clk_mac_ref", 894 "clk_mac_refout", "aclk_mac", 895 "pclk_mac"; 896 resets = <&cru SRST_GMAC2IO_A>; 897 reset-names = "stmmaceth"; 898 rockchip,grf = <&grf>; 899 snps,txpbl = <0x4>; 900 status = "disabled"; 901 }; 902 903 gmac2phy: ethernet@ff550000 { 904 compatible = "rockchip,rk3328-gmac"; 905 reg = <0x0 0xff550000 0x0 0x10000>; 906 rockchip,grf = <&grf>; 907 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 908 interrupt-names = "macirq"; 909 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 910 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 911 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 912 <&cru SCLK_MAC2PHY_OUT>; 913 clock-names = "stmmaceth", "mac_clk_rx", 914 "mac_clk_tx", "clk_mac_ref", 915 "aclk_mac", "pclk_mac", 916 "clk_macphy"; 917 resets = <&cru SRST_GMAC2PHY_A>; 918 reset-names = "stmmaceth"; 919 phy-mode = "rmii"; 920 phy-handle = <&phy>; 921 snps,txpbl = <0x4>; 922 clock_in_out = "output"; 923 status = "disabled"; 924 925 mdio { 926 compatible = "snps,dwmac-mdio"; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 930 phy: ethernet-phy@0 { 931 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 932 reg = <0>; 933 clocks = <&cru SCLK_MAC2PHY_OUT>; 934 resets = <&cru SRST_MACPHY>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 937 phy-is-integrated; 938 }; 939 }; 940 }; 941 942 usb20_otg: usb@ff580000 { 943 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 944 "snps,dwc2"; 945 reg = <0x0 0xff580000 0x0 0x40000>; 946 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&cru HCLK_OTG>; 948 clock-names = "otg"; 949 dr_mode = "otg"; 950 g-np-tx-fifo-size = <16>; 951 g-rx-fifo-size = <280>; 952 g-tx-fifo-size = <256 128 128 64 32 16>; 953 phys = <&u2phy_otg>; 954 phy-names = "usb2-phy"; 955 status = "disabled"; 956 }; 957 958 usb_host0_ehci: usb@ff5c0000 { 959 compatible = "generic-ehci"; 960 reg = <0x0 0xff5c0000 0x0 0x10000>; 961 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&cru HCLK_HOST0>, <&u2phy>; 963 phys = <&u2phy_host>; 964 phy-names = "usb"; 965 status = "disabled"; 966 }; 967 968 usb_host0_ohci: usb@ff5d0000 { 969 compatible = "generic-ohci"; 970 reg = <0x0 0xff5d0000 0x0 0x10000>; 971 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&cru HCLK_HOST0>, <&u2phy>; 973 phys = <&u2phy_host>; 974 phy-names = "usb"; 975 status = "disabled"; 976 }; 977 978 usbdrd3: usb@ff600000 { 979 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 980 reg = <0x0 0xff600000 0x0 0x100000>; 981 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 983 <&cru ACLK_USB3OTG>; 984 clock-names = "ref_clk", "suspend_clk", 985 "bus_clk"; 986 dr_mode = "otg"; 987 phy_type = "utmi_wide"; 988 snps,dis-del-phy-power-chg-quirk; 989 snps,dis_enblslpm_quirk; 990 snps,dis-tx-ipgap-linecheck-quirk; 991 snps,dis-u2-freeclk-exists-quirk; 992 snps,dis_u2_susphy_quirk; 993 snps,dis_u3_susphy_quirk; 994 status = "disabled"; 995 }; 996 997 gic: interrupt-controller@ff811000 { 998 compatible = "arm,gic-400"; 999 #interrupt-cells = <3>; 1000 #address-cells = <0>; 1001 interrupt-controller; 1002 reg = <0x0 0xff811000 0 0x1000>, 1003 <0x0 0xff812000 0 0x2000>, 1004 <0x0 0xff814000 0 0x2000>, 1005 <0x0 0xff816000 0 0x2000>; 1006 interrupts = <GIC_PPI 9 1007 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1008 }; 1009 1010 pinctrl: pinctrl { 1011 compatible = "rockchip,rk3328-pinctrl"; 1012 rockchip,grf = <&grf>; 1013 #address-cells = <2>; 1014 #size-cells = <2>; 1015 ranges; 1016 1017 gpio0: gpio@ff210000 { 1018 compatible = "rockchip,gpio-bank"; 1019 reg = <0x0 0xff210000 0x0 0x100>; 1020 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&cru PCLK_GPIO0>; 1022 1023 gpio-controller; 1024 #gpio-cells = <2>; 1025 1026 interrupt-controller; 1027 #interrupt-cells = <2>; 1028 }; 1029 1030 gpio1: gpio@ff220000 { 1031 compatible = "rockchip,gpio-bank"; 1032 reg = <0x0 0xff220000 0x0 0x100>; 1033 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&cru PCLK_GPIO1>; 1035 1036 gpio-controller; 1037 #gpio-cells = <2>; 1038 1039 interrupt-controller; 1040 #interrupt-cells = <2>; 1041 }; 1042 1043 gpio2: gpio@ff230000 { 1044 compatible = "rockchip,gpio-bank"; 1045 reg = <0x0 0xff230000 0x0 0x100>; 1046 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&cru PCLK_GPIO2>; 1048 1049 gpio-controller; 1050 #gpio-cells = <2>; 1051 1052 interrupt-controller; 1053 #interrupt-cells = <2>; 1054 }; 1055 1056 gpio3: gpio@ff240000 { 1057 compatible = "rockchip,gpio-bank"; 1058 reg = <0x0 0xff240000 0x0 0x100>; 1059 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&cru PCLK_GPIO3>; 1061 1062 gpio-controller; 1063 #gpio-cells = <2>; 1064 1065 interrupt-controller; 1066 #interrupt-cells = <2>; 1067 }; 1068 1069 pcfg_pull_up: pcfg-pull-up { 1070 bias-pull-up; 1071 }; 1072 1073 pcfg_pull_down: pcfg-pull-down { 1074 bias-pull-down; 1075 }; 1076 1077 pcfg_pull_none: pcfg-pull-none { 1078 bias-disable; 1079 }; 1080 1081 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1082 bias-disable; 1083 drive-strength = <2>; 1084 }; 1085 1086 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1087 bias-pull-up; 1088 drive-strength = <2>; 1089 }; 1090 1091 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1092 bias-pull-up; 1093 drive-strength = <4>; 1094 }; 1095 1096 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1097 bias-disable; 1098 drive-strength = <4>; 1099 }; 1100 1101 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1102 bias-pull-down; 1103 drive-strength = <4>; 1104 }; 1105 1106 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1107 bias-disable; 1108 drive-strength = <8>; 1109 }; 1110 1111 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1112 bias-pull-up; 1113 drive-strength = <8>; 1114 }; 1115 1116 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1117 bias-disable; 1118 drive-strength = <12>; 1119 }; 1120 1121 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1122 bias-pull-up; 1123 drive-strength = <12>; 1124 }; 1125 1126 pcfg_output_high: pcfg-output-high { 1127 output-high; 1128 }; 1129 1130 pcfg_output_low: pcfg-output-low { 1131 output-low; 1132 }; 1133 1134 pcfg_input_high: pcfg-input-high { 1135 bias-pull-up; 1136 input-enable; 1137 }; 1138 1139 pcfg_input: pcfg-input { 1140 input-enable; 1141 }; 1142 1143 i2c0 { 1144 i2c0_xfer: i2c0-xfer { 1145 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1146 <2 RK_PD1 1 &pcfg_pull_none>; 1147 }; 1148 }; 1149 1150 i2c1 { 1151 i2c1_xfer: i2c1-xfer { 1152 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1153 <2 RK_PA5 2 &pcfg_pull_none>; 1154 }; 1155 }; 1156 1157 i2c2 { 1158 i2c2_xfer: i2c2-xfer { 1159 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1160 <2 RK_PB6 1 &pcfg_pull_none>; 1161 }; 1162 }; 1163 1164 i2c3 { 1165 i2c3_xfer: i2c3-xfer { 1166 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1167 <0 RK_PA6 2 &pcfg_pull_none>; 1168 }; 1169 i2c3_pins: i2c3-pins { 1170 rockchip,pins = 1171 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1172 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1173 }; 1174 }; 1175 1176 hdmi_i2c { 1177 hdmii2c_xfer: hdmii2c-xfer { 1178 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1179 <0 RK_PA6 1 &pcfg_pull_none>; 1180 }; 1181 }; 1182 1183 pdm-0 { 1184 pdmm0_clk: pdmm0-clk { 1185 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1186 }; 1187 1188 pdmm0_fsync: pdmm0-fsync { 1189 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1190 }; 1191 1192 pdmm0_sdi0: pdmm0-sdi0 { 1193 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1194 }; 1195 1196 pdmm0_sdi1: pdmm0-sdi1 { 1197 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1198 }; 1199 1200 pdmm0_sdi2: pdmm0-sdi2 { 1201 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1202 }; 1203 1204 pdmm0_sdi3: pdmm0-sdi3 { 1205 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1206 }; 1207 1208 pdmm0_clk_sleep: pdmm0-clk-sleep { 1209 rockchip,pins = 1210 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1211 }; 1212 1213 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1214 rockchip,pins = 1215 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1216 }; 1217 1218 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1219 rockchip,pins = 1220 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1221 }; 1222 1223 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1224 rockchip,pins = 1225 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1226 }; 1227 1228 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1229 rockchip,pins = 1230 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1231 }; 1232 1233 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1234 rockchip,pins = 1235 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1236 }; 1237 }; 1238 1239 tsadc { 1240 otp_pin: otp-pin { 1241 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1242 }; 1243 1244 otp_out: otp-out { 1245 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1246 }; 1247 }; 1248 1249 uart0 { 1250 uart0_xfer: uart0-xfer { 1251 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1252 <1 RK_PB0 1 &pcfg_pull_up>; 1253 }; 1254 1255 uart0_cts: uart0-cts { 1256 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1257 }; 1258 1259 uart0_rts: uart0-rts { 1260 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1261 }; 1262 1263 uart0_rts_pin: uart0-rts-pin { 1264 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1265 }; 1266 }; 1267 1268 uart1 { 1269 uart1_xfer: uart1-xfer { 1270 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1271 <3 RK_PA6 4 &pcfg_pull_up>; 1272 }; 1273 1274 uart1_cts: uart1-cts { 1275 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1276 }; 1277 1278 uart1_rts: uart1-rts { 1279 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1280 }; 1281 1282 uart1_rts_pin: uart1-rts-pin { 1283 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1284 }; 1285 }; 1286 1287 uart2-0 { 1288 uart2m0_xfer: uart2m0-xfer { 1289 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1290 <1 RK_PA1 2 &pcfg_pull_up>; 1291 }; 1292 }; 1293 1294 uart2-1 { 1295 uart2m1_xfer: uart2m1-xfer { 1296 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1297 <2 RK_PA1 1 &pcfg_pull_up>; 1298 }; 1299 }; 1300 1301 spi0-0 { 1302 spi0m0_clk: spi0m0-clk { 1303 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1304 }; 1305 1306 spi0m0_cs0: spi0m0-cs0 { 1307 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1308 }; 1309 1310 spi0m0_tx: spi0m0-tx { 1311 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1312 }; 1313 1314 spi0m0_rx: spi0m0-rx { 1315 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1316 }; 1317 1318 spi0m0_cs1: spi0m0-cs1 { 1319 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1320 }; 1321 }; 1322 1323 spi0-1 { 1324 spi0m1_clk: spi0m1-clk { 1325 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1326 }; 1327 1328 spi0m1_cs0: spi0m1-cs0 { 1329 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1330 }; 1331 1332 spi0m1_tx: spi0m1-tx { 1333 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1334 }; 1335 1336 spi0m1_rx: spi0m1-rx { 1337 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1338 }; 1339 1340 spi0m1_cs1: spi0m1-cs1 { 1341 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1342 }; 1343 }; 1344 1345 spi0-2 { 1346 spi0m2_clk: spi0m2-clk { 1347 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1348 }; 1349 1350 spi0m2_cs0: spi0m2-cs0 { 1351 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1352 }; 1353 1354 spi0m2_tx: spi0m2-tx { 1355 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1356 }; 1357 1358 spi0m2_rx: spi0m2-rx { 1359 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1360 }; 1361 }; 1362 1363 i2s1 { 1364 i2s1_mclk: i2s1-mclk { 1365 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1366 }; 1367 1368 i2s1_sclk: i2s1-sclk { 1369 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1370 }; 1371 1372 i2s1_lrckrx: i2s1-lrckrx { 1373 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1374 }; 1375 1376 i2s1_lrcktx: i2s1-lrcktx { 1377 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1378 }; 1379 1380 i2s1_sdi: i2s1-sdi { 1381 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1382 }; 1383 1384 i2s1_sdo: i2s1-sdo { 1385 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1386 }; 1387 1388 i2s1_sdio1: i2s1-sdio1 { 1389 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1390 }; 1391 1392 i2s1_sdio2: i2s1-sdio2 { 1393 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1394 }; 1395 1396 i2s1_sdio3: i2s1-sdio3 { 1397 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1398 }; 1399 1400 i2s1_sleep: i2s1-sleep { 1401 rockchip,pins = 1402 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1403 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1404 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1405 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1406 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1407 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1408 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1409 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1410 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1411 }; 1412 }; 1413 1414 i2s2-0 { 1415 i2s2m0_mclk: i2s2m0-mclk { 1416 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1417 }; 1418 1419 i2s2m0_sclk: i2s2m0-sclk { 1420 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1421 }; 1422 1423 i2s2m0_lrckrx: i2s2m0-lrckrx { 1424 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1425 }; 1426 1427 i2s2m0_lrcktx: i2s2m0-lrcktx { 1428 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1429 }; 1430 1431 i2s2m0_sdi: i2s2m0-sdi { 1432 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1433 }; 1434 1435 i2s2m0_sdo: i2s2m0-sdo { 1436 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1437 }; 1438 1439 i2s2m0_sleep: i2s2m0-sleep { 1440 rockchip,pins = 1441 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1442 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1443 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1444 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1445 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1446 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1447 }; 1448 }; 1449 1450 i2s2-1 { 1451 i2s2m1_mclk: i2s2m1-mclk { 1452 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1453 }; 1454 1455 i2s2m1_sclk: i2s2m1-sclk { 1456 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1457 }; 1458 1459 i2s2m1_lrckrx: i2sm1-lrckrx { 1460 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1461 }; 1462 1463 i2s2m1_lrcktx: i2s2m1-lrcktx { 1464 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1465 }; 1466 1467 i2s2m1_sdi: i2s2m1-sdi { 1468 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1469 }; 1470 1471 i2s2m1_sdo: i2s2m1-sdo { 1472 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1473 }; 1474 1475 i2s2m1_sleep: i2s2m1-sleep { 1476 rockchip,pins = 1477 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1478 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1479 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1480 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1481 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1482 }; 1483 }; 1484 1485 spdif-0 { 1486 spdifm0_tx: spdifm0-tx { 1487 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1488 }; 1489 }; 1490 1491 spdif-1 { 1492 spdifm1_tx: spdifm1-tx { 1493 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1494 }; 1495 }; 1496 1497 spdif-2 { 1498 spdifm2_tx: spdifm2-tx { 1499 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1500 }; 1501 }; 1502 1503 sdmmc0-0 { 1504 sdmmc0m0_pwren: sdmmc0m0-pwren { 1505 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1506 }; 1507 1508 sdmmc0m0_pin: sdmmc0m0-pin { 1509 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1510 }; 1511 }; 1512 1513 sdmmc0-1 { 1514 sdmmc0m1_pwren: sdmmc0m1-pwren { 1515 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1516 }; 1517 1518 sdmmc0m1_pin: sdmmc0m1-pin { 1519 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1520 }; 1521 }; 1522 1523 sdmmc0 { 1524 sdmmc0_clk: sdmmc0-clk { 1525 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1526 }; 1527 1528 sdmmc0_cmd: sdmmc0-cmd { 1529 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1530 }; 1531 1532 sdmmc0_dectn: sdmmc0-dectn { 1533 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1534 }; 1535 1536 sdmmc0_wrprt: sdmmc0-wrprt { 1537 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1538 }; 1539 1540 sdmmc0_bus1: sdmmc0-bus1 { 1541 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1542 }; 1543 1544 sdmmc0_bus4: sdmmc0-bus4 { 1545 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1546 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1547 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1548 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1549 }; 1550 1551 sdmmc0_pins: sdmmc0-pins { 1552 rockchip,pins = 1553 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1554 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1555 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1556 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1557 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1558 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1559 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1560 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1561 }; 1562 }; 1563 1564 sdmmc0ext { 1565 sdmmc0ext_clk: sdmmc0ext-clk { 1566 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1567 }; 1568 1569 sdmmc0ext_cmd: sdmmc0ext-cmd { 1570 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1571 }; 1572 1573 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1574 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1575 }; 1576 1577 sdmmc0ext_dectn: sdmmc0ext-dectn { 1578 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1579 }; 1580 1581 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1582 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1583 }; 1584 1585 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1586 rockchip,pins = 1587 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1588 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1589 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1590 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1591 }; 1592 1593 sdmmc0ext_pins: sdmmc0ext-pins { 1594 rockchip,pins = 1595 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1596 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1597 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1598 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1599 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1600 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1601 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1602 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1603 }; 1604 }; 1605 1606 sdmmc1 { 1607 sdmmc1_clk: sdmmc1-clk { 1608 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1609 }; 1610 1611 sdmmc1_cmd: sdmmc1-cmd { 1612 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1613 }; 1614 1615 sdmmc1_pwren: sdmmc1-pwren { 1616 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1617 }; 1618 1619 sdmmc1_wrprt: sdmmc1-wrprt { 1620 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1621 }; 1622 1623 sdmmc1_dectn: sdmmc1-dectn { 1624 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1625 }; 1626 1627 sdmmc1_bus1: sdmmc1-bus1 { 1628 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1629 }; 1630 1631 sdmmc1_bus4: sdmmc1-bus4 { 1632 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1633 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1634 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1635 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1636 }; 1637 1638 sdmmc1_pins: sdmmc1-pins { 1639 rockchip,pins = 1640 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1641 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1642 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1643 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1644 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1645 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1646 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1647 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1648 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1649 }; 1650 }; 1651 1652 emmc { 1653 emmc_clk: emmc-clk { 1654 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1655 }; 1656 1657 emmc_cmd: emmc-cmd { 1658 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1659 }; 1660 1661 emmc_pwren: emmc-pwren { 1662 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1663 }; 1664 1665 emmc_rstnout: emmc-rstnout { 1666 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1667 }; 1668 1669 emmc_bus1: emmc-bus1 { 1670 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1671 }; 1672 1673 emmc_bus4: emmc-bus4 { 1674 rockchip,pins = 1675 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1676 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1677 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1678 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1679 }; 1680 1681 emmc_bus8: emmc-bus8 { 1682 rockchip,pins = 1683 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1684 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1685 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1686 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1687 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1688 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1689 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1690 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1691 }; 1692 }; 1693 1694 pwm0 { 1695 pwm0_pin: pwm0-pin { 1696 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1697 }; 1698 }; 1699 1700 pwm1 { 1701 pwm1_pin: pwm1-pin { 1702 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1703 }; 1704 }; 1705 1706 pwm2 { 1707 pwm2_pin: pwm2-pin { 1708 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1709 }; 1710 }; 1711 1712 pwmir { 1713 pwmir_pin: pwmir-pin { 1714 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1715 }; 1716 }; 1717 1718 gmac-1 { 1719 rgmiim1_pins: rgmiim1-pins { 1720 rockchip,pins = 1721 /* mac_txclk */ 1722 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1723 /* mac_rxclk */ 1724 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1725 /* mac_mdio */ 1726 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1727 /* mac_txen */ 1728 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1729 /* mac_clk */ 1730 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1731 /* mac_rxdv */ 1732 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1733 /* mac_mdc */ 1734 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1735 /* mac_rxd1 */ 1736 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1737 /* mac_rxd0 */ 1738 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1739 /* mac_txd1 */ 1740 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1741 /* mac_txd0 */ 1742 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1743 /* mac_rxd3 */ 1744 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1745 /* mac_rxd2 */ 1746 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1747 /* mac_txd3 */ 1748 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1749 /* mac_txd2 */ 1750 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1751 1752 /* mac_txclk */ 1753 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1754 /* mac_txen */ 1755 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1756 /* mac_clk */ 1757 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1758 /* mac_txd1 */ 1759 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1760 /* mac_txd0 */ 1761 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1762 /* mac_txd3 */ 1763 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1764 /* mac_txd2 */ 1765 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1766 }; 1767 1768 rmiim1_pins: rmiim1-pins { 1769 rockchip,pins = 1770 /* mac_mdio */ 1771 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1772 /* mac_txen */ 1773 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1774 /* mac_clk */ 1775 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1776 /* mac_rxer */ 1777 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1778 /* mac_rxdv */ 1779 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1780 /* mac_mdc */ 1781 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1782 /* mac_rxd1 */ 1783 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1784 /* mac_rxd0 */ 1785 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1786 /* mac_txd1 */ 1787 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1788 /* mac_txd0 */ 1789 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1790 1791 /* mac_mdio */ 1792 <0 RK_PB3 1 &pcfg_pull_none>, 1793 /* mac_txen */ 1794 <0 RK_PB4 1 &pcfg_pull_none>, 1795 /* mac_clk */ 1796 <0 RK_PD0 1 &pcfg_pull_none>, 1797 /* mac_mdc */ 1798 <0 RK_PC3 1 &pcfg_pull_none>, 1799 /* mac_txd1 */ 1800 <0 RK_PC0 1 &pcfg_pull_none>, 1801 /* mac_txd0 */ 1802 <0 RK_PC1 1 &pcfg_pull_none>; 1803 }; 1804 }; 1805 1806 gmac2phy { 1807 fephyled_speed10: fephyled-speed10 { 1808 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1809 }; 1810 1811 fephyled_duplex: fephyled-duplex { 1812 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1813 }; 1814 1815 fephyled_rxm1: fephyled-rxm1 { 1816 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1817 }; 1818 1819 fephyled_txm1: fephyled-txm1 { 1820 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1821 }; 1822 1823 fephyled_linkm1: fephyled-linkm1 { 1824 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1825 }; 1826 }; 1827 1828 tsadc_pin { 1829 tsadc_int: tsadc-int { 1830 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1831 }; 1832 tsadc_pin: tsadc-pin { 1833 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1834 }; 1835 }; 1836 1837 hdmi_pin { 1838 hdmi_cec: hdmi-cec { 1839 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1840 }; 1841 1842 hdmi_hpd: hdmi-hpd { 1843 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1844 }; 1845 }; 1846 1847 cif-0 { 1848 dvp_d2d9_m0:dvp-d2d9-m0 { 1849 rockchip,pins = 1850 /* cif_d0 */ 1851 <3 RK_PA4 2 &pcfg_pull_none>, 1852 /* cif_d1 */ 1853 <3 RK_PA5 2 &pcfg_pull_none>, 1854 /* cif_d2 */ 1855 <3 RK_PA6 2 &pcfg_pull_none>, 1856 /* cif_d3 */ 1857 <3 RK_PA7 2 &pcfg_pull_none>, 1858 /* cif_d4 */ 1859 <3 RK_PB0 2 &pcfg_pull_none>, 1860 /* cif_d5m0 */ 1861 <3 RK_PB1 2 &pcfg_pull_none>, 1862 /* cif_d6m0 */ 1863 <3 RK_PB2 2 &pcfg_pull_none>, 1864 /* cif_d7m0 */ 1865 <3 RK_PB3 2 &pcfg_pull_none>, 1866 /* cif_href */ 1867 <3 RK_PA1 2 &pcfg_pull_none>, 1868 /* cif_vsync */ 1869 <3 RK_PA0 2 &pcfg_pull_none>, 1870 /* cif_clkoutm0 */ 1871 <3 RK_PA3 2 &pcfg_pull_none>, 1872 /* cif_clkin */ 1873 <3 RK_PA2 2 &pcfg_pull_none>; 1874 }; 1875 }; 1876 1877 cif-1 { 1878 dvp_d2d9_m1:dvp-d2d9-m1 { 1879 rockchip,pins = 1880 /* cif_d0 */ 1881 <3 RK_PA4 2 &pcfg_pull_none>, 1882 /* cif_d1 */ 1883 <3 RK_PA5 2 &pcfg_pull_none>, 1884 /* cif_d2 */ 1885 <3 RK_PA6 2 &pcfg_pull_none>, 1886 /* cif_d3 */ 1887 <3 RK_PA7 2 &pcfg_pull_none>, 1888 /* cif_d4 */ 1889 <3 RK_PB0 2 &pcfg_pull_none>, 1890 /* cif_d5m1 */ 1891 <2 RK_PC0 4 &pcfg_pull_none>, 1892 /* cif_d6m1 */ 1893 <2 RK_PC1 4 &pcfg_pull_none>, 1894 /* cif_d7m1 */ 1895 <2 RK_PC2 4 &pcfg_pull_none>, 1896 /* cif_href */ 1897 <3 RK_PA1 2 &pcfg_pull_none>, 1898 /* cif_vsync */ 1899 <3 RK_PA0 2 &pcfg_pull_none>, 1900 /* cif_clkoutm1 */ 1901 <2 RK_PB7 4 &pcfg_pull_none>, 1902 /* cif_clkin */ 1903 <3 RK_PA2 2 &pcfg_pull_none>; 1904 }; 1905 }; 1906 }; 1907}; 1908