1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/rk3328-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/power/rk3328-power.h>
12#include <dt-bindings/soc/rockchip,boot-mode.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	compatible = "rockchip,rk3328";
17
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		serial0 = &uart0;
24		serial1 = &uart1;
25		serial2 = &uart2;
26		i2c0 = &i2c0;
27		i2c1 = &i2c1;
28		i2c2 = &i2c2;
29		i2c3 = &i2c3;
30		mmc0 = &sdmmc;
31		mmc1 = &sdio;
32		mmc2 = &emmc;
33		ethernet0 = &gmac2io;
34		ethernet1 = &gmac2phy;
35	};
36
37	cpus {
38		#address-cells = <2>;
39		#size-cells = <0>;
40
41		cpu0: cpu@0 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53";
44			reg = <0x0 0x0>;
45			clocks = <&cru ARMCLK>;
46			#cooling-cells = <2>;
47			cpu-idle-states = <&CPU_SLEEP>;
48			dynamic-power-coefficient = <120>;
49			enable-method = "psci";
50			next-level-cache = <&l2>;
51			operating-points-v2 = <&cpu0_opp_table>;
52		};
53
54		cpu1: cpu@1 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a53";
57			reg = <0x0 0x1>;
58			clocks = <&cru ARMCLK>;
59			#cooling-cells = <2>;
60			cpu-idle-states = <&CPU_SLEEP>;
61			dynamic-power-coefficient = <120>;
62			enable-method = "psci";
63			next-level-cache = <&l2>;
64			operating-points-v2 = <&cpu0_opp_table>;
65		};
66
67		cpu2: cpu@2 {
68			device_type = "cpu";
69			compatible = "arm,cortex-a53";
70			reg = <0x0 0x2>;
71			clocks = <&cru ARMCLK>;
72			#cooling-cells = <2>;
73			cpu-idle-states = <&CPU_SLEEP>;
74			dynamic-power-coefficient = <120>;
75			enable-method = "psci";
76			next-level-cache = <&l2>;
77			operating-points-v2 = <&cpu0_opp_table>;
78		};
79
80		cpu3: cpu@3 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a53";
83			reg = <0x0 0x3>;
84			clocks = <&cru ARMCLK>;
85			#cooling-cells = <2>;
86			cpu-idle-states = <&CPU_SLEEP>;
87			dynamic-power-coefficient = <120>;
88			enable-method = "psci";
89			next-level-cache = <&l2>;
90			operating-points-v2 = <&cpu0_opp_table>;
91		};
92
93		idle-states {
94			entry-method = "psci";
95
96			CPU_SLEEP: cpu-sleep {
97				compatible = "arm,idle-state";
98				local-timer-stop;
99				arm,psci-suspend-param = <0x0010000>;
100				entry-latency-us = <120>;
101				exit-latency-us = <250>;
102				min-residency-us = <900>;
103			};
104		};
105
106		l2: l2-cache0 {
107			compatible = "cache";
108		};
109	};
110
111	cpu0_opp_table: opp_table0 {
112		compatible = "operating-points-v2";
113		opp-shared;
114
115		opp-408000000 {
116			opp-hz = /bits/ 64 <408000000>;
117			opp-microvolt = <950000>;
118			clock-latency-ns = <40000>;
119			opp-suspend;
120		};
121		opp-600000000 {
122			opp-hz = /bits/ 64 <600000000>;
123			opp-microvolt = <950000>;
124			clock-latency-ns = <40000>;
125		};
126		opp-816000000 {
127			opp-hz = /bits/ 64 <816000000>;
128			opp-microvolt = <1000000>;
129			clock-latency-ns = <40000>;
130		};
131		opp-1008000000 {
132			opp-hz = /bits/ 64 <1008000000>;
133			opp-microvolt = <1100000>;
134			clock-latency-ns = <40000>;
135		};
136		opp-1200000000 {
137			opp-hz = /bits/ 64 <1200000000>;
138			opp-microvolt = <1225000>;
139			clock-latency-ns = <40000>;
140		};
141		opp-1296000000 {
142			opp-hz = /bits/ 64 <1296000000>;
143			opp-microvolt = <1300000>;
144			clock-latency-ns = <40000>;
145		};
146	};
147
148	analog_sound: analog-sound {
149		compatible = "simple-audio-card";
150		simple-audio-card,format = "i2s";
151		simple-audio-card,mclk-fs = <256>;
152		simple-audio-card,name = "Analog";
153		status = "disabled";
154
155		simple-audio-card,cpu {
156			sound-dai = <&i2s1>;
157		};
158
159		simple-audio-card,codec {
160			sound-dai = <&codec>;
161		};
162	};
163
164	arm-pmu {
165		compatible = "arm,cortex-a53-pmu";
166		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
167			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
168			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
169			     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
170		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
171	};
172
173	display_subsystem: display-subsystem {
174		compatible = "rockchip,display-subsystem";
175		ports = <&vop_out>;
176	};
177
178	hdmi_sound: hdmi-sound {
179		compatible = "simple-audio-card";
180		simple-audio-card,format = "i2s";
181		simple-audio-card,mclk-fs = <128>;
182		simple-audio-card,name = "HDMI";
183		status = "disabled";
184
185		simple-audio-card,cpu {
186			sound-dai = <&i2s0>;
187		};
188
189		simple-audio-card,codec {
190			sound-dai = <&hdmi>;
191		};
192	};
193
194	psci {
195		compatible = "arm,psci-1.0", "arm,psci-0.2";
196		method = "smc";
197	};
198
199	timer {
200		compatible = "arm,armv8-timer";
201		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
202			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
203			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
204			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
205	};
206
207	xin24m: xin24m {
208		compatible = "fixed-clock";
209		#clock-cells = <0>;
210		clock-frequency = <24000000>;
211		clock-output-names = "xin24m";
212	};
213
214	i2s0: i2s@ff000000 {
215		compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
216		reg = <0x0 0xff000000 0x0 0x1000>;
217		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
218		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
219		clock-names = "i2s_clk", "i2s_hclk";
220		dmas = <&dmac 11>, <&dmac 12>;
221		dma-names = "tx", "rx";
222		#sound-dai-cells = <0>;
223		status = "disabled";
224	};
225
226	i2s1: i2s@ff010000 {
227		compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
228		reg = <0x0 0xff010000 0x0 0x1000>;
229		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
230		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
231		clock-names = "i2s_clk", "i2s_hclk";
232		dmas = <&dmac 14>, <&dmac 15>;
233		dma-names = "tx", "rx";
234		#sound-dai-cells = <0>;
235		status = "disabled";
236	};
237
238	i2s2: i2s@ff020000 {
239		compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
240		reg = <0x0 0xff020000 0x0 0x1000>;
241		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
242		clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
243		clock-names = "i2s_clk", "i2s_hclk";
244		dmas = <&dmac 0>, <&dmac 1>;
245		dma-names = "tx", "rx";
246		#sound-dai-cells = <0>;
247		status = "disabled";
248	};
249
250	spdif: spdif@ff030000 {
251		compatible = "rockchip,rk3328-spdif";
252		reg = <0x0 0xff030000 0x0 0x1000>;
253		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
254		clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
255		clock-names = "mclk", "hclk";
256		dmas = <&dmac 10>;
257		dma-names = "tx";
258		pinctrl-names = "default";
259		pinctrl-0 = <&spdifm2_tx>;
260		#sound-dai-cells = <0>;
261		status = "disabled";
262	};
263
264	pdm: pdm@ff040000 {
265		compatible = "rockchip,pdm";
266		reg = <0x0 0xff040000 0x0 0x1000>;
267		clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
268		clock-names = "pdm_clk", "pdm_hclk";
269		dmas = <&dmac 16>;
270		dma-names = "rx";
271		pinctrl-names = "default", "sleep";
272		pinctrl-0 = <&pdmm0_clk
273			     &pdmm0_sdi0
274			     &pdmm0_sdi1
275			     &pdmm0_sdi2
276			     &pdmm0_sdi3>;
277		pinctrl-1 = <&pdmm0_clk_sleep
278			     &pdmm0_sdi0_sleep
279			     &pdmm0_sdi1_sleep
280			     &pdmm0_sdi2_sleep
281			     &pdmm0_sdi3_sleep>;
282		status = "disabled";
283	};
284
285	grf: syscon@ff100000 {
286		compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
287		reg = <0x0 0xff100000 0x0 0x1000>;
288
289		io_domains: io-domains {
290			compatible = "rockchip,rk3328-io-voltage-domain";
291			status = "disabled";
292		};
293
294		grf_gpio: grf-gpio {
295			compatible = "rockchip,rk3328-grf-gpio";
296			gpio-controller;
297			#gpio-cells = <2>;
298		};
299
300		power: power-controller {
301			compatible = "rockchip,rk3328-power-controller";
302			#power-domain-cells = <1>;
303			#address-cells = <1>;
304			#size-cells = <0>;
305
306			pd_hevc@RK3328_PD_HEVC {
307				reg = <RK3328_PD_HEVC>;
308			};
309			pd_video@RK3328_PD_VIDEO {
310				reg = <RK3328_PD_VIDEO>;
311			};
312			pd_vpu@RK3328_PD_VPU {
313				reg = <RK3328_PD_VPU>;
314				clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
315			};
316		};
317
318		reboot-mode {
319			compatible = "syscon-reboot-mode";
320			offset = <0x5c8>;
321			mode-normal = <BOOT_NORMAL>;
322			mode-recovery = <BOOT_RECOVERY>;
323			mode-bootloader = <BOOT_FASTBOOT>;
324			mode-loader = <BOOT_BL_DOWNLOAD>;
325		};
326	};
327
328	uart0: serial@ff110000 {
329		compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
330		reg = <0x0 0xff110000 0x0 0x100>;
331		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
332		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
333		clock-names = "baudclk", "apb_pclk";
334		dmas = <&dmac 2>, <&dmac 3>;
335		dma-names = "tx", "rx";
336		pinctrl-names = "default";
337		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
338		reg-io-width = <4>;
339		reg-shift = <2>;
340		status = "disabled";
341	};
342
343	uart1: serial@ff120000 {
344		compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
345		reg = <0x0 0xff120000 0x0 0x100>;
346		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
347		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
348		clock-names = "baudclk", "apb_pclk";
349		dmas = <&dmac 4>, <&dmac 5>;
350		dma-names = "tx", "rx";
351		pinctrl-names = "default";
352		pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
353		reg-io-width = <4>;
354		reg-shift = <2>;
355		status = "disabled";
356	};
357
358	uart2: serial@ff130000 {
359		compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
360		reg = <0x0 0xff130000 0x0 0x100>;
361		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
362		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
363		clock-names = "baudclk", "apb_pclk";
364		dmas = <&dmac 6>, <&dmac 7>;
365		dma-names = "tx", "rx";
366		pinctrl-names = "default";
367		pinctrl-0 = <&uart2m1_xfer>;
368		reg-io-width = <4>;
369		reg-shift = <2>;
370		status = "disabled";
371	};
372
373	i2c0: i2c@ff150000 {
374		compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
375		reg = <0x0 0xff150000 0x0 0x1000>;
376		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
377		#address-cells = <1>;
378		#size-cells = <0>;
379		clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
380		clock-names = "i2c", "pclk";
381		pinctrl-names = "default";
382		pinctrl-0 = <&i2c0_xfer>;
383		status = "disabled";
384	};
385
386	i2c1: i2c@ff160000 {
387		compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
388		reg = <0x0 0xff160000 0x0 0x1000>;
389		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
390		#address-cells = <1>;
391		#size-cells = <0>;
392		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
393		clock-names = "i2c", "pclk";
394		pinctrl-names = "default";
395		pinctrl-0 = <&i2c1_xfer>;
396		status = "disabled";
397	};
398
399	i2c2: i2c@ff170000 {
400		compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
401		reg = <0x0 0xff170000 0x0 0x1000>;
402		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
403		#address-cells = <1>;
404		#size-cells = <0>;
405		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
406		clock-names = "i2c", "pclk";
407		pinctrl-names = "default";
408		pinctrl-0 = <&i2c2_xfer>;
409		status = "disabled";
410	};
411
412	i2c3: i2c@ff180000 {
413		compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
414		reg = <0x0 0xff180000 0x0 0x1000>;
415		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
416		#address-cells = <1>;
417		#size-cells = <0>;
418		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
419		clock-names = "i2c", "pclk";
420		pinctrl-names = "default";
421		pinctrl-0 = <&i2c3_xfer>;
422		status = "disabled";
423	};
424
425	spi0: spi@ff190000 {
426		compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
427		reg = <0x0 0xff190000 0x0 0x1000>;
428		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
429		#address-cells = <1>;
430		#size-cells = <0>;
431		clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
432		clock-names = "spiclk", "apb_pclk";
433		dmas = <&dmac 8>, <&dmac 9>;
434		dma-names = "tx", "rx";
435		pinctrl-names = "default";
436		pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
437		status = "disabled";
438	};
439
440	wdt: watchdog@ff1a0000 {
441		compatible = "snps,dw-wdt";
442		reg = <0x0 0xff1a0000 0x0 0x100>;
443		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
444		clocks = <&cru PCLK_WDT>;
445	};
446
447	pwm0: pwm@ff1b0000 {
448		compatible = "rockchip,rk3328-pwm";
449		reg = <0x0 0xff1b0000 0x0 0x10>;
450		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
451		clock-names = "pwm", "pclk";
452		pinctrl-names = "default";
453		pinctrl-0 = <&pwm0_pin>;
454		#pwm-cells = <3>;
455		status = "disabled";
456	};
457
458	pwm1: pwm@ff1b0010 {
459		compatible = "rockchip,rk3328-pwm";
460		reg = <0x0 0xff1b0010 0x0 0x10>;
461		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
462		clock-names = "pwm", "pclk";
463		pinctrl-names = "default";
464		pinctrl-0 = <&pwm1_pin>;
465		#pwm-cells = <3>;
466		status = "disabled";
467	};
468
469	pwm2: pwm@ff1b0020 {
470		compatible = "rockchip,rk3328-pwm";
471		reg = <0x0 0xff1b0020 0x0 0x10>;
472		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
473		clock-names = "pwm", "pclk";
474		pinctrl-names = "default";
475		pinctrl-0 = <&pwm2_pin>;
476		#pwm-cells = <3>;
477		status = "disabled";
478	};
479
480	pwm3: pwm@ff1b0030 {
481		compatible = "rockchip,rk3328-pwm";
482		reg = <0x0 0xff1b0030 0x0 0x10>;
483		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
484		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
485		clock-names = "pwm", "pclk";
486		pinctrl-names = "default";
487		pinctrl-0 = <&pwmir_pin>;
488		#pwm-cells = <3>;
489		status = "disabled";
490	};
491
492	dmac: dmac@ff1f0000 {
493		compatible = "arm,pl330", "arm,primecell";
494		reg = <0x0 0xff1f0000 0x0 0x4000>;
495		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
496			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
497		arm,pl330-periph-burst;
498		clocks = <&cru ACLK_DMAC>;
499		clock-names = "apb_pclk";
500		#dma-cells = <1>;
501	};
502
503	thermal-zones {
504		soc_thermal: soc-thermal {
505			polling-delay-passive = <20>;
506			polling-delay = <1000>;
507			sustainable-power = <1000>;
508
509			thermal-sensors = <&tsadc 0>;
510
511			trips {
512				threshold: trip-point0 {
513					temperature = <70000>;
514					hysteresis = <2000>;
515					type = "passive";
516				};
517				target: trip-point1 {
518					temperature = <85000>;
519					hysteresis = <2000>;
520					type = "passive";
521				};
522				soc_crit: soc-crit {
523					temperature = <95000>;
524					hysteresis = <2000>;
525					type = "critical";
526				};
527			};
528
529			cooling-maps {
530				map0 {
531					trip = <&target>;
532					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
533							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
534							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
535							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
536					contribution = <4096>;
537				};
538			};
539		};
540
541	};
542
543	tsadc: tsadc@ff250000 {
544		compatible = "rockchip,rk3328-tsadc";
545		reg = <0x0 0xff250000 0x0 0x100>;
546		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
547		assigned-clocks = <&cru SCLK_TSADC>;
548		assigned-clock-rates = <50000>;
549		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
550		clock-names = "tsadc", "apb_pclk";
551		pinctrl-names = "init", "default", "sleep";
552		pinctrl-0 = <&otp_pin>;
553		pinctrl-1 = <&otp_out>;
554		pinctrl-2 = <&otp_pin>;
555		resets = <&cru SRST_TSADC>;
556		reset-names = "tsadc-apb";
557		rockchip,grf = <&grf>;
558		rockchip,hw-tshut-temp = <100000>;
559		#thermal-sensor-cells = <1>;
560		status = "disabled";
561	};
562
563	efuse: efuse@ff260000 {
564		compatible = "rockchip,rk3328-efuse";
565		reg = <0x0 0xff260000 0x0 0x50>;
566		#address-cells = <1>;
567		#size-cells = <1>;
568		clocks = <&cru SCLK_EFUSE>;
569		clock-names = "pclk_efuse";
570		rockchip,efuse-size = <0x20>;
571
572		/* Data cells */
573		efuse_id: id@7 {
574			reg = <0x07 0x10>;
575		};
576		cpu_leakage: cpu-leakage@17 {
577			reg = <0x17 0x1>;
578		};
579		logic_leakage: logic-leakage@19 {
580			reg = <0x19 0x1>;
581		};
582		efuse_cpu_version: cpu-version@1a {
583			reg = <0x1a 0x1>;
584			bits = <3 3>;
585		};
586	};
587
588	saradc: adc@ff280000 {
589		compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
590		reg = <0x0 0xff280000 0x0 0x100>;
591		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
592		#io-channel-cells = <1>;
593		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
594		clock-names = "saradc", "apb_pclk";
595		resets = <&cru SRST_SARADC_P>;
596		reset-names = "saradc-apb";
597		status = "disabled";
598	};
599
600	gpu: gpu@ff300000 {
601		compatible = "rockchip,rk3328-mali", "arm,mali-450";
602		reg = <0x0 0xff300000 0x0 0x40000>;
603		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
604			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
605			     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
606			     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
607			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
608			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
609			     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
610		interrupt-names = "gp",
611				  "gpmmu",
612				  "pp",
613				  "pp0",
614				  "ppmmu0",
615				  "pp1",
616				  "ppmmu1";
617		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
618		clock-names = "bus", "core";
619		resets = <&cru SRST_GPU_A>;
620	};
621
622	h265e_mmu: iommu@ff330200 {
623		compatible = "rockchip,iommu";
624		reg = <0x0 0xff330200 0 0x100>;
625		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
626		interrupt-names = "h265e_mmu";
627		clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
628		clock-names = "aclk", "iface";
629		#iommu-cells = <0>;
630		status = "disabled";
631	};
632
633	vepu_mmu: iommu@ff340800 {
634		compatible = "rockchip,iommu";
635		reg = <0x0 0xff340800 0x0 0x40>;
636		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
637		interrupt-names = "vepu_mmu";
638		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
639		clock-names = "aclk", "iface";
640		#iommu-cells = <0>;
641		status = "disabled";
642	};
643
644	vpu: video-codec@ff350000 {
645		compatible = "rockchip,rk3328-vpu";
646		reg = <0x0 0xff350000 0x0 0x800>;
647		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
648		interrupt-names = "vdpu";
649		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
650		clock-names = "aclk", "hclk";
651		iommus = <&vpu_mmu>;
652		power-domains = <&power RK3328_PD_VPU>;
653	};
654
655	vpu_mmu: iommu@ff350800 {
656		compatible = "rockchip,iommu";
657		reg = <0x0 0xff350800 0x0 0x40>;
658		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
659		interrupt-names = "vpu_mmu";
660		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
661		clock-names = "aclk", "iface";
662		#iommu-cells = <0>;
663		power-domains = <&power RK3328_PD_VPU>;
664	};
665
666	rkvdec_mmu: iommu@ff360480 {
667		compatible = "rockchip,iommu";
668		reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
669		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
670		interrupt-names = "rkvdec_mmu";
671		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
672		clock-names = "aclk", "iface";
673		#iommu-cells = <0>;
674		status = "disabled";
675	};
676
677	vop: vop@ff370000 {
678		compatible = "rockchip,rk3328-vop";
679		reg = <0x0 0xff370000 0x0 0x3efc>;
680		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
681		clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
682		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
683		resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
684		reset-names = "axi", "ahb", "dclk";
685		iommus = <&vop_mmu>;
686		status = "disabled";
687
688		vop_out: port {
689			#address-cells = <1>;
690			#size-cells = <0>;
691
692			vop_out_hdmi: endpoint@0 {
693				reg = <0>;
694				remote-endpoint = <&hdmi_in_vop>;
695			};
696		};
697	};
698
699	vop_mmu: iommu@ff373f00 {
700		compatible = "rockchip,iommu";
701		reg = <0x0 0xff373f00 0x0 0x100>;
702		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
703		interrupt-names = "vop_mmu";
704		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
705		clock-names = "aclk", "iface";
706		#iommu-cells = <0>;
707		status = "disabled";
708	};
709
710	hdmi: hdmi@ff3c0000 {
711		compatible = "rockchip,rk3328-dw-hdmi";
712		reg = <0x0 0xff3c0000 0x0 0x20000>;
713		reg-io-width = <4>;
714		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
715			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
716		clocks = <&cru PCLK_HDMI>,
717			 <&cru SCLK_HDMI_SFC>,
718			 <&cru SCLK_RTC32K>;
719		clock-names = "iahb",
720			      "isfr",
721			      "cec";
722		phys = <&hdmiphy>;
723		phy-names = "hdmi";
724		pinctrl-names = "default";
725		pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
726		rockchip,grf = <&grf>;
727		#sound-dai-cells = <0>;
728		status = "disabled";
729
730		ports {
731			hdmi_in: port {
732				hdmi_in_vop: endpoint {
733					remote-endpoint = <&vop_out_hdmi>;
734				};
735			};
736		};
737	};
738
739	codec: codec@ff410000 {
740		compatible = "rockchip,rk3328-codec";
741		reg = <0x0 0xff410000 0x0 0x1000>;
742		clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
743		clock-names = "pclk", "mclk";
744		rockchip,grf = <&grf>;
745		#sound-dai-cells = <0>;
746		status = "disabled";
747	};
748
749	hdmiphy: phy@ff430000 {
750		compatible = "rockchip,rk3328-hdmi-phy";
751		reg = <0x0 0xff430000 0x0 0x10000>;
752		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
753		clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
754		clock-names = "sysclk", "refoclk", "refpclk";
755		clock-output-names = "hdmi_phy";
756		#clock-cells = <0>;
757		nvmem-cells = <&efuse_cpu_version>;
758		nvmem-cell-names = "cpu-version";
759		#phy-cells = <0>;
760		status = "disabled";
761	};
762
763	cru: clock-controller@ff440000 {
764		compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
765		reg = <0x0 0xff440000 0x0 0x1000>;
766		rockchip,grf = <&grf>;
767		#clock-cells = <1>;
768		#reset-cells = <1>;
769		assigned-clocks =
770			/*
771			 * CPLL should run at 1200, but that is to high for
772			 * the initial dividers of most of its children.
773			 * We need set cpll child clk div first,
774			 * and then set the cpll frequency.
775			 */
776			<&cru DCLK_LCDC>, <&cru SCLK_PDM>,
777			<&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
778			<&cru SCLK_UART1>, <&cru SCLK_UART2>,
779			<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
780			<&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
781			<&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
782			<&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
783			<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
784			<&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
785			<&cru SCLK_SDIO>, <&cru SCLK_TSP>,
786			<&cru SCLK_WIFI>, <&cru ARMCLK>,
787			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
788			<&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
789			<&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
790			<&cru HCLK_PERI>, <&cru PCLK_PERI>,
791			<&cru SCLK_RTC32K>;
792		assigned-clock-parents =
793			<&cru HDMIPHY>, <&cru PLL_APLL>,
794			<&cru PLL_GPLL>, <&xin24m>,
795			<&xin24m>, <&xin24m>;
796		assigned-clock-rates =
797			<0>, <61440000>,
798			<0>, <24000000>,
799			<24000000>, <24000000>,
800			<15000000>, <15000000>,
801			<100000000>, <100000000>,
802			<100000000>, <100000000>,
803			<50000000>, <100000000>,
804			<100000000>, <100000000>,
805			<50000000>, <50000000>,
806			<50000000>, <50000000>,
807			<24000000>, <600000000>,
808			<491520000>, <1200000000>,
809			<150000000>, <75000000>,
810			<75000000>, <150000000>,
811			<75000000>, <75000000>,
812			<32768>;
813	};
814
815	usb2phy_grf: syscon@ff450000 {
816		compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
817			     "simple-mfd";
818		reg = <0x0 0xff450000 0x0 0x10000>;
819		#address-cells = <1>;
820		#size-cells = <1>;
821
822		u2phy: usb2-phy@100 {
823			compatible = "rockchip,rk3328-usb2phy";
824			reg = <0x100 0x10>;
825			clocks = <&xin24m>;
826			clock-names = "phyclk";
827			clock-output-names = "usb480m_phy";
828			#clock-cells = <0>;
829			assigned-clocks = <&cru USB480M>;
830			assigned-clock-parents = <&u2phy>;
831			status = "disabled";
832
833			u2phy_otg: otg-port {
834				#phy-cells = <0>;
835				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
836					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
837					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
838				interrupt-names = "otg-bvalid", "otg-id",
839						  "linestate";
840				status = "disabled";
841			};
842
843			u2phy_host: host-port {
844				#phy-cells = <0>;
845				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
846				interrupt-names = "linestate";
847				status = "disabled";
848			};
849		};
850	};
851
852	sdmmc: mmc@ff500000 {
853		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
854		reg = <0x0 0xff500000 0x0 0x4000>;
855		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
856		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
857			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
858		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
859		fifo-depth = <0x100>;
860		max-frequency = <150000000>;
861		status = "disabled";
862	};
863
864	sdio: mmc@ff510000 {
865		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
866		reg = <0x0 0xff510000 0x0 0x4000>;
867		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
868		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
869			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
870		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
871		fifo-depth = <0x100>;
872		max-frequency = <150000000>;
873		status = "disabled";
874	};
875
876	emmc: mmc@ff520000 {
877		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
878		reg = <0x0 0xff520000 0x0 0x4000>;
879		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
880		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
881			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
882		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
883		fifo-depth = <0x100>;
884		max-frequency = <150000000>;
885		status = "disabled";
886	};
887
888	gmac2io: ethernet@ff540000 {
889		compatible = "rockchip,rk3328-gmac";
890		reg = <0x0 0xff540000 0x0 0x10000>;
891		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
892		interrupt-names = "macirq";
893		clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
894			 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
895			 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
896			 <&cru PCLK_MAC2IO>;
897		clock-names = "stmmaceth", "mac_clk_rx",
898			      "mac_clk_tx", "clk_mac_ref",
899			      "clk_mac_refout", "aclk_mac",
900			      "pclk_mac";
901		resets = <&cru SRST_GMAC2IO_A>;
902		reset-names = "stmmaceth";
903		rockchip,grf = <&grf>;
904		snps,txpbl = <0x4>;
905		status = "disabled";
906	};
907
908	gmac2phy: ethernet@ff550000 {
909		compatible = "rockchip,rk3328-gmac";
910		reg = <0x0 0xff550000 0x0 0x10000>;
911		rockchip,grf = <&grf>;
912		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
913		interrupt-names = "macirq";
914		clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
915			 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
916			 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
917			 <&cru SCLK_MAC2PHY_OUT>;
918		clock-names = "stmmaceth", "mac_clk_rx",
919			      "mac_clk_tx", "clk_mac_ref",
920			      "aclk_mac", "pclk_mac",
921			      "clk_macphy";
922		resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
923		reset-names = "stmmaceth", "mac-phy";
924		phy-mode = "rmii";
925		phy-handle = <&phy>;
926		snps,txpbl = <0x4>;
927		clock_in_out = "output";
928		status = "disabled";
929
930		mdio {
931			compatible = "snps,dwmac-mdio";
932			#address-cells = <1>;
933			#size-cells = <0>;
934
935			phy: ethernet-phy@0 {
936				compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
937				reg = <0>;
938				clocks = <&cru SCLK_MAC2PHY_OUT>;
939				resets = <&cru SRST_MACPHY>;
940				pinctrl-names = "default";
941				pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
942				phy-is-integrated;
943			};
944		};
945	};
946
947	usb20_otg: usb@ff580000 {
948		compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
949			     "snps,dwc2";
950		reg = <0x0 0xff580000 0x0 0x40000>;
951		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
952		clocks = <&cru HCLK_OTG>;
953		clock-names = "otg";
954		dr_mode = "otg";
955		g-np-tx-fifo-size = <16>;
956		g-rx-fifo-size = <280>;
957		g-tx-fifo-size = <256 128 128 64 32 16>;
958		phys = <&u2phy_otg>;
959		phy-names = "usb2-phy";
960		status = "disabled";
961	};
962
963	usb_host0_ehci: usb@ff5c0000 {
964		compatible = "generic-ehci";
965		reg = <0x0 0xff5c0000 0x0 0x10000>;
966		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
967		clocks = <&cru HCLK_HOST0>, <&u2phy>;
968		phys = <&u2phy_host>;
969		phy-names = "usb";
970		status = "disabled";
971	};
972
973	usb_host0_ohci: usb@ff5d0000 {
974		compatible = "generic-ohci";
975		reg = <0x0 0xff5d0000 0x0 0x10000>;
976		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
977		clocks = <&cru HCLK_HOST0>, <&u2phy>;
978		phys = <&u2phy_host>;
979		phy-names = "usb";
980		status = "disabled";
981	};
982
983	gic: interrupt-controller@ff811000 {
984		compatible = "arm,gic-400";
985		#interrupt-cells = <3>;
986		#address-cells = <0>;
987		interrupt-controller;
988		reg = <0x0 0xff811000 0 0x1000>,
989		      <0x0 0xff812000 0 0x2000>,
990		      <0x0 0xff814000 0 0x2000>,
991		      <0x0 0xff816000 0 0x2000>;
992		interrupts = <GIC_PPI 9
993		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
994	};
995
996	pinctrl: pinctrl {
997		compatible = "rockchip,rk3328-pinctrl";
998		rockchip,grf = <&grf>;
999		#address-cells = <2>;
1000		#size-cells = <2>;
1001		ranges;
1002
1003		gpio0: gpio0@ff210000 {
1004			compatible = "rockchip,gpio-bank";
1005			reg = <0x0 0xff210000 0x0 0x100>;
1006			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1007			clocks = <&cru PCLK_GPIO0>;
1008
1009			gpio-controller;
1010			#gpio-cells = <2>;
1011
1012			interrupt-controller;
1013			#interrupt-cells = <2>;
1014		};
1015
1016		gpio1: gpio1@ff220000 {
1017			compatible = "rockchip,gpio-bank";
1018			reg = <0x0 0xff220000 0x0 0x100>;
1019			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1020			clocks = <&cru PCLK_GPIO1>;
1021
1022			gpio-controller;
1023			#gpio-cells = <2>;
1024
1025			interrupt-controller;
1026			#interrupt-cells = <2>;
1027		};
1028
1029		gpio2: gpio2@ff230000 {
1030			compatible = "rockchip,gpio-bank";
1031			reg = <0x0 0xff230000 0x0 0x100>;
1032			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1033			clocks = <&cru PCLK_GPIO2>;
1034
1035			gpio-controller;
1036			#gpio-cells = <2>;
1037
1038			interrupt-controller;
1039			#interrupt-cells = <2>;
1040		};
1041
1042		gpio3: gpio3@ff240000 {
1043			compatible = "rockchip,gpio-bank";
1044			reg = <0x0 0xff240000 0x0 0x100>;
1045			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1046			clocks = <&cru PCLK_GPIO3>;
1047
1048			gpio-controller;
1049			#gpio-cells = <2>;
1050
1051			interrupt-controller;
1052			#interrupt-cells = <2>;
1053		};
1054
1055		pcfg_pull_up: pcfg-pull-up {
1056			bias-pull-up;
1057		};
1058
1059		pcfg_pull_down: pcfg-pull-down {
1060			bias-pull-down;
1061		};
1062
1063		pcfg_pull_none: pcfg-pull-none {
1064			bias-disable;
1065		};
1066
1067		pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1068			bias-disable;
1069			drive-strength = <2>;
1070		};
1071
1072		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1073			bias-pull-up;
1074			drive-strength = <2>;
1075		};
1076
1077		pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1078			bias-pull-up;
1079			drive-strength = <4>;
1080		};
1081
1082		pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1083			bias-disable;
1084			drive-strength = <4>;
1085		};
1086
1087		pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1088			bias-pull-down;
1089			drive-strength = <4>;
1090		};
1091
1092		pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1093			bias-disable;
1094			drive-strength = <8>;
1095		};
1096
1097		pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1098			bias-pull-up;
1099			drive-strength = <8>;
1100		};
1101
1102		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1103			bias-disable;
1104			drive-strength = <12>;
1105		};
1106
1107		pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1108			bias-pull-up;
1109			drive-strength = <12>;
1110		};
1111
1112		pcfg_output_high: pcfg-output-high {
1113			output-high;
1114		};
1115
1116		pcfg_output_low: pcfg-output-low {
1117			output-low;
1118		};
1119
1120		pcfg_input_high: pcfg-input-high {
1121			bias-pull-up;
1122			input-enable;
1123		};
1124
1125		pcfg_input: pcfg-input {
1126			input-enable;
1127		};
1128
1129		i2c0 {
1130			i2c0_xfer: i2c0-xfer {
1131				rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1132						<2 RK_PD1 1 &pcfg_pull_none>;
1133			};
1134		};
1135
1136		i2c1 {
1137			i2c1_xfer: i2c1-xfer {
1138				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1139						<2 RK_PA5 2 &pcfg_pull_none>;
1140			};
1141		};
1142
1143		i2c2 {
1144			i2c2_xfer: i2c2-xfer {
1145				rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1146						<2 RK_PB6 1 &pcfg_pull_none>;
1147			};
1148		};
1149
1150		i2c3 {
1151			i2c3_xfer: i2c3-xfer {
1152				rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1153						<0 RK_PA6 2 &pcfg_pull_none>;
1154			};
1155			i2c3_pins: i2c3-pins {
1156				rockchip,pins =
1157					<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1158					<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1159			};
1160		};
1161
1162		hdmi_i2c {
1163			hdmii2c_xfer: hdmii2c-xfer {
1164				rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1165						<0 RK_PA6 1 &pcfg_pull_none>;
1166			};
1167		};
1168
1169		pdm-0 {
1170			pdmm0_clk: pdmm0-clk {
1171				rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1172			};
1173
1174			pdmm0_fsync: pdmm0-fsync {
1175				rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1176			};
1177
1178			pdmm0_sdi0: pdmm0-sdi0 {
1179				rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1180			};
1181
1182			pdmm0_sdi1: pdmm0-sdi1 {
1183				rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1184			};
1185
1186			pdmm0_sdi2: pdmm0-sdi2 {
1187				rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1188			};
1189
1190			pdmm0_sdi3: pdmm0-sdi3 {
1191				rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1192			};
1193
1194			pdmm0_clk_sleep: pdmm0-clk-sleep {
1195				rockchip,pins =
1196					<2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1197			};
1198
1199			pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1200				rockchip,pins =
1201					<2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1202			};
1203
1204			pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1205				rockchip,pins =
1206					<2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1207			};
1208
1209			pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1210				rockchip,pins =
1211					<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1212			};
1213
1214			pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1215				rockchip,pins =
1216					<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1217			};
1218
1219			pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1220				rockchip,pins =
1221					<2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1222			};
1223		};
1224
1225		tsadc {
1226			otp_pin: otp-pin {
1227				rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1228			};
1229
1230			otp_out: otp-out {
1231				rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1232			};
1233		};
1234
1235		uart0 {
1236			uart0_xfer: uart0-xfer {
1237				rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1238						<1 RK_PB0 1 &pcfg_pull_up>;
1239			};
1240
1241			uart0_cts: uart0-cts {
1242				rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1243			};
1244
1245			uart0_rts: uart0-rts {
1246				rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1247			};
1248
1249			uart0_rts_pin: uart0-rts-pin {
1250				rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1251			};
1252		};
1253
1254		uart1 {
1255			uart1_xfer: uart1-xfer {
1256				rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
1257						<3 RK_PA6 4 &pcfg_pull_up>;
1258			};
1259
1260			uart1_cts: uart1-cts {
1261				rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1262			};
1263
1264			uart1_rts: uart1-rts {
1265				rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1266			};
1267
1268			uart1_rts_pin: uart1-rts-pin {
1269				rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1270			};
1271		};
1272
1273		uart2-0 {
1274			uart2m0_xfer: uart2m0-xfer {
1275				rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
1276						<1 RK_PA1 2 &pcfg_pull_up>;
1277			};
1278		};
1279
1280		uart2-1 {
1281			uart2m1_xfer: uart2m1-xfer {
1282				rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
1283						<2 RK_PA1 1 &pcfg_pull_up>;
1284			};
1285		};
1286
1287		spi0-0 {
1288			spi0m0_clk: spi0m0-clk {
1289				rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1290			};
1291
1292			spi0m0_cs0: spi0m0-cs0 {
1293				rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1294			};
1295
1296			spi0m0_tx: spi0m0-tx {
1297				rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1298			};
1299
1300			spi0m0_rx: spi0m0-rx {
1301				rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1302			};
1303
1304			spi0m0_cs1: spi0m0-cs1 {
1305				rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1306			};
1307		};
1308
1309		spi0-1 {
1310			spi0m1_clk: spi0m1-clk {
1311				rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1312			};
1313
1314			spi0m1_cs0: spi0m1-cs0 {
1315				rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1316			};
1317
1318			spi0m1_tx: spi0m1-tx {
1319				rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1320			};
1321
1322			spi0m1_rx: spi0m1-rx {
1323				rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1324			};
1325
1326			spi0m1_cs1: spi0m1-cs1 {
1327				rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1328			};
1329		};
1330
1331		spi0-2 {
1332			spi0m2_clk: spi0m2-clk {
1333				rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1334			};
1335
1336			spi0m2_cs0: spi0m2-cs0 {
1337				rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1338			};
1339
1340			spi0m2_tx: spi0m2-tx {
1341				rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1342			};
1343
1344			spi0m2_rx: spi0m2-rx {
1345				rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1346			};
1347		};
1348
1349		i2s1 {
1350			i2s1_mclk: i2s1-mclk {
1351				rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1352			};
1353
1354			i2s1_sclk: i2s1-sclk {
1355				rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1356			};
1357
1358			i2s1_lrckrx: i2s1-lrckrx {
1359				rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1360			};
1361
1362			i2s1_lrcktx: i2s1-lrcktx {
1363				rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1364			};
1365
1366			i2s1_sdi: i2s1-sdi {
1367				rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1368			};
1369
1370			i2s1_sdo: i2s1-sdo {
1371				rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1372			};
1373
1374			i2s1_sdio1: i2s1-sdio1 {
1375				rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1376			};
1377
1378			i2s1_sdio2: i2s1-sdio2 {
1379				rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1380			};
1381
1382			i2s1_sdio3: i2s1-sdio3 {
1383				rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1384			};
1385
1386			i2s1_sleep: i2s1-sleep {
1387				rockchip,pins =
1388					<2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1389					<2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1390					<2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1391					<2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1392					<2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1393					<2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1394					<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1395					<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1396					<2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1397			};
1398		};
1399
1400		i2s2-0 {
1401			i2s2m0_mclk: i2s2m0-mclk {
1402				rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1403			};
1404
1405			i2s2m0_sclk: i2s2m0-sclk {
1406				rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1407			};
1408
1409			i2s2m0_lrckrx: i2s2m0-lrckrx {
1410				rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1411			};
1412
1413			i2s2m0_lrcktx: i2s2m0-lrcktx {
1414				rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1415			};
1416
1417			i2s2m0_sdi: i2s2m0-sdi {
1418				rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1419			};
1420
1421			i2s2m0_sdo: i2s2m0-sdo {
1422				rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1423			};
1424
1425			i2s2m0_sleep: i2s2m0-sleep {
1426				rockchip,pins =
1427					<1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1428					<1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1429					<1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1430					<1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1431					<1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1432					<1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1433			};
1434		};
1435
1436		i2s2-1 {
1437			i2s2m1_mclk: i2s2m1-mclk {
1438				rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1439			};
1440
1441			i2s2m1_sclk: i2s2m1-sclk {
1442				rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1443			};
1444
1445			i2s2m1_lrckrx: i2sm1-lrckrx {
1446				rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1447			};
1448
1449			i2s2m1_lrcktx: i2s2m1-lrcktx {
1450				rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1451			};
1452
1453			i2s2m1_sdi: i2s2m1-sdi {
1454				rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1455			};
1456
1457			i2s2m1_sdo: i2s2m1-sdo {
1458				rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1459			};
1460
1461			i2s2m1_sleep: i2s2m1-sleep {
1462				rockchip,pins =
1463					<1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1464					<3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1465					<3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1466					<3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1467					<3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1468			};
1469		};
1470
1471		spdif-0 {
1472			spdifm0_tx: spdifm0-tx {
1473				rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1474			};
1475		};
1476
1477		spdif-1 {
1478			spdifm1_tx: spdifm1-tx {
1479				rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1480			};
1481		};
1482
1483		spdif-2 {
1484			spdifm2_tx: spdifm2-tx {
1485				rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1486			};
1487		};
1488
1489		sdmmc0-0 {
1490			sdmmc0m0_pwren: sdmmc0m0-pwren {
1491				rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1492			};
1493
1494			sdmmc0m0_pin: sdmmc0m0-pin {
1495				rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1496			};
1497		};
1498
1499		sdmmc0-1 {
1500			sdmmc0m1_pwren: sdmmc0m1-pwren {
1501				rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1502			};
1503
1504			sdmmc0m1_pin: sdmmc0m1-pin {
1505				rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1506			};
1507		};
1508
1509		sdmmc0 {
1510			sdmmc0_clk: sdmmc0-clk {
1511				rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1512			};
1513
1514			sdmmc0_cmd: sdmmc0-cmd {
1515				rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1516			};
1517
1518			sdmmc0_dectn: sdmmc0-dectn {
1519				rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1520			};
1521
1522			sdmmc0_wrprt: sdmmc0-wrprt {
1523				rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1524			};
1525
1526			sdmmc0_bus1: sdmmc0-bus1 {
1527				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1528			};
1529
1530			sdmmc0_bus4: sdmmc0-bus4 {
1531				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1532						<1 RK_PA1 1 &pcfg_pull_up_8ma>,
1533						<1 RK_PA2 1 &pcfg_pull_up_8ma>,
1534						<1 RK_PA3 1 &pcfg_pull_up_8ma>;
1535			};
1536
1537			sdmmc0_pins: sdmmc0-pins {
1538				rockchip,pins =
1539					<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1540					<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1541					<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1542					<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1543					<1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1544					<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1545					<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1546					<1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1547			};
1548		};
1549
1550		sdmmc0ext {
1551			sdmmc0ext_clk: sdmmc0ext-clk {
1552				rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1553			};
1554
1555			sdmmc0ext_cmd: sdmmc0ext-cmd {
1556				rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1557			};
1558
1559			sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1560				rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1561			};
1562
1563			sdmmc0ext_dectn: sdmmc0ext-dectn {
1564				rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1565			};
1566
1567			sdmmc0ext_bus1: sdmmc0ext-bus1 {
1568				rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1569			};
1570
1571			sdmmc0ext_bus4: sdmmc0ext-bus4 {
1572				rockchip,pins =
1573					<3 RK_PA4 3 &pcfg_pull_up_4ma>,
1574					<3 RK_PA5 3 &pcfg_pull_up_4ma>,
1575					<3 RK_PA6 3 &pcfg_pull_up_4ma>,
1576					<3 RK_PA7 3 &pcfg_pull_up_4ma>;
1577			};
1578
1579			sdmmc0ext_pins: sdmmc0ext-pins {
1580				rockchip,pins =
1581					<3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1582					<3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1583					<3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1584					<3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1585					<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1586					<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1587					<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1588					<3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1589			};
1590		};
1591
1592		sdmmc1 {
1593			sdmmc1_clk: sdmmc1-clk {
1594				rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1595			};
1596
1597			sdmmc1_cmd: sdmmc1-cmd {
1598				rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1599			};
1600
1601			sdmmc1_pwren: sdmmc1-pwren {
1602				rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1603			};
1604
1605			sdmmc1_wrprt: sdmmc1-wrprt {
1606				rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1607			};
1608
1609			sdmmc1_dectn: sdmmc1-dectn {
1610				rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1611			};
1612
1613			sdmmc1_bus1: sdmmc1-bus1 {
1614				rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1615			};
1616
1617			sdmmc1_bus4: sdmmc1-bus4 {
1618				rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1619						<1 RK_PB7 1 &pcfg_pull_up_8ma>,
1620						<1 RK_PC0 1 &pcfg_pull_up_8ma>,
1621						<1 RK_PC1 1 &pcfg_pull_up_8ma>;
1622			};
1623
1624			sdmmc1_pins: sdmmc1-pins {
1625				rockchip,pins =
1626					<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1627					<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1628					<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1629					<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1630					<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1631					<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1632					<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1633					<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1634					<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1635			};
1636		};
1637
1638		emmc {
1639			emmc_clk: emmc-clk {
1640				rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1641			};
1642
1643			emmc_cmd: emmc-cmd {
1644				rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1645			};
1646
1647			emmc_pwren: emmc-pwren {
1648				rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1649			};
1650
1651			emmc_rstnout: emmc-rstnout {
1652				rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1653			};
1654
1655			emmc_bus1: emmc-bus1 {
1656				rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1657			};
1658
1659			emmc_bus4: emmc-bus4 {
1660				rockchip,pins =
1661					<0 RK_PA7 2 &pcfg_pull_up_12ma>,
1662					<2 RK_PD4 2 &pcfg_pull_up_12ma>,
1663					<2 RK_PD5 2 &pcfg_pull_up_12ma>,
1664					<2 RK_PD6 2 &pcfg_pull_up_12ma>;
1665			};
1666
1667			emmc_bus8: emmc-bus8 {
1668				rockchip,pins =
1669					<0 RK_PA7 2 &pcfg_pull_up_12ma>,
1670					<2 RK_PD4 2 &pcfg_pull_up_12ma>,
1671					<2 RK_PD5 2 &pcfg_pull_up_12ma>,
1672					<2 RK_PD6 2 &pcfg_pull_up_12ma>,
1673					<2 RK_PD7 2 &pcfg_pull_up_12ma>,
1674					<3 RK_PC0 2 &pcfg_pull_up_12ma>,
1675					<3 RK_PC1 2 &pcfg_pull_up_12ma>,
1676					<3 RK_PC2 2 &pcfg_pull_up_12ma>;
1677			};
1678		};
1679
1680		pwm0 {
1681			pwm0_pin: pwm0-pin {
1682				rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1683			};
1684		};
1685
1686		pwm1 {
1687			pwm1_pin: pwm1-pin {
1688				rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1689			};
1690		};
1691
1692		pwm2 {
1693			pwm2_pin: pwm2-pin {
1694				rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1695			};
1696		};
1697
1698		pwmir {
1699			pwmir_pin: pwmir-pin {
1700				rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1701			};
1702		};
1703
1704		gmac-1 {
1705			rgmiim1_pins: rgmiim1-pins {
1706				rockchip,pins =
1707					/* mac_txclk */
1708					<1 RK_PB4 2 &pcfg_pull_none_8ma>,
1709					/* mac_rxclk */
1710					<1 RK_PB5 2 &pcfg_pull_none_4ma>,
1711					/* mac_mdio */
1712					<1 RK_PC3 2 &pcfg_pull_none_4ma>,
1713					/* mac_txen */
1714					<1 RK_PD1 2 &pcfg_pull_none_8ma>,
1715					/* mac_clk */
1716					<1 RK_PC5 2 &pcfg_pull_none_4ma>,
1717					/* mac_rxdv */
1718					<1 RK_PC6 2 &pcfg_pull_none_4ma>,
1719					/* mac_mdc */
1720					<1 RK_PC7 2 &pcfg_pull_none_4ma>,
1721					/* mac_rxd1 */
1722					<1 RK_PB2 2 &pcfg_pull_none_4ma>,
1723					/* mac_rxd0 */
1724					<1 RK_PB3 2 &pcfg_pull_none_4ma>,
1725					/* mac_txd1 */
1726					<1 RK_PB0 2 &pcfg_pull_none_8ma>,
1727					/* mac_txd0 */
1728					<1 RK_PB1 2 &pcfg_pull_none_8ma>,
1729					/* mac_rxd3 */
1730					<1 RK_PB6 2 &pcfg_pull_none_4ma>,
1731					/* mac_rxd2 */
1732					<1 RK_PB7 2 &pcfg_pull_none_4ma>,
1733					/* mac_txd3 */
1734					<1 RK_PC0 2 &pcfg_pull_none_8ma>,
1735					/* mac_txd2 */
1736					<1 RK_PC1 2 &pcfg_pull_none_8ma>,
1737
1738					/* mac_txclk */
1739					<0 RK_PB0 1 &pcfg_pull_none_8ma>,
1740					/* mac_txen */
1741					<0 RK_PB4 1 &pcfg_pull_none_8ma>,
1742					/* mac_clk */
1743					<0 RK_PD0 1 &pcfg_pull_none_4ma>,
1744					/* mac_txd1 */
1745					<0 RK_PC0 1 &pcfg_pull_none_8ma>,
1746					/* mac_txd0 */
1747					<0 RK_PC1 1 &pcfg_pull_none_8ma>,
1748					/* mac_txd3 */
1749					<0 RK_PC7 1 &pcfg_pull_none_8ma>,
1750					/* mac_txd2 */
1751					<0 RK_PC6 1 &pcfg_pull_none_8ma>;
1752			};
1753
1754			rmiim1_pins: rmiim1-pins {
1755				rockchip,pins =
1756					/* mac_mdio */
1757					<1 RK_PC3 2 &pcfg_pull_none_2ma>,
1758					/* mac_txen */
1759					<1 RK_PD1 2 &pcfg_pull_none_12ma>,
1760					/* mac_clk */
1761					<1 RK_PC5 2 &pcfg_pull_none_2ma>,
1762					/* mac_rxer */
1763					<1 RK_PD0 2 &pcfg_pull_none_2ma>,
1764					/* mac_rxdv */
1765					<1 RK_PC6 2 &pcfg_pull_none_2ma>,
1766					/* mac_mdc */
1767					<1 RK_PC7 2 &pcfg_pull_none_2ma>,
1768					/* mac_rxd1 */
1769					<1 RK_PB2 2 &pcfg_pull_none_2ma>,
1770					/* mac_rxd0 */
1771					<1 RK_PB3 2 &pcfg_pull_none_2ma>,
1772					/* mac_txd1 */
1773					<1 RK_PB0 2 &pcfg_pull_none_12ma>,
1774					/* mac_txd0 */
1775					<1 RK_PB1 2 &pcfg_pull_none_12ma>,
1776
1777					/* mac_mdio */
1778					<0 RK_PB3 1 &pcfg_pull_none>,
1779					/* mac_txen */
1780					<0 RK_PB4 1 &pcfg_pull_none>,
1781					/* mac_clk */
1782					<0 RK_PD0 1 &pcfg_pull_none>,
1783					/* mac_mdc */
1784					<0 RK_PC3 1 &pcfg_pull_none>,
1785					/* mac_txd1 */
1786					<0 RK_PC0 1 &pcfg_pull_none>,
1787					/* mac_txd0 */
1788					<0 RK_PC1 1 &pcfg_pull_none>;
1789			};
1790		};
1791
1792		gmac2phy {
1793			fephyled_speed10: fephyled-speed10 {
1794				rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1795			};
1796
1797			fephyled_duplex: fephyled-duplex {
1798				rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1799			};
1800
1801			fephyled_rxm1: fephyled-rxm1 {
1802				rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1803			};
1804
1805			fephyled_txm1: fephyled-txm1 {
1806				rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1807			};
1808
1809			fephyled_linkm1: fephyled-linkm1 {
1810				rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1811			};
1812		};
1813
1814		tsadc_pin {
1815			tsadc_int: tsadc-int {
1816				rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1817			};
1818			tsadc_pin: tsadc-pin {
1819				rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1820			};
1821		};
1822
1823		hdmi_pin {
1824			hdmi_cec: hdmi-cec {
1825				rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1826			};
1827
1828			hdmi_hpd: hdmi-hpd {
1829				rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1830			};
1831		};
1832
1833		cif-0 {
1834			dvp_d2d9_m0:dvp-d2d9-m0 {
1835				rockchip,pins =
1836					/* cif_d0 */
1837					<3 RK_PA4 2 &pcfg_pull_none>,
1838					/* cif_d1 */
1839					<3 RK_PA5 2 &pcfg_pull_none>,
1840					/* cif_d2 */
1841					<3 RK_PA6 2 &pcfg_pull_none>,
1842					/* cif_d3 */
1843					<3 RK_PA7 2 &pcfg_pull_none>,
1844					/* cif_d4 */
1845					<3 RK_PB0 2 &pcfg_pull_none>,
1846					/* cif_d5m0 */
1847					<3 RK_PB1 2 &pcfg_pull_none>,
1848					/* cif_d6m0 */
1849					<3 RK_PB2 2 &pcfg_pull_none>,
1850					/* cif_d7m0 */
1851					<3 RK_PB3 2 &pcfg_pull_none>,
1852					/* cif_href */
1853					<3 RK_PA1 2 &pcfg_pull_none>,
1854					/* cif_vsync */
1855					<3 RK_PA0 2 &pcfg_pull_none>,
1856					/* cif_clkoutm0 */
1857					<3 RK_PA3 2 &pcfg_pull_none>,
1858					/* cif_clkin */
1859					<3 RK_PA2 2 &pcfg_pull_none>;
1860			};
1861		};
1862
1863		cif-1 {
1864			dvp_d2d9_m1:dvp-d2d9-m1 {
1865				rockchip,pins =
1866					/* cif_d0 */
1867					<3 RK_PA4 2 &pcfg_pull_none>,
1868					/* cif_d1 */
1869					<3 RK_PA5 2 &pcfg_pull_none>,
1870					/* cif_d2 */
1871					<3 RK_PA6 2 &pcfg_pull_none>,
1872					/* cif_d3 */
1873					<3 RK_PA7 2 &pcfg_pull_none>,
1874					/* cif_d4 */
1875					<3 RK_PB0 2 &pcfg_pull_none>,
1876					/* cif_d5m1 */
1877					<2 RK_PC0 4 &pcfg_pull_none>,
1878					/* cif_d6m1 */
1879					<2 RK_PC1 4 &pcfg_pull_none>,
1880					/* cif_d7m1 */
1881					<2 RK_PC2 4 &pcfg_pull_none>,
1882					/* cif_href */
1883					<3 RK_PA1 2 &pcfg_pull_none>,
1884					/* cif_vsync */
1885					<3 RK_PA0 2 &pcfg_pull_none>,
1886					/* cif_clkoutm1 */
1887					<2 RK_PB7 4 &pcfg_pull_none>,
1888					/* cif_clkin */
1889					<3 RK_PA2 2 &pcfg_pull_none>;
1890			};
1891		};
1892	};
1893};
1894