1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 dynamic-power-coefficient = <120>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 operating-points-v2 = <&cpu0_opp_table>; 48 }; 49 50 cpu1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x1>; 54 clocks = <&cru ARMCLK>; 55 #cooling-cells = <2>; 56 dynamic-power-coefficient = <120>; 57 enable-method = "psci"; 58 next-level-cache = <&l2>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 }; 61 62 cpu2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53"; 65 reg = <0x0 0x2>; 66 clocks = <&cru ARMCLK>; 67 #cooling-cells = <2>; 68 dynamic-power-coefficient = <120>; 69 enable-method = "psci"; 70 next-level-cache = <&l2>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x0 0x3>; 78 clocks = <&cru ARMCLK>; 79 #cooling-cells = <2>; 80 dynamic-power-coefficient = <120>; 81 enable-method = "psci"; 82 next-level-cache = <&l2>; 83 operating-points-v2 = <&cpu0_opp_table>; 84 }; 85 86 l2: l2-cache0 { 87 compatible = "cache"; 88 }; 89 }; 90 91 cpu0_opp_table: opp_table0 { 92 compatible = "operating-points-v2"; 93 opp-shared; 94 95 opp-408000000 { 96 opp-hz = /bits/ 64 <408000000>; 97 opp-microvolt = <950000>; 98 clock-latency-ns = <40000>; 99 opp-suspend; 100 }; 101 opp-600000000 { 102 opp-hz = /bits/ 64 <600000000>; 103 opp-microvolt = <950000>; 104 clock-latency-ns = <40000>; 105 }; 106 opp-816000000 { 107 opp-hz = /bits/ 64 <816000000>; 108 opp-microvolt = <1000000>; 109 clock-latency-ns = <40000>; 110 }; 111 opp-1008000000 { 112 opp-hz = /bits/ 64 <1008000000>; 113 opp-microvolt = <1100000>; 114 clock-latency-ns = <40000>; 115 }; 116 opp-1200000000 { 117 opp-hz = /bits/ 64 <1200000000>; 118 opp-microvolt = <1225000>; 119 clock-latency-ns = <40000>; 120 }; 121 opp-1296000000 { 122 opp-hz = /bits/ 64 <1296000000>; 123 opp-microvolt = <1300000>; 124 clock-latency-ns = <40000>; 125 }; 126 }; 127 128 amba { 129 compatible = "simple-bus"; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 134 dmac: dmac@ff1f0000 { 135 compatible = "arm,pl330", "arm,primecell"; 136 reg = <0x0 0xff1f0000 0x0 0x4000>; 137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&cru ACLK_DMAC>; 140 clock-names = "apb_pclk"; 141 #dma-cells = <1>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vop_out>; 157 }; 158 159 psci { 160 compatible = "arm,psci-1.0", "arm,psci-0.2"; 161 method = "smc"; 162 }; 163 164 timer { 165 compatible = "arm,armv8-timer"; 166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 170 }; 171 172 xin24m: xin24m { 173 compatible = "fixed-clock"; 174 #clock-cells = <0>; 175 clock-frequency = <24000000>; 176 clock-output-names = "xin24m"; 177 }; 178 179 i2s0: i2s@ff000000 { 180 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 181 reg = <0x0 0xff000000 0x0 0x1000>; 182 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 184 clock-names = "i2s_clk", "i2s_hclk"; 185 dmas = <&dmac 11>, <&dmac 12>; 186 dma-names = "tx", "rx"; 187 #sound-dai-cells = <0>; 188 status = "disabled"; 189 }; 190 191 i2s1: i2s@ff010000 { 192 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 193 reg = <0x0 0xff010000 0x0 0x1000>; 194 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 196 clock-names = "i2s_clk", "i2s_hclk"; 197 dmas = <&dmac 14>, <&dmac 15>; 198 dma-names = "tx", "rx"; 199 #sound-dai-cells = <0>; 200 status = "disabled"; 201 }; 202 203 i2s2: i2s@ff020000 { 204 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 205 reg = <0x0 0xff020000 0x0 0x1000>; 206 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 208 clock-names = "i2s_clk", "i2s_hclk"; 209 dmas = <&dmac 0>, <&dmac 1>; 210 dma-names = "tx", "rx"; 211 #sound-dai-cells = <0>; 212 status = "disabled"; 213 }; 214 215 spdif: spdif@ff030000 { 216 compatible = "rockchip,rk3328-spdif"; 217 reg = <0x0 0xff030000 0x0 0x1000>; 218 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 220 clock-names = "mclk", "hclk"; 221 dmas = <&dmac 10>; 222 dma-names = "tx"; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&spdifm2_tx>; 225 #sound-dai-cells = <0>; 226 status = "disabled"; 227 }; 228 229 pdm: pdm@ff040000 { 230 compatible = "rockchip,pdm"; 231 reg = <0x0 0xff040000 0x0 0x1000>; 232 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 233 clock-names = "pdm_clk", "pdm_hclk"; 234 dmas = <&dmac 16>; 235 dma-names = "rx"; 236 pinctrl-names = "default", "sleep"; 237 pinctrl-0 = <&pdmm0_clk 238 &pdmm0_sdi0 239 &pdmm0_sdi1 240 &pdmm0_sdi2 241 &pdmm0_sdi3>; 242 pinctrl-1 = <&pdmm0_clk_sleep 243 &pdmm0_sdi0_sleep 244 &pdmm0_sdi1_sleep 245 &pdmm0_sdi2_sleep 246 &pdmm0_sdi3_sleep>; 247 status = "disabled"; 248 }; 249 250 grf: syscon@ff100000 { 251 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 252 reg = <0x0 0xff100000 0x0 0x1000>; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 256 io_domains: io-domains { 257 compatible = "rockchip,rk3328-io-voltage-domain"; 258 status = "disabled"; 259 }; 260 261 grf_gpio: grf-gpio { 262 compatible = "rockchip,rk3328-grf-gpio"; 263 gpio-controller; 264 #gpio-cells = <2>; 265 }; 266 267 power: power-controller { 268 compatible = "rockchip,rk3328-power-controller"; 269 #power-domain-cells = <1>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 pd_hevc@RK3328_PD_HEVC { 274 reg = <RK3328_PD_HEVC>; 275 }; 276 pd_video@RK3328_PD_VIDEO { 277 reg = <RK3328_PD_VIDEO>; 278 }; 279 pd_vpu@RK3328_PD_VPU { 280 reg = <RK3328_PD_VPU>; 281 }; 282 }; 283 284 reboot-mode { 285 compatible = "syscon-reboot-mode"; 286 offset = <0x5c8>; 287 mode-normal = <BOOT_NORMAL>; 288 mode-recovery = <BOOT_RECOVERY>; 289 mode-bootloader = <BOOT_FASTBOOT>; 290 mode-loader = <BOOT_BL_DOWNLOAD>; 291 }; 292 }; 293 294 uart0: serial@ff110000 { 295 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 296 reg = <0x0 0xff110000 0x0 0x100>; 297 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 299 clock-names = "baudclk", "apb_pclk"; 300 dmas = <&dmac 2>, <&dmac 3>; 301 dma-names = "tx", "rx"; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 304 reg-io-width = <4>; 305 reg-shift = <2>; 306 status = "disabled"; 307 }; 308 309 uart1: serial@ff120000 { 310 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 311 reg = <0x0 0xff120000 0x0 0x100>; 312 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 314 clock-names = "baudclk", "apb_pclk"; 315 dmas = <&dmac 4>, <&dmac 5>; 316 dma-names = "tx", "rx"; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 319 reg-io-width = <4>; 320 reg-shift = <2>; 321 status = "disabled"; 322 }; 323 324 uart2: serial@ff130000 { 325 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 326 reg = <0x0 0xff130000 0x0 0x100>; 327 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 329 clock-names = "baudclk", "apb_pclk"; 330 dmas = <&dmac 6>, <&dmac 7>; 331 dma-names = "tx", "rx"; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&uart2m1_xfer>; 334 reg-io-width = <4>; 335 reg-shift = <2>; 336 status = "disabled"; 337 }; 338 339 i2c0: i2c@ff150000 { 340 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 341 reg = <0x0 0xff150000 0x0 0x1000>; 342 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 346 clock-names = "i2c", "pclk"; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&i2c0_xfer>; 349 status = "disabled"; 350 }; 351 352 i2c1: i2c@ff160000 { 353 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 354 reg = <0x0 0xff160000 0x0 0x1000>; 355 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 359 clock-names = "i2c", "pclk"; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&i2c1_xfer>; 362 status = "disabled"; 363 }; 364 365 i2c2: i2c@ff170000 { 366 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 367 reg = <0x0 0xff170000 0x0 0x1000>; 368 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 372 clock-names = "i2c", "pclk"; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&i2c2_xfer>; 375 status = "disabled"; 376 }; 377 378 i2c3: i2c@ff180000 { 379 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 380 reg = <0x0 0xff180000 0x0 0x1000>; 381 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 385 clock-names = "i2c", "pclk"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&i2c3_xfer>; 388 status = "disabled"; 389 }; 390 391 spi0: spi@ff190000 { 392 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 393 reg = <0x0 0xff190000 0x0 0x1000>; 394 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 398 clock-names = "spiclk", "apb_pclk"; 399 dmas = <&dmac 8>, <&dmac 9>; 400 dma-names = "tx", "rx"; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 403 status = "disabled"; 404 }; 405 406 wdt: watchdog@ff1a0000 { 407 compatible = "snps,dw-wdt"; 408 reg = <0x0 0xff1a0000 0x0 0x100>; 409 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 410 }; 411 412 pwm0: pwm@ff1b0000 { 413 compatible = "rockchip,rk3328-pwm"; 414 reg = <0x0 0xff1b0000 0x0 0x10>; 415 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 416 clock-names = "pwm", "pclk"; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&pwm0_pin>; 419 #pwm-cells = <3>; 420 status = "disabled"; 421 }; 422 423 pwm1: pwm@ff1b0010 { 424 compatible = "rockchip,rk3328-pwm"; 425 reg = <0x0 0xff1b0010 0x0 0x10>; 426 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 427 clock-names = "pwm", "pclk"; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&pwm1_pin>; 430 #pwm-cells = <3>; 431 status = "disabled"; 432 }; 433 434 pwm2: pwm@ff1b0020 { 435 compatible = "rockchip,rk3328-pwm"; 436 reg = <0x0 0xff1b0020 0x0 0x10>; 437 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 438 clock-names = "pwm", "pclk"; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&pwm2_pin>; 441 #pwm-cells = <3>; 442 status = "disabled"; 443 }; 444 445 pwm3: pwm@ff1b0030 { 446 compatible = "rockchip,rk3328-pwm"; 447 reg = <0x0 0xff1b0030 0x0 0x10>; 448 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 450 clock-names = "pwm", "pclk"; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pwmir_pin>; 453 #pwm-cells = <3>; 454 status = "disabled"; 455 }; 456 457 thermal-zones { 458 soc_thermal: soc-thermal { 459 polling-delay-passive = <20>; 460 polling-delay = <1000>; 461 sustainable-power = <1000>; 462 463 thermal-sensors = <&tsadc 0>; 464 465 trips { 466 threshold: trip-point0 { 467 temperature = <70000>; 468 hysteresis = <2000>; 469 type = "passive"; 470 }; 471 target: trip-point1 { 472 temperature = <85000>; 473 hysteresis = <2000>; 474 type = "passive"; 475 }; 476 soc_crit: soc-crit { 477 temperature = <95000>; 478 hysteresis = <2000>; 479 type = "critical"; 480 }; 481 }; 482 483 cooling-maps { 484 map0 { 485 trip = <&target>; 486 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 487 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 488 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 489 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 490 contribution = <4096>; 491 }; 492 }; 493 }; 494 495 }; 496 497 tsadc: tsadc@ff250000 { 498 compatible = "rockchip,rk3328-tsadc"; 499 reg = <0x0 0xff250000 0x0 0x100>; 500 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 501 assigned-clocks = <&cru SCLK_TSADC>; 502 assigned-clock-rates = <50000>; 503 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 504 clock-names = "tsadc", "apb_pclk"; 505 pinctrl-names = "init", "default", "sleep"; 506 pinctrl-0 = <&otp_gpio>; 507 pinctrl-1 = <&otp_out>; 508 pinctrl-2 = <&otp_gpio>; 509 resets = <&cru SRST_TSADC>; 510 reset-names = "tsadc-apb"; 511 rockchip,grf = <&grf>; 512 rockchip,hw-tshut-temp = <100000>; 513 #thermal-sensor-cells = <1>; 514 status = "disabled"; 515 }; 516 517 efuse: efuse@ff260000 { 518 compatible = "rockchip,rk3328-efuse"; 519 reg = <0x0 0xff260000 0x0 0x50>; 520 #address-cells = <1>; 521 #size-cells = <1>; 522 clocks = <&cru SCLK_EFUSE>; 523 clock-names = "pclk_efuse"; 524 rockchip,efuse-size = <0x20>; 525 526 /* Data cells */ 527 efuse_id: id@7 { 528 reg = <0x07 0x10>; 529 }; 530 cpu_leakage: cpu-leakage@17 { 531 reg = <0x17 0x1>; 532 }; 533 logic_leakage: logic-leakage@19 { 534 reg = <0x19 0x1>; 535 }; 536 efuse_cpu_version: cpu-version@1a { 537 reg = <0x1a 0x1>; 538 bits = <3 3>; 539 }; 540 }; 541 542 saradc: adc@ff280000 { 543 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 544 reg = <0x0 0xff280000 0x0 0x100>; 545 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 546 #io-channel-cells = <1>; 547 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 548 clock-names = "saradc", "apb_pclk"; 549 resets = <&cru SRST_SARADC_P>; 550 reset-names = "saradc-apb"; 551 status = "disabled"; 552 }; 553 554 gpu: gpu@ff300000 { 555 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 556 reg = <0x0 0xff300000 0x0 0x40000>; 557 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 564 interrupt-names = "gp", 565 "gpmmu", 566 "pp", 567 "pp0", 568 "ppmmu0", 569 "pp1", 570 "ppmmu1"; 571 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 572 clock-names = "bus", "core"; 573 resets = <&cru SRST_GPU_A>; 574 }; 575 576 h265e_mmu: iommu@ff330200 { 577 compatible = "rockchip,iommu"; 578 reg = <0x0 0xff330200 0 0x100>; 579 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 580 interrupt-names = "h265e_mmu"; 581 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 582 clock-names = "aclk", "iface"; 583 #iommu-cells = <0>; 584 status = "disabled"; 585 }; 586 587 vepu_mmu: iommu@ff340800 { 588 compatible = "rockchip,iommu"; 589 reg = <0x0 0xff340800 0x0 0x40>; 590 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 591 interrupt-names = "vepu_mmu"; 592 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 593 clock-names = "aclk", "iface"; 594 #iommu-cells = <0>; 595 status = "disabled"; 596 }; 597 598 vpu_mmu: iommu@ff350800 { 599 compatible = "rockchip,iommu"; 600 reg = <0x0 0xff350800 0x0 0x40>; 601 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 602 interrupt-names = "vpu_mmu"; 603 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 604 clock-names = "aclk", "iface"; 605 #iommu-cells = <0>; 606 status = "disabled"; 607 }; 608 609 rkvdec_mmu: iommu@ff360480 { 610 compatible = "rockchip,iommu"; 611 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 612 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 613 interrupt-names = "rkvdec_mmu"; 614 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 615 clock-names = "aclk", "iface"; 616 #iommu-cells = <0>; 617 status = "disabled"; 618 }; 619 620 vop: vop@ff370000 { 621 compatible = "rockchip,rk3328-vop"; 622 reg = <0x0 0xff370000 0x0 0x3efc>; 623 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 625 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 626 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 627 reset-names = "axi", "ahb", "dclk"; 628 iommus = <&vop_mmu>; 629 status = "disabled"; 630 631 vop_out: port { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 635 vop_out_hdmi: endpoint@0 { 636 reg = <0>; 637 remote-endpoint = <&hdmi_in_vop>; 638 }; 639 }; 640 }; 641 642 vop_mmu: iommu@ff373f00 { 643 compatible = "rockchip,iommu"; 644 reg = <0x0 0xff373f00 0x0 0x100>; 645 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 646 interrupt-names = "vop_mmu"; 647 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 648 clock-names = "aclk", "iface"; 649 #iommu-cells = <0>; 650 status = "disabled"; 651 }; 652 653 hdmi: hdmi@ff3c0000 { 654 compatible = "rockchip,rk3328-dw-hdmi"; 655 reg = <0x0 0xff3c0000 0x0 0x20000>; 656 reg-io-width = <4>; 657 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&cru PCLK_HDMI>, 660 <&cru SCLK_HDMI_SFC>, 661 <&cru SCLK_RTC32K>; 662 clock-names = "iahb", 663 "isfr", 664 "cec"; 665 phys = <&hdmiphy>; 666 phy-names = "hdmi"; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 669 rockchip,grf = <&grf>; 670 #sound-dai-cells = <0>; 671 status = "disabled"; 672 673 ports { 674 hdmi_in: port { 675 hdmi_in_vop: endpoint { 676 remote-endpoint = <&vop_out_hdmi>; 677 }; 678 }; 679 }; 680 }; 681 682 codec: codec@ff410000 { 683 compatible = "rockchip,rk3328-codec"; 684 reg = <0x0 0xff410000 0x0 0x1000>; 685 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 686 clock-names = "pclk", "mclk"; 687 rockchip,grf = <&grf>; 688 #sound-dai-cells = <0>; 689 status = "disabled"; 690 }; 691 692 hdmiphy: phy@ff430000 { 693 compatible = "rockchip,rk3328-hdmi-phy"; 694 reg = <0x0 0xff430000 0x0 0x10000>; 695 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 697 clock-names = "sysclk", "refoclk", "refpclk"; 698 clock-output-names = "hdmi_phy"; 699 #clock-cells = <0>; 700 nvmem-cells = <&efuse_cpu_version>; 701 nvmem-cell-names = "cpu-version"; 702 #phy-cells = <0>; 703 status = "disabled"; 704 }; 705 706 cru: clock-controller@ff440000 { 707 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 708 reg = <0x0 0xff440000 0x0 0x1000>; 709 rockchip,grf = <&grf>; 710 #clock-cells = <1>; 711 #reset-cells = <1>; 712 assigned-clocks = 713 /* 714 * CPLL should run at 1200, but that is to high for 715 * the initial dividers of most of its children. 716 * We need set cpll child clk div first, 717 * and then set the cpll frequency. 718 */ 719 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 720 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 721 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 722 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 723 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 724 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 725 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 726 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 727 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 728 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 729 <&cru SCLK_WIFI>, <&cru ARMCLK>, 730 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 731 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 732 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 733 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 734 <&cru SCLK_RTC32K>; 735 assigned-clock-parents = 736 <&cru HDMIPHY>, <&cru PLL_APLL>, 737 <&cru PLL_GPLL>, <&xin24m>, 738 <&xin24m>, <&xin24m>; 739 assigned-clock-rates = 740 <0>, <61440000>, 741 <0>, <24000000>, 742 <24000000>, <24000000>, 743 <15000000>, <15000000>, 744 <100000000>, <100000000>, 745 <100000000>, <100000000>, 746 <50000000>, <100000000>, 747 <100000000>, <100000000>, 748 <50000000>, <50000000>, 749 <50000000>, <50000000>, 750 <24000000>, <600000000>, 751 <491520000>, <1200000000>, 752 <150000000>, <75000000>, 753 <75000000>, <150000000>, 754 <75000000>, <75000000>, 755 <32768>; 756 }; 757 758 usb2phy_grf: syscon@ff450000 { 759 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 760 "simple-mfd"; 761 reg = <0x0 0xff450000 0x0 0x10000>; 762 #address-cells = <1>; 763 #size-cells = <1>; 764 765 u2phy: usb2-phy@100 { 766 compatible = "rockchip,rk3328-usb2phy"; 767 reg = <0x100 0x10>; 768 clocks = <&xin24m>; 769 clock-names = "phyclk"; 770 clock-output-names = "usb480m_phy"; 771 #clock-cells = <0>; 772 assigned-clocks = <&cru USB480M>; 773 assigned-clock-parents = <&u2phy>; 774 status = "disabled"; 775 776 u2phy_otg: otg-port { 777 #phy-cells = <0>; 778 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 781 interrupt-names = "otg-bvalid", "otg-id", 782 "linestate"; 783 status = "disabled"; 784 }; 785 786 u2phy_host: host-port { 787 #phy-cells = <0>; 788 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 789 interrupt-names = "linestate"; 790 status = "disabled"; 791 }; 792 }; 793 }; 794 795 sdmmc: dwmmc@ff500000 { 796 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 797 reg = <0x0 0xff500000 0x0 0x4000>; 798 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 800 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 801 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 802 fifo-depth = <0x100>; 803 status = "disabled"; 804 }; 805 806 sdio: dwmmc@ff510000 { 807 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 808 reg = <0x0 0xff510000 0x0 0x4000>; 809 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 811 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 812 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 813 fifo-depth = <0x100>; 814 status = "disabled"; 815 }; 816 817 emmc: dwmmc@ff520000 { 818 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 819 reg = <0x0 0xff520000 0x0 0x4000>; 820 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 822 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 823 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 824 fifo-depth = <0x100>; 825 status = "disabled"; 826 }; 827 828 gmac2io: ethernet@ff540000 { 829 compatible = "rockchip,rk3328-gmac"; 830 reg = <0x0 0xff540000 0x0 0x10000>; 831 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 832 interrupt-names = "macirq"; 833 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 834 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 835 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 836 <&cru PCLK_MAC2IO>; 837 clock-names = "stmmaceth", "mac_clk_rx", 838 "mac_clk_tx", "clk_mac_ref", 839 "clk_mac_refout", "aclk_mac", 840 "pclk_mac"; 841 resets = <&cru SRST_GMAC2IO_A>; 842 reset-names = "stmmaceth"; 843 rockchip,grf = <&grf>; 844 status = "disabled"; 845 }; 846 847 gmac2phy: ethernet@ff550000 { 848 compatible = "rockchip,rk3328-gmac"; 849 reg = <0x0 0xff550000 0x0 0x10000>; 850 rockchip,grf = <&grf>; 851 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 852 interrupt-names = "macirq"; 853 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 854 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 855 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 856 <&cru SCLK_MAC2PHY_OUT>; 857 clock-names = "stmmaceth", "mac_clk_rx", 858 "mac_clk_tx", "clk_mac_ref", 859 "aclk_mac", "pclk_mac", 860 "clk_macphy"; 861 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; 862 reset-names = "stmmaceth", "mac-phy"; 863 phy-mode = "rmii"; 864 phy-handle = <&phy>; 865 status = "disabled"; 866 867 mdio { 868 compatible = "snps,dwmac-mdio"; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 872 phy: phy@0 { 873 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 874 reg = <0>; 875 clocks = <&cru SCLK_MAC2PHY_OUT>; 876 resets = <&cru SRST_MACPHY>; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 879 phy-is-integrated; 880 }; 881 }; 882 }; 883 884 usb20_otg: usb@ff580000 { 885 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 886 "snps,dwc2"; 887 reg = <0x0 0xff580000 0x0 0x40000>; 888 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&cru HCLK_OTG>; 890 clock-names = "otg"; 891 dr_mode = "otg"; 892 g-np-tx-fifo-size = <16>; 893 g-rx-fifo-size = <280>; 894 g-tx-fifo-size = <256 128 128 64 32 16>; 895 g-use-dma; 896 phys = <&u2phy_otg>; 897 phy-names = "usb2-phy"; 898 status = "disabled"; 899 }; 900 901 usb_host0_ehci: usb@ff5c0000 { 902 compatible = "generic-ehci"; 903 reg = <0x0 0xff5c0000 0x0 0x10000>; 904 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&cru HCLK_HOST0>, <&u2phy>; 906 clock-names = "usbhost", "utmi"; 907 phys = <&u2phy_host>; 908 phy-names = "usb"; 909 status = "disabled"; 910 }; 911 912 usb_host0_ohci: usb@ff5d0000 { 913 compatible = "generic-ohci"; 914 reg = <0x0 0xff5d0000 0x0 0x10000>; 915 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&cru HCLK_HOST0>, <&u2phy>; 917 clock-names = "usbhost", "utmi"; 918 phys = <&u2phy_host>; 919 phy-names = "usb"; 920 status = "disabled"; 921 }; 922 923 gic: interrupt-controller@ff811000 { 924 compatible = "arm,gic-400"; 925 #interrupt-cells = <3>; 926 #address-cells = <0>; 927 interrupt-controller; 928 reg = <0x0 0xff811000 0 0x1000>, 929 <0x0 0xff812000 0 0x2000>, 930 <0x0 0xff814000 0 0x2000>, 931 <0x0 0xff816000 0 0x2000>; 932 interrupts = <GIC_PPI 9 933 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 934 }; 935 936 pinctrl: pinctrl { 937 compatible = "rockchip,rk3328-pinctrl"; 938 rockchip,grf = <&grf>; 939 #address-cells = <2>; 940 #size-cells = <2>; 941 ranges; 942 943 gpio0: gpio0@ff210000 { 944 compatible = "rockchip,gpio-bank"; 945 reg = <0x0 0xff210000 0x0 0x100>; 946 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&cru PCLK_GPIO0>; 948 949 gpio-controller; 950 #gpio-cells = <2>; 951 952 interrupt-controller; 953 #interrupt-cells = <2>; 954 }; 955 956 gpio1: gpio1@ff220000 { 957 compatible = "rockchip,gpio-bank"; 958 reg = <0x0 0xff220000 0x0 0x100>; 959 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&cru PCLK_GPIO1>; 961 962 gpio-controller; 963 #gpio-cells = <2>; 964 965 interrupt-controller; 966 #interrupt-cells = <2>; 967 }; 968 969 gpio2: gpio2@ff230000 { 970 compatible = "rockchip,gpio-bank"; 971 reg = <0x0 0xff230000 0x0 0x100>; 972 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&cru PCLK_GPIO2>; 974 975 gpio-controller; 976 #gpio-cells = <2>; 977 978 interrupt-controller; 979 #interrupt-cells = <2>; 980 }; 981 982 gpio3: gpio3@ff240000 { 983 compatible = "rockchip,gpio-bank"; 984 reg = <0x0 0xff240000 0x0 0x100>; 985 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&cru PCLK_GPIO3>; 987 988 gpio-controller; 989 #gpio-cells = <2>; 990 991 interrupt-controller; 992 #interrupt-cells = <2>; 993 }; 994 995 pcfg_pull_up: pcfg-pull-up { 996 bias-pull-up; 997 }; 998 999 pcfg_pull_down: pcfg-pull-down { 1000 bias-pull-down; 1001 }; 1002 1003 pcfg_pull_none: pcfg-pull-none { 1004 bias-disable; 1005 }; 1006 1007 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1008 bias-disable; 1009 drive-strength = <2>; 1010 }; 1011 1012 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1013 bias-pull-up; 1014 drive-strength = <2>; 1015 }; 1016 1017 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1018 bias-pull-up; 1019 drive-strength = <4>; 1020 }; 1021 1022 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1023 bias-disable; 1024 drive-strength = <4>; 1025 }; 1026 1027 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1028 bias-pull-down; 1029 drive-strength = <4>; 1030 }; 1031 1032 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1033 bias-disable; 1034 drive-strength = <8>; 1035 }; 1036 1037 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1038 bias-pull-up; 1039 drive-strength = <8>; 1040 }; 1041 1042 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1043 bias-disable; 1044 drive-strength = <12>; 1045 }; 1046 1047 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1048 bias-pull-up; 1049 drive-strength = <12>; 1050 }; 1051 1052 pcfg_output_high: pcfg-output-high { 1053 output-high; 1054 }; 1055 1056 pcfg_output_low: pcfg-output-low { 1057 output-low; 1058 }; 1059 1060 pcfg_input_high: pcfg-input-high { 1061 bias-pull-up; 1062 input-enable; 1063 }; 1064 1065 pcfg_input: pcfg-input { 1066 input-enable; 1067 }; 1068 1069 i2c0 { 1070 i2c0_xfer: i2c0-xfer { 1071 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1072 <2 RK_PD1 1 &pcfg_pull_none>; 1073 }; 1074 }; 1075 1076 i2c1 { 1077 i2c1_xfer: i2c1-xfer { 1078 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1079 <2 RK_PA5 2 &pcfg_pull_none>; 1080 }; 1081 }; 1082 1083 i2c2 { 1084 i2c2_xfer: i2c2-xfer { 1085 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1086 <2 RK_PB6 1 &pcfg_pull_none>; 1087 }; 1088 }; 1089 1090 i2c3 { 1091 i2c3_xfer: i2c3-xfer { 1092 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1093 <0 RK_PA6 2 &pcfg_pull_none>; 1094 }; 1095 i2c3_gpio: i2c3-gpio { 1096 rockchip,pins = 1097 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1098 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1099 }; 1100 }; 1101 1102 hdmi_i2c { 1103 hdmii2c_xfer: hdmii2c-xfer { 1104 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1105 <0 RK_PA6 1 &pcfg_pull_none>; 1106 }; 1107 }; 1108 1109 pdm-0 { 1110 pdmm0_clk: pdmm0-clk { 1111 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1112 }; 1113 1114 pdmm0_fsync: pdmm0-fsync { 1115 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1116 }; 1117 1118 pdmm0_sdi0: pdmm0-sdi0 { 1119 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1120 }; 1121 1122 pdmm0_sdi1: pdmm0-sdi1 { 1123 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1124 }; 1125 1126 pdmm0_sdi2: pdmm0-sdi2 { 1127 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1128 }; 1129 1130 pdmm0_sdi3: pdmm0-sdi3 { 1131 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1132 }; 1133 1134 pdmm0_clk_sleep: pdmm0-clk-sleep { 1135 rockchip,pins = 1136 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1137 }; 1138 1139 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1140 rockchip,pins = 1141 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1142 }; 1143 1144 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1145 rockchip,pins = 1146 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1147 }; 1148 1149 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1150 rockchip,pins = 1151 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1152 }; 1153 1154 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1155 rockchip,pins = 1156 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1157 }; 1158 1159 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1160 rockchip,pins = 1161 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1162 }; 1163 }; 1164 1165 tsadc { 1166 otp_gpio: otp-gpio { 1167 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1168 }; 1169 1170 otp_out: otp-out { 1171 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1172 }; 1173 }; 1174 1175 uart0 { 1176 uart0_xfer: uart0-xfer { 1177 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, 1178 <1 RK_PB0 1 &pcfg_pull_none>; 1179 }; 1180 1181 uart0_cts: uart0-cts { 1182 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1183 }; 1184 1185 uart0_rts: uart0-rts { 1186 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1187 }; 1188 1189 uart0_rts_gpio: uart0-rts-gpio { 1190 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1191 }; 1192 }; 1193 1194 uart1 { 1195 uart1_xfer: uart1-xfer { 1196 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, 1197 <3 RK_PA6 4 &pcfg_pull_none>; 1198 }; 1199 1200 uart1_cts: uart1-cts { 1201 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1202 }; 1203 1204 uart1_rts: uart1-rts { 1205 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1206 }; 1207 1208 uart1_rts_gpio: uart1-rts-gpio { 1209 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1210 }; 1211 }; 1212 1213 uart2-0 { 1214 uart2m0_xfer: uart2m0-xfer { 1215 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, 1216 <1 RK_PA1 2 &pcfg_pull_none>; 1217 }; 1218 }; 1219 1220 uart2-1 { 1221 uart2m1_xfer: uart2m1-xfer { 1222 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, 1223 <2 RK_PA1 1 &pcfg_pull_none>; 1224 }; 1225 }; 1226 1227 spi0-0 { 1228 spi0m0_clk: spi0m0-clk { 1229 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1230 }; 1231 1232 spi0m0_cs0: spi0m0-cs0 { 1233 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1234 }; 1235 1236 spi0m0_tx: spi0m0-tx { 1237 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1238 }; 1239 1240 spi0m0_rx: spi0m0-rx { 1241 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1242 }; 1243 1244 spi0m0_cs1: spi0m0-cs1 { 1245 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1246 }; 1247 }; 1248 1249 spi0-1 { 1250 spi0m1_clk: spi0m1-clk { 1251 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1252 }; 1253 1254 spi0m1_cs0: spi0m1-cs0 { 1255 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1256 }; 1257 1258 spi0m1_tx: spi0m1-tx { 1259 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1260 }; 1261 1262 spi0m1_rx: spi0m1-rx { 1263 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1264 }; 1265 1266 spi0m1_cs1: spi0m1-cs1 { 1267 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1268 }; 1269 }; 1270 1271 spi0-2 { 1272 spi0m2_clk: spi0m2-clk { 1273 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1274 }; 1275 1276 spi0m2_cs0: spi0m2-cs0 { 1277 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1278 }; 1279 1280 spi0m2_tx: spi0m2-tx { 1281 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1282 }; 1283 1284 spi0m2_rx: spi0m2-rx { 1285 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1286 }; 1287 }; 1288 1289 i2s1 { 1290 i2s1_mclk: i2s1-mclk { 1291 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1292 }; 1293 1294 i2s1_sclk: i2s1-sclk { 1295 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1296 }; 1297 1298 i2s1_lrckrx: i2s1-lrckrx { 1299 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1300 }; 1301 1302 i2s1_lrcktx: i2s1-lrcktx { 1303 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1304 }; 1305 1306 i2s1_sdi: i2s1-sdi { 1307 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1308 }; 1309 1310 i2s1_sdo: i2s1-sdo { 1311 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1312 }; 1313 1314 i2s1_sdio1: i2s1-sdio1 { 1315 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1316 }; 1317 1318 i2s1_sdio2: i2s1-sdio2 { 1319 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1320 }; 1321 1322 i2s1_sdio3: i2s1-sdio3 { 1323 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1324 }; 1325 1326 i2s1_sleep: i2s1-sleep { 1327 rockchip,pins = 1328 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1329 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1330 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1331 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1332 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1333 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1334 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1335 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1336 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1337 }; 1338 }; 1339 1340 i2s2-0 { 1341 i2s2m0_mclk: i2s2m0-mclk { 1342 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1343 }; 1344 1345 i2s2m0_sclk: i2s2m0-sclk { 1346 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1347 }; 1348 1349 i2s2m0_lrckrx: i2s2m0-lrckrx { 1350 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1351 }; 1352 1353 i2s2m0_lrcktx: i2s2m0-lrcktx { 1354 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1355 }; 1356 1357 i2s2m0_sdi: i2s2m0-sdi { 1358 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1359 }; 1360 1361 i2s2m0_sdo: i2s2m0-sdo { 1362 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1363 }; 1364 1365 i2s2m0_sleep: i2s2m0-sleep { 1366 rockchip,pins = 1367 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1368 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1369 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1370 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1371 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1372 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1373 }; 1374 }; 1375 1376 i2s2-1 { 1377 i2s2m1_mclk: i2s2m1-mclk { 1378 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1379 }; 1380 1381 i2s2m1_sclk: i2s2m1-sclk { 1382 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1383 }; 1384 1385 i2s2m1_lrckrx: i2sm1-lrckrx { 1386 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1387 }; 1388 1389 i2s2m1_lrcktx: i2s2m1-lrcktx { 1390 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1391 }; 1392 1393 i2s2m1_sdi: i2s2m1-sdi { 1394 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1395 }; 1396 1397 i2s2m1_sdo: i2s2m1-sdo { 1398 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1399 }; 1400 1401 i2s2m1_sleep: i2s2m1-sleep { 1402 rockchip,pins = 1403 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1404 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1405 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1406 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1407 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1408 }; 1409 }; 1410 1411 spdif-0 { 1412 spdifm0_tx: spdifm0-tx { 1413 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1414 }; 1415 }; 1416 1417 spdif-1 { 1418 spdifm1_tx: spdifm1-tx { 1419 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1420 }; 1421 }; 1422 1423 spdif-2 { 1424 spdifm2_tx: spdifm2-tx { 1425 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1426 }; 1427 }; 1428 1429 sdmmc0-0 { 1430 sdmmc0m0_pwren: sdmmc0m0-pwren { 1431 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1432 }; 1433 1434 sdmmc0m0_gpio: sdmmc0m0-gpio { 1435 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1436 }; 1437 }; 1438 1439 sdmmc0-1 { 1440 sdmmc0m1_pwren: sdmmc0m1-pwren { 1441 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1442 }; 1443 1444 sdmmc0m1_gpio: sdmmc0m1-gpio { 1445 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1446 }; 1447 }; 1448 1449 sdmmc0 { 1450 sdmmc0_clk: sdmmc0-clk { 1451 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1452 }; 1453 1454 sdmmc0_cmd: sdmmc0-cmd { 1455 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1456 }; 1457 1458 sdmmc0_dectn: sdmmc0-dectn { 1459 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1460 }; 1461 1462 sdmmc0_wrprt: sdmmc0-wrprt { 1463 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1464 }; 1465 1466 sdmmc0_bus1: sdmmc0-bus1 { 1467 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1468 }; 1469 1470 sdmmc0_bus4: sdmmc0-bus4 { 1471 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1472 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1473 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1474 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1475 }; 1476 1477 sdmmc0_gpio: sdmmc0-gpio { 1478 rockchip,pins = 1479 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1480 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1481 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1482 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1483 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1484 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1485 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1486 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1487 }; 1488 }; 1489 1490 sdmmc0ext { 1491 sdmmc0ext_clk: sdmmc0ext-clk { 1492 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1493 }; 1494 1495 sdmmc0ext_cmd: sdmmc0ext-cmd { 1496 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1497 }; 1498 1499 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1500 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1501 }; 1502 1503 sdmmc0ext_dectn: sdmmc0ext-dectn { 1504 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1505 }; 1506 1507 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1508 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1509 }; 1510 1511 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1512 rockchip,pins = 1513 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1514 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1515 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1516 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1517 }; 1518 1519 sdmmc0ext_gpio: sdmmc0ext-gpio { 1520 rockchip,pins = 1521 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1522 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1523 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1524 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1525 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1526 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1527 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1528 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1529 }; 1530 }; 1531 1532 sdmmc1 { 1533 sdmmc1_clk: sdmmc1-clk { 1534 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1535 }; 1536 1537 sdmmc1_cmd: sdmmc1-cmd { 1538 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1539 }; 1540 1541 sdmmc1_pwren: sdmmc1-pwren { 1542 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1543 }; 1544 1545 sdmmc1_wrprt: sdmmc1-wrprt { 1546 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1547 }; 1548 1549 sdmmc1_dectn: sdmmc1-dectn { 1550 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1551 }; 1552 1553 sdmmc1_bus1: sdmmc1-bus1 { 1554 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1555 }; 1556 1557 sdmmc1_bus4: sdmmc1-bus4 { 1558 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1559 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1560 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1561 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1562 }; 1563 1564 sdmmc1_gpio: sdmmc1-gpio { 1565 rockchip,pins = 1566 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1567 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1568 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1569 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1570 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1571 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1572 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1573 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1574 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1575 }; 1576 }; 1577 1578 emmc { 1579 emmc_clk: emmc-clk { 1580 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1581 }; 1582 1583 emmc_cmd: emmc-cmd { 1584 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1585 }; 1586 1587 emmc_pwren: emmc-pwren { 1588 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1589 }; 1590 1591 emmc_rstnout: emmc-rstnout { 1592 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1593 }; 1594 1595 emmc_bus1: emmc-bus1 { 1596 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1597 }; 1598 1599 emmc_bus4: emmc-bus4 { 1600 rockchip,pins = 1601 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1602 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1603 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1604 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1605 }; 1606 1607 emmc_bus8: emmc-bus8 { 1608 rockchip,pins = 1609 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1610 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1611 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1612 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1613 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1614 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1615 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1616 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1617 }; 1618 }; 1619 1620 pwm0 { 1621 pwm0_pin: pwm0-pin { 1622 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1623 }; 1624 }; 1625 1626 pwm1 { 1627 pwm1_pin: pwm1-pin { 1628 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1629 }; 1630 }; 1631 1632 pwm2 { 1633 pwm2_pin: pwm2-pin { 1634 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1635 }; 1636 }; 1637 1638 pwmir { 1639 pwmir_pin: pwmir-pin { 1640 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1641 }; 1642 }; 1643 1644 gmac-1 { 1645 rgmiim1_pins: rgmiim1-pins { 1646 rockchip,pins = 1647 /* mac_txclk */ 1648 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1649 /* mac_rxclk */ 1650 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1651 /* mac_mdio */ 1652 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1653 /* mac_txen */ 1654 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1655 /* mac_clk */ 1656 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1657 /* mac_rxdv */ 1658 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1659 /* mac_mdc */ 1660 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1661 /* mac_rxd1 */ 1662 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1663 /* mac_rxd0 */ 1664 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1665 /* mac_txd1 */ 1666 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1667 /* mac_txd0 */ 1668 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1669 /* mac_rxd3 */ 1670 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1671 /* mac_rxd2 */ 1672 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1673 /* mac_txd3 */ 1674 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1675 /* mac_txd2 */ 1676 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1677 1678 /* mac_txclk */ 1679 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1680 /* mac_txen */ 1681 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1682 /* mac_clk */ 1683 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1684 /* mac_txd1 */ 1685 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1686 /* mac_txd0 */ 1687 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1688 /* mac_txd3 */ 1689 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1690 /* mac_txd2 */ 1691 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1692 }; 1693 1694 rmiim1_pins: rmiim1-pins { 1695 rockchip,pins = 1696 /* mac_mdio */ 1697 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1698 /* mac_txen */ 1699 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1700 /* mac_clk */ 1701 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1702 /* mac_rxer */ 1703 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1704 /* mac_rxdv */ 1705 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1706 /* mac_mdc */ 1707 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1708 /* mac_rxd1 */ 1709 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1710 /* mac_rxd0 */ 1711 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1712 /* mac_txd1 */ 1713 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1714 /* mac_txd0 */ 1715 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1716 1717 /* mac_mdio */ 1718 <0 RK_PB3 1 &pcfg_pull_none>, 1719 /* mac_txen */ 1720 <0 RK_PB4 1 &pcfg_pull_none>, 1721 /* mac_clk */ 1722 <0 RK_PD0 1 &pcfg_pull_none>, 1723 /* mac_mdc */ 1724 <0 RK_PC3 1 &pcfg_pull_none>, 1725 /* mac_txd1 */ 1726 <0 RK_PC0 1 &pcfg_pull_none>, 1727 /* mac_txd0 */ 1728 <0 RK_PC1 1 &pcfg_pull_none>; 1729 }; 1730 }; 1731 1732 gmac2phy { 1733 fephyled_speed100: fephyled-speed100 { 1734 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 1735 }; 1736 1737 fephyled_speed10: fephyled-speed10 { 1738 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1739 }; 1740 1741 fephyled_duplex: fephyled-duplex { 1742 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1743 }; 1744 1745 fephyled_rxm0: fephyled-rxm0 { 1746 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>; 1747 }; 1748 1749 fephyled_txm0: fephyled-txm0 { 1750 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>; 1751 }; 1752 1753 fephyled_linkm0: fephyled-linkm0 { 1754 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1755 }; 1756 1757 fephyled_rxm1: fephyled-rxm1 { 1758 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1759 }; 1760 1761 fephyled_txm1: fephyled-txm1 { 1762 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1763 }; 1764 1765 fephyled_linkm1: fephyled-linkm1 { 1766 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1767 }; 1768 }; 1769 1770 tsadc_pin { 1771 tsadc_int: tsadc-int { 1772 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1773 }; 1774 tsadc_gpio: tsadc-gpio { 1775 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1776 }; 1777 }; 1778 1779 hdmi_pin { 1780 hdmi_cec: hdmi-cec { 1781 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1782 }; 1783 1784 hdmi_hpd: hdmi-hpd { 1785 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1786 }; 1787 }; 1788 1789 cif-0 { 1790 dvp_d2d9_m0:dvp-d2d9-m0 { 1791 rockchip,pins = 1792 /* cif_d0 */ 1793 <3 RK_PA4 2 &pcfg_pull_none>, 1794 /* cif_d1 */ 1795 <3 RK_PA5 2 &pcfg_pull_none>, 1796 /* cif_d2 */ 1797 <3 RK_PA6 2 &pcfg_pull_none>, 1798 /* cif_d3 */ 1799 <3 RK_PA7 2 &pcfg_pull_none>, 1800 /* cif_d4 */ 1801 <3 RK_PB0 2 &pcfg_pull_none>, 1802 /* cif_d5m0 */ 1803 <3 RK_PB1 2 &pcfg_pull_none>, 1804 /* cif_d6m0 */ 1805 <3 RK_PB2 2 &pcfg_pull_none>, 1806 /* cif_d7m0 */ 1807 <3 RK_PB3 2 &pcfg_pull_none>, 1808 /* cif_href */ 1809 <3 RK_PA1 2 &pcfg_pull_none>, 1810 /* cif_vsync */ 1811 <3 RK_PA0 2 &pcfg_pull_none>, 1812 /* cif_clkoutm0 */ 1813 <3 RK_PA3 2 &pcfg_pull_none>, 1814 /* cif_clkin */ 1815 <3 RK_PA2 2 &pcfg_pull_none>; 1816 }; 1817 }; 1818 1819 cif-1 { 1820 dvp_d2d9_m1:dvp-d2d9-m1 { 1821 rockchip,pins = 1822 /* cif_d0 */ 1823 <3 RK_PA4 2 &pcfg_pull_none>, 1824 /* cif_d1 */ 1825 <3 RK_PA5 2 &pcfg_pull_none>, 1826 /* cif_d2 */ 1827 <3 RK_PA6 2 &pcfg_pull_none>, 1828 /* cif_d3 */ 1829 <3 RK_PA7 2 &pcfg_pull_none>, 1830 /* cif_d4 */ 1831 <3 RK_PB0 2 &pcfg_pull_none>, 1832 /* cif_d5m1 */ 1833 <2 RK_PC0 4 &pcfg_pull_none>, 1834 /* cif_d6m1 */ 1835 <2 RK_PC1 4 &pcfg_pull_none>, 1836 /* cif_d7m1 */ 1837 <2 RK_PC2 4 &pcfg_pull_none>, 1838 /* cif_href */ 1839 <3 RK_PA1 2 &pcfg_pull_none>, 1840 /* cif_vsync */ 1841 <3 RK_PA0 2 &pcfg_pull_none>, 1842 /* cif_clkoutm1 */ 1843 <2 RK_PB7 4 &pcfg_pull_none>, 1844 /* cif_clkin */ 1845 <3 RK_PA2 2 &pcfg_pull_none>; 1846 }; 1847 }; 1848 }; 1849}; 1850