1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 cpu-idle-states = <&CPU_SLEEP>; 45 dynamic-power-coefficient = <120>; 46 enable-method = "psci"; 47 next-level-cache = <&l2>; 48 operating-points-v2 = <&cpu0_opp_table>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x0 0x1>; 55 clocks = <&cru ARMCLK>; 56 #cooling-cells = <2>; 57 cpu-idle-states = <&CPU_SLEEP>; 58 dynamic-power-coefficient = <120>; 59 enable-method = "psci"; 60 next-level-cache = <&l2>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0 0x2>; 68 clocks = <&cru ARMCLK>; 69 #cooling-cells = <2>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 dynamic-power-coefficient = <120>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 }; 76 77 cpu3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x0 0x3>; 81 clocks = <&cru ARMCLK>; 82 #cooling-cells = <2>; 83 cpu-idle-states = <&CPU_SLEEP>; 84 dynamic-power-coefficient = <120>; 85 enable-method = "psci"; 86 next-level-cache = <&l2>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 }; 102 103 l2: l2-cache0 { 104 compatible = "cache"; 105 cache-level = <2>; 106 cache-unified; 107 }; 108 }; 109 110 cpu0_opp_table: opp-table-0 { 111 compatible = "operating-points-v2"; 112 opp-shared; 113 114 opp-408000000 { 115 opp-hz = /bits/ 64 <408000000>; 116 opp-microvolt = <950000>; 117 clock-latency-ns = <40000>; 118 opp-suspend; 119 }; 120 opp-600000000 { 121 opp-hz = /bits/ 64 <600000000>; 122 opp-microvolt = <950000>; 123 clock-latency-ns = <40000>; 124 }; 125 opp-816000000 { 126 opp-hz = /bits/ 64 <816000000>; 127 opp-microvolt = <1000000>; 128 clock-latency-ns = <40000>; 129 }; 130 opp-1008000000 { 131 opp-hz = /bits/ 64 <1008000000>; 132 opp-microvolt = <1100000>; 133 clock-latency-ns = <40000>; 134 }; 135 opp-1200000000 { 136 opp-hz = /bits/ 64 <1200000000>; 137 opp-microvolt = <1225000>; 138 clock-latency-ns = <40000>; 139 }; 140 opp-1296000000 { 141 opp-hz = /bits/ 64 <1296000000>; 142 opp-microvolt = <1300000>; 143 clock-latency-ns = <40000>; 144 }; 145 }; 146 147 analog_sound: analog-sound { 148 compatible = "simple-audio-card"; 149 simple-audio-card,format = "i2s"; 150 simple-audio-card,mclk-fs = <256>; 151 simple-audio-card,name = "Analog"; 152 status = "disabled"; 153 154 simple-audio-card,cpu { 155 sound-dai = <&i2s1>; 156 }; 157 158 simple-audio-card,codec { 159 sound-dai = <&codec>; 160 }; 161 }; 162 163 arm-pmu { 164 compatible = "arm,cortex-a53-pmu"; 165 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 169 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 170 }; 171 172 display_subsystem: display-subsystem { 173 compatible = "rockchip,display-subsystem"; 174 ports = <&vop_out>; 175 }; 176 177 hdmi_sound: hdmi-sound { 178 compatible = "simple-audio-card"; 179 simple-audio-card,format = "i2s"; 180 simple-audio-card,mclk-fs = <128>; 181 simple-audio-card,name = "HDMI"; 182 status = "disabled"; 183 184 simple-audio-card,cpu { 185 sound-dai = <&i2s0>; 186 }; 187 188 simple-audio-card,codec { 189 sound-dai = <&hdmi>; 190 }; 191 }; 192 193 psci { 194 compatible = "arm,psci-1.0", "arm,psci-0.2"; 195 method = "smc"; 196 }; 197 198 timer { 199 compatible = "arm,armv8-timer"; 200 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 201 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 202 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 203 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 204 }; 205 206 xin24m: xin24m { 207 compatible = "fixed-clock"; 208 #clock-cells = <0>; 209 clock-frequency = <24000000>; 210 clock-output-names = "xin24m"; 211 }; 212 213 i2s0: i2s@ff000000 { 214 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 215 reg = <0x0 0xff000000 0x0 0x1000>; 216 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 218 clock-names = "i2s_clk", "i2s_hclk"; 219 dmas = <&dmac 11>, <&dmac 12>; 220 dma-names = "tx", "rx"; 221 #sound-dai-cells = <0>; 222 status = "disabled"; 223 }; 224 225 i2s1: i2s@ff010000 { 226 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 227 reg = <0x0 0xff010000 0x0 0x1000>; 228 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 230 clock-names = "i2s_clk", "i2s_hclk"; 231 dmas = <&dmac 14>, <&dmac 15>; 232 dma-names = "tx", "rx"; 233 #sound-dai-cells = <0>; 234 status = "disabled"; 235 }; 236 237 i2s2: i2s@ff020000 { 238 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 239 reg = <0x0 0xff020000 0x0 0x1000>; 240 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 242 clock-names = "i2s_clk", "i2s_hclk"; 243 dmas = <&dmac 0>, <&dmac 1>; 244 dma-names = "tx", "rx"; 245 #sound-dai-cells = <0>; 246 status = "disabled"; 247 }; 248 249 spdif: spdif@ff030000 { 250 compatible = "rockchip,rk3328-spdif"; 251 reg = <0x0 0xff030000 0x0 0x1000>; 252 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 254 clock-names = "mclk", "hclk"; 255 dmas = <&dmac 10>; 256 dma-names = "tx"; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&spdifm2_tx>; 259 #sound-dai-cells = <0>; 260 status = "disabled"; 261 }; 262 263 pdm: pdm@ff040000 { 264 compatible = "rockchip,pdm"; 265 reg = <0x0 0xff040000 0x0 0x1000>; 266 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 267 clock-names = "pdm_clk", "pdm_hclk"; 268 dmas = <&dmac 16>; 269 dma-names = "rx"; 270 pinctrl-names = "default", "sleep"; 271 pinctrl-0 = <&pdmm0_clk 272 &pdmm0_sdi0 273 &pdmm0_sdi1 274 &pdmm0_sdi2 275 &pdmm0_sdi3>; 276 pinctrl-1 = <&pdmm0_clk_sleep 277 &pdmm0_sdi0_sleep 278 &pdmm0_sdi1_sleep 279 &pdmm0_sdi2_sleep 280 &pdmm0_sdi3_sleep>; 281 status = "disabled"; 282 }; 283 284 grf: syscon@ff100000 { 285 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 286 reg = <0x0 0xff100000 0x0 0x1000>; 287 288 io_domains: io-domains { 289 compatible = "rockchip,rk3328-io-voltage-domain"; 290 status = "disabled"; 291 }; 292 293 grf_gpio: gpio { 294 compatible = "rockchip,rk3328-grf-gpio"; 295 gpio-controller; 296 #gpio-cells = <2>; 297 }; 298 299 power: power-controller { 300 compatible = "rockchip,rk3328-power-controller"; 301 #power-domain-cells = <1>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 power-domain@RK3328_PD_HEVC { 306 reg = <RK3328_PD_HEVC>; 307 #power-domain-cells = <0>; 308 }; 309 power-domain@RK3328_PD_VIDEO { 310 reg = <RK3328_PD_VIDEO>; 311 clocks = <&cru ACLK_RKVDEC>, 312 <&cru HCLK_RKVDEC>, 313 <&cru SCLK_VDEC_CABAC>, 314 <&cru SCLK_VDEC_CORE>; 315 #power-domain-cells = <0>; 316 }; 317 power-domain@RK3328_PD_VPU { 318 reg = <RK3328_PD_VPU>; 319 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 320 #power-domain-cells = <0>; 321 }; 322 }; 323 324 reboot-mode { 325 compatible = "syscon-reboot-mode"; 326 offset = <0x5c8>; 327 mode-normal = <BOOT_NORMAL>; 328 mode-recovery = <BOOT_RECOVERY>; 329 mode-bootloader = <BOOT_FASTBOOT>; 330 mode-loader = <BOOT_BL_DOWNLOAD>; 331 }; 332 }; 333 334 uart0: serial@ff110000 { 335 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 336 reg = <0x0 0xff110000 0x0 0x100>; 337 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 339 clock-names = "baudclk", "apb_pclk"; 340 dmas = <&dmac 2>, <&dmac 3>; 341 dma-names = "tx", "rx"; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 344 reg-io-width = <4>; 345 reg-shift = <2>; 346 status = "disabled"; 347 }; 348 349 uart1: serial@ff120000 { 350 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 351 reg = <0x0 0xff120000 0x0 0x100>; 352 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 354 clock-names = "baudclk", "apb_pclk"; 355 dmas = <&dmac 4>, <&dmac 5>; 356 dma-names = "tx", "rx"; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 359 reg-io-width = <4>; 360 reg-shift = <2>; 361 status = "disabled"; 362 }; 363 364 uart2: serial@ff130000 { 365 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 366 reg = <0x0 0xff130000 0x0 0x100>; 367 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 369 clock-names = "baudclk", "apb_pclk"; 370 dmas = <&dmac 6>, <&dmac 7>; 371 dma-names = "tx", "rx"; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&uart2m1_xfer>; 374 reg-io-width = <4>; 375 reg-shift = <2>; 376 status = "disabled"; 377 }; 378 379 i2c0: i2c@ff150000 { 380 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 381 reg = <0x0 0xff150000 0x0 0x1000>; 382 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 386 clock-names = "i2c", "pclk"; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&i2c0_xfer>; 389 status = "disabled"; 390 }; 391 392 i2c1: i2c@ff160000 { 393 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 394 reg = <0x0 0xff160000 0x0 0x1000>; 395 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 399 clock-names = "i2c", "pclk"; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&i2c1_xfer>; 402 status = "disabled"; 403 }; 404 405 i2c2: i2c@ff170000 { 406 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 407 reg = <0x0 0xff170000 0x0 0x1000>; 408 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 412 clock-names = "i2c", "pclk"; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&i2c2_xfer>; 415 status = "disabled"; 416 }; 417 418 i2c3: i2c@ff180000 { 419 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 420 reg = <0x0 0xff180000 0x0 0x1000>; 421 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 425 clock-names = "i2c", "pclk"; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&i2c3_xfer>; 428 status = "disabled"; 429 }; 430 431 spi0: spi@ff190000 { 432 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 433 reg = <0x0 0xff190000 0x0 0x1000>; 434 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 438 clock-names = "spiclk", "apb_pclk"; 439 dmas = <&dmac 8>, <&dmac 9>; 440 dma-names = "tx", "rx"; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 443 status = "disabled"; 444 }; 445 446 wdt: watchdog@ff1a0000 { 447 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 448 reg = <0x0 0xff1a0000 0x0 0x100>; 449 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&cru PCLK_WDT>; 451 }; 452 453 pwm0: pwm@ff1b0000 { 454 compatible = "rockchip,rk3328-pwm"; 455 reg = <0x0 0xff1b0000 0x0 0x10>; 456 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 457 clock-names = "pwm", "pclk"; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&pwm0_pin>; 460 #pwm-cells = <3>; 461 status = "disabled"; 462 }; 463 464 pwm1: pwm@ff1b0010 { 465 compatible = "rockchip,rk3328-pwm"; 466 reg = <0x0 0xff1b0010 0x0 0x10>; 467 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 468 clock-names = "pwm", "pclk"; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&pwm1_pin>; 471 #pwm-cells = <3>; 472 status = "disabled"; 473 }; 474 475 pwm2: pwm@ff1b0020 { 476 compatible = "rockchip,rk3328-pwm"; 477 reg = <0x0 0xff1b0020 0x0 0x10>; 478 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 479 clock-names = "pwm", "pclk"; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pwm2_pin>; 482 #pwm-cells = <3>; 483 status = "disabled"; 484 }; 485 486 pwm3: pwm@ff1b0030 { 487 compatible = "rockchip,rk3328-pwm"; 488 reg = <0x0 0xff1b0030 0x0 0x10>; 489 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 491 clock-names = "pwm", "pclk"; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&pwmir_pin>; 494 #pwm-cells = <3>; 495 status = "disabled"; 496 }; 497 498 dmac: dma-controller@ff1f0000 { 499 compatible = "arm,pl330", "arm,primecell"; 500 reg = <0x0 0xff1f0000 0x0 0x4000>; 501 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 503 arm,pl330-periph-burst; 504 clocks = <&cru ACLK_DMAC>; 505 clock-names = "apb_pclk"; 506 #dma-cells = <1>; 507 }; 508 509 thermal-zones { 510 soc_thermal: soc-thermal { 511 polling-delay-passive = <20>; 512 polling-delay = <1000>; 513 sustainable-power = <1000>; 514 515 thermal-sensors = <&tsadc 0>; 516 517 trips { 518 threshold: trip-point0 { 519 temperature = <70000>; 520 hysteresis = <2000>; 521 type = "passive"; 522 }; 523 target: trip-point1 { 524 temperature = <85000>; 525 hysteresis = <2000>; 526 type = "passive"; 527 }; 528 soc_crit: soc-crit { 529 temperature = <95000>; 530 hysteresis = <2000>; 531 type = "critical"; 532 }; 533 }; 534 535 cooling-maps { 536 map0 { 537 trip = <&target>; 538 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 539 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 540 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 541 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 542 contribution = <4096>; 543 }; 544 }; 545 }; 546 547 }; 548 549 tsadc: tsadc@ff250000 { 550 compatible = "rockchip,rk3328-tsadc"; 551 reg = <0x0 0xff250000 0x0 0x100>; 552 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 553 assigned-clocks = <&cru SCLK_TSADC>; 554 assigned-clock-rates = <50000>; 555 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 556 clock-names = "tsadc", "apb_pclk"; 557 pinctrl-names = "init", "default", "sleep"; 558 pinctrl-0 = <&otp_pin>; 559 pinctrl-1 = <&otp_out>; 560 pinctrl-2 = <&otp_pin>; 561 resets = <&cru SRST_TSADC>; 562 reset-names = "tsadc-apb"; 563 rockchip,grf = <&grf>; 564 rockchip,hw-tshut-temp = <100000>; 565 #thermal-sensor-cells = <1>; 566 status = "disabled"; 567 }; 568 569 efuse: efuse@ff260000 { 570 compatible = "rockchip,rk3328-efuse"; 571 reg = <0x0 0xff260000 0x0 0x50>; 572 #address-cells = <1>; 573 #size-cells = <1>; 574 clocks = <&cru SCLK_EFUSE>; 575 clock-names = "pclk_efuse"; 576 rockchip,efuse-size = <0x20>; 577 578 /* Data cells */ 579 efuse_id: id@7 { 580 reg = <0x07 0x10>; 581 }; 582 cpu_leakage: cpu-leakage@17 { 583 reg = <0x17 0x1>; 584 }; 585 logic_leakage: logic-leakage@19 { 586 reg = <0x19 0x1>; 587 }; 588 efuse_cpu_version: cpu-version@1a { 589 reg = <0x1a 0x1>; 590 bits = <3 3>; 591 }; 592 }; 593 594 saradc: adc@ff280000 { 595 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 596 reg = <0x0 0xff280000 0x0 0x100>; 597 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 598 #io-channel-cells = <1>; 599 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 600 clock-names = "saradc", "apb_pclk"; 601 resets = <&cru SRST_SARADC_P>; 602 reset-names = "saradc-apb"; 603 status = "disabled"; 604 }; 605 606 gpu: gpu@ff300000 { 607 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 608 reg = <0x0 0xff300000 0x0 0x30000>; 609 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 616 interrupt-names = "gp", 617 "gpmmu", 618 "pp", 619 "pp0", 620 "ppmmu0", 621 "pp1", 622 "ppmmu1"; 623 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 624 clock-names = "bus", "core"; 625 resets = <&cru SRST_GPU_A>; 626 }; 627 628 h265e_mmu: iommu@ff330200 { 629 compatible = "rockchip,iommu"; 630 reg = <0x0 0xff330200 0 0x100>; 631 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 633 clock-names = "aclk", "iface"; 634 #iommu-cells = <0>; 635 status = "disabled"; 636 }; 637 638 vepu_mmu: iommu@ff340800 { 639 compatible = "rockchip,iommu"; 640 reg = <0x0 0xff340800 0x0 0x40>; 641 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 643 clock-names = "aclk", "iface"; 644 #iommu-cells = <0>; 645 status = "disabled"; 646 }; 647 648 vpu: video-codec@ff350000 { 649 compatible = "rockchip,rk3328-vpu"; 650 reg = <0x0 0xff350000 0x0 0x800>; 651 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 652 interrupt-names = "vdpu"; 653 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 654 clock-names = "aclk", "hclk"; 655 iommus = <&vpu_mmu>; 656 power-domains = <&power RK3328_PD_VPU>; 657 }; 658 659 vpu_mmu: iommu@ff350800 { 660 compatible = "rockchip,iommu"; 661 reg = <0x0 0xff350800 0x0 0x40>; 662 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 664 clock-names = "aclk", "iface"; 665 #iommu-cells = <0>; 666 power-domains = <&power RK3328_PD_VPU>; 667 }; 668 669 vdec: video-codec@ff360000 { 670 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; 671 reg = <0x0 0xff360000 0x0 0x480>; 672 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 674 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 675 clock-names = "axi", "ahb", "cabac", "core"; 676 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, 677 <&cru SCLK_VDEC_CORE>; 678 assigned-clock-rates = <400000000>, <400000000>, <300000000>; 679 iommus = <&vdec_mmu>; 680 power-domains = <&power RK3328_PD_VIDEO>; 681 }; 682 683 vdec_mmu: iommu@ff360480 { 684 compatible = "rockchip,iommu"; 685 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 686 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 688 clock-names = "aclk", "iface"; 689 #iommu-cells = <0>; 690 power-domains = <&power RK3328_PD_VIDEO>; 691 }; 692 693 vop: vop@ff370000 { 694 compatible = "rockchip,rk3328-vop"; 695 reg = <0x0 0xff370000 0x0 0x3efc>; 696 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 698 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 699 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 700 reset-names = "axi", "ahb", "dclk"; 701 iommus = <&vop_mmu>; 702 status = "disabled"; 703 704 vop_out: port { 705 #address-cells = <1>; 706 #size-cells = <0>; 707 708 vop_out_hdmi: endpoint@0 { 709 reg = <0>; 710 remote-endpoint = <&hdmi_in_vop>; 711 }; 712 }; 713 }; 714 715 vop_mmu: iommu@ff373f00 { 716 compatible = "rockchip,iommu"; 717 reg = <0x0 0xff373f00 0x0 0x100>; 718 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 720 clock-names = "aclk", "iface"; 721 #iommu-cells = <0>; 722 status = "disabled"; 723 }; 724 725 hdmi: hdmi@ff3c0000 { 726 compatible = "rockchip,rk3328-dw-hdmi"; 727 reg = <0x0 0xff3c0000 0x0 0x20000>; 728 reg-io-width = <4>; 729 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&cru PCLK_HDMI>, 732 <&cru SCLK_HDMI_SFC>, 733 <&cru SCLK_RTC32K>; 734 clock-names = "iahb", 735 "isfr", 736 "cec"; 737 phys = <&hdmiphy>; 738 phy-names = "hdmi"; 739 pinctrl-names = "default"; 740 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 741 rockchip,grf = <&grf>; 742 #sound-dai-cells = <0>; 743 status = "disabled"; 744 745 ports { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 749 hdmi_in: port@0 { 750 reg = <0>; 751 752 hdmi_in_vop: endpoint { 753 remote-endpoint = <&vop_out_hdmi>; 754 }; 755 }; 756 757 hdmi_out: port@1 { 758 reg = <1>; 759 }; 760 }; 761 }; 762 763 codec: codec@ff410000 { 764 compatible = "rockchip,rk3328-codec"; 765 reg = <0x0 0xff410000 0x0 0x1000>; 766 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 767 clock-names = "pclk", "mclk"; 768 rockchip,grf = <&grf>; 769 #sound-dai-cells = <0>; 770 status = "disabled"; 771 }; 772 773 hdmiphy: phy@ff430000 { 774 compatible = "rockchip,rk3328-hdmi-phy"; 775 reg = <0x0 0xff430000 0x0 0x10000>; 776 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 778 clock-names = "sysclk", "refoclk", "refpclk"; 779 clock-output-names = "hdmi_phy"; 780 #clock-cells = <0>; 781 nvmem-cells = <&efuse_cpu_version>; 782 nvmem-cell-names = "cpu-version"; 783 #phy-cells = <0>; 784 status = "disabled"; 785 }; 786 787 cru: clock-controller@ff440000 { 788 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 789 reg = <0x0 0xff440000 0x0 0x1000>; 790 rockchip,grf = <&grf>; 791 #clock-cells = <1>; 792 #reset-cells = <1>; 793 assigned-clocks = 794 /* 795 * CPLL should run at 1200, but that is to high for 796 * the initial dividers of most of its children. 797 * We need set cpll child clk div first, 798 * and then set the cpll frequency. 799 */ 800 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 801 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 802 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 803 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 804 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 805 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 806 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 807 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 808 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 809 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 810 <&cru SCLK_WIFI>, <&cru ARMCLK>, 811 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 812 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 813 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 814 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 815 <&cru SCLK_RTC32K>; 816 assigned-clock-parents = 817 <&cru HDMIPHY>, <&cru PLL_APLL>, 818 <&cru PLL_GPLL>, <&xin24m>, 819 <&xin24m>, <&xin24m>; 820 assigned-clock-rates = 821 <0>, <61440000>, 822 <0>, <24000000>, 823 <24000000>, <24000000>, 824 <15000000>, <15000000>, 825 <300000000>, <100000000>, 826 <400000000>, <100000000>, 827 <50000000>, <100000000>, 828 <100000000>, <100000000>, 829 <50000000>, <50000000>, 830 <50000000>, <50000000>, 831 <24000000>, <600000000>, 832 <491520000>, <1200000000>, 833 <150000000>, <75000000>, 834 <75000000>, <150000000>, 835 <75000000>, <75000000>, 836 <32768>; 837 }; 838 839 usb2phy_grf: syscon@ff450000 { 840 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 841 "simple-mfd"; 842 reg = <0x0 0xff450000 0x0 0x10000>; 843 #address-cells = <1>; 844 #size-cells = <1>; 845 846 u2phy: usb2phy@100 { 847 compatible = "rockchip,rk3328-usb2phy"; 848 reg = <0x100 0x10>; 849 clocks = <&xin24m>; 850 clock-names = "phyclk"; 851 clock-output-names = "usb480m_phy"; 852 #clock-cells = <0>; 853 assigned-clocks = <&cru USB480M>; 854 assigned-clock-parents = <&u2phy>; 855 status = "disabled"; 856 857 u2phy_otg: otg-port { 858 #phy-cells = <0>; 859 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 862 interrupt-names = "otg-bvalid", "otg-id", 863 "linestate"; 864 status = "disabled"; 865 }; 866 867 u2phy_host: host-port { 868 #phy-cells = <0>; 869 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 870 interrupt-names = "linestate"; 871 status = "disabled"; 872 }; 873 }; 874 }; 875 876 sdmmc: mmc@ff500000 { 877 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 878 reg = <0x0 0xff500000 0x0 0x4000>; 879 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 881 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 882 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 883 fifo-depth = <0x100>; 884 max-frequency = <150000000>; 885 status = "disabled"; 886 }; 887 888 sdio: mmc@ff510000 { 889 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 890 reg = <0x0 0xff510000 0x0 0x4000>; 891 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 893 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 894 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 895 fifo-depth = <0x100>; 896 max-frequency = <150000000>; 897 status = "disabled"; 898 }; 899 900 emmc: mmc@ff520000 { 901 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 902 reg = <0x0 0xff520000 0x0 0x4000>; 903 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 905 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 906 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 907 fifo-depth = <0x100>; 908 max-frequency = <150000000>; 909 status = "disabled"; 910 }; 911 912 gmac2io: ethernet@ff540000 { 913 compatible = "rockchip,rk3328-gmac"; 914 reg = <0x0 0xff540000 0x0 0x10000>; 915 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 916 interrupt-names = "macirq"; 917 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 918 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 919 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 920 <&cru PCLK_MAC2IO>; 921 clock-names = "stmmaceth", "mac_clk_rx", 922 "mac_clk_tx", "clk_mac_ref", 923 "clk_mac_refout", "aclk_mac", 924 "pclk_mac"; 925 resets = <&cru SRST_GMAC2IO_A>; 926 reset-names = "stmmaceth"; 927 rockchip,grf = <&grf>; 928 snps,txpbl = <0x4>; 929 status = "disabled"; 930 }; 931 932 gmac2phy: ethernet@ff550000 { 933 compatible = "rockchip,rk3328-gmac"; 934 reg = <0x0 0xff550000 0x0 0x10000>; 935 rockchip,grf = <&grf>; 936 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 937 interrupt-names = "macirq"; 938 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 939 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 940 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 941 <&cru SCLK_MAC2PHY_OUT>; 942 clock-names = "stmmaceth", "mac_clk_rx", 943 "mac_clk_tx", "clk_mac_ref", 944 "aclk_mac", "pclk_mac", 945 "clk_macphy"; 946 resets = <&cru SRST_GMAC2PHY_A>; 947 reset-names = "stmmaceth"; 948 phy-mode = "rmii"; 949 phy-handle = <&phy>; 950 snps,txpbl = <0x4>; 951 clock_in_out = "output"; 952 status = "disabled"; 953 954 mdio { 955 compatible = "snps,dwmac-mdio"; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 959 phy: ethernet-phy@0 { 960 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 961 reg = <0>; 962 clocks = <&cru SCLK_MAC2PHY_OUT>; 963 resets = <&cru SRST_MACPHY>; 964 pinctrl-names = "default"; 965 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 966 phy-is-integrated; 967 }; 968 }; 969 }; 970 971 usb20_otg: usb@ff580000 { 972 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 973 "snps,dwc2"; 974 reg = <0x0 0xff580000 0x0 0x40000>; 975 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&cru HCLK_OTG>; 977 clock-names = "otg"; 978 dr_mode = "otg"; 979 g-np-tx-fifo-size = <16>; 980 g-rx-fifo-size = <280>; 981 g-tx-fifo-size = <256 128 128 64 32 16>; 982 phys = <&u2phy_otg>; 983 phy-names = "usb2-phy"; 984 status = "disabled"; 985 }; 986 987 usb_host0_ehci: usb@ff5c0000 { 988 compatible = "generic-ehci"; 989 reg = <0x0 0xff5c0000 0x0 0x10000>; 990 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&cru HCLK_HOST0>, <&u2phy>; 992 phys = <&u2phy_host>; 993 phy-names = "usb"; 994 status = "disabled"; 995 }; 996 997 usb_host0_ohci: usb@ff5d0000 { 998 compatible = "generic-ohci"; 999 reg = <0x0 0xff5d0000 0x0 0x10000>; 1000 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&cru HCLK_HOST0>, <&u2phy>; 1002 phys = <&u2phy_host>; 1003 phy-names = "usb"; 1004 status = "disabled"; 1005 }; 1006 1007 usbdrd3: usb@ff600000 { 1008 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 1009 reg = <0x0 0xff600000 0x0 0x100000>; 1010 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 1012 <&cru ACLK_USB3OTG>; 1013 clock-names = "ref_clk", "suspend_clk", 1014 "bus_clk"; 1015 dr_mode = "otg"; 1016 phy_type = "utmi_wide"; 1017 snps,dis-del-phy-power-chg-quirk; 1018 snps,dis_enblslpm_quirk; 1019 snps,dis-tx-ipgap-linecheck-quirk; 1020 snps,dis-u2-freeclk-exists-quirk; 1021 snps,dis_u2_susphy_quirk; 1022 snps,dis_u3_susphy_quirk; 1023 status = "disabled"; 1024 }; 1025 1026 gic: interrupt-controller@ff811000 { 1027 compatible = "arm,gic-400"; 1028 #interrupt-cells = <3>; 1029 #address-cells = <0>; 1030 interrupt-controller; 1031 reg = <0x0 0xff811000 0 0x1000>, 1032 <0x0 0xff812000 0 0x2000>, 1033 <0x0 0xff814000 0 0x2000>, 1034 <0x0 0xff816000 0 0x2000>; 1035 interrupts = <GIC_PPI 9 1036 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1037 }; 1038 1039 crypto: crypto@ff060000 { 1040 compatible = "rockchip,rk3328-crypto"; 1041 reg = <0x0 0xff060000 0x0 0x4000>; 1042 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1043 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, 1044 <&cru SCLK_CRYPTO>; 1045 clock-names = "hclk_master", "hclk_slave", "sclk"; 1046 resets = <&cru SRST_CRYPTO>; 1047 reset-names = "crypto-rst"; 1048 }; 1049 1050 pinctrl: pinctrl { 1051 compatible = "rockchip,rk3328-pinctrl"; 1052 rockchip,grf = <&grf>; 1053 #address-cells = <2>; 1054 #size-cells = <2>; 1055 ranges; 1056 1057 gpio0: gpio@ff210000 { 1058 compatible = "rockchip,gpio-bank"; 1059 reg = <0x0 0xff210000 0x0 0x100>; 1060 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1061 clocks = <&cru PCLK_GPIO0>; 1062 1063 gpio-controller; 1064 #gpio-cells = <2>; 1065 1066 interrupt-controller; 1067 #interrupt-cells = <2>; 1068 }; 1069 1070 gpio1: gpio@ff220000 { 1071 compatible = "rockchip,gpio-bank"; 1072 reg = <0x0 0xff220000 0x0 0x100>; 1073 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&cru PCLK_GPIO1>; 1075 1076 gpio-controller; 1077 #gpio-cells = <2>; 1078 1079 interrupt-controller; 1080 #interrupt-cells = <2>; 1081 }; 1082 1083 gpio2: gpio@ff230000 { 1084 compatible = "rockchip,gpio-bank"; 1085 reg = <0x0 0xff230000 0x0 0x100>; 1086 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1087 clocks = <&cru PCLK_GPIO2>; 1088 1089 gpio-controller; 1090 #gpio-cells = <2>; 1091 1092 interrupt-controller; 1093 #interrupt-cells = <2>; 1094 }; 1095 1096 gpio3: gpio@ff240000 { 1097 compatible = "rockchip,gpio-bank"; 1098 reg = <0x0 0xff240000 0x0 0x100>; 1099 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&cru PCLK_GPIO3>; 1101 1102 gpio-controller; 1103 #gpio-cells = <2>; 1104 1105 interrupt-controller; 1106 #interrupt-cells = <2>; 1107 }; 1108 1109 pcfg_pull_up: pcfg-pull-up { 1110 bias-pull-up; 1111 }; 1112 1113 pcfg_pull_down: pcfg-pull-down { 1114 bias-pull-down; 1115 }; 1116 1117 pcfg_pull_none: pcfg-pull-none { 1118 bias-disable; 1119 }; 1120 1121 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1122 bias-disable; 1123 drive-strength = <2>; 1124 }; 1125 1126 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1127 bias-pull-up; 1128 drive-strength = <2>; 1129 }; 1130 1131 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1132 bias-pull-up; 1133 drive-strength = <4>; 1134 }; 1135 1136 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1137 bias-disable; 1138 drive-strength = <4>; 1139 }; 1140 1141 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1142 bias-pull-down; 1143 drive-strength = <4>; 1144 }; 1145 1146 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1147 bias-disable; 1148 drive-strength = <8>; 1149 }; 1150 1151 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1152 bias-pull-up; 1153 drive-strength = <8>; 1154 }; 1155 1156 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1157 bias-disable; 1158 drive-strength = <12>; 1159 }; 1160 1161 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1162 bias-pull-up; 1163 drive-strength = <12>; 1164 }; 1165 1166 pcfg_output_high: pcfg-output-high { 1167 output-high; 1168 }; 1169 1170 pcfg_output_low: pcfg-output-low { 1171 output-low; 1172 }; 1173 1174 pcfg_input_high: pcfg-input-high { 1175 bias-pull-up; 1176 input-enable; 1177 }; 1178 1179 pcfg_input: pcfg-input { 1180 input-enable; 1181 }; 1182 1183 i2c0 { 1184 i2c0_xfer: i2c0-xfer { 1185 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1186 <2 RK_PD1 1 &pcfg_pull_none>; 1187 }; 1188 }; 1189 1190 i2c1 { 1191 i2c1_xfer: i2c1-xfer { 1192 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1193 <2 RK_PA5 2 &pcfg_pull_none>; 1194 }; 1195 }; 1196 1197 i2c2 { 1198 i2c2_xfer: i2c2-xfer { 1199 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1200 <2 RK_PB6 1 &pcfg_pull_none>; 1201 }; 1202 }; 1203 1204 i2c3 { 1205 i2c3_xfer: i2c3-xfer { 1206 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1207 <0 RK_PA6 2 &pcfg_pull_none>; 1208 }; 1209 i2c3_pins: i2c3-pins { 1210 rockchip,pins = 1211 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1212 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1213 }; 1214 }; 1215 1216 hdmi_i2c { 1217 hdmii2c_xfer: hdmii2c-xfer { 1218 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1219 <0 RK_PA6 1 &pcfg_pull_none>; 1220 }; 1221 }; 1222 1223 pdm-0 { 1224 pdmm0_clk: pdmm0-clk { 1225 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1226 }; 1227 1228 pdmm0_fsync: pdmm0-fsync { 1229 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1230 }; 1231 1232 pdmm0_sdi0: pdmm0-sdi0 { 1233 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1234 }; 1235 1236 pdmm0_sdi1: pdmm0-sdi1 { 1237 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1238 }; 1239 1240 pdmm0_sdi2: pdmm0-sdi2 { 1241 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1242 }; 1243 1244 pdmm0_sdi3: pdmm0-sdi3 { 1245 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1246 }; 1247 1248 pdmm0_clk_sleep: pdmm0-clk-sleep { 1249 rockchip,pins = 1250 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1251 }; 1252 1253 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1254 rockchip,pins = 1255 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1256 }; 1257 1258 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1259 rockchip,pins = 1260 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1261 }; 1262 1263 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1264 rockchip,pins = 1265 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1266 }; 1267 1268 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1269 rockchip,pins = 1270 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1271 }; 1272 1273 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1274 rockchip,pins = 1275 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1276 }; 1277 }; 1278 1279 tsadc { 1280 otp_pin: otp-pin { 1281 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1282 }; 1283 1284 otp_out: otp-out { 1285 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1286 }; 1287 }; 1288 1289 uart0 { 1290 uart0_xfer: uart0-xfer { 1291 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1292 <1 RK_PB0 1 &pcfg_pull_up>; 1293 }; 1294 1295 uart0_cts: uart0-cts { 1296 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1297 }; 1298 1299 uart0_rts: uart0-rts { 1300 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1301 }; 1302 1303 uart0_rts_pin: uart0-rts-pin { 1304 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1305 }; 1306 }; 1307 1308 uart1 { 1309 uart1_xfer: uart1-xfer { 1310 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1311 <3 RK_PA6 4 &pcfg_pull_up>; 1312 }; 1313 1314 uart1_cts: uart1-cts { 1315 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1316 }; 1317 1318 uart1_rts: uart1-rts { 1319 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1320 }; 1321 1322 uart1_rts_pin: uart1-rts-pin { 1323 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1324 }; 1325 }; 1326 1327 uart2-0 { 1328 uart2m0_xfer: uart2m0-xfer { 1329 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1330 <1 RK_PA1 2 &pcfg_pull_up>; 1331 }; 1332 }; 1333 1334 uart2-1 { 1335 uart2m1_xfer: uart2m1-xfer { 1336 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1337 <2 RK_PA1 1 &pcfg_pull_up>; 1338 }; 1339 }; 1340 1341 spi0-0 { 1342 spi0m0_clk: spi0m0-clk { 1343 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1344 }; 1345 1346 spi0m0_cs0: spi0m0-cs0 { 1347 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1348 }; 1349 1350 spi0m0_tx: spi0m0-tx { 1351 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1352 }; 1353 1354 spi0m0_rx: spi0m0-rx { 1355 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1356 }; 1357 1358 spi0m0_cs1: spi0m0-cs1 { 1359 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1360 }; 1361 }; 1362 1363 spi0-1 { 1364 spi0m1_clk: spi0m1-clk { 1365 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1366 }; 1367 1368 spi0m1_cs0: spi0m1-cs0 { 1369 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1370 }; 1371 1372 spi0m1_tx: spi0m1-tx { 1373 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1374 }; 1375 1376 spi0m1_rx: spi0m1-rx { 1377 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1378 }; 1379 1380 spi0m1_cs1: spi0m1-cs1 { 1381 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1382 }; 1383 }; 1384 1385 spi0-2 { 1386 spi0m2_clk: spi0m2-clk { 1387 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1388 }; 1389 1390 spi0m2_cs0: spi0m2-cs0 { 1391 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1392 }; 1393 1394 spi0m2_tx: spi0m2-tx { 1395 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1396 }; 1397 1398 spi0m2_rx: spi0m2-rx { 1399 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1400 }; 1401 }; 1402 1403 i2s1 { 1404 i2s1_mclk: i2s1-mclk { 1405 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1406 }; 1407 1408 i2s1_sclk: i2s1-sclk { 1409 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1410 }; 1411 1412 i2s1_lrckrx: i2s1-lrckrx { 1413 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1414 }; 1415 1416 i2s1_lrcktx: i2s1-lrcktx { 1417 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1418 }; 1419 1420 i2s1_sdi: i2s1-sdi { 1421 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1422 }; 1423 1424 i2s1_sdo: i2s1-sdo { 1425 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1426 }; 1427 1428 i2s1_sdio1: i2s1-sdio1 { 1429 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1430 }; 1431 1432 i2s1_sdio2: i2s1-sdio2 { 1433 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1434 }; 1435 1436 i2s1_sdio3: i2s1-sdio3 { 1437 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1438 }; 1439 1440 i2s1_sleep: i2s1-sleep { 1441 rockchip,pins = 1442 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1443 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1444 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1445 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1446 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1447 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1448 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1449 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1450 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1451 }; 1452 }; 1453 1454 i2s2-0 { 1455 i2s2m0_mclk: i2s2m0-mclk { 1456 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1457 }; 1458 1459 i2s2m0_sclk: i2s2m0-sclk { 1460 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1461 }; 1462 1463 i2s2m0_lrckrx: i2s2m0-lrckrx { 1464 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1465 }; 1466 1467 i2s2m0_lrcktx: i2s2m0-lrcktx { 1468 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1469 }; 1470 1471 i2s2m0_sdi: i2s2m0-sdi { 1472 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1473 }; 1474 1475 i2s2m0_sdo: i2s2m0-sdo { 1476 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1477 }; 1478 1479 i2s2m0_sleep: i2s2m0-sleep { 1480 rockchip,pins = 1481 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1482 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1483 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1484 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1485 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1486 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1487 }; 1488 }; 1489 1490 i2s2-1 { 1491 i2s2m1_mclk: i2s2m1-mclk { 1492 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1493 }; 1494 1495 i2s2m1_sclk: i2s2m1-sclk { 1496 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1497 }; 1498 1499 i2s2m1_lrckrx: i2sm1-lrckrx { 1500 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1501 }; 1502 1503 i2s2m1_lrcktx: i2s2m1-lrcktx { 1504 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1505 }; 1506 1507 i2s2m1_sdi: i2s2m1-sdi { 1508 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1509 }; 1510 1511 i2s2m1_sdo: i2s2m1-sdo { 1512 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1513 }; 1514 1515 i2s2m1_sleep: i2s2m1-sleep { 1516 rockchip,pins = 1517 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1518 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1519 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1520 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1521 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1522 }; 1523 }; 1524 1525 spdif-0 { 1526 spdifm0_tx: spdifm0-tx { 1527 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1528 }; 1529 }; 1530 1531 spdif-1 { 1532 spdifm1_tx: spdifm1-tx { 1533 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1534 }; 1535 }; 1536 1537 spdif-2 { 1538 spdifm2_tx: spdifm2-tx { 1539 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1540 }; 1541 }; 1542 1543 sdmmc0-0 { 1544 sdmmc0m0_pwren: sdmmc0m0-pwren { 1545 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1546 }; 1547 1548 sdmmc0m0_pin: sdmmc0m0-pin { 1549 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1550 }; 1551 }; 1552 1553 sdmmc0-1 { 1554 sdmmc0m1_pwren: sdmmc0m1-pwren { 1555 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1556 }; 1557 1558 sdmmc0m1_pin: sdmmc0m1-pin { 1559 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1560 }; 1561 }; 1562 1563 sdmmc0 { 1564 sdmmc0_clk: sdmmc0-clk { 1565 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1566 }; 1567 1568 sdmmc0_cmd: sdmmc0-cmd { 1569 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1570 }; 1571 1572 sdmmc0_dectn: sdmmc0-dectn { 1573 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1574 }; 1575 1576 sdmmc0_wrprt: sdmmc0-wrprt { 1577 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1578 }; 1579 1580 sdmmc0_bus1: sdmmc0-bus1 { 1581 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1582 }; 1583 1584 sdmmc0_bus4: sdmmc0-bus4 { 1585 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1586 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1587 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1588 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1589 }; 1590 1591 sdmmc0_pins: sdmmc0-pins { 1592 rockchip,pins = 1593 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1594 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1595 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1596 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1597 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1598 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1599 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1600 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1601 }; 1602 }; 1603 1604 sdmmc0ext { 1605 sdmmc0ext_clk: sdmmc0ext-clk { 1606 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1607 }; 1608 1609 sdmmc0ext_cmd: sdmmc0ext-cmd { 1610 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1611 }; 1612 1613 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1614 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1615 }; 1616 1617 sdmmc0ext_dectn: sdmmc0ext-dectn { 1618 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1619 }; 1620 1621 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1622 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1623 }; 1624 1625 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1626 rockchip,pins = 1627 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1628 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1629 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1630 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1631 }; 1632 1633 sdmmc0ext_pins: sdmmc0ext-pins { 1634 rockchip,pins = 1635 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1636 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1637 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1638 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1639 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1640 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1641 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1642 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1643 }; 1644 }; 1645 1646 sdmmc1 { 1647 sdmmc1_clk: sdmmc1-clk { 1648 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1649 }; 1650 1651 sdmmc1_cmd: sdmmc1-cmd { 1652 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1653 }; 1654 1655 sdmmc1_pwren: sdmmc1-pwren { 1656 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1657 }; 1658 1659 sdmmc1_wrprt: sdmmc1-wrprt { 1660 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1661 }; 1662 1663 sdmmc1_dectn: sdmmc1-dectn { 1664 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1665 }; 1666 1667 sdmmc1_bus1: sdmmc1-bus1 { 1668 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1669 }; 1670 1671 sdmmc1_bus4: sdmmc1-bus4 { 1672 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1673 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1674 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1675 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1676 }; 1677 1678 sdmmc1_pins: sdmmc1-pins { 1679 rockchip,pins = 1680 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1681 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1682 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1683 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1684 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1685 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1686 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1687 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1688 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1689 }; 1690 }; 1691 1692 emmc { 1693 emmc_clk: emmc-clk { 1694 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1695 }; 1696 1697 emmc_cmd: emmc-cmd { 1698 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1699 }; 1700 1701 emmc_pwren: emmc-pwren { 1702 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1703 }; 1704 1705 emmc_rstnout: emmc-rstnout { 1706 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1707 }; 1708 1709 emmc_bus1: emmc-bus1 { 1710 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1711 }; 1712 1713 emmc_bus4: emmc-bus4 { 1714 rockchip,pins = 1715 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1716 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1717 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1718 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1719 }; 1720 1721 emmc_bus8: emmc-bus8 { 1722 rockchip,pins = 1723 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1724 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1725 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1726 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1727 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1728 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1729 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1730 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1731 }; 1732 }; 1733 1734 pwm0 { 1735 pwm0_pin: pwm0-pin { 1736 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1737 }; 1738 }; 1739 1740 pwm1 { 1741 pwm1_pin: pwm1-pin { 1742 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1743 }; 1744 }; 1745 1746 pwm2 { 1747 pwm2_pin: pwm2-pin { 1748 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1749 }; 1750 }; 1751 1752 pwmir { 1753 pwmir_pin: pwmir-pin { 1754 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1755 }; 1756 }; 1757 1758 gmac-1 { 1759 rgmiim1_pins: rgmiim1-pins { 1760 rockchip,pins = 1761 /* mac_txclk */ 1762 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1763 /* mac_rxclk */ 1764 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1765 /* mac_mdio */ 1766 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1767 /* mac_txen */ 1768 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1769 /* mac_clk */ 1770 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1771 /* mac_rxdv */ 1772 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1773 /* mac_mdc */ 1774 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1775 /* mac_rxd1 */ 1776 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1777 /* mac_rxd0 */ 1778 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1779 /* mac_txd1 */ 1780 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1781 /* mac_txd0 */ 1782 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1783 /* mac_rxd3 */ 1784 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1785 /* mac_rxd2 */ 1786 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1787 /* mac_txd3 */ 1788 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1789 /* mac_txd2 */ 1790 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1791 1792 /* mac_txclk */ 1793 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1794 /* mac_txen */ 1795 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1796 /* mac_clk */ 1797 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1798 /* mac_txd1 */ 1799 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1800 /* mac_txd0 */ 1801 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1802 /* mac_txd3 */ 1803 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1804 /* mac_txd2 */ 1805 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1806 }; 1807 1808 rmiim1_pins: rmiim1-pins { 1809 rockchip,pins = 1810 /* mac_mdio */ 1811 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1812 /* mac_txen */ 1813 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1814 /* mac_clk */ 1815 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1816 /* mac_rxer */ 1817 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1818 /* mac_rxdv */ 1819 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1820 /* mac_mdc */ 1821 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1822 /* mac_rxd1 */ 1823 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1824 /* mac_rxd0 */ 1825 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1826 /* mac_txd1 */ 1827 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1828 /* mac_txd0 */ 1829 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1830 1831 /* mac_mdio */ 1832 <0 RK_PB3 1 &pcfg_pull_none>, 1833 /* mac_txen */ 1834 <0 RK_PB4 1 &pcfg_pull_none>, 1835 /* mac_clk */ 1836 <0 RK_PD0 1 &pcfg_pull_none>, 1837 /* mac_mdc */ 1838 <0 RK_PC3 1 &pcfg_pull_none>, 1839 /* mac_txd1 */ 1840 <0 RK_PC0 1 &pcfg_pull_none>, 1841 /* mac_txd0 */ 1842 <0 RK_PC1 1 &pcfg_pull_none>; 1843 }; 1844 }; 1845 1846 gmac2phy { 1847 fephyled_speed10: fephyled-speed10 { 1848 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1849 }; 1850 1851 fephyled_duplex: fephyled-duplex { 1852 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1853 }; 1854 1855 fephyled_rxm1: fephyled-rxm1 { 1856 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1857 }; 1858 1859 fephyled_txm1: fephyled-txm1 { 1860 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1861 }; 1862 1863 fephyled_linkm1: fephyled-linkm1 { 1864 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1865 }; 1866 }; 1867 1868 tsadc_pin { 1869 tsadc_int: tsadc-int { 1870 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1871 }; 1872 tsadc_pin: tsadc-pin { 1873 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1874 }; 1875 }; 1876 1877 hdmi_pin { 1878 hdmi_cec: hdmi-cec { 1879 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1880 }; 1881 1882 hdmi_hpd: hdmi-hpd { 1883 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1884 }; 1885 }; 1886 1887 cif-0 { 1888 dvp_d2d9_m0:dvp-d2d9-m0 { 1889 rockchip,pins = 1890 /* cif_d0 */ 1891 <3 RK_PA4 2 &pcfg_pull_none>, 1892 /* cif_d1 */ 1893 <3 RK_PA5 2 &pcfg_pull_none>, 1894 /* cif_d2 */ 1895 <3 RK_PA6 2 &pcfg_pull_none>, 1896 /* cif_d3 */ 1897 <3 RK_PA7 2 &pcfg_pull_none>, 1898 /* cif_d4 */ 1899 <3 RK_PB0 2 &pcfg_pull_none>, 1900 /* cif_d5m0 */ 1901 <3 RK_PB1 2 &pcfg_pull_none>, 1902 /* cif_d6m0 */ 1903 <3 RK_PB2 2 &pcfg_pull_none>, 1904 /* cif_d7m0 */ 1905 <3 RK_PB3 2 &pcfg_pull_none>, 1906 /* cif_href */ 1907 <3 RK_PA1 2 &pcfg_pull_none>, 1908 /* cif_vsync */ 1909 <3 RK_PA0 2 &pcfg_pull_none>, 1910 /* cif_clkoutm0 */ 1911 <3 RK_PA3 2 &pcfg_pull_none>, 1912 /* cif_clkin */ 1913 <3 RK_PA2 2 &pcfg_pull_none>; 1914 }; 1915 }; 1916 1917 cif-1 { 1918 dvp_d2d9_m1:dvp-d2d9-m1 { 1919 rockchip,pins = 1920 /* cif_d0 */ 1921 <3 RK_PA4 2 &pcfg_pull_none>, 1922 /* cif_d1 */ 1923 <3 RK_PA5 2 &pcfg_pull_none>, 1924 /* cif_d2 */ 1925 <3 RK_PA6 2 &pcfg_pull_none>, 1926 /* cif_d3 */ 1927 <3 RK_PA7 2 &pcfg_pull_none>, 1928 /* cif_d4 */ 1929 <3 RK_PB0 2 &pcfg_pull_none>, 1930 /* cif_d5m1 */ 1931 <2 RK_PC0 4 &pcfg_pull_none>, 1932 /* cif_d6m1 */ 1933 <2 RK_PC1 4 &pcfg_pull_none>, 1934 /* cif_d7m1 */ 1935 <2 RK_PC2 4 &pcfg_pull_none>, 1936 /* cif_href */ 1937 <3 RK_PA1 2 &pcfg_pull_none>, 1938 /* cif_vsync */ 1939 <3 RK_PA0 2 &pcfg_pull_none>, 1940 /* cif_clkoutm1 */ 1941 <2 RK_PB7 4 &pcfg_pull_none>, 1942 /* cif_clkin */ 1943 <3 RK_PA2 2 &pcfg_pull_none>; 1944 }; 1945 }; 1946 }; 1947}; 1948