1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7#include <dt-bindings/clock/rk3308-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3308"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 serial3 = &uart3; 31 serial4 = &uart4; 32 spi0 = &spi0; 33 spi1 = &spi1; 34 spi2 = &spi2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 clocks = <&cru ARMCLK>; 47 #cooling-cells = <2>; 48 dynamic-power-coefficient = <90>; 49 operating-points-v2 = <&cpu0_opp_table>; 50 cpu-idle-states = <&CPU_SLEEP>; 51 next-level-cache = <&l2>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 cpu-idle-states = <&CPU_SLEEP>; 61 next-level-cache = <&l2>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a35"; 67 reg = <0x0 0x2>; 68 enable-method = "psci"; 69 operating-points-v2 = <&cpu0_opp_table>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 next-level-cache = <&l2>; 72 }; 73 74 cpu3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a35"; 77 reg = <0x0 0x3>; 78 enable-method = "psci"; 79 operating-points-v2 = <&cpu0_opp_table>; 80 cpu-idle-states = <&CPU_SLEEP>; 81 next-level-cache = <&l2>; 82 }; 83 84 idle-states { 85 entry-method = "psci"; 86 87 CPU_SLEEP: cpu-sleep { 88 compatible = "arm,idle-state"; 89 local-timer-stop; 90 arm,psci-suspend-param = <0x0010000>; 91 entry-latency-us = <120>; 92 exit-latency-us = <250>; 93 min-residency-us = <900>; 94 }; 95 }; 96 97 l2: l2-cache { 98 compatible = "cache"; 99 }; 100 }; 101 102 cpu0_opp_table: cpu0-opp-table { 103 compatible = "operating-points-v2"; 104 opp-shared; 105 106 opp-408000000 { 107 opp-hz = /bits/ 64 <408000000>; 108 opp-microvolt = <950000 950000 1340000>; 109 clock-latency-ns = <40000>; 110 opp-suspend; 111 }; 112 opp-600000000 { 113 opp-hz = /bits/ 64 <600000000>; 114 opp-microvolt = <950000 950000 1340000>; 115 clock-latency-ns = <40000>; 116 }; 117 opp-816000000 { 118 opp-hz = /bits/ 64 <816000000>; 119 opp-microvolt = <1025000 1025000 1340000>; 120 clock-latency-ns = <40000>; 121 }; 122 opp-1008000000 { 123 opp-hz = /bits/ 64 <1008000000>; 124 opp-microvolt = <1125000 1125000 1340000>; 125 clock-latency-ns = <40000>; 126 }; 127 }; 128 129 arm-pmu { 130 compatible = "arm,cortex-a35-pmu"; 131 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 136 }; 137 138 mac_clkin: external-mac-clock { 139 compatible = "fixed-clock"; 140 clock-frequency = <50000000>; 141 clock-output-names = "mac_clkin"; 142 #clock-cells = <0>; 143 }; 144 145 psci { 146 compatible = "arm,psci-1.0"; 147 method = "smc"; 148 }; 149 150 timer { 151 compatible = "arm,armv8-timer"; 152 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 153 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 154 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 155 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 156 }; 157 158 xin24m: xin24m { 159 compatible = "fixed-clock"; 160 #clock-cells = <0>; 161 clock-frequency = <24000000>; 162 clock-output-names = "xin24m"; 163 }; 164 165 grf: grf@ff000000 { 166 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 167 reg = <0x0 0xff000000 0x0 0x10000>; 168 169 reboot-mode { 170 compatible = "syscon-reboot-mode"; 171 offset = <0x500>; 172 mode-bootloader = <BOOT_BL_DOWNLOAD>; 173 mode-loader = <BOOT_BL_DOWNLOAD>; 174 mode-normal = <BOOT_NORMAL>; 175 mode-recovery = <BOOT_RECOVERY>; 176 mode-fastboot = <BOOT_FASTBOOT>; 177 }; 178 }; 179 180 detect_grf: syscon@ff00b000 { 181 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; 182 reg = <0x0 0xff00b000 0x0 0x1000>; 183 #address-cells = <1>; 184 #size-cells = <1>; 185 }; 186 187 core_grf: syscon@ff00c000 { 188 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; 189 reg = <0x0 0xff00c000 0x0 0x1000>; 190 #address-cells = <1>; 191 #size-cells = <1>; 192 }; 193 194 i2c0: i2c@ff040000 { 195 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 196 reg = <0x0 0xff040000 0x0 0x1000>; 197 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 198 clock-names = "i2c", "pclk"; 199 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&i2c0_xfer>; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 status = "disabled"; 205 }; 206 207 i2c1: i2c@ff050000 { 208 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 209 reg = <0x0 0xff050000 0x0 0x1000>; 210 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 211 clock-names = "i2c", "pclk"; 212 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&i2c1_xfer>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 status = "disabled"; 218 }; 219 220 i2c2: i2c@ff060000 { 221 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 222 reg = <0x0 0xff060000 0x0 0x1000>; 223 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 224 clock-names = "i2c", "pclk"; 225 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&i2c2_xfer>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 status = "disabled"; 231 }; 232 233 i2c3: i2c@ff070000 { 234 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 235 reg = <0x0 0xff070000 0x0 0x1000>; 236 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 237 clock-names = "i2c", "pclk"; 238 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 239 pinctrl-names = "default"; 240 pinctrl-0 = <&i2c3m0_xfer>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 status = "disabled"; 244 }; 245 246 wdt: watchdog@ff080000 { 247 compatible = "snps,dw-wdt"; 248 reg = <0x0 0xff080000 0x0 0x100>; 249 clocks = <&cru PCLK_WDT>; 250 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 251 status = "disabled"; 252 }; 253 254 uart0: serial@ff0a0000 { 255 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 256 reg = <0x0 0xff0a0000 0x0 0x100>; 257 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 259 clock-names = "baudclk", "apb_pclk"; 260 reg-shift = <2>; 261 reg-io-width = <4>; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 264 status = "disabled"; 265 }; 266 267 uart1: serial@ff0b0000 { 268 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 269 reg = <0x0 0xff0b0000 0x0 0x100>; 270 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 272 clock-names = "baudclk", "apb_pclk"; 273 reg-shift = <2>; 274 reg-io-width = <4>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 277 status = "disabled"; 278 }; 279 280 uart2: serial@ff0c0000 { 281 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 282 reg = <0x0 0xff0c0000 0x0 0x100>; 283 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 285 clock-names = "baudclk", "apb_pclk"; 286 reg-shift = <2>; 287 reg-io-width = <4>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&uart2m0_xfer>; 290 status = "disabled"; 291 }; 292 293 uart3: serial@ff0d0000 { 294 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 295 reg = <0x0 0xff0d0000 0x0 0x100>; 296 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 298 clock-names = "baudclk", "apb_pclk"; 299 reg-shift = <2>; 300 reg-io-width = <4>; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&uart3_xfer>; 303 status = "disabled"; 304 }; 305 306 uart4: serial@ff0e0000 { 307 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 308 reg = <0x0 0xff0e0000 0x0 0x100>; 309 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 311 clock-names = "baudclk", "apb_pclk"; 312 reg-shift = <2>; 313 reg-io-width = <4>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 316 status = "disabled"; 317 }; 318 319 spi0: spi@ff120000 { 320 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 321 reg = <0x0 0xff120000 0x0 0x1000>; 322 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 326 clock-names = "spiclk", "apb_pclk"; 327 dmas = <&dmac0 0>, <&dmac0 1>; 328 dma-names = "tx", "rx"; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; 331 status = "disabled"; 332 }; 333 334 spi1: spi@ff130000 { 335 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 336 reg = <0x0 0xff130000 0x0 0x1000>; 337 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 341 clock-names = "spiclk", "apb_pclk"; 342 dmas = <&dmac0 2>, <&dmac0 3>; 343 dma-names = "tx", "rx"; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; 346 status = "disabled"; 347 }; 348 349 spi2: spi@ff140000 { 350 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 351 reg = <0x0 0xff140000 0x0 0x1000>; 352 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 356 clock-names = "spiclk", "apb_pclk"; 357 dmas = <&dmac1 16>, <&dmac1 17>; 358 dma-names = "tx", "rx"; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; 361 status = "disabled"; 362 }; 363 364 pwm8: pwm@ff160000 { 365 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 366 reg = <0x0 0xff160000 0x0 0x10>; 367 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 368 clock-names = "pwm", "pclk"; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pwm8_pin>; 371 #pwm-cells = <3>; 372 status = "disabled"; 373 }; 374 375 pwm9: pwm@ff160010 { 376 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 377 reg = <0x0 0xff160010 0x0 0x10>; 378 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 379 clock-names = "pwm", "pclk"; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&pwm9_pin>; 382 #pwm-cells = <3>; 383 status = "disabled"; 384 }; 385 386 pwm10: pwm@ff160020 { 387 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 388 reg = <0x0 0xff160020 0x0 0x10>; 389 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 390 clock-names = "pwm", "pclk"; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&pwm10_pin>; 393 #pwm-cells = <3>; 394 status = "disabled"; 395 }; 396 397 pwm11: pwm@ff160030 { 398 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 399 reg = <0x0 0xff160030 0x0 0x10>; 400 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 401 clock-names = "pwm", "pclk"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pwm11_pin>; 404 #pwm-cells = <3>; 405 status = "disabled"; 406 }; 407 408 pwm4: pwm@ff170000 { 409 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 410 reg = <0x0 0xff170000 0x0 0x10>; 411 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 412 clock-names = "pwm", "pclk"; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pwm4_pin>; 415 #pwm-cells = <3>; 416 status = "disabled"; 417 }; 418 419 pwm5: pwm@ff170010 { 420 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 421 reg = <0x0 0xff170010 0x0 0x10>; 422 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 423 clock-names = "pwm", "pclk"; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&pwm5_pin>; 426 #pwm-cells = <3>; 427 status = "disabled"; 428 }; 429 430 pwm6: pwm@ff170020 { 431 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 432 reg = <0x0 0xff170020 0x0 0x10>; 433 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 434 clock-names = "pwm", "pclk"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&pwm6_pin>; 437 #pwm-cells = <3>; 438 status = "disabled"; 439 }; 440 441 pwm7: pwm@ff170030 { 442 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 443 reg = <0x0 0xff170030 0x0 0x10>; 444 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 445 clock-names = "pwm", "pclk"; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&pwm7_pin>; 448 #pwm-cells = <3>; 449 status = "disabled"; 450 }; 451 452 pwm0: pwm@ff180000 { 453 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 454 reg = <0x0 0xff180000 0x0 0x10>; 455 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 456 clock-names = "pwm", "pclk"; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&pwm0_pin>; 459 #pwm-cells = <3>; 460 status = "disabled"; 461 }; 462 463 pwm1: pwm@ff180010 { 464 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 465 reg = <0x0 0xff180010 0x0 0x10>; 466 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 467 clock-names = "pwm", "pclk"; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pwm1_pin>; 470 #pwm-cells = <3>; 471 status = "disabled"; 472 }; 473 474 pwm2: pwm@ff180020 { 475 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 476 reg = <0x0 0xff180020 0x0 0x10>; 477 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 478 clock-names = "pwm", "pclk"; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pwm2_pin>; 481 #pwm-cells = <3>; 482 status = "disabled"; 483 }; 484 485 pwm3: pwm@ff180030 { 486 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 487 reg = <0x0 0xff180030 0x0 0x10>; 488 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 489 clock-names = "pwm", "pclk"; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pwm3_pin>; 492 #pwm-cells = <3>; 493 status = "disabled"; 494 }; 495 496 rktimer: rktimer@ff1a0000 { 497 compatible = "rockchip,rk3288-timer"; 498 reg = <0x0 0xff1a0000 0x0 0x20>; 499 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 501 clock-names = "pclk", "timer"; 502 }; 503 504 saradc: saradc@ff1e0000 { 505 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 506 reg = <0x0 0xff1e0000 0x0 0x100>; 507 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 509 clock-names = "saradc", "apb_pclk"; 510 #io-channel-cells = <1>; 511 resets = <&cru SRST_SARADC_P>; 512 reset-names = "saradc-apb"; 513 status = "disabled"; 514 }; 515 516 amba: bus { 517 compatible = "simple-bus"; 518 #address-cells = <2>; 519 #size-cells = <2>; 520 ranges; 521 522 dmac0: dma-controller@ff2c0000 { 523 compatible = "arm,pl330", "arm,primecell"; 524 reg = <0x0 0xff2c0000 0x0 0x4000>; 525 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 527 arm,pl330-periph-burst; 528 clocks = <&cru ACLK_DMAC0>; 529 clock-names = "apb_pclk"; 530 #dma-cells = <1>; 531 }; 532 533 dmac1: dma-controller@ff2d0000 { 534 compatible = "arm,pl330", "arm,primecell"; 535 reg = <0x0 0xff2d0000 0x0 0x4000>; 536 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 538 arm,pl330-periph-burst; 539 clocks = <&cru ACLK_DMAC1>; 540 clock-names = "apb_pclk"; 541 #dma-cells = <1>; 542 }; 543 }; 544 545 i2s_2ch_0: i2s@ff350000 { 546 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 547 reg = <0x0 0xff350000 0x0 0x1000>; 548 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; 550 clock-names = "i2s_clk", "i2s_hclk"; 551 dmas = <&dmac1 8>, <&dmac1 9>; 552 dma-names = "tx", "rx"; 553 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; 554 reset-names = "reset-m", "reset-h"; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&i2s_2ch_0_sclk 557 &i2s_2ch_0_lrck 558 &i2s_2ch_0_sdi 559 &i2s_2ch_0_sdo>; 560 status = "disabled"; 561 }; 562 563 i2s_2ch_1: i2s@ff360000 { 564 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 565 reg = <0x0 0xff360000 0x0 0x1000>; 566 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 568 clock-names = "i2s_clk", "i2s_hclk"; 569 dmas = <&dmac1 11>; 570 dma-names = "rx"; 571 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; 572 reset-names = "reset-m", "reset-h"; 573 status = "disabled"; 574 }; 575 576 spdif_tx: spdif-tx@ff3a0000 { 577 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; 578 reg = <0x0 0xff3a0000 0x0 0x1000>; 579 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; 581 clock-names = "mclk", "hclk"; 582 dmas = <&dmac1 13>; 583 dma-names = "tx"; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&spdif_out>; 586 status = "disabled"; 587 }; 588 589 sdmmc: mmc@ff480000 { 590 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 591 reg = <0x0 0xff480000 0x0 0x4000>; 592 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 593 bus-width = <4>; 594 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 595 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 596 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 597 fifo-depth = <0x100>; 598 max-frequency = <150000000>; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 601 status = "disabled"; 602 }; 603 604 emmc: mmc@ff490000 { 605 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 606 reg = <0x0 0xff490000 0x0 0x4000>; 607 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 608 bus-width = <8>; 609 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 610 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 611 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 612 fifo-depth = <0x100>; 613 max-frequency = <150000000>; 614 status = "disabled"; 615 }; 616 617 sdio: mmc@ff4a0000 { 618 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 619 reg = <0x0 0xff4a0000 0x0 0x4000>; 620 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 621 bus-width = <4>; 622 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 623 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 624 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 625 fifo-depth = <0x100>; 626 max-frequency = <150000000>; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 629 status = "disabled"; 630 }; 631 632 nfc: nand-controller@ff4b0000 { 633 compatible = "rockchip,rk3308-nfc", 634 "rockchip,rv1108-nfc"; 635 reg = <0x0 0xff4b0000 0x0 0x4000>; 636 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 638 clock-names = "ahb", "nfc"; 639 assigned-clocks = <&cru SCLK_NANDC>; 640 assigned-clock-rates = <150000000>; 641 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 642 &flash_rdn &flash_rdy &flash_wrn>; 643 pinctrl-names = "default"; 644 status = "disabled"; 645 }; 646 647 cru: clock-controller@ff500000 { 648 compatible = "rockchip,rk3308-cru"; 649 reg = <0x0 0xff500000 0x0 0x1000>; 650 #clock-cells = <1>; 651 #reset-cells = <1>; 652 rockchip,grf = <&grf>; 653 654 assigned-clocks = <&cru SCLK_RTC32K>; 655 assigned-clock-rates = <32768>; 656 }; 657 658 gic: interrupt-controller@ff580000 { 659 compatible = "arm,gic-400"; 660 reg = <0x0 0xff581000 0x0 0x1000>, 661 <0x0 0xff582000 0x0 0x2000>, 662 <0x0 0xff584000 0x0 0x2000>, 663 <0x0 0xff586000 0x0 0x2000>; 664 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 665 #interrupt-cells = <3>; 666 interrupt-controller; 667 #address-cells = <0>; 668 }; 669 670 sram: sram@fff80000 { 671 compatible = "mmio-sram"; 672 reg = <0x0 0xfff80000 0x0 0x40000>; 673 ranges = <0 0x0 0xfff80000 0x40000>; 674 #address-cells = <1>; 675 #size-cells = <1>; 676 677 /* reserved for ddr dvfs and system suspend/resume */ 678 ddr-sram@0 { 679 reg = <0x0 0x8000>; 680 }; 681 682 /* reserved for vad audio buffer */ 683 vad_sram: vad-sram@8000 { 684 reg = <0x8000 0x38000>; 685 }; 686 }; 687 688 pinctrl: pinctrl { 689 compatible = "rockchip,rk3308-pinctrl"; 690 rockchip,grf = <&grf>; 691 #address-cells = <2>; 692 #size-cells = <2>; 693 ranges; 694 695 gpio0: gpio0@ff220000 { 696 compatible = "rockchip,gpio-bank"; 697 reg = <0x0 0xff220000 0x0 0x100>; 698 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cru PCLK_GPIO0>; 700 gpio-controller; 701 #gpio-cells = <2>; 702 interrupt-controller; 703 #interrupt-cells = <2>; 704 }; 705 706 gpio1: gpio1@ff230000 { 707 compatible = "rockchip,gpio-bank"; 708 reg = <0x0 0xff230000 0x0 0x100>; 709 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&cru PCLK_GPIO1>; 711 gpio-controller; 712 #gpio-cells = <2>; 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 }; 716 717 gpio2: gpio2@ff240000 { 718 compatible = "rockchip,gpio-bank"; 719 reg = <0x0 0xff240000 0x0 0x100>; 720 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&cru PCLK_GPIO2>; 722 gpio-controller; 723 #gpio-cells = <2>; 724 interrupt-controller; 725 #interrupt-cells = <2>; 726 }; 727 728 gpio3: gpio3@ff250000 { 729 compatible = "rockchip,gpio-bank"; 730 reg = <0x0 0xff250000 0x0 0x100>; 731 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&cru PCLK_GPIO3>; 733 gpio-controller; 734 #gpio-cells = <2>; 735 interrupt-controller; 736 #interrupt-cells = <2>; 737 }; 738 739 gpio4: gpio4@ff260000 { 740 compatible = "rockchip,gpio-bank"; 741 reg = <0x0 0xff260000 0x0 0x100>; 742 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&cru PCLK_GPIO4>; 744 gpio-controller; 745 #gpio-cells = <2>; 746 interrupt-controller; 747 #interrupt-cells = <2>; 748 }; 749 750 pcfg_pull_up: pcfg-pull-up { 751 bias-pull-up; 752 }; 753 754 pcfg_pull_down: pcfg-pull-down { 755 bias-pull-down; 756 }; 757 758 pcfg_pull_none: pcfg-pull-none { 759 bias-disable; 760 }; 761 762 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 763 bias-disable; 764 drive-strength = <2>; 765 }; 766 767 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 768 bias-pull-up; 769 drive-strength = <2>; 770 }; 771 772 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 773 bias-pull-up; 774 drive-strength = <4>; 775 }; 776 777 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 778 bias-disable; 779 drive-strength = <4>; 780 }; 781 782 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 783 bias-pull-down; 784 drive-strength = <4>; 785 }; 786 787 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 788 bias-disable; 789 drive-strength = <8>; 790 }; 791 792 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 793 bias-pull-up; 794 drive-strength = <8>; 795 }; 796 797 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 798 bias-disable; 799 drive-strength = <12>; 800 }; 801 802 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 803 bias-pull-up; 804 drive-strength = <12>; 805 }; 806 807 pcfg_pull_none_smt: pcfg-pull-none-smt { 808 bias-disable; 809 input-schmitt-enable; 810 }; 811 812 pcfg_output_high: pcfg-output-high { 813 output-high; 814 }; 815 816 pcfg_output_low: pcfg-output-low { 817 output-low; 818 }; 819 820 pcfg_input_high: pcfg-input-high { 821 bias-pull-up; 822 input-enable; 823 }; 824 825 pcfg_input: pcfg-input { 826 input-enable; 827 }; 828 829 emmc { 830 emmc_clk: emmc-clk { 831 rockchip,pins = 832 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 833 }; 834 835 emmc_cmd: emmc-cmd { 836 rockchip,pins = 837 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 838 }; 839 840 emmc_pwren: emmc-pwren { 841 rockchip,pins = 842 <3 RK_PB3 2 &pcfg_pull_none>; 843 }; 844 845 emmc_rstn: emmc-rstn { 846 rockchip,pins = 847 <3 RK_PB2 2 &pcfg_pull_none>; 848 }; 849 850 emmc_bus1: emmc-bus1 { 851 rockchip,pins = 852 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 853 }; 854 855 emmc_bus4: emmc-bus4 { 856 rockchip,pins = 857 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 858 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 859 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 860 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 861 }; 862 863 emmc_bus8: emmc-bus8 { 864 rockchip,pins = 865 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 866 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 867 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 868 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 869 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 870 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 871 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 872 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 873 }; 874 }; 875 876 flash { 877 flash_csn0: flash-csn0 { 878 rockchip,pins = 879 <3 RK_PB5 1 &pcfg_pull_none>; 880 }; 881 882 flash_rdy: flash-rdy { 883 rockchip,pins = 884 <3 RK_PB4 1 &pcfg_pull_none>; 885 }; 886 887 flash_ale: flash-ale { 888 rockchip,pins = 889 <3 RK_PB3 1 &pcfg_pull_none>; 890 }; 891 892 flash_cle: flash-cle { 893 rockchip,pins = 894 <3 RK_PB1 1 &pcfg_pull_none>; 895 }; 896 897 flash_wrn: flash-wrn { 898 rockchip,pins = 899 <3 RK_PB0 1 &pcfg_pull_none>; 900 }; 901 902 flash_rdn: flash-rdn { 903 rockchip,pins = 904 <3 RK_PB2 1 &pcfg_pull_none>; 905 }; 906 907 flash_bus8: flash-bus8 { 908 rockchip,pins = 909 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 910 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 911 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 912 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 913 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 914 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 915 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 916 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 917 }; 918 }; 919 920 gmac { 921 rmii_pins: rmii-pins { 922 rockchip,pins = 923 /* mac_txen */ 924 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 925 /* mac_txd1 */ 926 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 927 /* mac_txd0 */ 928 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 929 /* mac_rxd0 */ 930 <1 RK_PC4 3 &pcfg_pull_none>, 931 /* mac_rxd1 */ 932 <1 RK_PC5 3 &pcfg_pull_none>, 933 /* mac_rxer */ 934 <1 RK_PB7 3 &pcfg_pull_none>, 935 /* mac_rxdv */ 936 <1 RK_PC0 3 &pcfg_pull_none>, 937 /* mac_mdio */ 938 <1 RK_PB6 3 &pcfg_pull_none>, 939 /* mac_mdc */ 940 <1 RK_PB5 3 &pcfg_pull_none>; 941 }; 942 943 mac_refclk_12ma: mac-refclk-12ma { 944 rockchip,pins = 945 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 946 }; 947 948 mac_refclk: mac-refclk { 949 rockchip,pins = 950 <1 RK_PB4 3 &pcfg_pull_none>; 951 }; 952 }; 953 954 gmac-m1 { 955 rmiim1_pins: rmiim1-pins { 956 rockchip,pins = 957 /* mac_txen */ 958 <4 RK_PB7 2 &pcfg_pull_none_12ma>, 959 /* mac_txd1 */ 960 <4 RK_PA5 2 &pcfg_pull_none_12ma>, 961 /* mac_txd0 */ 962 <4 RK_PA4 2 &pcfg_pull_none_12ma>, 963 /* mac_rxd0 */ 964 <4 RK_PA2 2 &pcfg_pull_none>, 965 /* mac_rxd1 */ 966 <4 RK_PA3 2 &pcfg_pull_none>, 967 /* mac_rxer */ 968 <4 RK_PA0 2 &pcfg_pull_none>, 969 /* mac_rxdv */ 970 <4 RK_PA1 2 &pcfg_pull_none>, 971 /* mac_mdio */ 972 <4 RK_PB6 2 &pcfg_pull_none>, 973 /* mac_mdc */ 974 <4 RK_PB5 2 &pcfg_pull_none>; 975 }; 976 977 macm1_refclk_12ma: macm1-refclk-12ma { 978 rockchip,pins = 979 <4 RK_PB4 2 &pcfg_pull_none_12ma>; 980 }; 981 982 macm1_refclk: macm1-refclk { 983 rockchip,pins = 984 <4 RK_PB4 2 &pcfg_pull_none>; 985 }; 986 }; 987 988 i2c0 { 989 i2c0_xfer: i2c0-xfer { 990 rockchip,pins = 991 <1 RK_PD0 2 &pcfg_pull_none_smt>, 992 <1 RK_PD1 2 &pcfg_pull_none_smt>; 993 }; 994 }; 995 996 i2c1 { 997 i2c1_xfer: i2c1-xfer { 998 rockchip,pins = 999 <0 RK_PB3 1 &pcfg_pull_none_smt>, 1000 <0 RK_PB4 1 &pcfg_pull_none_smt>; 1001 }; 1002 }; 1003 1004 i2c2 { 1005 i2c2_xfer: i2c2-xfer { 1006 rockchip,pins = 1007 <2 RK_PA2 3 &pcfg_pull_none_smt>, 1008 <2 RK_PA3 3 &pcfg_pull_none_smt>; 1009 }; 1010 }; 1011 1012 i2c3-m0 { 1013 i2c3m0_xfer: i2c3m0-xfer { 1014 rockchip,pins = 1015 <0 RK_PB7 2 &pcfg_pull_none_smt>, 1016 <0 RK_PC0 2 &pcfg_pull_none_smt>; 1017 }; 1018 }; 1019 1020 i2c3-m1 { 1021 i2c3m1_xfer: i2c3m1-xfer { 1022 rockchip,pins = 1023 <3 RK_PB4 2 &pcfg_pull_none_smt>, 1024 <3 RK_PB5 2 &pcfg_pull_none_smt>; 1025 }; 1026 }; 1027 1028 i2c3-m2 { 1029 i2c3m2_xfer: i2c3m2-xfer { 1030 rockchip,pins = 1031 <2 RK_PA1 3 &pcfg_pull_none_smt>, 1032 <2 RK_PA0 3 &pcfg_pull_none_smt>; 1033 }; 1034 }; 1035 1036 i2s_2ch_0 { 1037 i2s_2ch_0_mclk: i2s-2ch-0-mclk { 1038 rockchip,pins = 1039 <4 RK_PB4 1 &pcfg_pull_none>; 1040 }; 1041 1042 i2s_2ch_0_sclk: i2s-2ch-0-sclk { 1043 rockchip,pins = 1044 <4 RK_PB5 1 &pcfg_pull_none>; 1045 }; 1046 1047 i2s_2ch_0_lrck: i2s-2ch-0-lrck { 1048 rockchip,pins = 1049 <4 RK_PB6 1 &pcfg_pull_none>; 1050 }; 1051 1052 i2s_2ch_0_sdo: i2s-2ch-0-sdo { 1053 rockchip,pins = 1054 <4 RK_PB7 1 &pcfg_pull_none>; 1055 }; 1056 1057 i2s_2ch_0_sdi: i2s-2ch-0-sdi { 1058 rockchip,pins = 1059 <4 RK_PC0 1 &pcfg_pull_none>; 1060 }; 1061 }; 1062 1063 i2s_8ch_0 { 1064 i2s_8ch_0_mclk: i2s-8ch-0-mclk { 1065 rockchip,pins = 1066 <2 RK_PA4 1 &pcfg_pull_none>; 1067 }; 1068 1069 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { 1070 rockchip,pins = 1071 <2 RK_PA5 1 &pcfg_pull_none>; 1072 }; 1073 1074 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { 1075 rockchip,pins = 1076 <2 RK_PA6 1 &pcfg_pull_none>; 1077 }; 1078 1079 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { 1080 rockchip,pins = 1081 <2 RK_PA7 1 &pcfg_pull_none>; 1082 }; 1083 1084 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { 1085 rockchip,pins = 1086 <2 RK_PB0 1 &pcfg_pull_none>; 1087 }; 1088 1089 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { 1090 rockchip,pins = 1091 <2 RK_PB1 1 &pcfg_pull_none>; 1092 }; 1093 1094 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { 1095 rockchip,pins = 1096 <2 RK_PB2 1 &pcfg_pull_none>; 1097 }; 1098 1099 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { 1100 rockchip,pins = 1101 <2 RK_PB3 1 &pcfg_pull_none>; 1102 }; 1103 1104 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { 1105 rockchip,pins = 1106 <2 RK_PB4 1 &pcfg_pull_none>; 1107 }; 1108 1109 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { 1110 rockchip,pins = 1111 <2 RK_PB5 1 &pcfg_pull_none>; 1112 }; 1113 1114 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { 1115 rockchip,pins = 1116 <2 RK_PB6 1 &pcfg_pull_none>; 1117 }; 1118 1119 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { 1120 rockchip,pins = 1121 <2 RK_PB7 1 &pcfg_pull_none>; 1122 }; 1123 1124 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { 1125 rockchip,pins = 1126 <2 RK_PC0 1 &pcfg_pull_none>; 1127 }; 1128 }; 1129 1130 i2s_8ch_1_m0 { 1131 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { 1132 rockchip,pins = 1133 <1 RK_PA2 2 &pcfg_pull_none>; 1134 }; 1135 1136 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { 1137 rockchip,pins = 1138 <1 RK_PA3 2 &pcfg_pull_none>; 1139 }; 1140 1141 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { 1142 rockchip,pins = 1143 <1 RK_PA4 2 &pcfg_pull_none>; 1144 }; 1145 1146 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { 1147 rockchip,pins = 1148 <1 RK_PA5 2 &pcfg_pull_none>; 1149 }; 1150 1151 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { 1152 rockchip,pins = 1153 <1 RK_PA6 2 &pcfg_pull_none>; 1154 }; 1155 1156 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { 1157 rockchip,pins = 1158 <1 RK_PA7 2 &pcfg_pull_none>; 1159 }; 1160 1161 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { 1162 rockchip,pins = 1163 <1 RK_PB0 2 &pcfg_pull_none>; 1164 }; 1165 1166 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { 1167 rockchip,pins = 1168 <1 RK_PB1 2 &pcfg_pull_none>; 1169 }; 1170 1171 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { 1172 rockchip,pins = 1173 <1 RK_PB2 2 &pcfg_pull_none>; 1174 }; 1175 1176 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { 1177 rockchip,pins = 1178 <1 RK_PB3 2 &pcfg_pull_none>; 1179 }; 1180 }; 1181 1182 i2s_8ch_1_m1 { 1183 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { 1184 rockchip,pins = 1185 <1 RK_PB4 2 &pcfg_pull_none>; 1186 }; 1187 1188 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { 1189 rockchip,pins = 1190 <1 RK_PB5 2 &pcfg_pull_none>; 1191 }; 1192 1193 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { 1194 rockchip,pins = 1195 <1 RK_PB6 2 &pcfg_pull_none>; 1196 }; 1197 1198 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { 1199 rockchip,pins = 1200 <1 RK_PB7 2 &pcfg_pull_none>; 1201 }; 1202 1203 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { 1204 rockchip,pins = 1205 <1 RK_PC0 2 &pcfg_pull_none>; 1206 }; 1207 1208 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { 1209 rockchip,pins = 1210 <1 RK_PC1 2 &pcfg_pull_none>; 1211 }; 1212 1213 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { 1214 rockchip,pins = 1215 <1 RK_PC2 2 &pcfg_pull_none>; 1216 }; 1217 1218 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { 1219 rockchip,pins = 1220 <1 RK_PC3 2 &pcfg_pull_none>; 1221 }; 1222 1223 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { 1224 rockchip,pins = 1225 <1 RK_PC4 2 &pcfg_pull_none>; 1226 }; 1227 1228 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { 1229 rockchip,pins = 1230 <1 RK_PC5 2 &pcfg_pull_none>; 1231 }; 1232 }; 1233 1234 pdm_m0 { 1235 pdm_m0_clk: pdm-m0-clk { 1236 rockchip,pins = 1237 <1 RK_PA4 3 &pcfg_pull_none>; 1238 }; 1239 1240 pdm_m0_sdi0: pdm-m0-sdi0 { 1241 rockchip,pins = 1242 <1 RK_PB3 3 &pcfg_pull_none>; 1243 }; 1244 1245 pdm_m0_sdi1: pdm-m0-sdi1 { 1246 rockchip,pins = 1247 <1 RK_PB2 3 &pcfg_pull_none>; 1248 }; 1249 1250 pdm_m0_sdi2: pdm-m0-sdi2 { 1251 rockchip,pins = 1252 <1 RK_PB1 3 &pcfg_pull_none>; 1253 }; 1254 1255 pdm_m0_sdi3: pdm-m0-sdi3 { 1256 rockchip,pins = 1257 <1 RK_PB0 3 &pcfg_pull_none>; 1258 }; 1259 }; 1260 1261 pdm_m1 { 1262 pdm_m1_clk: pdm-m1-clk { 1263 rockchip,pins = 1264 <1 RK_PB6 4 &pcfg_pull_none>; 1265 }; 1266 1267 pdm_m1_sdi0: pdm-m1-sdi0 { 1268 rockchip,pins = 1269 <1 RK_PC5 4 &pcfg_pull_none>; 1270 }; 1271 1272 pdm_m1_sdi1: pdm-m1-sdi1 { 1273 rockchip,pins = 1274 <1 RK_PC4 4 &pcfg_pull_none>; 1275 }; 1276 1277 pdm_m1_sdi2: pdm-m1-sdi2 { 1278 rockchip,pins = 1279 <1 RK_PC3 4 &pcfg_pull_none>; 1280 }; 1281 1282 pdm_m1_sdi3: pdm-m1-sdi3 { 1283 rockchip,pins = 1284 <1 RK_PC2 4 &pcfg_pull_none>; 1285 }; 1286 }; 1287 1288 pdm_m2 { 1289 pdm_m2_clkm: pdm-m2-clkm { 1290 rockchip,pins = 1291 <2 RK_PA4 3 &pcfg_pull_none>; 1292 }; 1293 1294 pdm_m2_clk: pdm-m2-clk { 1295 rockchip,pins = 1296 <2 RK_PA6 2 &pcfg_pull_none>; 1297 }; 1298 1299 pdm_m2_sdi0: pdm-m2-sdi0 { 1300 rockchip,pins = 1301 <2 RK_PB5 2 &pcfg_pull_none>; 1302 }; 1303 1304 pdm_m2_sdi1: pdm-m2-sdi1 { 1305 rockchip,pins = 1306 <2 RK_PB6 2 &pcfg_pull_none>; 1307 }; 1308 1309 pdm_m2_sdi2: pdm-m2-sdi2 { 1310 rockchip,pins = 1311 <2 RK_PB7 2 &pcfg_pull_none>; 1312 }; 1313 1314 pdm_m2_sdi3: pdm-m2-sdi3 { 1315 rockchip,pins = 1316 <2 RK_PC0 2 &pcfg_pull_none>; 1317 }; 1318 }; 1319 1320 pwm0 { 1321 pwm0_pin: pwm0-pin { 1322 rockchip,pins = 1323 <0 RK_PB5 1 &pcfg_pull_none>; 1324 }; 1325 1326 pwm0_pin_pull_down: pwm0-pin-pull-down { 1327 rockchip,pins = 1328 <0 RK_PB5 1 &pcfg_pull_down>; 1329 }; 1330 }; 1331 1332 pwm1 { 1333 pwm1_pin: pwm1-pin { 1334 rockchip,pins = 1335 <0 RK_PB6 1 &pcfg_pull_none>; 1336 }; 1337 1338 pwm1_pin_pull_down: pwm1-pin-pull-down { 1339 rockchip,pins = 1340 <0 RK_PB6 1 &pcfg_pull_down>; 1341 }; 1342 }; 1343 1344 pwm2 { 1345 pwm2_pin: pwm2-pin { 1346 rockchip,pins = 1347 <0 RK_PB7 1 &pcfg_pull_none>; 1348 }; 1349 1350 pwm2_pin_pull_down: pwm2-pin-pull-down { 1351 rockchip,pins = 1352 <0 RK_PB7 1 &pcfg_pull_down>; 1353 }; 1354 }; 1355 1356 pwm3 { 1357 pwm3_pin: pwm3-pin { 1358 rockchip,pins = 1359 <0 RK_PC0 1 &pcfg_pull_none>; 1360 }; 1361 1362 pwm3_pin_pull_down: pwm3-pin-pull-down { 1363 rockchip,pins = 1364 <0 RK_PC0 1 &pcfg_pull_down>; 1365 }; 1366 }; 1367 1368 pwm4 { 1369 pwm4_pin: pwm4-pin { 1370 rockchip,pins = 1371 <0 RK_PA1 2 &pcfg_pull_none>; 1372 }; 1373 1374 pwm4_pin_pull_down: pwm4-pin-pull-down { 1375 rockchip,pins = 1376 <0 RK_PA1 2 &pcfg_pull_down>; 1377 }; 1378 }; 1379 1380 pwm5 { 1381 pwm5_pin: pwm5-pin { 1382 rockchip,pins = 1383 <0 RK_PC1 2 &pcfg_pull_none>; 1384 }; 1385 1386 pwm5_pin_pull_down: pwm5-pin-pull-down { 1387 rockchip,pins = 1388 <0 RK_PC1 2 &pcfg_pull_down>; 1389 }; 1390 }; 1391 1392 pwm6 { 1393 pwm6_pin: pwm6-pin { 1394 rockchip,pins = 1395 <0 RK_PC2 2 &pcfg_pull_none>; 1396 }; 1397 1398 pwm6_pin_pull_down: pwm6-pin-pull-down { 1399 rockchip,pins = 1400 <0 RK_PC2 2 &pcfg_pull_down>; 1401 }; 1402 }; 1403 1404 pwm7 { 1405 pwm7_pin: pwm7-pin { 1406 rockchip,pins = 1407 <2 RK_PB0 2 &pcfg_pull_none>; 1408 }; 1409 1410 pwm7_pin_pull_down: pwm7-pin-pull-down { 1411 rockchip,pins = 1412 <2 RK_PB0 2 &pcfg_pull_down>; 1413 }; 1414 }; 1415 1416 pwm8 { 1417 pwm8_pin: pwm8-pin { 1418 rockchip,pins = 1419 <2 RK_PB2 2 &pcfg_pull_none>; 1420 }; 1421 1422 pwm8_pin_pull_down: pwm8-pin-pull-down { 1423 rockchip,pins = 1424 <2 RK_PB2 2 &pcfg_pull_down>; 1425 }; 1426 }; 1427 1428 pwm9 { 1429 pwm9_pin: pwm9-pin { 1430 rockchip,pins = 1431 <2 RK_PB3 2 &pcfg_pull_none>; 1432 }; 1433 1434 pwm9_pin_pull_down: pwm9-pin-pull-down { 1435 rockchip,pins = 1436 <2 RK_PB3 2 &pcfg_pull_down>; 1437 }; 1438 }; 1439 1440 pwm10 { 1441 pwm10_pin: pwm10-pin { 1442 rockchip,pins = 1443 <2 RK_PB4 2 &pcfg_pull_none>; 1444 }; 1445 1446 pwm10_pin_pull_down: pwm10-pin-pull-down { 1447 rockchip,pins = 1448 <2 RK_PB4 2 &pcfg_pull_down>; 1449 }; 1450 }; 1451 1452 pwm11 { 1453 pwm11_pin: pwm11-pin { 1454 rockchip,pins = 1455 <2 RK_PC0 4 &pcfg_pull_none>; 1456 }; 1457 1458 pwm11_pin_pull_down: pwm11-pin-pull-down { 1459 rockchip,pins = 1460 <2 RK_PC0 4 &pcfg_pull_down>; 1461 }; 1462 }; 1463 1464 rtc { 1465 rtc_32k: rtc-32k { 1466 rockchip,pins = 1467 <0 RK_PC3 1 &pcfg_pull_none>; 1468 }; 1469 }; 1470 1471 sdmmc { 1472 sdmmc_clk: sdmmc-clk { 1473 rockchip,pins = 1474 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 1475 }; 1476 1477 sdmmc_cmd: sdmmc-cmd { 1478 rockchip,pins = 1479 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 1480 }; 1481 1482 sdmmc_det: sdmmc-det { 1483 rockchip,pins = 1484 <0 RK_PA3 1 &pcfg_pull_up_4ma>; 1485 }; 1486 1487 sdmmc_pwren: sdmmc-pwren { 1488 rockchip,pins = 1489 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 1490 }; 1491 1492 sdmmc_bus1: sdmmc-bus1 { 1493 rockchip,pins = 1494 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 1495 }; 1496 1497 sdmmc_bus4: sdmmc-bus4 { 1498 rockchip,pins = 1499 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 1500 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 1501 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 1502 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 1503 }; 1504 }; 1505 1506 sdio { 1507 sdio_clk: sdio-clk { 1508 rockchip,pins = 1509 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 1510 }; 1511 1512 sdio_cmd: sdio-cmd { 1513 rockchip,pins = 1514 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 1515 }; 1516 1517 sdio_pwren: sdio-pwren { 1518 rockchip,pins = 1519 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 1520 }; 1521 1522 sdio_wrpt: sdio-wrpt { 1523 rockchip,pins = 1524 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 1525 }; 1526 1527 sdio_intn: sdio-intn { 1528 rockchip,pins = 1529 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 1530 }; 1531 1532 sdio_bus1: sdio-bus1 { 1533 rockchip,pins = 1534 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 1535 }; 1536 1537 sdio_bus4: sdio-bus4 { 1538 rockchip,pins = 1539 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 1540 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 1541 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 1542 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 1543 }; 1544 }; 1545 1546 spdif_in { 1547 spdif_in: spdif-in { 1548 rockchip,pins = 1549 <0 RK_PC2 1 &pcfg_pull_none>; 1550 }; 1551 }; 1552 1553 spdif_out { 1554 spdif_out: spdif-out { 1555 rockchip,pins = 1556 <0 RK_PC1 1 &pcfg_pull_none>; 1557 }; 1558 }; 1559 1560 spi0 { 1561 spi0_clk: spi0-clk { 1562 rockchip,pins = 1563 <2 RK_PA2 2 &pcfg_pull_up_4ma>; 1564 }; 1565 1566 spi0_csn0: spi0-csn0 { 1567 rockchip,pins = 1568 <2 RK_PA3 2 &pcfg_pull_up_4ma>; 1569 }; 1570 1571 spi0_miso: spi0-miso { 1572 rockchip,pins = 1573 <2 RK_PA0 2 &pcfg_pull_up_4ma>; 1574 }; 1575 1576 spi0_mosi: spi0-mosi { 1577 rockchip,pins = 1578 <2 RK_PA1 2 &pcfg_pull_up_4ma>; 1579 }; 1580 }; 1581 1582 spi1 { 1583 spi1_clk: spi1-clk { 1584 rockchip,pins = 1585 <3 RK_PB3 3 &pcfg_pull_up_4ma>; 1586 }; 1587 1588 spi1_csn0: spi1-csn0 { 1589 rockchip,pins = 1590 <3 RK_PB5 3 &pcfg_pull_up_4ma>; 1591 }; 1592 1593 spi1_miso: spi1-miso { 1594 rockchip,pins = 1595 <3 RK_PB2 3 &pcfg_pull_up_4ma>; 1596 }; 1597 1598 spi1_mosi: spi1-mosi { 1599 rockchip,pins = 1600 <3 RK_PB4 3 &pcfg_pull_up_4ma>; 1601 }; 1602 }; 1603 1604 spi1-m1 { 1605 spi1m1_miso: spi1m1-miso { 1606 rockchip,pins = 1607 <2 RK_PA4 2 &pcfg_pull_up_4ma>; 1608 }; 1609 1610 spi1m1_mosi: spi1m1-mosi { 1611 rockchip,pins = 1612 <2 RK_PA5 2 &pcfg_pull_up_4ma>; 1613 }; 1614 1615 spi1m1_clk: spi1m1-clk { 1616 rockchip,pins = 1617 <2 RK_PA7 2 &pcfg_pull_up_4ma>; 1618 }; 1619 1620 spi1m1_csn0: spi1m1-csn0 { 1621 rockchip,pins = 1622 <2 RK_PB1 2 &pcfg_pull_up_4ma>; 1623 }; 1624 }; 1625 1626 spi2 { 1627 spi2_clk: spi2-clk { 1628 rockchip,pins = 1629 <1 RK_PD0 3 &pcfg_pull_up_4ma>; 1630 }; 1631 1632 spi2_csn0: spi2-csn0 { 1633 rockchip,pins = 1634 <1 RK_PD1 3 &pcfg_pull_up_4ma>; 1635 }; 1636 1637 spi2_miso: spi2-miso { 1638 rockchip,pins = 1639 <1 RK_PC6 3 &pcfg_pull_up_4ma>; 1640 }; 1641 1642 spi2_mosi: spi2-mosi { 1643 rockchip,pins = 1644 <1 RK_PC7 3 &pcfg_pull_up_4ma>; 1645 }; 1646 }; 1647 1648 tsadc { 1649 tsadc_otp_pin: tsadc-otp-pin { 1650 rockchip,pins = 1651 <0 RK_PB2 0 &pcfg_pull_none>; 1652 }; 1653 1654 tsadc_otp_out: tsadc-otp-out { 1655 rockchip,pins = 1656 <0 RK_PB2 1 &pcfg_pull_none>; 1657 }; 1658 }; 1659 1660 uart0 { 1661 uart0_xfer: uart0-xfer { 1662 rockchip,pins = 1663 <2 RK_PA1 1 &pcfg_pull_up>, 1664 <2 RK_PA0 1 &pcfg_pull_up>; 1665 }; 1666 1667 uart0_cts: uart0-cts { 1668 rockchip,pins = 1669 <2 RK_PA2 1 &pcfg_pull_none>; 1670 }; 1671 1672 uart0_rts: uart0-rts { 1673 rockchip,pins = 1674 <2 RK_PA3 1 &pcfg_pull_none>; 1675 }; 1676 1677 uart0_rts_pin: uart0-rts-pin { 1678 rockchip,pins = 1679 <2 RK_PA3 0 &pcfg_pull_none>; 1680 }; 1681 }; 1682 1683 uart1 { 1684 uart1_xfer: uart1-xfer { 1685 rockchip,pins = 1686 <1 RK_PD1 1 &pcfg_pull_up>, 1687 <1 RK_PD0 1 &pcfg_pull_up>; 1688 }; 1689 1690 uart1_cts: uart1-cts { 1691 rockchip,pins = 1692 <1 RK_PC6 1 &pcfg_pull_none>; 1693 }; 1694 1695 uart1_rts: uart1-rts { 1696 rockchip,pins = 1697 <1 RK_PC7 1 &pcfg_pull_none>; 1698 }; 1699 }; 1700 1701 uart2-m0 { 1702 uart2m0_xfer: uart2m0-xfer { 1703 rockchip,pins = 1704 <1 RK_PC7 2 &pcfg_pull_up>, 1705 <1 RK_PC6 2 &pcfg_pull_up>; 1706 }; 1707 }; 1708 1709 uart2-m1 { 1710 uart2m1_xfer: uart2m1-xfer { 1711 rockchip,pins = 1712 <4 RK_PD3 2 &pcfg_pull_up>, 1713 <4 RK_PD2 2 &pcfg_pull_up>; 1714 }; 1715 }; 1716 1717 uart3 { 1718 uart3_xfer: uart3-xfer { 1719 rockchip,pins = 1720 <3 RK_PB5 4 &pcfg_pull_up>, 1721 <3 RK_PB4 4 &pcfg_pull_up>; 1722 }; 1723 }; 1724 1725 uart3-m1 { 1726 uart3m1_xfer: uart3m1-xfer { 1727 rockchip,pins = 1728 <0 RK_PC2 3 &pcfg_pull_up>, 1729 <0 RK_PC1 3 &pcfg_pull_up>; 1730 }; 1731 }; 1732 1733 uart4 { 1734 uart4_xfer: uart4-xfer { 1735 rockchip,pins = 1736 <4 RK_PB1 1 &pcfg_pull_up>, 1737 <4 RK_PB0 1 &pcfg_pull_up>; 1738 }; 1739 1740 uart4_cts: uart4-cts { 1741 rockchip,pins = 1742 <4 RK_PA6 1 &pcfg_pull_none>; 1743 }; 1744 1745 uart4_rts: uart4-rts { 1746 rockchip,pins = 1747 <4 RK_PA7 1 &pcfg_pull_none>; 1748 }; 1749 1750 uart4_rts_pin: uart4-rts-pin { 1751 rockchip,pins = 1752 <4 RK_PA7 0 &pcfg_pull_none>; 1753 }; 1754 }; 1755 }; 1756}; 1757