1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7#include <dt-bindings/clock/rk3308-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3308"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 serial3 = &uart3; 31 serial4 = &uart4; 32 spi0 = &spi0; 33 spi1 = &spi1; 34 spi2 = &spi2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 clocks = <&cru ARMCLK>; 47 #cooling-cells = <2>; 48 dynamic-power-coefficient = <90>; 49 operating-points-v2 = <&cpu0_opp_table>; 50 cpu-idle-states = <&CPU_SLEEP>; 51 next-level-cache = <&l2>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 cpu-idle-states = <&CPU_SLEEP>; 61 next-level-cache = <&l2>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a35"; 67 reg = <0x0 0x2>; 68 enable-method = "psci"; 69 operating-points-v2 = <&cpu0_opp_table>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 next-level-cache = <&l2>; 72 }; 73 74 cpu3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a35"; 77 reg = <0x0 0x3>; 78 enable-method = "psci"; 79 operating-points-v2 = <&cpu0_opp_table>; 80 cpu-idle-states = <&CPU_SLEEP>; 81 next-level-cache = <&l2>; 82 }; 83 84 idle-states { 85 entry-method = "psci"; 86 87 CPU_SLEEP: cpu-sleep { 88 compatible = "arm,idle-state"; 89 local-timer-stop; 90 arm,psci-suspend-param = <0x0010000>; 91 entry-latency-us = <120>; 92 exit-latency-us = <250>; 93 min-residency-us = <900>; 94 }; 95 }; 96 97 l2: l2-cache { 98 compatible = "cache"; 99 }; 100 }; 101 102 cpu0_opp_table: cpu0-opp-table { 103 compatible = "operating-points-v2"; 104 opp-shared; 105 106 opp-408000000 { 107 opp-hz = /bits/ 64 <408000000>; 108 opp-microvolt = <950000 950000 1340000>; 109 clock-latency-ns = <40000>; 110 opp-suspend; 111 }; 112 opp-600000000 { 113 opp-hz = /bits/ 64 <600000000>; 114 opp-microvolt = <950000 950000 1340000>; 115 clock-latency-ns = <40000>; 116 }; 117 opp-816000000 { 118 opp-hz = /bits/ 64 <816000000>; 119 opp-microvolt = <1025000 1025000 1340000>; 120 clock-latency-ns = <40000>; 121 }; 122 opp-1008000000 { 123 opp-hz = /bits/ 64 <1008000000>; 124 opp-microvolt = <1125000 1125000 1340000>; 125 clock-latency-ns = <40000>; 126 }; 127 }; 128 129 arm-pmu { 130 compatible = "arm,cortex-a35-pmu"; 131 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 136 }; 137 138 mac_clkin: external-mac-clock { 139 compatible = "fixed-clock"; 140 clock-frequency = <50000000>; 141 clock-output-names = "mac_clkin"; 142 #clock-cells = <0>; 143 }; 144 145 psci { 146 compatible = "arm,psci-1.0"; 147 method = "smc"; 148 }; 149 150 timer { 151 compatible = "arm,armv8-timer"; 152 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 153 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 154 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 155 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 156 }; 157 158 xin24m: xin24m { 159 compatible = "fixed-clock"; 160 #clock-cells = <0>; 161 clock-frequency = <24000000>; 162 clock-output-names = "xin24m"; 163 }; 164 165 grf: grf@ff000000 { 166 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 167 reg = <0x0 0xff000000 0x0 0x08000>; 168 169 reboot-mode { 170 compatible = "syscon-reboot-mode"; 171 offset = <0x500>; 172 mode-bootloader = <BOOT_BL_DOWNLOAD>; 173 mode-loader = <BOOT_BL_DOWNLOAD>; 174 mode-normal = <BOOT_NORMAL>; 175 mode-recovery = <BOOT_RECOVERY>; 176 mode-fastboot = <BOOT_FASTBOOT>; 177 }; 178 }; 179 180 usb2phy_grf: syscon@ff008000 { 181 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; 182 reg = <0x0 0xff008000 0x0 0x4000>; 183 #address-cells = <1>; 184 #size-cells = <1>; 185 186 u2phy: usb2phy@100 { 187 compatible = "rockchip,rk3308-usb2phy"; 188 reg = <0x100 0x10>; 189 assigned-clocks = <&cru USB480M>; 190 assigned-clock-parents = <&u2phy>; 191 clocks = <&cru SCLK_USBPHY_REF>; 192 clock-names = "phyclk"; 193 clock-output-names = "usb480m_phy"; 194 #clock-cells = <0>; 195 status = "disabled"; 196 197 u2phy_otg: otg-port { 198 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 201 interrupt-names = "otg-bvalid", "otg-id", 202 "linestate"; 203 #phy-cells = <0>; 204 status = "disabled"; 205 }; 206 207 u2phy_host: host-port { 208 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 209 interrupt-names = "linestate"; 210 #phy-cells = <0>; 211 status = "disabled"; 212 }; 213 }; 214 }; 215 216 detect_grf: syscon@ff00b000 { 217 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; 218 reg = <0x0 0xff00b000 0x0 0x1000>; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 }; 222 223 core_grf: syscon@ff00c000 { 224 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; 225 reg = <0x0 0xff00c000 0x0 0x1000>; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 }; 229 230 i2c0: i2c@ff040000 { 231 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 232 reg = <0x0 0xff040000 0x0 0x1000>; 233 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 234 clock-names = "i2c", "pclk"; 235 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&i2c0_xfer>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 i2c1: i2c@ff050000 { 244 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 245 reg = <0x0 0xff050000 0x0 0x1000>; 246 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 247 clock-names = "i2c", "pclk"; 248 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&i2c1_xfer>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 status = "disabled"; 254 }; 255 256 i2c2: i2c@ff060000 { 257 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 258 reg = <0x0 0xff060000 0x0 0x1000>; 259 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 260 clock-names = "i2c", "pclk"; 261 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&i2c2_xfer>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 status = "disabled"; 267 }; 268 269 i2c3: i2c@ff070000 { 270 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 271 reg = <0x0 0xff070000 0x0 0x1000>; 272 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 273 clock-names = "i2c", "pclk"; 274 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&i2c3m0_xfer>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 status = "disabled"; 280 }; 281 282 wdt: watchdog@ff080000 { 283 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; 284 reg = <0x0 0xff080000 0x0 0x100>; 285 clocks = <&cru PCLK_WDT>; 286 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 287 status = "disabled"; 288 }; 289 290 uart0: serial@ff0a0000 { 291 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 292 reg = <0x0 0xff0a0000 0x0 0x100>; 293 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 295 clock-names = "baudclk", "apb_pclk"; 296 reg-shift = <2>; 297 reg-io-width = <4>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 300 status = "disabled"; 301 }; 302 303 uart1: serial@ff0b0000 { 304 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 305 reg = <0x0 0xff0b0000 0x0 0x100>; 306 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 308 clock-names = "baudclk", "apb_pclk"; 309 reg-shift = <2>; 310 reg-io-width = <4>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 313 status = "disabled"; 314 }; 315 316 uart2: serial@ff0c0000 { 317 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 318 reg = <0x0 0xff0c0000 0x0 0x100>; 319 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 321 clock-names = "baudclk", "apb_pclk"; 322 reg-shift = <2>; 323 reg-io-width = <4>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&uart2m0_xfer>; 326 status = "disabled"; 327 }; 328 329 uart3: serial@ff0d0000 { 330 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 331 reg = <0x0 0xff0d0000 0x0 0x100>; 332 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 334 clock-names = "baudclk", "apb_pclk"; 335 reg-shift = <2>; 336 reg-io-width = <4>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&uart3_xfer>; 339 status = "disabled"; 340 }; 341 342 uart4: serial@ff0e0000 { 343 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 344 reg = <0x0 0xff0e0000 0x0 0x100>; 345 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 347 clock-names = "baudclk", "apb_pclk"; 348 reg-shift = <2>; 349 reg-io-width = <4>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 352 status = "disabled"; 353 }; 354 355 spi0: spi@ff120000 { 356 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 357 reg = <0x0 0xff120000 0x0 0x1000>; 358 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 362 clock-names = "spiclk", "apb_pclk"; 363 dmas = <&dmac0 0>, <&dmac0 1>; 364 dma-names = "tx", "rx"; 365 pinctrl-names = "default"; 366 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; 367 status = "disabled"; 368 }; 369 370 spi1: spi@ff130000 { 371 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 372 reg = <0x0 0xff130000 0x0 0x1000>; 373 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 377 clock-names = "spiclk", "apb_pclk"; 378 dmas = <&dmac0 2>, <&dmac0 3>; 379 dma-names = "tx", "rx"; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; 382 status = "disabled"; 383 }; 384 385 spi2: spi@ff140000 { 386 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 387 reg = <0x0 0xff140000 0x0 0x1000>; 388 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 392 clock-names = "spiclk", "apb_pclk"; 393 dmas = <&dmac1 16>, <&dmac1 17>; 394 dma-names = "tx", "rx"; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; 397 status = "disabled"; 398 }; 399 400 pwm8: pwm@ff160000 { 401 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 402 reg = <0x0 0xff160000 0x0 0x10>; 403 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 404 clock-names = "pwm", "pclk"; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&pwm8_pin>; 407 #pwm-cells = <3>; 408 status = "disabled"; 409 }; 410 411 pwm9: pwm@ff160010 { 412 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 413 reg = <0x0 0xff160010 0x0 0x10>; 414 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 415 clock-names = "pwm", "pclk"; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pwm9_pin>; 418 #pwm-cells = <3>; 419 status = "disabled"; 420 }; 421 422 pwm10: pwm@ff160020 { 423 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 424 reg = <0x0 0xff160020 0x0 0x10>; 425 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 426 clock-names = "pwm", "pclk"; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&pwm10_pin>; 429 #pwm-cells = <3>; 430 status = "disabled"; 431 }; 432 433 pwm11: pwm@ff160030 { 434 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 435 reg = <0x0 0xff160030 0x0 0x10>; 436 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 437 clock-names = "pwm", "pclk"; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&pwm11_pin>; 440 #pwm-cells = <3>; 441 status = "disabled"; 442 }; 443 444 pwm4: pwm@ff170000 { 445 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 446 reg = <0x0 0xff170000 0x0 0x10>; 447 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 448 clock-names = "pwm", "pclk"; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pwm4_pin>; 451 #pwm-cells = <3>; 452 status = "disabled"; 453 }; 454 455 pwm5: pwm@ff170010 { 456 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 457 reg = <0x0 0xff170010 0x0 0x10>; 458 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 459 clock-names = "pwm", "pclk"; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&pwm5_pin>; 462 #pwm-cells = <3>; 463 status = "disabled"; 464 }; 465 466 pwm6: pwm@ff170020 { 467 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 468 reg = <0x0 0xff170020 0x0 0x10>; 469 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 470 clock-names = "pwm", "pclk"; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&pwm6_pin>; 473 #pwm-cells = <3>; 474 status = "disabled"; 475 }; 476 477 pwm7: pwm@ff170030 { 478 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 479 reg = <0x0 0xff170030 0x0 0x10>; 480 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 481 clock-names = "pwm", "pclk"; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&pwm7_pin>; 484 #pwm-cells = <3>; 485 status = "disabled"; 486 }; 487 488 pwm0: pwm@ff180000 { 489 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 490 reg = <0x0 0xff180000 0x0 0x10>; 491 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 492 clock-names = "pwm", "pclk"; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pwm0_pin>; 495 #pwm-cells = <3>; 496 status = "disabled"; 497 }; 498 499 pwm1: pwm@ff180010 { 500 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 501 reg = <0x0 0xff180010 0x0 0x10>; 502 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 503 clock-names = "pwm", "pclk"; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pwm1_pin>; 506 #pwm-cells = <3>; 507 status = "disabled"; 508 }; 509 510 pwm2: pwm@ff180020 { 511 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 512 reg = <0x0 0xff180020 0x0 0x10>; 513 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 514 clock-names = "pwm", "pclk"; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&pwm2_pin>; 517 #pwm-cells = <3>; 518 status = "disabled"; 519 }; 520 521 pwm3: pwm@ff180030 { 522 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 523 reg = <0x0 0xff180030 0x0 0x10>; 524 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 525 clock-names = "pwm", "pclk"; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&pwm3_pin>; 528 #pwm-cells = <3>; 529 status = "disabled"; 530 }; 531 532 rktimer: rktimer@ff1a0000 { 533 compatible = "rockchip,rk3288-timer"; 534 reg = <0x0 0xff1a0000 0x0 0x20>; 535 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 537 clock-names = "pclk", "timer"; 538 }; 539 540 saradc: saradc@ff1e0000 { 541 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 542 reg = <0x0 0xff1e0000 0x0 0x100>; 543 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 545 clock-names = "saradc", "apb_pclk"; 546 #io-channel-cells = <1>; 547 resets = <&cru SRST_SARADC_P>; 548 reset-names = "saradc-apb"; 549 status = "disabled"; 550 }; 551 552 dmac0: dma-controller@ff2c0000 { 553 compatible = "arm,pl330", "arm,primecell"; 554 reg = <0x0 0xff2c0000 0x0 0x4000>; 555 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 557 arm,pl330-periph-burst; 558 clocks = <&cru ACLK_DMAC0>; 559 clock-names = "apb_pclk"; 560 #dma-cells = <1>; 561 }; 562 563 dmac1: dma-controller@ff2d0000 { 564 compatible = "arm,pl330", "arm,primecell"; 565 reg = <0x0 0xff2d0000 0x0 0x4000>; 566 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 568 arm,pl330-periph-burst; 569 clocks = <&cru ACLK_DMAC1>; 570 clock-names = "apb_pclk"; 571 #dma-cells = <1>; 572 }; 573 574 i2s_2ch_0: i2s@ff350000 { 575 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 576 reg = <0x0 0xff350000 0x0 0x1000>; 577 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; 579 clock-names = "i2s_clk", "i2s_hclk"; 580 dmas = <&dmac1 8>, <&dmac1 9>; 581 dma-names = "tx", "rx"; 582 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; 583 reset-names = "reset-m", "reset-h"; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&i2s_2ch_0_sclk 586 &i2s_2ch_0_lrck 587 &i2s_2ch_0_sdi 588 &i2s_2ch_0_sdo>; 589 status = "disabled"; 590 }; 591 592 i2s_2ch_1: i2s@ff360000 { 593 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 594 reg = <0x0 0xff360000 0x0 0x1000>; 595 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 597 clock-names = "i2s_clk", "i2s_hclk"; 598 dmas = <&dmac1 11>; 599 dma-names = "rx"; 600 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; 601 reset-names = "reset-m", "reset-h"; 602 status = "disabled"; 603 }; 604 605 spdif_tx: spdif-tx@ff3a0000 { 606 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; 607 reg = <0x0 0xff3a0000 0x0 0x1000>; 608 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; 610 clock-names = "mclk", "hclk"; 611 dmas = <&dmac1 13>; 612 dma-names = "tx"; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&spdif_out>; 615 status = "disabled"; 616 }; 617 618 usb20_otg: usb@ff400000 { 619 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 620 "snps,dwc2"; 621 reg = <0x0 0xff400000 0x0 0x40000>; 622 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&cru HCLK_OTG>; 624 clock-names = "otg"; 625 dr_mode = "otg"; 626 g-np-tx-fifo-size = <16>; 627 g-rx-fifo-size = <280>; 628 g-tx-fifo-size = <256 128 128 64 32 16>; 629 phys = <&u2phy_otg>; 630 phy-names = "usb2-phy"; 631 status = "disabled"; 632 }; 633 634 usb_host_ehci: usb@ff440000 { 635 compatible = "generic-ehci"; 636 reg = <0x0 0xff440000 0x0 0x10000>; 637 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; 639 phys = <&u2phy_host>; 640 phy-names = "usb"; 641 status = "disabled"; 642 }; 643 644 usb_host_ohci: usb@ff450000 { 645 compatible = "generic-ohci"; 646 reg = <0x0 0xff450000 0x0 0x10000>; 647 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; 649 phys = <&u2phy_host>; 650 phy-names = "usb"; 651 status = "disabled"; 652 }; 653 654 sdmmc: mmc@ff480000 { 655 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 656 reg = <0x0 0xff480000 0x0 0x4000>; 657 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 658 bus-width = <4>; 659 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 660 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 661 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 662 fifo-depth = <0x100>; 663 max-frequency = <150000000>; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 666 status = "disabled"; 667 }; 668 669 emmc: mmc@ff490000 { 670 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 671 reg = <0x0 0xff490000 0x0 0x4000>; 672 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 673 bus-width = <8>; 674 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 675 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 676 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 677 fifo-depth = <0x100>; 678 max-frequency = <150000000>; 679 status = "disabled"; 680 }; 681 682 sdio: mmc@ff4a0000 { 683 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 684 reg = <0x0 0xff4a0000 0x0 0x4000>; 685 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 686 bus-width = <4>; 687 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 688 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 689 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 690 fifo-depth = <0x100>; 691 max-frequency = <150000000>; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 694 status = "disabled"; 695 }; 696 697 nfc: nand-controller@ff4b0000 { 698 compatible = "rockchip,rk3308-nfc", 699 "rockchip,rv1108-nfc"; 700 reg = <0x0 0xff4b0000 0x0 0x4000>; 701 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 703 clock-names = "ahb", "nfc"; 704 assigned-clocks = <&cru SCLK_NANDC>; 705 assigned-clock-rates = <150000000>; 706 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 707 &flash_rdn &flash_rdy &flash_wrn>; 708 pinctrl-names = "default"; 709 status = "disabled"; 710 }; 711 712 cru: clock-controller@ff500000 { 713 compatible = "rockchip,rk3308-cru"; 714 reg = <0x0 0xff500000 0x0 0x1000>; 715 #clock-cells = <1>; 716 #reset-cells = <1>; 717 rockchip,grf = <&grf>; 718 719 assigned-clocks = <&cru SCLK_RTC32K>; 720 assigned-clock-rates = <32768>; 721 }; 722 723 gic: interrupt-controller@ff580000 { 724 compatible = "arm,gic-400"; 725 reg = <0x0 0xff581000 0x0 0x1000>, 726 <0x0 0xff582000 0x0 0x2000>, 727 <0x0 0xff584000 0x0 0x2000>, 728 <0x0 0xff586000 0x0 0x2000>; 729 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 730 #interrupt-cells = <3>; 731 interrupt-controller; 732 #address-cells = <0>; 733 }; 734 735 sram: sram@fff80000 { 736 compatible = "mmio-sram"; 737 reg = <0x0 0xfff80000 0x0 0x40000>; 738 ranges = <0 0x0 0xfff80000 0x40000>; 739 #address-cells = <1>; 740 #size-cells = <1>; 741 742 /* reserved for ddr dvfs and system suspend/resume */ 743 ddr-sram@0 { 744 reg = <0x0 0x8000>; 745 }; 746 747 /* reserved for vad audio buffer */ 748 vad_sram: vad-sram@8000 { 749 reg = <0x8000 0x38000>; 750 }; 751 }; 752 753 pinctrl: pinctrl { 754 compatible = "rockchip,rk3308-pinctrl"; 755 rockchip,grf = <&grf>; 756 #address-cells = <2>; 757 #size-cells = <2>; 758 ranges; 759 760 gpio0: gpio0@ff220000 { 761 compatible = "rockchip,gpio-bank"; 762 reg = <0x0 0xff220000 0x0 0x100>; 763 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&cru PCLK_GPIO0>; 765 gpio-controller; 766 #gpio-cells = <2>; 767 interrupt-controller; 768 #interrupt-cells = <2>; 769 }; 770 771 gpio1: gpio1@ff230000 { 772 compatible = "rockchip,gpio-bank"; 773 reg = <0x0 0xff230000 0x0 0x100>; 774 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&cru PCLK_GPIO1>; 776 gpio-controller; 777 #gpio-cells = <2>; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 782 gpio2: gpio2@ff240000 { 783 compatible = "rockchip,gpio-bank"; 784 reg = <0x0 0xff240000 0x0 0x100>; 785 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&cru PCLK_GPIO2>; 787 gpio-controller; 788 #gpio-cells = <2>; 789 interrupt-controller; 790 #interrupt-cells = <2>; 791 }; 792 793 gpio3: gpio3@ff250000 { 794 compatible = "rockchip,gpio-bank"; 795 reg = <0x0 0xff250000 0x0 0x100>; 796 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cru PCLK_GPIO3>; 798 gpio-controller; 799 #gpio-cells = <2>; 800 interrupt-controller; 801 #interrupt-cells = <2>; 802 }; 803 804 gpio4: gpio4@ff260000 { 805 compatible = "rockchip,gpio-bank"; 806 reg = <0x0 0xff260000 0x0 0x100>; 807 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&cru PCLK_GPIO4>; 809 gpio-controller; 810 #gpio-cells = <2>; 811 interrupt-controller; 812 #interrupt-cells = <2>; 813 }; 814 815 pcfg_pull_up: pcfg-pull-up { 816 bias-pull-up; 817 }; 818 819 pcfg_pull_down: pcfg-pull-down { 820 bias-pull-down; 821 }; 822 823 pcfg_pull_none: pcfg-pull-none { 824 bias-disable; 825 }; 826 827 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 828 bias-disable; 829 drive-strength = <2>; 830 }; 831 832 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 833 bias-pull-up; 834 drive-strength = <2>; 835 }; 836 837 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 838 bias-pull-up; 839 drive-strength = <4>; 840 }; 841 842 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 843 bias-disable; 844 drive-strength = <4>; 845 }; 846 847 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 848 bias-pull-down; 849 drive-strength = <4>; 850 }; 851 852 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 853 bias-disable; 854 drive-strength = <8>; 855 }; 856 857 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 858 bias-pull-up; 859 drive-strength = <8>; 860 }; 861 862 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 863 bias-disable; 864 drive-strength = <12>; 865 }; 866 867 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 868 bias-pull-up; 869 drive-strength = <12>; 870 }; 871 872 pcfg_pull_none_smt: pcfg-pull-none-smt { 873 bias-disable; 874 input-schmitt-enable; 875 }; 876 877 pcfg_output_high: pcfg-output-high { 878 output-high; 879 }; 880 881 pcfg_output_low: pcfg-output-low { 882 output-low; 883 }; 884 885 pcfg_input_high: pcfg-input-high { 886 bias-pull-up; 887 input-enable; 888 }; 889 890 pcfg_input: pcfg-input { 891 input-enable; 892 }; 893 894 emmc { 895 emmc_clk: emmc-clk { 896 rockchip,pins = 897 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 898 }; 899 900 emmc_cmd: emmc-cmd { 901 rockchip,pins = 902 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 903 }; 904 905 emmc_pwren: emmc-pwren { 906 rockchip,pins = 907 <3 RK_PB3 2 &pcfg_pull_none>; 908 }; 909 910 emmc_rstn: emmc-rstn { 911 rockchip,pins = 912 <3 RK_PB2 2 &pcfg_pull_none>; 913 }; 914 915 emmc_bus1: emmc-bus1 { 916 rockchip,pins = 917 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 918 }; 919 920 emmc_bus4: emmc-bus4 { 921 rockchip,pins = 922 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 923 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 924 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 925 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 926 }; 927 928 emmc_bus8: emmc-bus8 { 929 rockchip,pins = 930 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 931 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 932 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 933 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 934 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 935 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 936 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 937 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 938 }; 939 }; 940 941 flash { 942 flash_csn0: flash-csn0 { 943 rockchip,pins = 944 <3 RK_PB5 1 &pcfg_pull_none>; 945 }; 946 947 flash_rdy: flash-rdy { 948 rockchip,pins = 949 <3 RK_PB4 1 &pcfg_pull_none>; 950 }; 951 952 flash_ale: flash-ale { 953 rockchip,pins = 954 <3 RK_PB3 1 &pcfg_pull_none>; 955 }; 956 957 flash_cle: flash-cle { 958 rockchip,pins = 959 <3 RK_PB1 1 &pcfg_pull_none>; 960 }; 961 962 flash_wrn: flash-wrn { 963 rockchip,pins = 964 <3 RK_PB0 1 &pcfg_pull_none>; 965 }; 966 967 flash_rdn: flash-rdn { 968 rockchip,pins = 969 <3 RK_PB2 1 &pcfg_pull_none>; 970 }; 971 972 flash_bus8: flash-bus8 { 973 rockchip,pins = 974 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 975 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 976 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 977 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 978 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 979 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 980 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 981 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 982 }; 983 }; 984 985 gmac { 986 rmii_pins: rmii-pins { 987 rockchip,pins = 988 /* mac_txen */ 989 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 990 /* mac_txd1 */ 991 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 992 /* mac_txd0 */ 993 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 994 /* mac_rxd0 */ 995 <1 RK_PC4 3 &pcfg_pull_none>, 996 /* mac_rxd1 */ 997 <1 RK_PC5 3 &pcfg_pull_none>, 998 /* mac_rxer */ 999 <1 RK_PB7 3 &pcfg_pull_none>, 1000 /* mac_rxdv */ 1001 <1 RK_PC0 3 &pcfg_pull_none>, 1002 /* mac_mdio */ 1003 <1 RK_PB6 3 &pcfg_pull_none>, 1004 /* mac_mdc */ 1005 <1 RK_PB5 3 &pcfg_pull_none>; 1006 }; 1007 1008 mac_refclk_12ma: mac-refclk-12ma { 1009 rockchip,pins = 1010 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 1011 }; 1012 1013 mac_refclk: mac-refclk { 1014 rockchip,pins = 1015 <1 RK_PB4 3 &pcfg_pull_none>; 1016 }; 1017 }; 1018 1019 gmac-m1 { 1020 rmiim1_pins: rmiim1-pins { 1021 rockchip,pins = 1022 /* mac_txen */ 1023 <4 RK_PB7 2 &pcfg_pull_none_12ma>, 1024 /* mac_txd1 */ 1025 <4 RK_PA5 2 &pcfg_pull_none_12ma>, 1026 /* mac_txd0 */ 1027 <4 RK_PA4 2 &pcfg_pull_none_12ma>, 1028 /* mac_rxd0 */ 1029 <4 RK_PA2 2 &pcfg_pull_none>, 1030 /* mac_rxd1 */ 1031 <4 RK_PA3 2 &pcfg_pull_none>, 1032 /* mac_rxer */ 1033 <4 RK_PA0 2 &pcfg_pull_none>, 1034 /* mac_rxdv */ 1035 <4 RK_PA1 2 &pcfg_pull_none>, 1036 /* mac_mdio */ 1037 <4 RK_PB6 2 &pcfg_pull_none>, 1038 /* mac_mdc */ 1039 <4 RK_PB5 2 &pcfg_pull_none>; 1040 }; 1041 1042 macm1_refclk_12ma: macm1-refclk-12ma { 1043 rockchip,pins = 1044 <4 RK_PB4 2 &pcfg_pull_none_12ma>; 1045 }; 1046 1047 macm1_refclk: macm1-refclk { 1048 rockchip,pins = 1049 <4 RK_PB4 2 &pcfg_pull_none>; 1050 }; 1051 }; 1052 1053 i2c0 { 1054 i2c0_xfer: i2c0-xfer { 1055 rockchip,pins = 1056 <1 RK_PD0 2 &pcfg_pull_none_smt>, 1057 <1 RK_PD1 2 &pcfg_pull_none_smt>; 1058 }; 1059 }; 1060 1061 i2c1 { 1062 i2c1_xfer: i2c1-xfer { 1063 rockchip,pins = 1064 <0 RK_PB3 1 &pcfg_pull_none_smt>, 1065 <0 RK_PB4 1 &pcfg_pull_none_smt>; 1066 }; 1067 }; 1068 1069 i2c2 { 1070 i2c2_xfer: i2c2-xfer { 1071 rockchip,pins = 1072 <2 RK_PA2 3 &pcfg_pull_none_smt>, 1073 <2 RK_PA3 3 &pcfg_pull_none_smt>; 1074 }; 1075 }; 1076 1077 i2c3-m0 { 1078 i2c3m0_xfer: i2c3m0-xfer { 1079 rockchip,pins = 1080 <0 RK_PB7 2 &pcfg_pull_none_smt>, 1081 <0 RK_PC0 2 &pcfg_pull_none_smt>; 1082 }; 1083 }; 1084 1085 i2c3-m1 { 1086 i2c3m1_xfer: i2c3m1-xfer { 1087 rockchip,pins = 1088 <3 RK_PB4 2 &pcfg_pull_none_smt>, 1089 <3 RK_PB5 2 &pcfg_pull_none_smt>; 1090 }; 1091 }; 1092 1093 i2c3-m2 { 1094 i2c3m2_xfer: i2c3m2-xfer { 1095 rockchip,pins = 1096 <2 RK_PA1 3 &pcfg_pull_none_smt>, 1097 <2 RK_PA0 3 &pcfg_pull_none_smt>; 1098 }; 1099 }; 1100 1101 i2s_2ch_0 { 1102 i2s_2ch_0_mclk: i2s-2ch-0-mclk { 1103 rockchip,pins = 1104 <4 RK_PB4 1 &pcfg_pull_none>; 1105 }; 1106 1107 i2s_2ch_0_sclk: i2s-2ch-0-sclk { 1108 rockchip,pins = 1109 <4 RK_PB5 1 &pcfg_pull_none>; 1110 }; 1111 1112 i2s_2ch_0_lrck: i2s-2ch-0-lrck { 1113 rockchip,pins = 1114 <4 RK_PB6 1 &pcfg_pull_none>; 1115 }; 1116 1117 i2s_2ch_0_sdo: i2s-2ch-0-sdo { 1118 rockchip,pins = 1119 <4 RK_PB7 1 &pcfg_pull_none>; 1120 }; 1121 1122 i2s_2ch_0_sdi: i2s-2ch-0-sdi { 1123 rockchip,pins = 1124 <4 RK_PC0 1 &pcfg_pull_none>; 1125 }; 1126 }; 1127 1128 i2s_8ch_0 { 1129 i2s_8ch_0_mclk: i2s-8ch-0-mclk { 1130 rockchip,pins = 1131 <2 RK_PA4 1 &pcfg_pull_none>; 1132 }; 1133 1134 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { 1135 rockchip,pins = 1136 <2 RK_PA5 1 &pcfg_pull_none>; 1137 }; 1138 1139 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { 1140 rockchip,pins = 1141 <2 RK_PA6 1 &pcfg_pull_none>; 1142 }; 1143 1144 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { 1145 rockchip,pins = 1146 <2 RK_PA7 1 &pcfg_pull_none>; 1147 }; 1148 1149 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { 1150 rockchip,pins = 1151 <2 RK_PB0 1 &pcfg_pull_none>; 1152 }; 1153 1154 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { 1155 rockchip,pins = 1156 <2 RK_PB1 1 &pcfg_pull_none>; 1157 }; 1158 1159 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { 1160 rockchip,pins = 1161 <2 RK_PB2 1 &pcfg_pull_none>; 1162 }; 1163 1164 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { 1165 rockchip,pins = 1166 <2 RK_PB3 1 &pcfg_pull_none>; 1167 }; 1168 1169 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { 1170 rockchip,pins = 1171 <2 RK_PB4 1 &pcfg_pull_none>; 1172 }; 1173 1174 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { 1175 rockchip,pins = 1176 <2 RK_PB5 1 &pcfg_pull_none>; 1177 }; 1178 1179 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { 1180 rockchip,pins = 1181 <2 RK_PB6 1 &pcfg_pull_none>; 1182 }; 1183 1184 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { 1185 rockchip,pins = 1186 <2 RK_PB7 1 &pcfg_pull_none>; 1187 }; 1188 1189 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { 1190 rockchip,pins = 1191 <2 RK_PC0 1 &pcfg_pull_none>; 1192 }; 1193 }; 1194 1195 i2s_8ch_1_m0 { 1196 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { 1197 rockchip,pins = 1198 <1 RK_PA2 2 &pcfg_pull_none>; 1199 }; 1200 1201 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { 1202 rockchip,pins = 1203 <1 RK_PA3 2 &pcfg_pull_none>; 1204 }; 1205 1206 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { 1207 rockchip,pins = 1208 <1 RK_PA4 2 &pcfg_pull_none>; 1209 }; 1210 1211 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { 1212 rockchip,pins = 1213 <1 RK_PA5 2 &pcfg_pull_none>; 1214 }; 1215 1216 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { 1217 rockchip,pins = 1218 <1 RK_PA6 2 &pcfg_pull_none>; 1219 }; 1220 1221 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { 1222 rockchip,pins = 1223 <1 RK_PA7 2 &pcfg_pull_none>; 1224 }; 1225 1226 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { 1227 rockchip,pins = 1228 <1 RK_PB0 2 &pcfg_pull_none>; 1229 }; 1230 1231 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { 1232 rockchip,pins = 1233 <1 RK_PB1 2 &pcfg_pull_none>; 1234 }; 1235 1236 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { 1237 rockchip,pins = 1238 <1 RK_PB2 2 &pcfg_pull_none>; 1239 }; 1240 1241 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { 1242 rockchip,pins = 1243 <1 RK_PB3 2 &pcfg_pull_none>; 1244 }; 1245 }; 1246 1247 i2s_8ch_1_m1 { 1248 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { 1249 rockchip,pins = 1250 <1 RK_PB4 2 &pcfg_pull_none>; 1251 }; 1252 1253 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { 1254 rockchip,pins = 1255 <1 RK_PB5 2 &pcfg_pull_none>; 1256 }; 1257 1258 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { 1259 rockchip,pins = 1260 <1 RK_PB6 2 &pcfg_pull_none>; 1261 }; 1262 1263 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { 1264 rockchip,pins = 1265 <1 RK_PB7 2 &pcfg_pull_none>; 1266 }; 1267 1268 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { 1269 rockchip,pins = 1270 <1 RK_PC0 2 &pcfg_pull_none>; 1271 }; 1272 1273 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { 1274 rockchip,pins = 1275 <1 RK_PC1 2 &pcfg_pull_none>; 1276 }; 1277 1278 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { 1279 rockchip,pins = 1280 <1 RK_PC2 2 &pcfg_pull_none>; 1281 }; 1282 1283 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { 1284 rockchip,pins = 1285 <1 RK_PC3 2 &pcfg_pull_none>; 1286 }; 1287 1288 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { 1289 rockchip,pins = 1290 <1 RK_PC4 2 &pcfg_pull_none>; 1291 }; 1292 1293 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { 1294 rockchip,pins = 1295 <1 RK_PC5 2 &pcfg_pull_none>; 1296 }; 1297 }; 1298 1299 pdm_m0 { 1300 pdm_m0_clk: pdm-m0-clk { 1301 rockchip,pins = 1302 <1 RK_PA4 3 &pcfg_pull_none>; 1303 }; 1304 1305 pdm_m0_sdi0: pdm-m0-sdi0 { 1306 rockchip,pins = 1307 <1 RK_PB3 3 &pcfg_pull_none>; 1308 }; 1309 1310 pdm_m0_sdi1: pdm-m0-sdi1 { 1311 rockchip,pins = 1312 <1 RK_PB2 3 &pcfg_pull_none>; 1313 }; 1314 1315 pdm_m0_sdi2: pdm-m0-sdi2 { 1316 rockchip,pins = 1317 <1 RK_PB1 3 &pcfg_pull_none>; 1318 }; 1319 1320 pdm_m0_sdi3: pdm-m0-sdi3 { 1321 rockchip,pins = 1322 <1 RK_PB0 3 &pcfg_pull_none>; 1323 }; 1324 }; 1325 1326 pdm_m1 { 1327 pdm_m1_clk: pdm-m1-clk { 1328 rockchip,pins = 1329 <1 RK_PB6 4 &pcfg_pull_none>; 1330 }; 1331 1332 pdm_m1_sdi0: pdm-m1-sdi0 { 1333 rockchip,pins = 1334 <1 RK_PC5 4 &pcfg_pull_none>; 1335 }; 1336 1337 pdm_m1_sdi1: pdm-m1-sdi1 { 1338 rockchip,pins = 1339 <1 RK_PC4 4 &pcfg_pull_none>; 1340 }; 1341 1342 pdm_m1_sdi2: pdm-m1-sdi2 { 1343 rockchip,pins = 1344 <1 RK_PC3 4 &pcfg_pull_none>; 1345 }; 1346 1347 pdm_m1_sdi3: pdm-m1-sdi3 { 1348 rockchip,pins = 1349 <1 RK_PC2 4 &pcfg_pull_none>; 1350 }; 1351 }; 1352 1353 pdm_m2 { 1354 pdm_m2_clkm: pdm-m2-clkm { 1355 rockchip,pins = 1356 <2 RK_PA4 3 &pcfg_pull_none>; 1357 }; 1358 1359 pdm_m2_clk: pdm-m2-clk { 1360 rockchip,pins = 1361 <2 RK_PA6 2 &pcfg_pull_none>; 1362 }; 1363 1364 pdm_m2_sdi0: pdm-m2-sdi0 { 1365 rockchip,pins = 1366 <2 RK_PB5 2 &pcfg_pull_none>; 1367 }; 1368 1369 pdm_m2_sdi1: pdm-m2-sdi1 { 1370 rockchip,pins = 1371 <2 RK_PB6 2 &pcfg_pull_none>; 1372 }; 1373 1374 pdm_m2_sdi2: pdm-m2-sdi2 { 1375 rockchip,pins = 1376 <2 RK_PB7 2 &pcfg_pull_none>; 1377 }; 1378 1379 pdm_m2_sdi3: pdm-m2-sdi3 { 1380 rockchip,pins = 1381 <2 RK_PC0 2 &pcfg_pull_none>; 1382 }; 1383 }; 1384 1385 pwm0 { 1386 pwm0_pin: pwm0-pin { 1387 rockchip,pins = 1388 <0 RK_PB5 1 &pcfg_pull_none>; 1389 }; 1390 1391 pwm0_pin_pull_down: pwm0-pin-pull-down { 1392 rockchip,pins = 1393 <0 RK_PB5 1 &pcfg_pull_down>; 1394 }; 1395 }; 1396 1397 pwm1 { 1398 pwm1_pin: pwm1-pin { 1399 rockchip,pins = 1400 <0 RK_PB6 1 &pcfg_pull_none>; 1401 }; 1402 1403 pwm1_pin_pull_down: pwm1-pin-pull-down { 1404 rockchip,pins = 1405 <0 RK_PB6 1 &pcfg_pull_down>; 1406 }; 1407 }; 1408 1409 pwm2 { 1410 pwm2_pin: pwm2-pin { 1411 rockchip,pins = 1412 <0 RK_PB7 1 &pcfg_pull_none>; 1413 }; 1414 1415 pwm2_pin_pull_down: pwm2-pin-pull-down { 1416 rockchip,pins = 1417 <0 RK_PB7 1 &pcfg_pull_down>; 1418 }; 1419 }; 1420 1421 pwm3 { 1422 pwm3_pin: pwm3-pin { 1423 rockchip,pins = 1424 <0 RK_PC0 1 &pcfg_pull_none>; 1425 }; 1426 1427 pwm3_pin_pull_down: pwm3-pin-pull-down { 1428 rockchip,pins = 1429 <0 RK_PC0 1 &pcfg_pull_down>; 1430 }; 1431 }; 1432 1433 pwm4 { 1434 pwm4_pin: pwm4-pin { 1435 rockchip,pins = 1436 <0 RK_PA1 2 &pcfg_pull_none>; 1437 }; 1438 1439 pwm4_pin_pull_down: pwm4-pin-pull-down { 1440 rockchip,pins = 1441 <0 RK_PA1 2 &pcfg_pull_down>; 1442 }; 1443 }; 1444 1445 pwm5 { 1446 pwm5_pin: pwm5-pin { 1447 rockchip,pins = 1448 <0 RK_PC1 2 &pcfg_pull_none>; 1449 }; 1450 1451 pwm5_pin_pull_down: pwm5-pin-pull-down { 1452 rockchip,pins = 1453 <0 RK_PC1 2 &pcfg_pull_down>; 1454 }; 1455 }; 1456 1457 pwm6 { 1458 pwm6_pin: pwm6-pin { 1459 rockchip,pins = 1460 <0 RK_PC2 2 &pcfg_pull_none>; 1461 }; 1462 1463 pwm6_pin_pull_down: pwm6-pin-pull-down { 1464 rockchip,pins = 1465 <0 RK_PC2 2 &pcfg_pull_down>; 1466 }; 1467 }; 1468 1469 pwm7 { 1470 pwm7_pin: pwm7-pin { 1471 rockchip,pins = 1472 <2 RK_PB0 2 &pcfg_pull_none>; 1473 }; 1474 1475 pwm7_pin_pull_down: pwm7-pin-pull-down { 1476 rockchip,pins = 1477 <2 RK_PB0 2 &pcfg_pull_down>; 1478 }; 1479 }; 1480 1481 pwm8 { 1482 pwm8_pin: pwm8-pin { 1483 rockchip,pins = 1484 <2 RK_PB2 2 &pcfg_pull_none>; 1485 }; 1486 1487 pwm8_pin_pull_down: pwm8-pin-pull-down { 1488 rockchip,pins = 1489 <2 RK_PB2 2 &pcfg_pull_down>; 1490 }; 1491 }; 1492 1493 pwm9 { 1494 pwm9_pin: pwm9-pin { 1495 rockchip,pins = 1496 <2 RK_PB3 2 &pcfg_pull_none>; 1497 }; 1498 1499 pwm9_pin_pull_down: pwm9-pin-pull-down { 1500 rockchip,pins = 1501 <2 RK_PB3 2 &pcfg_pull_down>; 1502 }; 1503 }; 1504 1505 pwm10 { 1506 pwm10_pin: pwm10-pin { 1507 rockchip,pins = 1508 <2 RK_PB4 2 &pcfg_pull_none>; 1509 }; 1510 1511 pwm10_pin_pull_down: pwm10-pin-pull-down { 1512 rockchip,pins = 1513 <2 RK_PB4 2 &pcfg_pull_down>; 1514 }; 1515 }; 1516 1517 pwm11 { 1518 pwm11_pin: pwm11-pin { 1519 rockchip,pins = 1520 <2 RK_PC0 4 &pcfg_pull_none>; 1521 }; 1522 1523 pwm11_pin_pull_down: pwm11-pin-pull-down { 1524 rockchip,pins = 1525 <2 RK_PC0 4 &pcfg_pull_down>; 1526 }; 1527 }; 1528 1529 rtc { 1530 rtc_32k: rtc-32k { 1531 rockchip,pins = 1532 <0 RK_PC3 1 &pcfg_pull_none>; 1533 }; 1534 }; 1535 1536 sdmmc { 1537 sdmmc_clk: sdmmc-clk { 1538 rockchip,pins = 1539 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 1540 }; 1541 1542 sdmmc_cmd: sdmmc-cmd { 1543 rockchip,pins = 1544 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 1545 }; 1546 1547 sdmmc_det: sdmmc-det { 1548 rockchip,pins = 1549 <0 RK_PA3 1 &pcfg_pull_up_4ma>; 1550 }; 1551 1552 sdmmc_pwren: sdmmc-pwren { 1553 rockchip,pins = 1554 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 1555 }; 1556 1557 sdmmc_bus1: sdmmc-bus1 { 1558 rockchip,pins = 1559 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 1560 }; 1561 1562 sdmmc_bus4: sdmmc-bus4 { 1563 rockchip,pins = 1564 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 1565 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 1566 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 1567 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 1568 }; 1569 }; 1570 1571 sdio { 1572 sdio_clk: sdio-clk { 1573 rockchip,pins = 1574 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 1575 }; 1576 1577 sdio_cmd: sdio-cmd { 1578 rockchip,pins = 1579 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 1580 }; 1581 1582 sdio_pwren: sdio-pwren { 1583 rockchip,pins = 1584 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 1585 }; 1586 1587 sdio_wrpt: sdio-wrpt { 1588 rockchip,pins = 1589 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 1590 }; 1591 1592 sdio_intn: sdio-intn { 1593 rockchip,pins = 1594 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 1595 }; 1596 1597 sdio_bus1: sdio-bus1 { 1598 rockchip,pins = 1599 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 1600 }; 1601 1602 sdio_bus4: sdio-bus4 { 1603 rockchip,pins = 1604 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 1605 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 1606 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 1607 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 1608 }; 1609 }; 1610 1611 spdif_in { 1612 spdif_in: spdif-in { 1613 rockchip,pins = 1614 <0 RK_PC2 1 &pcfg_pull_none>; 1615 }; 1616 }; 1617 1618 spdif_out { 1619 spdif_out: spdif-out { 1620 rockchip,pins = 1621 <0 RK_PC1 1 &pcfg_pull_none>; 1622 }; 1623 }; 1624 1625 spi0 { 1626 spi0_clk: spi0-clk { 1627 rockchip,pins = 1628 <2 RK_PA2 2 &pcfg_pull_up_4ma>; 1629 }; 1630 1631 spi0_csn0: spi0-csn0 { 1632 rockchip,pins = 1633 <2 RK_PA3 2 &pcfg_pull_up_4ma>; 1634 }; 1635 1636 spi0_miso: spi0-miso { 1637 rockchip,pins = 1638 <2 RK_PA0 2 &pcfg_pull_up_4ma>; 1639 }; 1640 1641 spi0_mosi: spi0-mosi { 1642 rockchip,pins = 1643 <2 RK_PA1 2 &pcfg_pull_up_4ma>; 1644 }; 1645 }; 1646 1647 spi1 { 1648 spi1_clk: spi1-clk { 1649 rockchip,pins = 1650 <3 RK_PB3 3 &pcfg_pull_up_4ma>; 1651 }; 1652 1653 spi1_csn0: spi1-csn0 { 1654 rockchip,pins = 1655 <3 RK_PB5 3 &pcfg_pull_up_4ma>; 1656 }; 1657 1658 spi1_miso: spi1-miso { 1659 rockchip,pins = 1660 <3 RK_PB2 3 &pcfg_pull_up_4ma>; 1661 }; 1662 1663 spi1_mosi: spi1-mosi { 1664 rockchip,pins = 1665 <3 RK_PB4 3 &pcfg_pull_up_4ma>; 1666 }; 1667 }; 1668 1669 spi1-m1 { 1670 spi1m1_miso: spi1m1-miso { 1671 rockchip,pins = 1672 <2 RK_PA4 2 &pcfg_pull_up_4ma>; 1673 }; 1674 1675 spi1m1_mosi: spi1m1-mosi { 1676 rockchip,pins = 1677 <2 RK_PA5 2 &pcfg_pull_up_4ma>; 1678 }; 1679 1680 spi1m1_clk: spi1m1-clk { 1681 rockchip,pins = 1682 <2 RK_PA7 2 &pcfg_pull_up_4ma>; 1683 }; 1684 1685 spi1m1_csn0: spi1m1-csn0 { 1686 rockchip,pins = 1687 <2 RK_PB1 2 &pcfg_pull_up_4ma>; 1688 }; 1689 }; 1690 1691 spi2 { 1692 spi2_clk: spi2-clk { 1693 rockchip,pins = 1694 <1 RK_PD0 3 &pcfg_pull_up_4ma>; 1695 }; 1696 1697 spi2_csn0: spi2-csn0 { 1698 rockchip,pins = 1699 <1 RK_PD1 3 &pcfg_pull_up_4ma>; 1700 }; 1701 1702 spi2_miso: spi2-miso { 1703 rockchip,pins = 1704 <1 RK_PC6 3 &pcfg_pull_up_4ma>; 1705 }; 1706 1707 spi2_mosi: spi2-mosi { 1708 rockchip,pins = 1709 <1 RK_PC7 3 &pcfg_pull_up_4ma>; 1710 }; 1711 }; 1712 1713 tsadc { 1714 tsadc_otp_pin: tsadc-otp-pin { 1715 rockchip,pins = 1716 <0 RK_PB2 0 &pcfg_pull_none>; 1717 }; 1718 1719 tsadc_otp_out: tsadc-otp-out { 1720 rockchip,pins = 1721 <0 RK_PB2 1 &pcfg_pull_none>; 1722 }; 1723 }; 1724 1725 uart0 { 1726 uart0_xfer: uart0-xfer { 1727 rockchip,pins = 1728 <2 RK_PA1 1 &pcfg_pull_up>, 1729 <2 RK_PA0 1 &pcfg_pull_up>; 1730 }; 1731 1732 uart0_cts: uart0-cts { 1733 rockchip,pins = 1734 <2 RK_PA2 1 &pcfg_pull_none>; 1735 }; 1736 1737 uart0_rts: uart0-rts { 1738 rockchip,pins = 1739 <2 RK_PA3 1 &pcfg_pull_none>; 1740 }; 1741 1742 uart0_rts_pin: uart0-rts-pin { 1743 rockchip,pins = 1744 <2 RK_PA3 0 &pcfg_pull_none>; 1745 }; 1746 }; 1747 1748 uart1 { 1749 uart1_xfer: uart1-xfer { 1750 rockchip,pins = 1751 <1 RK_PD1 1 &pcfg_pull_up>, 1752 <1 RK_PD0 1 &pcfg_pull_up>; 1753 }; 1754 1755 uart1_cts: uart1-cts { 1756 rockchip,pins = 1757 <1 RK_PC6 1 &pcfg_pull_none>; 1758 }; 1759 1760 uart1_rts: uart1-rts { 1761 rockchip,pins = 1762 <1 RK_PC7 1 &pcfg_pull_none>; 1763 }; 1764 }; 1765 1766 uart2-m0 { 1767 uart2m0_xfer: uart2m0-xfer { 1768 rockchip,pins = 1769 <1 RK_PC7 2 &pcfg_pull_up>, 1770 <1 RK_PC6 2 &pcfg_pull_up>; 1771 }; 1772 }; 1773 1774 uart2-m1 { 1775 uart2m1_xfer: uart2m1-xfer { 1776 rockchip,pins = 1777 <4 RK_PD3 2 &pcfg_pull_up>, 1778 <4 RK_PD2 2 &pcfg_pull_up>; 1779 }; 1780 }; 1781 1782 uart3 { 1783 uart3_xfer: uart3-xfer { 1784 rockchip,pins = 1785 <3 RK_PB5 4 &pcfg_pull_up>, 1786 <3 RK_PB4 4 &pcfg_pull_up>; 1787 }; 1788 }; 1789 1790 uart3-m1 { 1791 uart3m1_xfer: uart3m1-xfer { 1792 rockchip,pins = 1793 <0 RK_PC2 3 &pcfg_pull_up>, 1794 <0 RK_PC1 3 &pcfg_pull_up>; 1795 }; 1796 }; 1797 1798 uart4 { 1799 uart4_xfer: uart4-xfer { 1800 rockchip,pins = 1801 <4 RK_PB1 1 &pcfg_pull_up>, 1802 <4 RK_PB0 1 &pcfg_pull_up>; 1803 }; 1804 1805 uart4_cts: uart4-cts { 1806 rockchip,pins = 1807 <4 RK_PA6 1 &pcfg_pull_none>; 1808 }; 1809 1810 uart4_rts: uart4-rts { 1811 rockchip,pins = 1812 <4 RK_PA7 1 &pcfg_pull_none>; 1813 }; 1814 1815 uart4_rts_pin: uart4-rts-pin { 1816 rockchip,pins = 1817 <4 RK_PA7 0 &pcfg_pull_none>; 1818 }; 1819 }; 1820 }; 1821}; 1822