1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7#include <dt-bindings/clock/rk3308-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3308"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 serial3 = &uart3; 31 serial4 = &uart4; 32 spi0 = &spi0; 33 spi1 = &spi1; 34 spi2 = &spi2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 clocks = <&cru ARMCLK>; 47 #cooling-cells = <2>; 48 dynamic-power-coefficient = <90>; 49 operating-points-v2 = <&cpu0_opp_table>; 50 cpu-idle-states = <&CPU_SLEEP>; 51 next-level-cache = <&l2>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 cpu-idle-states = <&CPU_SLEEP>; 61 next-level-cache = <&l2>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a35"; 67 reg = <0x0 0x2>; 68 enable-method = "psci"; 69 operating-points-v2 = <&cpu0_opp_table>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 next-level-cache = <&l2>; 72 }; 73 74 cpu3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a35"; 77 reg = <0x0 0x3>; 78 enable-method = "psci"; 79 operating-points-v2 = <&cpu0_opp_table>; 80 cpu-idle-states = <&CPU_SLEEP>; 81 next-level-cache = <&l2>; 82 }; 83 84 idle-states { 85 entry-method = "psci"; 86 87 CPU_SLEEP: cpu-sleep { 88 compatible = "arm,idle-state"; 89 local-timer-stop; 90 arm,psci-suspend-param = <0x0010000>; 91 entry-latency-us = <120>; 92 exit-latency-us = <250>; 93 min-residency-us = <900>; 94 }; 95 }; 96 97 l2: l2-cache { 98 compatible = "cache"; 99 cache-level = <2>; 100 cache-unified; 101 }; 102 }; 103 104 cpu0_opp_table: opp-table-0 { 105 compatible = "operating-points-v2"; 106 opp-shared; 107 108 opp-408000000 { 109 opp-hz = /bits/ 64 <408000000>; 110 opp-microvolt = <950000 950000 1340000>; 111 clock-latency-ns = <40000>; 112 opp-suspend; 113 }; 114 opp-600000000 { 115 opp-hz = /bits/ 64 <600000000>; 116 opp-microvolt = <950000 950000 1340000>; 117 clock-latency-ns = <40000>; 118 }; 119 opp-816000000 { 120 opp-hz = /bits/ 64 <816000000>; 121 opp-microvolt = <1025000 1025000 1340000>; 122 clock-latency-ns = <40000>; 123 }; 124 opp-1008000000 { 125 opp-hz = /bits/ 64 <1008000000>; 126 opp-microvolt = <1125000 1125000 1340000>; 127 clock-latency-ns = <40000>; 128 }; 129 }; 130 131 arm-pmu { 132 compatible = "arm,cortex-a35-pmu"; 133 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 137 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 138 }; 139 140 mac_clkin: external-mac-clock { 141 compatible = "fixed-clock"; 142 clock-frequency = <50000000>; 143 clock-output-names = "mac_clkin"; 144 #clock-cells = <0>; 145 }; 146 147 psci { 148 compatible = "arm,psci-1.0"; 149 method = "smc"; 150 }; 151 152 timer { 153 compatible = "arm,armv8-timer"; 154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 158 }; 159 160 xin24m: xin24m { 161 compatible = "fixed-clock"; 162 #clock-cells = <0>; 163 clock-frequency = <24000000>; 164 clock-output-names = "xin24m"; 165 }; 166 167 grf: grf@ff000000 { 168 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 169 reg = <0x0 0xff000000 0x0 0x08000>; 170 171 reboot-mode { 172 compatible = "syscon-reboot-mode"; 173 offset = <0x500>; 174 mode-bootloader = <BOOT_BL_DOWNLOAD>; 175 mode-loader = <BOOT_BL_DOWNLOAD>; 176 mode-normal = <BOOT_NORMAL>; 177 mode-recovery = <BOOT_RECOVERY>; 178 mode-fastboot = <BOOT_FASTBOOT>; 179 }; 180 }; 181 182 usb2phy_grf: syscon@ff008000 { 183 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; 184 reg = <0x0 0xff008000 0x0 0x4000>; 185 #address-cells = <1>; 186 #size-cells = <1>; 187 188 u2phy: usb2phy@100 { 189 compatible = "rockchip,rk3308-usb2phy"; 190 reg = <0x100 0x10>; 191 assigned-clocks = <&cru USB480M>; 192 assigned-clock-parents = <&u2phy>; 193 clocks = <&cru SCLK_USBPHY_REF>; 194 clock-names = "phyclk"; 195 clock-output-names = "usb480m_phy"; 196 #clock-cells = <0>; 197 status = "disabled"; 198 199 u2phy_otg: otg-port { 200 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 203 interrupt-names = "otg-bvalid", "otg-id", 204 "linestate"; 205 #phy-cells = <0>; 206 status = "disabled"; 207 }; 208 209 u2phy_host: host-port { 210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 211 interrupt-names = "linestate"; 212 #phy-cells = <0>; 213 status = "disabled"; 214 }; 215 }; 216 }; 217 218 detect_grf: syscon@ff00b000 { 219 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; 220 reg = <0x0 0xff00b000 0x0 0x1000>; 221 #address-cells = <1>; 222 #size-cells = <1>; 223 }; 224 225 core_grf: syscon@ff00c000 { 226 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; 227 reg = <0x0 0xff00c000 0x0 0x1000>; 228 #address-cells = <1>; 229 #size-cells = <1>; 230 }; 231 232 i2c0: i2c@ff040000 { 233 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 234 reg = <0x0 0xff040000 0x0 0x1000>; 235 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 236 clock-names = "i2c", "pclk"; 237 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&i2c0_xfer>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 status = "disabled"; 243 }; 244 245 i2c1: i2c@ff050000 { 246 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 247 reg = <0x0 0xff050000 0x0 0x1000>; 248 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 249 clock-names = "i2c", "pclk"; 250 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&i2c1_xfer>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 status = "disabled"; 256 }; 257 258 i2c2: i2c@ff060000 { 259 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 260 reg = <0x0 0xff060000 0x0 0x1000>; 261 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 262 clock-names = "i2c", "pclk"; 263 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&i2c2_xfer>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 status = "disabled"; 269 }; 270 271 i2c3: i2c@ff070000 { 272 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 273 reg = <0x0 0xff070000 0x0 0x1000>; 274 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 275 clock-names = "i2c", "pclk"; 276 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&i2c3m0_xfer>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 status = "disabled"; 282 }; 283 284 wdt: watchdog@ff080000 { 285 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; 286 reg = <0x0 0xff080000 0x0 0x100>; 287 clocks = <&cru PCLK_WDT>; 288 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 289 status = "disabled"; 290 }; 291 292 uart0: serial@ff0a0000 { 293 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 294 reg = <0x0 0xff0a0000 0x0 0x100>; 295 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 297 clock-names = "baudclk", "apb_pclk"; 298 reg-shift = <2>; 299 reg-io-width = <4>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 302 status = "disabled"; 303 }; 304 305 uart1: serial@ff0b0000 { 306 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 307 reg = <0x0 0xff0b0000 0x0 0x100>; 308 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 310 clock-names = "baudclk", "apb_pclk"; 311 reg-shift = <2>; 312 reg-io-width = <4>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 315 status = "disabled"; 316 }; 317 318 uart2: serial@ff0c0000 { 319 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 320 reg = <0x0 0xff0c0000 0x0 0x100>; 321 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 323 clock-names = "baudclk", "apb_pclk"; 324 reg-shift = <2>; 325 reg-io-width = <4>; 326 pinctrl-names = "default"; 327 pinctrl-0 = <&uart2m0_xfer>; 328 status = "disabled"; 329 }; 330 331 uart3: serial@ff0d0000 { 332 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 333 reg = <0x0 0xff0d0000 0x0 0x100>; 334 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 336 clock-names = "baudclk", "apb_pclk"; 337 reg-shift = <2>; 338 reg-io-width = <4>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&uart3_xfer>; 341 status = "disabled"; 342 }; 343 344 uart4: serial@ff0e0000 { 345 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 346 reg = <0x0 0xff0e0000 0x0 0x100>; 347 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 349 clock-names = "baudclk", "apb_pclk"; 350 reg-shift = <2>; 351 reg-io-width = <4>; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 354 status = "disabled"; 355 }; 356 357 spi0: spi@ff120000 { 358 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 359 reg = <0x0 0xff120000 0x0 0x1000>; 360 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 364 clock-names = "spiclk", "apb_pclk"; 365 dmas = <&dmac0 0>, <&dmac0 1>; 366 dma-names = "tx", "rx"; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; 369 status = "disabled"; 370 }; 371 372 spi1: spi@ff130000 { 373 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 374 reg = <0x0 0xff130000 0x0 0x1000>; 375 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 379 clock-names = "spiclk", "apb_pclk"; 380 dmas = <&dmac0 2>, <&dmac0 3>; 381 dma-names = "tx", "rx"; 382 pinctrl-names = "default"; 383 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; 384 status = "disabled"; 385 }; 386 387 spi2: spi@ff140000 { 388 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 389 reg = <0x0 0xff140000 0x0 0x1000>; 390 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 394 clock-names = "spiclk", "apb_pclk"; 395 dmas = <&dmac1 16>, <&dmac1 17>; 396 dma-names = "tx", "rx"; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; 399 status = "disabled"; 400 }; 401 402 pwm8: pwm@ff160000 { 403 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 404 reg = <0x0 0xff160000 0x0 0x10>; 405 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 406 clock-names = "pwm", "pclk"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pwm8_pin>; 409 #pwm-cells = <3>; 410 status = "disabled"; 411 }; 412 413 pwm9: pwm@ff160010 { 414 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 415 reg = <0x0 0xff160010 0x0 0x10>; 416 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 417 clock-names = "pwm", "pclk"; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&pwm9_pin>; 420 #pwm-cells = <3>; 421 status = "disabled"; 422 }; 423 424 pwm10: pwm@ff160020 { 425 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 426 reg = <0x0 0xff160020 0x0 0x10>; 427 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 428 clock-names = "pwm", "pclk"; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&pwm10_pin>; 431 #pwm-cells = <3>; 432 status = "disabled"; 433 }; 434 435 pwm11: pwm@ff160030 { 436 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 437 reg = <0x0 0xff160030 0x0 0x10>; 438 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 439 clock-names = "pwm", "pclk"; 440 pinctrl-names = "default"; 441 pinctrl-0 = <&pwm11_pin>; 442 #pwm-cells = <3>; 443 status = "disabled"; 444 }; 445 446 pwm4: pwm@ff170000 { 447 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 448 reg = <0x0 0xff170000 0x0 0x10>; 449 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 450 clock-names = "pwm", "pclk"; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pwm4_pin>; 453 #pwm-cells = <3>; 454 status = "disabled"; 455 }; 456 457 pwm5: pwm@ff170010 { 458 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 459 reg = <0x0 0xff170010 0x0 0x10>; 460 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 461 clock-names = "pwm", "pclk"; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pwm5_pin>; 464 #pwm-cells = <3>; 465 status = "disabled"; 466 }; 467 468 pwm6: pwm@ff170020 { 469 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 470 reg = <0x0 0xff170020 0x0 0x10>; 471 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 472 clock-names = "pwm", "pclk"; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&pwm6_pin>; 475 #pwm-cells = <3>; 476 status = "disabled"; 477 }; 478 479 pwm7: pwm@ff170030 { 480 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 481 reg = <0x0 0xff170030 0x0 0x10>; 482 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 483 clock-names = "pwm", "pclk"; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&pwm7_pin>; 486 #pwm-cells = <3>; 487 status = "disabled"; 488 }; 489 490 pwm0: pwm@ff180000 { 491 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 492 reg = <0x0 0xff180000 0x0 0x10>; 493 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 494 clock-names = "pwm", "pclk"; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&pwm0_pin>; 497 #pwm-cells = <3>; 498 status = "disabled"; 499 }; 500 501 pwm1: pwm@ff180010 { 502 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 503 reg = <0x0 0xff180010 0x0 0x10>; 504 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 505 clock-names = "pwm", "pclk"; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&pwm1_pin>; 508 #pwm-cells = <3>; 509 status = "disabled"; 510 }; 511 512 pwm2: pwm@ff180020 { 513 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 514 reg = <0x0 0xff180020 0x0 0x10>; 515 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 516 clock-names = "pwm", "pclk"; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&pwm2_pin>; 519 #pwm-cells = <3>; 520 status = "disabled"; 521 }; 522 523 pwm3: pwm@ff180030 { 524 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 525 reg = <0x0 0xff180030 0x0 0x10>; 526 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 527 clock-names = "pwm", "pclk"; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&pwm3_pin>; 530 #pwm-cells = <3>; 531 status = "disabled"; 532 }; 533 534 rktimer: rktimer@ff1a0000 { 535 compatible = "rockchip,rk3288-timer"; 536 reg = <0x0 0xff1a0000 0x0 0x20>; 537 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 539 clock-names = "pclk", "timer"; 540 }; 541 542 saradc: saradc@ff1e0000 { 543 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 544 reg = <0x0 0xff1e0000 0x0 0x100>; 545 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 547 clock-names = "saradc", "apb_pclk"; 548 #io-channel-cells = <1>; 549 resets = <&cru SRST_SARADC_P>; 550 reset-names = "saradc-apb"; 551 status = "disabled"; 552 }; 553 554 dmac0: dma-controller@ff2c0000 { 555 compatible = "arm,pl330", "arm,primecell"; 556 reg = <0x0 0xff2c0000 0x0 0x4000>; 557 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 559 arm,pl330-periph-burst; 560 clocks = <&cru ACLK_DMAC0>; 561 clock-names = "apb_pclk"; 562 #dma-cells = <1>; 563 }; 564 565 dmac1: dma-controller@ff2d0000 { 566 compatible = "arm,pl330", "arm,primecell"; 567 reg = <0x0 0xff2d0000 0x0 0x4000>; 568 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 570 arm,pl330-periph-burst; 571 clocks = <&cru ACLK_DMAC1>; 572 clock-names = "apb_pclk"; 573 #dma-cells = <1>; 574 }; 575 576 i2s_2ch_0: i2s@ff350000 { 577 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 578 reg = <0x0 0xff350000 0x0 0x1000>; 579 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; 581 clock-names = "i2s_clk", "i2s_hclk"; 582 dmas = <&dmac1 8>, <&dmac1 9>; 583 dma-names = "tx", "rx"; 584 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; 585 reset-names = "reset-m", "reset-h"; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&i2s_2ch_0_sclk 588 &i2s_2ch_0_lrck 589 &i2s_2ch_0_sdi 590 &i2s_2ch_0_sdo>; 591 status = "disabled"; 592 }; 593 594 i2s_2ch_1: i2s@ff360000 { 595 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 596 reg = <0x0 0xff360000 0x0 0x1000>; 597 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 599 clock-names = "i2s_clk", "i2s_hclk"; 600 dmas = <&dmac1 11>; 601 dma-names = "rx"; 602 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; 603 reset-names = "reset-m", "reset-h"; 604 status = "disabled"; 605 }; 606 607 spdif_tx: spdif-tx@ff3a0000 { 608 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; 609 reg = <0x0 0xff3a0000 0x0 0x1000>; 610 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; 612 clock-names = "mclk", "hclk"; 613 dmas = <&dmac1 13>; 614 dma-names = "tx"; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&spdif_out>; 617 status = "disabled"; 618 }; 619 620 usb20_otg: usb@ff400000 { 621 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 622 "snps,dwc2"; 623 reg = <0x0 0xff400000 0x0 0x40000>; 624 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&cru HCLK_OTG>; 626 clock-names = "otg"; 627 dr_mode = "otg"; 628 g-np-tx-fifo-size = <16>; 629 g-rx-fifo-size = <280>; 630 g-tx-fifo-size = <256 128 128 64 32 16>; 631 phys = <&u2phy_otg>; 632 phy-names = "usb2-phy"; 633 status = "disabled"; 634 }; 635 636 usb_host_ehci: usb@ff440000 { 637 compatible = "generic-ehci"; 638 reg = <0x0 0xff440000 0x0 0x10000>; 639 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; 641 phys = <&u2phy_host>; 642 phy-names = "usb"; 643 status = "disabled"; 644 }; 645 646 usb_host_ohci: usb@ff450000 { 647 compatible = "generic-ohci"; 648 reg = <0x0 0xff450000 0x0 0x10000>; 649 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; 651 phys = <&u2phy_host>; 652 phy-names = "usb"; 653 status = "disabled"; 654 }; 655 656 sdmmc: mmc@ff480000 { 657 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 658 reg = <0x0 0xff480000 0x0 0x4000>; 659 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 660 bus-width = <4>; 661 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 662 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 663 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 664 fifo-depth = <0x100>; 665 max-frequency = <150000000>; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 668 status = "disabled"; 669 }; 670 671 emmc: mmc@ff490000 { 672 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 673 reg = <0x0 0xff490000 0x0 0x4000>; 674 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 675 bus-width = <8>; 676 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 677 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 678 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 679 fifo-depth = <0x100>; 680 max-frequency = <150000000>; 681 status = "disabled"; 682 }; 683 684 sdio: mmc@ff4a0000 { 685 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 686 reg = <0x0 0xff4a0000 0x0 0x4000>; 687 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 688 bus-width = <4>; 689 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 690 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 691 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 692 fifo-depth = <0x100>; 693 max-frequency = <150000000>; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 696 status = "disabled"; 697 }; 698 699 nfc: nand-controller@ff4b0000 { 700 compatible = "rockchip,rk3308-nfc", 701 "rockchip,rv1108-nfc"; 702 reg = <0x0 0xff4b0000 0x0 0x4000>; 703 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 705 clock-names = "ahb", "nfc"; 706 assigned-clocks = <&cru SCLK_NANDC>; 707 assigned-clock-rates = <150000000>; 708 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 709 &flash_rdn &flash_rdy &flash_wrn>; 710 pinctrl-names = "default"; 711 status = "disabled"; 712 }; 713 714 gmac: ethernet@ff4e0000 { 715 compatible = "rockchip,rk3308-gmac"; 716 reg = <0x0 0xff4e0000 0x0 0x10000>; 717 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 718 interrupt-names = "macirq"; 719 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, 720 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, 721 <&cru SCLK_MAC>, <&cru ACLK_MAC>, 722 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; 723 clock-names = "stmmaceth", "mac_clk_rx", 724 "mac_clk_tx", "clk_mac_ref", 725 "clk_mac_refout", "aclk_mac", 726 "pclk_mac", "clk_mac_speed"; 727 phy-mode = "rmii"; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 730 resets = <&cru SRST_MAC_A>; 731 reset-names = "stmmaceth"; 732 rockchip,grf = <&grf>; 733 status = "disabled"; 734 }; 735 736 sfc: spi@ff4c0000 { 737 compatible = "rockchip,sfc"; 738 reg = <0x0 0xff4c0000 0x0 0x4000>; 739 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 741 clock-names = "clk_sfc", "hclk_sfc"; 742 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; 743 pinctrl-names = "default"; 744 status = "disabled"; 745 }; 746 747 cru: clock-controller@ff500000 { 748 compatible = "rockchip,rk3308-cru"; 749 reg = <0x0 0xff500000 0x0 0x1000>; 750 clocks = <&xin24m>; 751 clock-names = "xin24m"; 752 rockchip,grf = <&grf>; 753 #clock-cells = <1>; 754 #reset-cells = <1>; 755 assigned-clocks = <&cru SCLK_RTC32K>; 756 assigned-clock-rates = <32768>; 757 }; 758 759 gic: interrupt-controller@ff580000 { 760 compatible = "arm,gic-400"; 761 reg = <0x0 0xff581000 0x0 0x1000>, 762 <0x0 0xff582000 0x0 0x2000>, 763 <0x0 0xff584000 0x0 0x2000>, 764 <0x0 0xff586000 0x0 0x2000>; 765 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 766 #interrupt-cells = <3>; 767 interrupt-controller; 768 #address-cells = <0>; 769 }; 770 771 sram: sram@fff80000 { 772 compatible = "mmio-sram"; 773 reg = <0x0 0xfff80000 0x0 0x40000>; 774 ranges = <0 0x0 0xfff80000 0x40000>; 775 #address-cells = <1>; 776 #size-cells = <1>; 777 778 /* reserved for ddr dvfs and system suspend/resume */ 779 ddr-sram@0 { 780 reg = <0x0 0x8000>; 781 }; 782 783 /* reserved for vad audio buffer */ 784 vad_sram: vad-sram@8000 { 785 reg = <0x8000 0x38000>; 786 }; 787 }; 788 789 pinctrl: pinctrl { 790 compatible = "rockchip,rk3308-pinctrl"; 791 rockchip,grf = <&grf>; 792 #address-cells = <2>; 793 #size-cells = <2>; 794 ranges; 795 796 gpio0: gpio@ff220000 { 797 compatible = "rockchip,gpio-bank"; 798 reg = <0x0 0xff220000 0x0 0x100>; 799 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&cru PCLK_GPIO0>; 801 gpio-controller; 802 #gpio-cells = <2>; 803 interrupt-controller; 804 #interrupt-cells = <2>; 805 }; 806 807 gpio1: gpio@ff230000 { 808 compatible = "rockchip,gpio-bank"; 809 reg = <0x0 0xff230000 0x0 0x100>; 810 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&cru PCLK_GPIO1>; 812 gpio-controller; 813 #gpio-cells = <2>; 814 interrupt-controller; 815 #interrupt-cells = <2>; 816 }; 817 818 gpio2: gpio@ff240000 { 819 compatible = "rockchip,gpio-bank"; 820 reg = <0x0 0xff240000 0x0 0x100>; 821 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&cru PCLK_GPIO2>; 823 gpio-controller; 824 #gpio-cells = <2>; 825 interrupt-controller; 826 #interrupt-cells = <2>; 827 }; 828 829 gpio3: gpio@ff250000 { 830 compatible = "rockchip,gpio-bank"; 831 reg = <0x0 0xff250000 0x0 0x100>; 832 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&cru PCLK_GPIO3>; 834 gpio-controller; 835 #gpio-cells = <2>; 836 interrupt-controller; 837 #interrupt-cells = <2>; 838 }; 839 840 gpio4: gpio@ff260000 { 841 compatible = "rockchip,gpio-bank"; 842 reg = <0x0 0xff260000 0x0 0x100>; 843 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&cru PCLK_GPIO4>; 845 gpio-controller; 846 #gpio-cells = <2>; 847 interrupt-controller; 848 #interrupt-cells = <2>; 849 }; 850 851 pcfg_pull_up: pcfg-pull-up { 852 bias-pull-up; 853 }; 854 855 pcfg_pull_down: pcfg-pull-down { 856 bias-pull-down; 857 }; 858 859 pcfg_pull_none: pcfg-pull-none { 860 bias-disable; 861 }; 862 863 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 864 bias-disable; 865 drive-strength = <2>; 866 }; 867 868 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 869 bias-pull-up; 870 drive-strength = <2>; 871 }; 872 873 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 874 bias-pull-up; 875 drive-strength = <4>; 876 }; 877 878 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 879 bias-disable; 880 drive-strength = <4>; 881 }; 882 883 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 884 bias-pull-down; 885 drive-strength = <4>; 886 }; 887 888 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 889 bias-disable; 890 drive-strength = <8>; 891 }; 892 893 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 894 bias-pull-up; 895 drive-strength = <8>; 896 }; 897 898 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 899 bias-disable; 900 drive-strength = <12>; 901 }; 902 903 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 904 bias-pull-up; 905 drive-strength = <12>; 906 }; 907 908 pcfg_pull_none_smt: pcfg-pull-none-smt { 909 bias-disable; 910 input-schmitt-enable; 911 }; 912 913 pcfg_output_high: pcfg-output-high { 914 output-high; 915 }; 916 917 pcfg_output_low: pcfg-output-low { 918 output-low; 919 }; 920 921 pcfg_input_high: pcfg-input-high { 922 bias-pull-up; 923 input-enable; 924 }; 925 926 pcfg_input: pcfg-input { 927 input-enable; 928 }; 929 930 emmc { 931 emmc_clk: emmc-clk { 932 rockchip,pins = 933 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 934 }; 935 936 emmc_cmd: emmc-cmd { 937 rockchip,pins = 938 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 939 }; 940 941 emmc_pwren: emmc-pwren { 942 rockchip,pins = 943 <3 RK_PB3 2 &pcfg_pull_none>; 944 }; 945 946 emmc_rstn: emmc-rstn { 947 rockchip,pins = 948 <3 RK_PB2 2 &pcfg_pull_none>; 949 }; 950 951 emmc_bus1: emmc-bus1 { 952 rockchip,pins = 953 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 954 }; 955 956 emmc_bus4: emmc-bus4 { 957 rockchip,pins = 958 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 959 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 960 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 961 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 962 }; 963 964 emmc_bus8: emmc-bus8 { 965 rockchip,pins = 966 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 967 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 968 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 969 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 970 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 971 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 972 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 973 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 974 }; 975 }; 976 977 flash { 978 flash_csn0: flash-csn0 { 979 rockchip,pins = 980 <3 RK_PB5 1 &pcfg_pull_none>; 981 }; 982 983 flash_rdy: flash-rdy { 984 rockchip,pins = 985 <3 RK_PB4 1 &pcfg_pull_none>; 986 }; 987 988 flash_ale: flash-ale { 989 rockchip,pins = 990 <3 RK_PB3 1 &pcfg_pull_none>; 991 }; 992 993 flash_cle: flash-cle { 994 rockchip,pins = 995 <3 RK_PB1 1 &pcfg_pull_none>; 996 }; 997 998 flash_wrn: flash-wrn { 999 rockchip,pins = 1000 <3 RK_PB0 1 &pcfg_pull_none>; 1001 }; 1002 1003 flash_rdn: flash-rdn { 1004 rockchip,pins = 1005 <3 RK_PB2 1 &pcfg_pull_none>; 1006 }; 1007 1008 flash_bus8: flash-bus8 { 1009 rockchip,pins = 1010 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 1011 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 1012 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 1013 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 1014 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 1015 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 1016 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 1017 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 1018 }; 1019 }; 1020 1021 sfc { 1022 sfc_bus4: sfc-bus4 { 1023 rockchip,pins = 1024 <3 RK_PA0 3 &pcfg_pull_none>, 1025 <3 RK_PA1 3 &pcfg_pull_none>, 1026 <3 RK_PA2 3 &pcfg_pull_none>, 1027 <3 RK_PA3 3 &pcfg_pull_none>; 1028 }; 1029 1030 sfc_bus2: sfc-bus2 { 1031 rockchip,pins = 1032 <3 RK_PA0 3 &pcfg_pull_none>, 1033 <3 RK_PA1 3 &pcfg_pull_none>; 1034 }; 1035 1036 sfc_cs0: sfc-cs0 { 1037 rockchip,pins = 1038 <3 RK_PA4 3 &pcfg_pull_none>; 1039 }; 1040 1041 sfc_clk: sfc-clk { 1042 rockchip,pins = 1043 <3 RK_PA5 3 &pcfg_pull_none>; 1044 }; 1045 }; 1046 1047 gmac { 1048 rmii_pins: rmii-pins { 1049 rockchip,pins = 1050 /* mac_txen */ 1051 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1052 /* mac_txd1 */ 1053 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1054 /* mac_txd0 */ 1055 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1056 /* mac_rxd0 */ 1057 <1 RK_PC4 3 &pcfg_pull_none>, 1058 /* mac_rxd1 */ 1059 <1 RK_PC5 3 &pcfg_pull_none>, 1060 /* mac_rxer */ 1061 <1 RK_PB7 3 &pcfg_pull_none>, 1062 /* mac_rxdv */ 1063 <1 RK_PC0 3 &pcfg_pull_none>, 1064 /* mac_mdio */ 1065 <1 RK_PB6 3 &pcfg_pull_none>, 1066 /* mac_mdc */ 1067 <1 RK_PB5 3 &pcfg_pull_none>; 1068 }; 1069 1070 mac_refclk_12ma: mac-refclk-12ma { 1071 rockchip,pins = 1072 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 1073 }; 1074 1075 mac_refclk: mac-refclk { 1076 rockchip,pins = 1077 <1 RK_PB4 3 &pcfg_pull_none>; 1078 }; 1079 }; 1080 1081 gmac-m1 { 1082 rmiim1_pins: rmiim1-pins { 1083 rockchip,pins = 1084 /* mac_txen */ 1085 <4 RK_PB7 2 &pcfg_pull_none_12ma>, 1086 /* mac_txd1 */ 1087 <4 RK_PA5 2 &pcfg_pull_none_12ma>, 1088 /* mac_txd0 */ 1089 <4 RK_PA4 2 &pcfg_pull_none_12ma>, 1090 /* mac_rxd0 */ 1091 <4 RK_PA2 2 &pcfg_pull_none>, 1092 /* mac_rxd1 */ 1093 <4 RK_PA3 2 &pcfg_pull_none>, 1094 /* mac_rxer */ 1095 <4 RK_PA0 2 &pcfg_pull_none>, 1096 /* mac_rxdv */ 1097 <4 RK_PA1 2 &pcfg_pull_none>, 1098 /* mac_mdio */ 1099 <4 RK_PB6 2 &pcfg_pull_none>, 1100 /* mac_mdc */ 1101 <4 RK_PB5 2 &pcfg_pull_none>; 1102 }; 1103 1104 macm1_refclk_12ma: macm1-refclk-12ma { 1105 rockchip,pins = 1106 <4 RK_PB4 2 &pcfg_pull_none_12ma>; 1107 }; 1108 1109 macm1_refclk: macm1-refclk { 1110 rockchip,pins = 1111 <4 RK_PB4 2 &pcfg_pull_none>; 1112 }; 1113 }; 1114 1115 i2c0 { 1116 i2c0_xfer: i2c0-xfer { 1117 rockchip,pins = 1118 <1 RK_PD0 2 &pcfg_pull_none_smt>, 1119 <1 RK_PD1 2 &pcfg_pull_none_smt>; 1120 }; 1121 }; 1122 1123 i2c1 { 1124 i2c1_xfer: i2c1-xfer { 1125 rockchip,pins = 1126 <0 RK_PB3 1 &pcfg_pull_none_smt>, 1127 <0 RK_PB4 1 &pcfg_pull_none_smt>; 1128 }; 1129 }; 1130 1131 i2c2 { 1132 i2c2_xfer: i2c2-xfer { 1133 rockchip,pins = 1134 <2 RK_PA2 3 &pcfg_pull_none_smt>, 1135 <2 RK_PA3 3 &pcfg_pull_none_smt>; 1136 }; 1137 }; 1138 1139 i2c3-m0 { 1140 i2c3m0_xfer: i2c3m0-xfer { 1141 rockchip,pins = 1142 <0 RK_PB7 2 &pcfg_pull_none_smt>, 1143 <0 RK_PC0 2 &pcfg_pull_none_smt>; 1144 }; 1145 }; 1146 1147 i2c3-m1 { 1148 i2c3m1_xfer: i2c3m1-xfer { 1149 rockchip,pins = 1150 <3 RK_PB4 2 &pcfg_pull_none_smt>, 1151 <3 RK_PB5 2 &pcfg_pull_none_smt>; 1152 }; 1153 }; 1154 1155 i2c3-m2 { 1156 i2c3m2_xfer: i2c3m2-xfer { 1157 rockchip,pins = 1158 <2 RK_PA1 3 &pcfg_pull_none_smt>, 1159 <2 RK_PA0 3 &pcfg_pull_none_smt>; 1160 }; 1161 }; 1162 1163 i2s_2ch_0 { 1164 i2s_2ch_0_mclk: i2s-2ch-0-mclk { 1165 rockchip,pins = 1166 <4 RK_PB4 1 &pcfg_pull_none>; 1167 }; 1168 1169 i2s_2ch_0_sclk: i2s-2ch-0-sclk { 1170 rockchip,pins = 1171 <4 RK_PB5 1 &pcfg_pull_none>; 1172 }; 1173 1174 i2s_2ch_0_lrck: i2s-2ch-0-lrck { 1175 rockchip,pins = 1176 <4 RK_PB6 1 &pcfg_pull_none>; 1177 }; 1178 1179 i2s_2ch_0_sdo: i2s-2ch-0-sdo { 1180 rockchip,pins = 1181 <4 RK_PB7 1 &pcfg_pull_none>; 1182 }; 1183 1184 i2s_2ch_0_sdi: i2s-2ch-0-sdi { 1185 rockchip,pins = 1186 <4 RK_PC0 1 &pcfg_pull_none>; 1187 }; 1188 }; 1189 1190 i2s_8ch_0 { 1191 i2s_8ch_0_mclk: i2s-8ch-0-mclk { 1192 rockchip,pins = 1193 <2 RK_PA4 1 &pcfg_pull_none>; 1194 }; 1195 1196 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { 1197 rockchip,pins = 1198 <2 RK_PA5 1 &pcfg_pull_none>; 1199 }; 1200 1201 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { 1202 rockchip,pins = 1203 <2 RK_PA6 1 &pcfg_pull_none>; 1204 }; 1205 1206 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { 1207 rockchip,pins = 1208 <2 RK_PA7 1 &pcfg_pull_none>; 1209 }; 1210 1211 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { 1212 rockchip,pins = 1213 <2 RK_PB0 1 &pcfg_pull_none>; 1214 }; 1215 1216 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { 1217 rockchip,pins = 1218 <2 RK_PB1 1 &pcfg_pull_none>; 1219 }; 1220 1221 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { 1222 rockchip,pins = 1223 <2 RK_PB2 1 &pcfg_pull_none>; 1224 }; 1225 1226 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { 1227 rockchip,pins = 1228 <2 RK_PB3 1 &pcfg_pull_none>; 1229 }; 1230 1231 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { 1232 rockchip,pins = 1233 <2 RK_PB4 1 &pcfg_pull_none>; 1234 }; 1235 1236 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { 1237 rockchip,pins = 1238 <2 RK_PB5 1 &pcfg_pull_none>; 1239 }; 1240 1241 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { 1242 rockchip,pins = 1243 <2 RK_PB6 1 &pcfg_pull_none>; 1244 }; 1245 1246 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { 1247 rockchip,pins = 1248 <2 RK_PB7 1 &pcfg_pull_none>; 1249 }; 1250 1251 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { 1252 rockchip,pins = 1253 <2 RK_PC0 1 &pcfg_pull_none>; 1254 }; 1255 }; 1256 1257 i2s_8ch_1_m0 { 1258 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { 1259 rockchip,pins = 1260 <1 RK_PA2 2 &pcfg_pull_none>; 1261 }; 1262 1263 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { 1264 rockchip,pins = 1265 <1 RK_PA3 2 &pcfg_pull_none>; 1266 }; 1267 1268 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { 1269 rockchip,pins = 1270 <1 RK_PA4 2 &pcfg_pull_none>; 1271 }; 1272 1273 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { 1274 rockchip,pins = 1275 <1 RK_PA5 2 &pcfg_pull_none>; 1276 }; 1277 1278 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { 1279 rockchip,pins = 1280 <1 RK_PA6 2 &pcfg_pull_none>; 1281 }; 1282 1283 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { 1284 rockchip,pins = 1285 <1 RK_PA7 2 &pcfg_pull_none>; 1286 }; 1287 1288 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { 1289 rockchip,pins = 1290 <1 RK_PB0 2 &pcfg_pull_none>; 1291 }; 1292 1293 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { 1294 rockchip,pins = 1295 <1 RK_PB1 2 &pcfg_pull_none>; 1296 }; 1297 1298 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { 1299 rockchip,pins = 1300 <1 RK_PB2 2 &pcfg_pull_none>; 1301 }; 1302 1303 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { 1304 rockchip,pins = 1305 <1 RK_PB3 2 &pcfg_pull_none>; 1306 }; 1307 }; 1308 1309 i2s_8ch_1_m1 { 1310 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { 1311 rockchip,pins = 1312 <1 RK_PB4 2 &pcfg_pull_none>; 1313 }; 1314 1315 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { 1316 rockchip,pins = 1317 <1 RK_PB5 2 &pcfg_pull_none>; 1318 }; 1319 1320 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { 1321 rockchip,pins = 1322 <1 RK_PB6 2 &pcfg_pull_none>; 1323 }; 1324 1325 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { 1326 rockchip,pins = 1327 <1 RK_PB7 2 &pcfg_pull_none>; 1328 }; 1329 1330 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { 1331 rockchip,pins = 1332 <1 RK_PC0 2 &pcfg_pull_none>; 1333 }; 1334 1335 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { 1336 rockchip,pins = 1337 <1 RK_PC1 2 &pcfg_pull_none>; 1338 }; 1339 1340 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { 1341 rockchip,pins = 1342 <1 RK_PC2 2 &pcfg_pull_none>; 1343 }; 1344 1345 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { 1346 rockchip,pins = 1347 <1 RK_PC3 2 &pcfg_pull_none>; 1348 }; 1349 1350 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { 1351 rockchip,pins = 1352 <1 RK_PC4 2 &pcfg_pull_none>; 1353 }; 1354 1355 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { 1356 rockchip,pins = 1357 <1 RK_PC5 2 &pcfg_pull_none>; 1358 }; 1359 }; 1360 1361 pdm_m0 { 1362 pdm_m0_clk: pdm-m0-clk { 1363 rockchip,pins = 1364 <1 RK_PA4 3 &pcfg_pull_none>; 1365 }; 1366 1367 pdm_m0_sdi0: pdm-m0-sdi0 { 1368 rockchip,pins = 1369 <1 RK_PB3 3 &pcfg_pull_none>; 1370 }; 1371 1372 pdm_m0_sdi1: pdm-m0-sdi1 { 1373 rockchip,pins = 1374 <1 RK_PB2 3 &pcfg_pull_none>; 1375 }; 1376 1377 pdm_m0_sdi2: pdm-m0-sdi2 { 1378 rockchip,pins = 1379 <1 RK_PB1 3 &pcfg_pull_none>; 1380 }; 1381 1382 pdm_m0_sdi3: pdm-m0-sdi3 { 1383 rockchip,pins = 1384 <1 RK_PB0 3 &pcfg_pull_none>; 1385 }; 1386 }; 1387 1388 pdm_m1 { 1389 pdm_m1_clk: pdm-m1-clk { 1390 rockchip,pins = 1391 <1 RK_PB6 4 &pcfg_pull_none>; 1392 }; 1393 1394 pdm_m1_sdi0: pdm-m1-sdi0 { 1395 rockchip,pins = 1396 <1 RK_PC5 4 &pcfg_pull_none>; 1397 }; 1398 1399 pdm_m1_sdi1: pdm-m1-sdi1 { 1400 rockchip,pins = 1401 <1 RK_PC4 4 &pcfg_pull_none>; 1402 }; 1403 1404 pdm_m1_sdi2: pdm-m1-sdi2 { 1405 rockchip,pins = 1406 <1 RK_PC3 4 &pcfg_pull_none>; 1407 }; 1408 1409 pdm_m1_sdi3: pdm-m1-sdi3 { 1410 rockchip,pins = 1411 <1 RK_PC2 4 &pcfg_pull_none>; 1412 }; 1413 }; 1414 1415 pdm_m2 { 1416 pdm_m2_clkm: pdm-m2-clkm { 1417 rockchip,pins = 1418 <2 RK_PA4 3 &pcfg_pull_none>; 1419 }; 1420 1421 pdm_m2_clk: pdm-m2-clk { 1422 rockchip,pins = 1423 <2 RK_PA6 2 &pcfg_pull_none>; 1424 }; 1425 1426 pdm_m2_sdi0: pdm-m2-sdi0 { 1427 rockchip,pins = 1428 <2 RK_PB5 2 &pcfg_pull_none>; 1429 }; 1430 1431 pdm_m2_sdi1: pdm-m2-sdi1 { 1432 rockchip,pins = 1433 <2 RK_PB6 2 &pcfg_pull_none>; 1434 }; 1435 1436 pdm_m2_sdi2: pdm-m2-sdi2 { 1437 rockchip,pins = 1438 <2 RK_PB7 2 &pcfg_pull_none>; 1439 }; 1440 1441 pdm_m2_sdi3: pdm-m2-sdi3 { 1442 rockchip,pins = 1443 <2 RK_PC0 2 &pcfg_pull_none>; 1444 }; 1445 }; 1446 1447 pwm0 { 1448 pwm0_pin: pwm0-pin { 1449 rockchip,pins = 1450 <0 RK_PB5 1 &pcfg_pull_none>; 1451 }; 1452 1453 pwm0_pin_pull_down: pwm0-pin-pull-down { 1454 rockchip,pins = 1455 <0 RK_PB5 1 &pcfg_pull_down>; 1456 }; 1457 }; 1458 1459 pwm1 { 1460 pwm1_pin: pwm1-pin { 1461 rockchip,pins = 1462 <0 RK_PB6 1 &pcfg_pull_none>; 1463 }; 1464 1465 pwm1_pin_pull_down: pwm1-pin-pull-down { 1466 rockchip,pins = 1467 <0 RK_PB6 1 &pcfg_pull_down>; 1468 }; 1469 }; 1470 1471 pwm2 { 1472 pwm2_pin: pwm2-pin { 1473 rockchip,pins = 1474 <0 RK_PB7 1 &pcfg_pull_none>; 1475 }; 1476 1477 pwm2_pin_pull_down: pwm2-pin-pull-down { 1478 rockchip,pins = 1479 <0 RK_PB7 1 &pcfg_pull_down>; 1480 }; 1481 }; 1482 1483 pwm3 { 1484 pwm3_pin: pwm3-pin { 1485 rockchip,pins = 1486 <0 RK_PC0 1 &pcfg_pull_none>; 1487 }; 1488 1489 pwm3_pin_pull_down: pwm3-pin-pull-down { 1490 rockchip,pins = 1491 <0 RK_PC0 1 &pcfg_pull_down>; 1492 }; 1493 }; 1494 1495 pwm4 { 1496 pwm4_pin: pwm4-pin { 1497 rockchip,pins = 1498 <0 RK_PA1 2 &pcfg_pull_none>; 1499 }; 1500 1501 pwm4_pin_pull_down: pwm4-pin-pull-down { 1502 rockchip,pins = 1503 <0 RK_PA1 2 &pcfg_pull_down>; 1504 }; 1505 }; 1506 1507 pwm5 { 1508 pwm5_pin: pwm5-pin { 1509 rockchip,pins = 1510 <0 RK_PC1 2 &pcfg_pull_none>; 1511 }; 1512 1513 pwm5_pin_pull_down: pwm5-pin-pull-down { 1514 rockchip,pins = 1515 <0 RK_PC1 2 &pcfg_pull_down>; 1516 }; 1517 }; 1518 1519 pwm6 { 1520 pwm6_pin: pwm6-pin { 1521 rockchip,pins = 1522 <0 RK_PC2 2 &pcfg_pull_none>; 1523 }; 1524 1525 pwm6_pin_pull_down: pwm6-pin-pull-down { 1526 rockchip,pins = 1527 <0 RK_PC2 2 &pcfg_pull_down>; 1528 }; 1529 }; 1530 1531 pwm7 { 1532 pwm7_pin: pwm7-pin { 1533 rockchip,pins = 1534 <2 RK_PB0 2 &pcfg_pull_none>; 1535 }; 1536 1537 pwm7_pin_pull_down: pwm7-pin-pull-down { 1538 rockchip,pins = 1539 <2 RK_PB0 2 &pcfg_pull_down>; 1540 }; 1541 }; 1542 1543 pwm8 { 1544 pwm8_pin: pwm8-pin { 1545 rockchip,pins = 1546 <2 RK_PB2 2 &pcfg_pull_none>; 1547 }; 1548 1549 pwm8_pin_pull_down: pwm8-pin-pull-down { 1550 rockchip,pins = 1551 <2 RK_PB2 2 &pcfg_pull_down>; 1552 }; 1553 }; 1554 1555 pwm9 { 1556 pwm9_pin: pwm9-pin { 1557 rockchip,pins = 1558 <2 RK_PB3 2 &pcfg_pull_none>; 1559 }; 1560 1561 pwm9_pin_pull_down: pwm9-pin-pull-down { 1562 rockchip,pins = 1563 <2 RK_PB3 2 &pcfg_pull_down>; 1564 }; 1565 }; 1566 1567 pwm10 { 1568 pwm10_pin: pwm10-pin { 1569 rockchip,pins = 1570 <2 RK_PB4 2 &pcfg_pull_none>; 1571 }; 1572 1573 pwm10_pin_pull_down: pwm10-pin-pull-down { 1574 rockchip,pins = 1575 <2 RK_PB4 2 &pcfg_pull_down>; 1576 }; 1577 }; 1578 1579 pwm11 { 1580 pwm11_pin: pwm11-pin { 1581 rockchip,pins = 1582 <2 RK_PC0 4 &pcfg_pull_none>; 1583 }; 1584 1585 pwm11_pin_pull_down: pwm11-pin-pull-down { 1586 rockchip,pins = 1587 <2 RK_PC0 4 &pcfg_pull_down>; 1588 }; 1589 }; 1590 1591 rtc { 1592 rtc_32k: rtc-32k { 1593 rockchip,pins = 1594 <0 RK_PC3 1 &pcfg_pull_none>; 1595 }; 1596 }; 1597 1598 sdmmc { 1599 sdmmc_clk: sdmmc-clk { 1600 rockchip,pins = 1601 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 1602 }; 1603 1604 sdmmc_cmd: sdmmc-cmd { 1605 rockchip,pins = 1606 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 1607 }; 1608 1609 sdmmc_det: sdmmc-det { 1610 rockchip,pins = 1611 <0 RK_PA3 1 &pcfg_pull_up_4ma>; 1612 }; 1613 1614 sdmmc_pwren: sdmmc-pwren { 1615 rockchip,pins = 1616 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 1617 }; 1618 1619 sdmmc_bus1: sdmmc-bus1 { 1620 rockchip,pins = 1621 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 1622 }; 1623 1624 sdmmc_bus4: sdmmc-bus4 { 1625 rockchip,pins = 1626 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 1627 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 1628 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 1629 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 1630 }; 1631 }; 1632 1633 sdio { 1634 sdio_clk: sdio-clk { 1635 rockchip,pins = 1636 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 1637 }; 1638 1639 sdio_cmd: sdio-cmd { 1640 rockchip,pins = 1641 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 1642 }; 1643 1644 sdio_pwren: sdio-pwren { 1645 rockchip,pins = 1646 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 1647 }; 1648 1649 sdio_wrpt: sdio-wrpt { 1650 rockchip,pins = 1651 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 1652 }; 1653 1654 sdio_intn: sdio-intn { 1655 rockchip,pins = 1656 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 1657 }; 1658 1659 sdio_bus1: sdio-bus1 { 1660 rockchip,pins = 1661 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 1662 }; 1663 1664 sdio_bus4: sdio-bus4 { 1665 rockchip,pins = 1666 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 1667 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 1668 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 1669 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 1670 }; 1671 }; 1672 1673 spdif_in { 1674 spdif_in: spdif-in { 1675 rockchip,pins = 1676 <0 RK_PC2 1 &pcfg_pull_none>; 1677 }; 1678 }; 1679 1680 spdif_out { 1681 spdif_out: spdif-out { 1682 rockchip,pins = 1683 <0 RK_PC1 1 &pcfg_pull_none>; 1684 }; 1685 }; 1686 1687 spi0 { 1688 spi0_clk: spi0-clk { 1689 rockchip,pins = 1690 <2 RK_PA2 2 &pcfg_pull_up_4ma>; 1691 }; 1692 1693 spi0_csn0: spi0-csn0 { 1694 rockchip,pins = 1695 <2 RK_PA3 2 &pcfg_pull_up_4ma>; 1696 }; 1697 1698 spi0_miso: spi0-miso { 1699 rockchip,pins = 1700 <2 RK_PA0 2 &pcfg_pull_up_4ma>; 1701 }; 1702 1703 spi0_mosi: spi0-mosi { 1704 rockchip,pins = 1705 <2 RK_PA1 2 &pcfg_pull_up_4ma>; 1706 }; 1707 }; 1708 1709 spi1 { 1710 spi1_clk: spi1-clk { 1711 rockchip,pins = 1712 <3 RK_PB3 3 &pcfg_pull_up_4ma>; 1713 }; 1714 1715 spi1_csn0: spi1-csn0 { 1716 rockchip,pins = 1717 <3 RK_PB5 3 &pcfg_pull_up_4ma>; 1718 }; 1719 1720 spi1_miso: spi1-miso { 1721 rockchip,pins = 1722 <3 RK_PB2 3 &pcfg_pull_up_4ma>; 1723 }; 1724 1725 spi1_mosi: spi1-mosi { 1726 rockchip,pins = 1727 <3 RK_PB4 3 &pcfg_pull_up_4ma>; 1728 }; 1729 }; 1730 1731 spi1-m1 { 1732 spi1m1_miso: spi1m1-miso { 1733 rockchip,pins = 1734 <2 RK_PA4 2 &pcfg_pull_up_4ma>; 1735 }; 1736 1737 spi1m1_mosi: spi1m1-mosi { 1738 rockchip,pins = 1739 <2 RK_PA5 2 &pcfg_pull_up_4ma>; 1740 }; 1741 1742 spi1m1_clk: spi1m1-clk { 1743 rockchip,pins = 1744 <2 RK_PA7 2 &pcfg_pull_up_4ma>; 1745 }; 1746 1747 spi1m1_csn0: spi1m1-csn0 { 1748 rockchip,pins = 1749 <2 RK_PB1 2 &pcfg_pull_up_4ma>; 1750 }; 1751 }; 1752 1753 spi2 { 1754 spi2_clk: spi2-clk { 1755 rockchip,pins = 1756 <1 RK_PD0 3 &pcfg_pull_up_4ma>; 1757 }; 1758 1759 spi2_csn0: spi2-csn0 { 1760 rockchip,pins = 1761 <1 RK_PD1 3 &pcfg_pull_up_4ma>; 1762 }; 1763 1764 spi2_miso: spi2-miso { 1765 rockchip,pins = 1766 <1 RK_PC6 3 &pcfg_pull_up_4ma>; 1767 }; 1768 1769 spi2_mosi: spi2-mosi { 1770 rockchip,pins = 1771 <1 RK_PC7 3 &pcfg_pull_up_4ma>; 1772 }; 1773 }; 1774 1775 tsadc { 1776 tsadc_otp_pin: tsadc-otp-pin { 1777 rockchip,pins = 1778 <0 RK_PB2 0 &pcfg_pull_none>; 1779 }; 1780 1781 tsadc_otp_out: tsadc-otp-out { 1782 rockchip,pins = 1783 <0 RK_PB2 1 &pcfg_pull_none>; 1784 }; 1785 }; 1786 1787 uart0 { 1788 uart0_xfer: uart0-xfer { 1789 rockchip,pins = 1790 <2 RK_PA1 1 &pcfg_pull_up>, 1791 <2 RK_PA0 1 &pcfg_pull_up>; 1792 }; 1793 1794 uart0_cts: uart0-cts { 1795 rockchip,pins = 1796 <2 RK_PA2 1 &pcfg_pull_none>; 1797 }; 1798 1799 uart0_rts: uart0-rts { 1800 rockchip,pins = 1801 <2 RK_PA3 1 &pcfg_pull_none>; 1802 }; 1803 1804 uart0_rts_pin: uart0-rts-pin { 1805 rockchip,pins = 1806 <2 RK_PA3 0 &pcfg_pull_none>; 1807 }; 1808 }; 1809 1810 uart1 { 1811 uart1_xfer: uart1-xfer { 1812 rockchip,pins = 1813 <1 RK_PD1 1 &pcfg_pull_up>, 1814 <1 RK_PD0 1 &pcfg_pull_up>; 1815 }; 1816 1817 uart1_cts: uart1-cts { 1818 rockchip,pins = 1819 <1 RK_PC6 1 &pcfg_pull_none>; 1820 }; 1821 1822 uart1_rts: uart1-rts { 1823 rockchip,pins = 1824 <1 RK_PC7 1 &pcfg_pull_none>; 1825 }; 1826 }; 1827 1828 uart2-m0 { 1829 uart2m0_xfer: uart2m0-xfer { 1830 rockchip,pins = 1831 <1 RK_PC7 2 &pcfg_pull_up>, 1832 <1 RK_PC6 2 &pcfg_pull_up>; 1833 }; 1834 }; 1835 1836 uart2-m1 { 1837 uart2m1_xfer: uart2m1-xfer { 1838 rockchip,pins = 1839 <4 RK_PD3 2 &pcfg_pull_up>, 1840 <4 RK_PD2 2 &pcfg_pull_up>; 1841 }; 1842 }; 1843 1844 uart3 { 1845 uart3_xfer: uart3-xfer { 1846 rockchip,pins = 1847 <3 RK_PB5 4 &pcfg_pull_up>, 1848 <3 RK_PB4 4 &pcfg_pull_up>; 1849 }; 1850 }; 1851 1852 uart3-m1 { 1853 uart3m1_xfer: uart3m1-xfer { 1854 rockchip,pins = 1855 <0 RK_PC2 3 &pcfg_pull_up>, 1856 <0 RK_PC1 3 &pcfg_pull_up>; 1857 }; 1858 }; 1859 1860 uart4 { 1861 uart4_xfer: uart4-xfer { 1862 rockchip,pins = 1863 <4 RK_PB1 1 &pcfg_pull_up>, 1864 <4 RK_PB0 1 &pcfg_pull_up>; 1865 }; 1866 1867 uart4_cts: uart4-cts { 1868 rockchip,pins = 1869 <4 RK_PA6 1 &pcfg_pull_none>; 1870 }; 1871 1872 uart4_rts: uart4-rts { 1873 rockchip,pins = 1874 <4 RK_PA7 1 &pcfg_pull_none>; 1875 }; 1876 1877 uart4_rts_pin: uart4-rts-pin { 1878 rockchip,pins = 1879 <4 RK_PA7 0 &pcfg_pull_none>; 1880 }; 1881 }; 1882 }; 1883}; 1884