1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7#include <dt-bindings/clock/rk3308-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3308"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 mmc0 = &sdmmc; 28 mmc1 = &emmc; 29 mmc2 = &sdio; 30 serial0 = &uart0; 31 serial1 = &uart1; 32 serial2 = &uart2; 33 serial3 = &uart3; 34 serial4 = &uart4; 35 spi0 = &spi0; 36 spi1 = &spi1; 37 spi2 = &spi2; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 cpu0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a35"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 clocks = <&cru ARMCLK>; 50 #cooling-cells = <2>; 51 dynamic-power-coefficient = <90>; 52 operating-points-v2 = <&cpu0_opp_table>; 53 cpu-idle-states = <&CPU_SLEEP>; 54 next-level-cache = <&l2>; 55 }; 56 57 cpu1: cpu@1 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a35"; 60 reg = <0x0 0x1>; 61 enable-method = "psci"; 62 operating-points-v2 = <&cpu0_opp_table>; 63 cpu-idle-states = <&CPU_SLEEP>; 64 next-level-cache = <&l2>; 65 }; 66 67 cpu2: cpu@2 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a35"; 70 reg = <0x0 0x2>; 71 enable-method = "psci"; 72 operating-points-v2 = <&cpu0_opp_table>; 73 cpu-idle-states = <&CPU_SLEEP>; 74 next-level-cache = <&l2>; 75 }; 76 77 cpu3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a35"; 80 reg = <0x0 0x3>; 81 enable-method = "psci"; 82 operating-points-v2 = <&cpu0_opp_table>; 83 cpu-idle-states = <&CPU_SLEEP>; 84 next-level-cache = <&l2>; 85 }; 86 87 idle-states { 88 entry-method = "psci"; 89 90 CPU_SLEEP: cpu-sleep { 91 compatible = "arm,idle-state"; 92 local-timer-stop; 93 arm,psci-suspend-param = <0x0010000>; 94 entry-latency-us = <120>; 95 exit-latency-us = <250>; 96 min-residency-us = <900>; 97 }; 98 }; 99 100 l2: l2-cache { 101 compatible = "cache"; 102 }; 103 }; 104 105 cpu0_opp_table: cpu0-opp-table { 106 compatible = "operating-points-v2"; 107 opp-shared; 108 109 opp-408000000 { 110 opp-hz = /bits/ 64 <408000000>; 111 opp-microvolt = <950000 950000 1340000>; 112 clock-latency-ns = <40000>; 113 opp-suspend; 114 }; 115 opp-600000000 { 116 opp-hz = /bits/ 64 <600000000>; 117 opp-microvolt = <950000 950000 1340000>; 118 clock-latency-ns = <40000>; 119 }; 120 opp-816000000 { 121 opp-hz = /bits/ 64 <816000000>; 122 opp-microvolt = <1025000 1025000 1340000>; 123 clock-latency-ns = <40000>; 124 }; 125 opp-1008000000 { 126 opp-hz = /bits/ 64 <1008000000>; 127 opp-microvolt = <1125000 1125000 1340000>; 128 clock-latency-ns = <40000>; 129 }; 130 }; 131 132 arm-pmu { 133 compatible = "arm,cortex-a35-pmu"; 134 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 138 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 139 }; 140 141 mac_clkin: external-mac-clock { 142 compatible = "fixed-clock"; 143 clock-frequency = <50000000>; 144 clock-output-names = "mac_clkin"; 145 #clock-cells = <0>; 146 }; 147 148 psci { 149 compatible = "arm,psci-1.0"; 150 method = "smc"; 151 }; 152 153 timer { 154 compatible = "arm,armv8-timer"; 155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 159 }; 160 161 xin24m: xin24m { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <24000000>; 165 clock-output-names = "xin24m"; 166 }; 167 168 grf: grf@ff000000 { 169 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 170 reg = <0x0 0xff000000 0x0 0x10000>; 171 172 reboot-mode { 173 compatible = "syscon-reboot-mode"; 174 offset = <0x500>; 175 mode-bootloader = <BOOT_BL_DOWNLOAD>; 176 mode-loader = <BOOT_BL_DOWNLOAD>; 177 mode-normal = <BOOT_NORMAL>; 178 mode-recovery = <BOOT_RECOVERY>; 179 mode-fastboot = <BOOT_FASTBOOT>; 180 }; 181 }; 182 183 detect_grf: syscon@ff00b000 { 184 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; 185 reg = <0x0 0xff00b000 0x0 0x1000>; 186 #address-cells = <1>; 187 #size-cells = <1>; 188 }; 189 190 core_grf: syscon@ff00c000 { 191 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; 192 reg = <0x0 0xff00c000 0x0 0x1000>; 193 #address-cells = <1>; 194 #size-cells = <1>; 195 }; 196 197 i2c0: i2c@ff040000 { 198 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 199 reg = <0x0 0xff040000 0x0 0x1000>; 200 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 201 clock-names = "i2c", "pclk"; 202 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 203 pinctrl-names = "default"; 204 pinctrl-0 = <&i2c0_xfer>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 status = "disabled"; 208 }; 209 210 i2c1: i2c@ff050000 { 211 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 212 reg = <0x0 0xff050000 0x0 0x1000>; 213 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 214 clock-names = "i2c", "pclk"; 215 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&i2c1_xfer>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2c2: i2c@ff060000 { 224 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 225 reg = <0x0 0xff060000 0x0 0x1000>; 226 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 227 clock-names = "i2c", "pclk"; 228 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&i2c2_xfer>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 status = "disabled"; 234 }; 235 236 i2c3: i2c@ff070000 { 237 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 238 reg = <0x0 0xff070000 0x0 0x1000>; 239 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 240 clock-names = "i2c", "pclk"; 241 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&i2c3m0_xfer>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 status = "disabled"; 247 }; 248 249 wdt: watchdog@ff080000 { 250 compatible = "snps,dw-wdt"; 251 reg = <0x0 0xff080000 0x0 0x100>; 252 clocks = <&cru PCLK_WDT>; 253 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 254 status = "disabled"; 255 }; 256 257 uart0: serial@ff0a0000 { 258 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 259 reg = <0x0 0xff0a0000 0x0 0x100>; 260 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 262 clock-names = "baudclk", "apb_pclk"; 263 reg-shift = <2>; 264 reg-io-width = <4>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 267 status = "disabled"; 268 }; 269 270 uart1: serial@ff0b0000 { 271 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 272 reg = <0x0 0xff0b0000 0x0 0x100>; 273 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 275 clock-names = "baudclk", "apb_pclk"; 276 reg-shift = <2>; 277 reg-io-width = <4>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 280 status = "disabled"; 281 }; 282 283 uart2: serial@ff0c0000 { 284 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 285 reg = <0x0 0xff0c0000 0x0 0x100>; 286 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 288 clock-names = "baudclk", "apb_pclk"; 289 reg-shift = <2>; 290 reg-io-width = <4>; 291 pinctrl-names = "default"; 292 pinctrl-0 = <&uart2m0_xfer>; 293 status = "disabled"; 294 }; 295 296 uart3: serial@ff0d0000 { 297 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 298 reg = <0x0 0xff0d0000 0x0 0x100>; 299 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 301 clock-names = "baudclk", "apb_pclk"; 302 reg-shift = <2>; 303 reg-io-width = <4>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&uart3_xfer>; 306 status = "disabled"; 307 }; 308 309 uart4: serial@ff0e0000 { 310 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 311 reg = <0x0 0xff0e0000 0x0 0x100>; 312 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 314 clock-names = "baudclk", "apb_pclk"; 315 reg-shift = <2>; 316 reg-io-width = <4>; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 319 status = "disabled"; 320 }; 321 322 spi0: spi@ff120000 { 323 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 324 reg = <0x0 0xff120000 0x0 0x1000>; 325 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 329 clock-names = "spiclk", "apb_pclk"; 330 dmas = <&dmac0 0>, <&dmac0 1>; 331 dma-names = "tx", "rx"; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; 334 status = "disabled"; 335 }; 336 337 spi1: spi@ff130000 { 338 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 339 reg = <0x0 0xff130000 0x0 0x1000>; 340 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 344 clock-names = "spiclk", "apb_pclk"; 345 dmas = <&dmac0 2>, <&dmac0 3>; 346 dma-names = "tx", "rx"; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; 349 status = "disabled"; 350 }; 351 352 spi2: spi@ff140000 { 353 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 354 reg = <0x0 0xff140000 0x0 0x1000>; 355 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 359 clock-names = "spiclk", "apb_pclk"; 360 dmas = <&dmac1 16>, <&dmac1 17>; 361 dma-names = "tx", "rx"; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; 364 status = "disabled"; 365 }; 366 367 pwm8: pwm@ff160000 { 368 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 369 reg = <0x0 0xff160000 0x0 0x10>; 370 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 371 clock-names = "pwm", "pclk"; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&pwm8_pin>; 374 #pwm-cells = <3>; 375 status = "disabled"; 376 }; 377 378 pwm9: pwm@ff160010 { 379 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 380 reg = <0x0 0xff160010 0x0 0x10>; 381 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 382 clock-names = "pwm", "pclk"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pwm9_pin>; 385 #pwm-cells = <3>; 386 status = "disabled"; 387 }; 388 389 pwm10: pwm@ff160020 { 390 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 391 reg = <0x0 0xff160020 0x0 0x10>; 392 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 393 clock-names = "pwm", "pclk"; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&pwm10_pin>; 396 #pwm-cells = <3>; 397 status = "disabled"; 398 }; 399 400 pwm11: pwm@ff160030 { 401 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 402 reg = <0x0 0xff160030 0x0 0x10>; 403 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 404 clock-names = "pwm", "pclk"; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&pwm11_pin>; 407 #pwm-cells = <3>; 408 status = "disabled"; 409 }; 410 411 pwm4: pwm@ff170000 { 412 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 413 reg = <0x0 0xff170000 0x0 0x10>; 414 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 415 clock-names = "pwm", "pclk"; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pwm4_pin>; 418 #pwm-cells = <3>; 419 status = "disabled"; 420 }; 421 422 pwm5: pwm@ff170010 { 423 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 424 reg = <0x0 0xff170010 0x0 0x10>; 425 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 426 clock-names = "pwm", "pclk"; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&pwm5_pin>; 429 #pwm-cells = <3>; 430 status = "disabled"; 431 }; 432 433 pwm6: pwm@ff170020 { 434 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 435 reg = <0x0 0xff170020 0x0 0x10>; 436 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 437 clock-names = "pwm", "pclk"; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&pwm6_pin>; 440 #pwm-cells = <3>; 441 status = "disabled"; 442 }; 443 444 pwm7: pwm@ff170030 { 445 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 446 reg = <0x0 0xff170030 0x0 0x10>; 447 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 448 clock-names = "pwm", "pclk"; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pwm7_pin>; 451 #pwm-cells = <3>; 452 status = "disabled"; 453 }; 454 455 pwm0: pwm@ff180000 { 456 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 457 reg = <0x0 0xff180000 0x0 0x10>; 458 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 459 clock-names = "pwm", "pclk"; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&pwm0_pin>; 462 #pwm-cells = <3>; 463 status = "disabled"; 464 }; 465 466 pwm1: pwm@ff180010 { 467 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 468 reg = <0x0 0xff180010 0x0 0x10>; 469 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 470 clock-names = "pwm", "pclk"; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&pwm1_pin>; 473 #pwm-cells = <3>; 474 status = "disabled"; 475 }; 476 477 pwm2: pwm@ff180020 { 478 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 479 reg = <0x0 0xff180020 0x0 0x10>; 480 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 481 clock-names = "pwm", "pclk"; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&pwm2_pin>; 484 #pwm-cells = <3>; 485 status = "disabled"; 486 }; 487 488 pwm3: pwm@ff180030 { 489 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 490 reg = <0x0 0xff180030 0x0 0x10>; 491 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 492 clock-names = "pwm", "pclk"; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pwm3_pin>; 495 #pwm-cells = <3>; 496 status = "disabled"; 497 }; 498 499 rktimer: rktimer@ff1a0000 { 500 compatible = "rockchip,rk3288-timer"; 501 reg = <0x0 0xff1a0000 0x0 0x20>; 502 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 504 clock-names = "pclk", "timer"; 505 }; 506 507 saradc: saradc@ff1e0000 { 508 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 509 reg = <0x0 0xff1e0000 0x0 0x100>; 510 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 512 clock-names = "saradc", "apb_pclk"; 513 #io-channel-cells = <1>; 514 resets = <&cru SRST_SARADC_P>; 515 reset-names = "saradc-apb"; 516 status = "disabled"; 517 }; 518 519 dmac0: dma-controller@ff2c0000 { 520 compatible = "arm,pl330", "arm,primecell"; 521 reg = <0x0 0xff2c0000 0x0 0x4000>; 522 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 524 arm,pl330-periph-burst; 525 clocks = <&cru ACLK_DMAC0>; 526 clock-names = "apb_pclk"; 527 #dma-cells = <1>; 528 }; 529 530 dmac1: dma-controller@ff2d0000 { 531 compatible = "arm,pl330", "arm,primecell"; 532 reg = <0x0 0xff2d0000 0x0 0x4000>; 533 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 535 arm,pl330-periph-burst; 536 clocks = <&cru ACLK_DMAC1>; 537 clock-names = "apb_pclk"; 538 #dma-cells = <1>; 539 }; 540 541 i2s_2ch_0: i2s@ff350000 { 542 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 543 reg = <0x0 0xff350000 0x0 0x1000>; 544 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; 546 clock-names = "i2s_clk", "i2s_hclk"; 547 dmas = <&dmac1 8>, <&dmac1 9>; 548 dma-names = "tx", "rx"; 549 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; 550 reset-names = "reset-m", "reset-h"; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&i2s_2ch_0_sclk 553 &i2s_2ch_0_lrck 554 &i2s_2ch_0_sdi 555 &i2s_2ch_0_sdo>; 556 status = "disabled"; 557 }; 558 559 i2s_2ch_1: i2s@ff360000 { 560 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 561 reg = <0x0 0xff360000 0x0 0x1000>; 562 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 564 clock-names = "i2s_clk", "i2s_hclk"; 565 dmas = <&dmac1 11>; 566 dma-names = "rx"; 567 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; 568 reset-names = "reset-m", "reset-h"; 569 status = "disabled"; 570 }; 571 572 spdif_tx: spdif-tx@ff3a0000 { 573 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; 574 reg = <0x0 0xff3a0000 0x0 0x1000>; 575 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; 577 clock-names = "mclk", "hclk"; 578 dmas = <&dmac1 13>; 579 dma-names = "tx"; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&spdif_out>; 582 status = "disabled"; 583 }; 584 585 sdmmc: mmc@ff480000 { 586 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 587 reg = <0x0 0xff480000 0x0 0x4000>; 588 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 589 bus-width = <4>; 590 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 591 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 592 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 593 fifo-depth = <0x100>; 594 max-frequency = <150000000>; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 597 status = "disabled"; 598 }; 599 600 emmc: mmc@ff490000 { 601 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 602 reg = <0x0 0xff490000 0x0 0x4000>; 603 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 604 bus-width = <8>; 605 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 606 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 607 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 608 fifo-depth = <0x100>; 609 max-frequency = <150000000>; 610 status = "disabled"; 611 }; 612 613 sdio: mmc@ff4a0000 { 614 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 615 reg = <0x0 0xff4a0000 0x0 0x4000>; 616 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 617 bus-width = <4>; 618 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 619 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 620 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 621 fifo-depth = <0x100>; 622 max-frequency = <150000000>; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 625 status = "disabled"; 626 }; 627 628 nfc: nand-controller@ff4b0000 { 629 compatible = "rockchip,rk3308-nfc", 630 "rockchip,rv1108-nfc"; 631 reg = <0x0 0xff4b0000 0x0 0x4000>; 632 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 634 clock-names = "ahb", "nfc"; 635 assigned-clocks = <&cru SCLK_NANDC>; 636 assigned-clock-rates = <150000000>; 637 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 638 &flash_rdn &flash_rdy &flash_wrn>; 639 pinctrl-names = "default"; 640 status = "disabled"; 641 }; 642 643 cru: clock-controller@ff500000 { 644 compatible = "rockchip,rk3308-cru"; 645 reg = <0x0 0xff500000 0x0 0x1000>; 646 #clock-cells = <1>; 647 #reset-cells = <1>; 648 rockchip,grf = <&grf>; 649 650 assigned-clocks = <&cru SCLK_RTC32K>; 651 assigned-clock-rates = <32768>; 652 }; 653 654 gic: interrupt-controller@ff580000 { 655 compatible = "arm,gic-400"; 656 reg = <0x0 0xff581000 0x0 0x1000>, 657 <0x0 0xff582000 0x0 0x2000>, 658 <0x0 0xff584000 0x0 0x2000>, 659 <0x0 0xff586000 0x0 0x2000>; 660 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 661 #interrupt-cells = <3>; 662 interrupt-controller; 663 #address-cells = <0>; 664 }; 665 666 sram: sram@fff80000 { 667 compatible = "mmio-sram"; 668 reg = <0x0 0xfff80000 0x0 0x40000>; 669 ranges = <0 0x0 0xfff80000 0x40000>; 670 #address-cells = <1>; 671 #size-cells = <1>; 672 673 /* reserved for ddr dvfs and system suspend/resume */ 674 ddr-sram@0 { 675 reg = <0x0 0x8000>; 676 }; 677 678 /* reserved for vad audio buffer */ 679 vad_sram: vad-sram@8000 { 680 reg = <0x8000 0x38000>; 681 }; 682 }; 683 684 pinctrl: pinctrl { 685 compatible = "rockchip,rk3308-pinctrl"; 686 rockchip,grf = <&grf>; 687 #address-cells = <2>; 688 #size-cells = <2>; 689 ranges; 690 691 gpio0: gpio0@ff220000 { 692 compatible = "rockchip,gpio-bank"; 693 reg = <0x0 0xff220000 0x0 0x100>; 694 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&cru PCLK_GPIO0>; 696 gpio-controller; 697 #gpio-cells = <2>; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 }; 701 702 gpio1: gpio1@ff230000 { 703 compatible = "rockchip,gpio-bank"; 704 reg = <0x0 0xff230000 0x0 0x100>; 705 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&cru PCLK_GPIO1>; 707 gpio-controller; 708 #gpio-cells = <2>; 709 interrupt-controller; 710 #interrupt-cells = <2>; 711 }; 712 713 gpio2: gpio2@ff240000 { 714 compatible = "rockchip,gpio-bank"; 715 reg = <0x0 0xff240000 0x0 0x100>; 716 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&cru PCLK_GPIO2>; 718 gpio-controller; 719 #gpio-cells = <2>; 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 }; 723 724 gpio3: gpio3@ff250000 { 725 compatible = "rockchip,gpio-bank"; 726 reg = <0x0 0xff250000 0x0 0x100>; 727 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&cru PCLK_GPIO3>; 729 gpio-controller; 730 #gpio-cells = <2>; 731 interrupt-controller; 732 #interrupt-cells = <2>; 733 }; 734 735 gpio4: gpio4@ff260000 { 736 compatible = "rockchip,gpio-bank"; 737 reg = <0x0 0xff260000 0x0 0x100>; 738 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&cru PCLK_GPIO4>; 740 gpio-controller; 741 #gpio-cells = <2>; 742 interrupt-controller; 743 #interrupt-cells = <2>; 744 }; 745 746 pcfg_pull_up: pcfg-pull-up { 747 bias-pull-up; 748 }; 749 750 pcfg_pull_down: pcfg-pull-down { 751 bias-pull-down; 752 }; 753 754 pcfg_pull_none: pcfg-pull-none { 755 bias-disable; 756 }; 757 758 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 759 bias-disable; 760 drive-strength = <2>; 761 }; 762 763 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 764 bias-pull-up; 765 drive-strength = <2>; 766 }; 767 768 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 769 bias-pull-up; 770 drive-strength = <4>; 771 }; 772 773 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 774 bias-disable; 775 drive-strength = <4>; 776 }; 777 778 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 779 bias-pull-down; 780 drive-strength = <4>; 781 }; 782 783 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 784 bias-disable; 785 drive-strength = <8>; 786 }; 787 788 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 789 bias-pull-up; 790 drive-strength = <8>; 791 }; 792 793 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 794 bias-disable; 795 drive-strength = <12>; 796 }; 797 798 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 799 bias-pull-up; 800 drive-strength = <12>; 801 }; 802 803 pcfg_pull_none_smt: pcfg-pull-none-smt { 804 bias-disable; 805 input-schmitt-enable; 806 }; 807 808 pcfg_output_high: pcfg-output-high { 809 output-high; 810 }; 811 812 pcfg_output_low: pcfg-output-low { 813 output-low; 814 }; 815 816 pcfg_input_high: pcfg-input-high { 817 bias-pull-up; 818 input-enable; 819 }; 820 821 pcfg_input: pcfg-input { 822 input-enable; 823 }; 824 825 emmc { 826 emmc_clk: emmc-clk { 827 rockchip,pins = 828 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 829 }; 830 831 emmc_cmd: emmc-cmd { 832 rockchip,pins = 833 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 834 }; 835 836 emmc_pwren: emmc-pwren { 837 rockchip,pins = 838 <3 RK_PB3 2 &pcfg_pull_none>; 839 }; 840 841 emmc_rstn: emmc-rstn { 842 rockchip,pins = 843 <3 RK_PB2 2 &pcfg_pull_none>; 844 }; 845 846 emmc_bus1: emmc-bus1 { 847 rockchip,pins = 848 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 849 }; 850 851 emmc_bus4: emmc-bus4 { 852 rockchip,pins = 853 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 854 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 855 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 856 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 857 }; 858 859 emmc_bus8: emmc-bus8 { 860 rockchip,pins = 861 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 862 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 863 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 864 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 865 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 866 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 867 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 868 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 869 }; 870 }; 871 872 flash { 873 flash_csn0: flash-csn0 { 874 rockchip,pins = 875 <3 RK_PB5 1 &pcfg_pull_none>; 876 }; 877 878 flash_rdy: flash-rdy { 879 rockchip,pins = 880 <3 RK_PB4 1 &pcfg_pull_none>; 881 }; 882 883 flash_ale: flash-ale { 884 rockchip,pins = 885 <3 RK_PB3 1 &pcfg_pull_none>; 886 }; 887 888 flash_cle: flash-cle { 889 rockchip,pins = 890 <3 RK_PB1 1 &pcfg_pull_none>; 891 }; 892 893 flash_wrn: flash-wrn { 894 rockchip,pins = 895 <3 RK_PB0 1 &pcfg_pull_none>; 896 }; 897 898 flash_rdn: flash-rdn { 899 rockchip,pins = 900 <3 RK_PB2 1 &pcfg_pull_none>; 901 }; 902 903 flash_bus8: flash-bus8 { 904 rockchip,pins = 905 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 906 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 907 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 908 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 909 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 910 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 911 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 912 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 913 }; 914 }; 915 916 gmac { 917 rmii_pins: rmii-pins { 918 rockchip,pins = 919 /* mac_txen */ 920 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 921 /* mac_txd1 */ 922 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 923 /* mac_txd0 */ 924 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 925 /* mac_rxd0 */ 926 <1 RK_PC4 3 &pcfg_pull_none>, 927 /* mac_rxd1 */ 928 <1 RK_PC5 3 &pcfg_pull_none>, 929 /* mac_rxer */ 930 <1 RK_PB7 3 &pcfg_pull_none>, 931 /* mac_rxdv */ 932 <1 RK_PC0 3 &pcfg_pull_none>, 933 /* mac_mdio */ 934 <1 RK_PB6 3 &pcfg_pull_none>, 935 /* mac_mdc */ 936 <1 RK_PB5 3 &pcfg_pull_none>; 937 }; 938 939 mac_refclk_12ma: mac-refclk-12ma { 940 rockchip,pins = 941 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 942 }; 943 944 mac_refclk: mac-refclk { 945 rockchip,pins = 946 <1 RK_PB4 3 &pcfg_pull_none>; 947 }; 948 }; 949 950 gmac-m1 { 951 rmiim1_pins: rmiim1-pins { 952 rockchip,pins = 953 /* mac_txen */ 954 <4 RK_PB7 2 &pcfg_pull_none_12ma>, 955 /* mac_txd1 */ 956 <4 RK_PA5 2 &pcfg_pull_none_12ma>, 957 /* mac_txd0 */ 958 <4 RK_PA4 2 &pcfg_pull_none_12ma>, 959 /* mac_rxd0 */ 960 <4 RK_PA2 2 &pcfg_pull_none>, 961 /* mac_rxd1 */ 962 <4 RK_PA3 2 &pcfg_pull_none>, 963 /* mac_rxer */ 964 <4 RK_PA0 2 &pcfg_pull_none>, 965 /* mac_rxdv */ 966 <4 RK_PA1 2 &pcfg_pull_none>, 967 /* mac_mdio */ 968 <4 RK_PB6 2 &pcfg_pull_none>, 969 /* mac_mdc */ 970 <4 RK_PB5 2 &pcfg_pull_none>; 971 }; 972 973 macm1_refclk_12ma: macm1-refclk-12ma { 974 rockchip,pins = 975 <4 RK_PB4 2 &pcfg_pull_none_12ma>; 976 }; 977 978 macm1_refclk: macm1-refclk { 979 rockchip,pins = 980 <4 RK_PB4 2 &pcfg_pull_none>; 981 }; 982 }; 983 984 i2c0 { 985 i2c0_xfer: i2c0-xfer { 986 rockchip,pins = 987 <1 RK_PD0 2 &pcfg_pull_none_smt>, 988 <1 RK_PD1 2 &pcfg_pull_none_smt>; 989 }; 990 }; 991 992 i2c1 { 993 i2c1_xfer: i2c1-xfer { 994 rockchip,pins = 995 <0 RK_PB3 1 &pcfg_pull_none_smt>, 996 <0 RK_PB4 1 &pcfg_pull_none_smt>; 997 }; 998 }; 999 1000 i2c2 { 1001 i2c2_xfer: i2c2-xfer { 1002 rockchip,pins = 1003 <2 RK_PA2 3 &pcfg_pull_none_smt>, 1004 <2 RK_PA3 3 &pcfg_pull_none_smt>; 1005 }; 1006 }; 1007 1008 i2c3-m0 { 1009 i2c3m0_xfer: i2c3m0-xfer { 1010 rockchip,pins = 1011 <0 RK_PB7 2 &pcfg_pull_none_smt>, 1012 <0 RK_PC0 2 &pcfg_pull_none_smt>; 1013 }; 1014 }; 1015 1016 i2c3-m1 { 1017 i2c3m1_xfer: i2c3m1-xfer { 1018 rockchip,pins = 1019 <3 RK_PB4 2 &pcfg_pull_none_smt>, 1020 <3 RK_PB5 2 &pcfg_pull_none_smt>; 1021 }; 1022 }; 1023 1024 i2c3-m2 { 1025 i2c3m2_xfer: i2c3m2-xfer { 1026 rockchip,pins = 1027 <2 RK_PA1 3 &pcfg_pull_none_smt>, 1028 <2 RK_PA0 3 &pcfg_pull_none_smt>; 1029 }; 1030 }; 1031 1032 i2s_2ch_0 { 1033 i2s_2ch_0_mclk: i2s-2ch-0-mclk { 1034 rockchip,pins = 1035 <4 RK_PB4 1 &pcfg_pull_none>; 1036 }; 1037 1038 i2s_2ch_0_sclk: i2s-2ch-0-sclk { 1039 rockchip,pins = 1040 <4 RK_PB5 1 &pcfg_pull_none>; 1041 }; 1042 1043 i2s_2ch_0_lrck: i2s-2ch-0-lrck { 1044 rockchip,pins = 1045 <4 RK_PB6 1 &pcfg_pull_none>; 1046 }; 1047 1048 i2s_2ch_0_sdo: i2s-2ch-0-sdo { 1049 rockchip,pins = 1050 <4 RK_PB7 1 &pcfg_pull_none>; 1051 }; 1052 1053 i2s_2ch_0_sdi: i2s-2ch-0-sdi { 1054 rockchip,pins = 1055 <4 RK_PC0 1 &pcfg_pull_none>; 1056 }; 1057 }; 1058 1059 i2s_8ch_0 { 1060 i2s_8ch_0_mclk: i2s-8ch-0-mclk { 1061 rockchip,pins = 1062 <2 RK_PA4 1 &pcfg_pull_none>; 1063 }; 1064 1065 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { 1066 rockchip,pins = 1067 <2 RK_PA5 1 &pcfg_pull_none>; 1068 }; 1069 1070 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { 1071 rockchip,pins = 1072 <2 RK_PA6 1 &pcfg_pull_none>; 1073 }; 1074 1075 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { 1076 rockchip,pins = 1077 <2 RK_PA7 1 &pcfg_pull_none>; 1078 }; 1079 1080 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { 1081 rockchip,pins = 1082 <2 RK_PB0 1 &pcfg_pull_none>; 1083 }; 1084 1085 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { 1086 rockchip,pins = 1087 <2 RK_PB1 1 &pcfg_pull_none>; 1088 }; 1089 1090 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { 1091 rockchip,pins = 1092 <2 RK_PB2 1 &pcfg_pull_none>; 1093 }; 1094 1095 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { 1096 rockchip,pins = 1097 <2 RK_PB3 1 &pcfg_pull_none>; 1098 }; 1099 1100 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { 1101 rockchip,pins = 1102 <2 RK_PB4 1 &pcfg_pull_none>; 1103 }; 1104 1105 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { 1106 rockchip,pins = 1107 <2 RK_PB5 1 &pcfg_pull_none>; 1108 }; 1109 1110 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { 1111 rockchip,pins = 1112 <2 RK_PB6 1 &pcfg_pull_none>; 1113 }; 1114 1115 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { 1116 rockchip,pins = 1117 <2 RK_PB7 1 &pcfg_pull_none>; 1118 }; 1119 1120 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { 1121 rockchip,pins = 1122 <2 RK_PC0 1 &pcfg_pull_none>; 1123 }; 1124 }; 1125 1126 i2s_8ch_1_m0 { 1127 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { 1128 rockchip,pins = 1129 <1 RK_PA2 2 &pcfg_pull_none>; 1130 }; 1131 1132 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { 1133 rockchip,pins = 1134 <1 RK_PA3 2 &pcfg_pull_none>; 1135 }; 1136 1137 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { 1138 rockchip,pins = 1139 <1 RK_PA4 2 &pcfg_pull_none>; 1140 }; 1141 1142 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { 1143 rockchip,pins = 1144 <1 RK_PA5 2 &pcfg_pull_none>; 1145 }; 1146 1147 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { 1148 rockchip,pins = 1149 <1 RK_PA6 2 &pcfg_pull_none>; 1150 }; 1151 1152 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { 1153 rockchip,pins = 1154 <1 RK_PA7 2 &pcfg_pull_none>; 1155 }; 1156 1157 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { 1158 rockchip,pins = 1159 <1 RK_PB0 2 &pcfg_pull_none>; 1160 }; 1161 1162 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { 1163 rockchip,pins = 1164 <1 RK_PB1 2 &pcfg_pull_none>; 1165 }; 1166 1167 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { 1168 rockchip,pins = 1169 <1 RK_PB2 2 &pcfg_pull_none>; 1170 }; 1171 1172 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { 1173 rockchip,pins = 1174 <1 RK_PB3 2 &pcfg_pull_none>; 1175 }; 1176 }; 1177 1178 i2s_8ch_1_m1 { 1179 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { 1180 rockchip,pins = 1181 <1 RK_PB4 2 &pcfg_pull_none>; 1182 }; 1183 1184 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { 1185 rockchip,pins = 1186 <1 RK_PB5 2 &pcfg_pull_none>; 1187 }; 1188 1189 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { 1190 rockchip,pins = 1191 <1 RK_PB6 2 &pcfg_pull_none>; 1192 }; 1193 1194 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { 1195 rockchip,pins = 1196 <1 RK_PB7 2 &pcfg_pull_none>; 1197 }; 1198 1199 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { 1200 rockchip,pins = 1201 <1 RK_PC0 2 &pcfg_pull_none>; 1202 }; 1203 1204 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { 1205 rockchip,pins = 1206 <1 RK_PC1 2 &pcfg_pull_none>; 1207 }; 1208 1209 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { 1210 rockchip,pins = 1211 <1 RK_PC2 2 &pcfg_pull_none>; 1212 }; 1213 1214 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { 1215 rockchip,pins = 1216 <1 RK_PC3 2 &pcfg_pull_none>; 1217 }; 1218 1219 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { 1220 rockchip,pins = 1221 <1 RK_PC4 2 &pcfg_pull_none>; 1222 }; 1223 1224 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { 1225 rockchip,pins = 1226 <1 RK_PC5 2 &pcfg_pull_none>; 1227 }; 1228 }; 1229 1230 pdm_m0 { 1231 pdm_m0_clk: pdm-m0-clk { 1232 rockchip,pins = 1233 <1 RK_PA4 3 &pcfg_pull_none>; 1234 }; 1235 1236 pdm_m0_sdi0: pdm-m0-sdi0 { 1237 rockchip,pins = 1238 <1 RK_PB3 3 &pcfg_pull_none>; 1239 }; 1240 1241 pdm_m0_sdi1: pdm-m0-sdi1 { 1242 rockchip,pins = 1243 <1 RK_PB2 3 &pcfg_pull_none>; 1244 }; 1245 1246 pdm_m0_sdi2: pdm-m0-sdi2 { 1247 rockchip,pins = 1248 <1 RK_PB1 3 &pcfg_pull_none>; 1249 }; 1250 1251 pdm_m0_sdi3: pdm-m0-sdi3 { 1252 rockchip,pins = 1253 <1 RK_PB0 3 &pcfg_pull_none>; 1254 }; 1255 }; 1256 1257 pdm_m1 { 1258 pdm_m1_clk: pdm-m1-clk { 1259 rockchip,pins = 1260 <1 RK_PB6 4 &pcfg_pull_none>; 1261 }; 1262 1263 pdm_m1_sdi0: pdm-m1-sdi0 { 1264 rockchip,pins = 1265 <1 RK_PC5 4 &pcfg_pull_none>; 1266 }; 1267 1268 pdm_m1_sdi1: pdm-m1-sdi1 { 1269 rockchip,pins = 1270 <1 RK_PC4 4 &pcfg_pull_none>; 1271 }; 1272 1273 pdm_m1_sdi2: pdm-m1-sdi2 { 1274 rockchip,pins = 1275 <1 RK_PC3 4 &pcfg_pull_none>; 1276 }; 1277 1278 pdm_m1_sdi3: pdm-m1-sdi3 { 1279 rockchip,pins = 1280 <1 RK_PC2 4 &pcfg_pull_none>; 1281 }; 1282 }; 1283 1284 pdm_m2 { 1285 pdm_m2_clkm: pdm-m2-clkm { 1286 rockchip,pins = 1287 <2 RK_PA4 3 &pcfg_pull_none>; 1288 }; 1289 1290 pdm_m2_clk: pdm-m2-clk { 1291 rockchip,pins = 1292 <2 RK_PA6 2 &pcfg_pull_none>; 1293 }; 1294 1295 pdm_m2_sdi0: pdm-m2-sdi0 { 1296 rockchip,pins = 1297 <2 RK_PB5 2 &pcfg_pull_none>; 1298 }; 1299 1300 pdm_m2_sdi1: pdm-m2-sdi1 { 1301 rockchip,pins = 1302 <2 RK_PB6 2 &pcfg_pull_none>; 1303 }; 1304 1305 pdm_m2_sdi2: pdm-m2-sdi2 { 1306 rockchip,pins = 1307 <2 RK_PB7 2 &pcfg_pull_none>; 1308 }; 1309 1310 pdm_m2_sdi3: pdm-m2-sdi3 { 1311 rockchip,pins = 1312 <2 RK_PC0 2 &pcfg_pull_none>; 1313 }; 1314 }; 1315 1316 pwm0 { 1317 pwm0_pin: pwm0-pin { 1318 rockchip,pins = 1319 <0 RK_PB5 1 &pcfg_pull_none>; 1320 }; 1321 1322 pwm0_pin_pull_down: pwm0-pin-pull-down { 1323 rockchip,pins = 1324 <0 RK_PB5 1 &pcfg_pull_down>; 1325 }; 1326 }; 1327 1328 pwm1 { 1329 pwm1_pin: pwm1-pin { 1330 rockchip,pins = 1331 <0 RK_PB6 1 &pcfg_pull_none>; 1332 }; 1333 1334 pwm1_pin_pull_down: pwm1-pin-pull-down { 1335 rockchip,pins = 1336 <0 RK_PB6 1 &pcfg_pull_down>; 1337 }; 1338 }; 1339 1340 pwm2 { 1341 pwm2_pin: pwm2-pin { 1342 rockchip,pins = 1343 <0 RK_PB7 1 &pcfg_pull_none>; 1344 }; 1345 1346 pwm2_pin_pull_down: pwm2-pin-pull-down { 1347 rockchip,pins = 1348 <0 RK_PB7 1 &pcfg_pull_down>; 1349 }; 1350 }; 1351 1352 pwm3 { 1353 pwm3_pin: pwm3-pin { 1354 rockchip,pins = 1355 <0 RK_PC0 1 &pcfg_pull_none>; 1356 }; 1357 1358 pwm3_pin_pull_down: pwm3-pin-pull-down { 1359 rockchip,pins = 1360 <0 RK_PC0 1 &pcfg_pull_down>; 1361 }; 1362 }; 1363 1364 pwm4 { 1365 pwm4_pin: pwm4-pin { 1366 rockchip,pins = 1367 <0 RK_PA1 2 &pcfg_pull_none>; 1368 }; 1369 1370 pwm4_pin_pull_down: pwm4-pin-pull-down { 1371 rockchip,pins = 1372 <0 RK_PA1 2 &pcfg_pull_down>; 1373 }; 1374 }; 1375 1376 pwm5 { 1377 pwm5_pin: pwm5-pin { 1378 rockchip,pins = 1379 <0 RK_PC1 2 &pcfg_pull_none>; 1380 }; 1381 1382 pwm5_pin_pull_down: pwm5-pin-pull-down { 1383 rockchip,pins = 1384 <0 RK_PC1 2 &pcfg_pull_down>; 1385 }; 1386 }; 1387 1388 pwm6 { 1389 pwm6_pin: pwm6-pin { 1390 rockchip,pins = 1391 <0 RK_PC2 2 &pcfg_pull_none>; 1392 }; 1393 1394 pwm6_pin_pull_down: pwm6-pin-pull-down { 1395 rockchip,pins = 1396 <0 RK_PC2 2 &pcfg_pull_down>; 1397 }; 1398 }; 1399 1400 pwm7 { 1401 pwm7_pin: pwm7-pin { 1402 rockchip,pins = 1403 <2 RK_PB0 2 &pcfg_pull_none>; 1404 }; 1405 1406 pwm7_pin_pull_down: pwm7-pin-pull-down { 1407 rockchip,pins = 1408 <2 RK_PB0 2 &pcfg_pull_down>; 1409 }; 1410 }; 1411 1412 pwm8 { 1413 pwm8_pin: pwm8-pin { 1414 rockchip,pins = 1415 <2 RK_PB2 2 &pcfg_pull_none>; 1416 }; 1417 1418 pwm8_pin_pull_down: pwm8-pin-pull-down { 1419 rockchip,pins = 1420 <2 RK_PB2 2 &pcfg_pull_down>; 1421 }; 1422 }; 1423 1424 pwm9 { 1425 pwm9_pin: pwm9-pin { 1426 rockchip,pins = 1427 <2 RK_PB3 2 &pcfg_pull_none>; 1428 }; 1429 1430 pwm9_pin_pull_down: pwm9-pin-pull-down { 1431 rockchip,pins = 1432 <2 RK_PB3 2 &pcfg_pull_down>; 1433 }; 1434 }; 1435 1436 pwm10 { 1437 pwm10_pin: pwm10-pin { 1438 rockchip,pins = 1439 <2 RK_PB4 2 &pcfg_pull_none>; 1440 }; 1441 1442 pwm10_pin_pull_down: pwm10-pin-pull-down { 1443 rockchip,pins = 1444 <2 RK_PB4 2 &pcfg_pull_down>; 1445 }; 1446 }; 1447 1448 pwm11 { 1449 pwm11_pin: pwm11-pin { 1450 rockchip,pins = 1451 <2 RK_PC0 4 &pcfg_pull_none>; 1452 }; 1453 1454 pwm11_pin_pull_down: pwm11-pin-pull-down { 1455 rockchip,pins = 1456 <2 RK_PC0 4 &pcfg_pull_down>; 1457 }; 1458 }; 1459 1460 rtc { 1461 rtc_32k: rtc-32k { 1462 rockchip,pins = 1463 <0 RK_PC3 1 &pcfg_pull_none>; 1464 }; 1465 }; 1466 1467 sdmmc { 1468 sdmmc_clk: sdmmc-clk { 1469 rockchip,pins = 1470 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 1471 }; 1472 1473 sdmmc_cmd: sdmmc-cmd { 1474 rockchip,pins = 1475 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 1476 }; 1477 1478 sdmmc_det: sdmmc-det { 1479 rockchip,pins = 1480 <0 RK_PA3 1 &pcfg_pull_up_4ma>; 1481 }; 1482 1483 sdmmc_pwren: sdmmc-pwren { 1484 rockchip,pins = 1485 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 1486 }; 1487 1488 sdmmc_bus1: sdmmc-bus1 { 1489 rockchip,pins = 1490 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 1491 }; 1492 1493 sdmmc_bus4: sdmmc-bus4 { 1494 rockchip,pins = 1495 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 1496 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 1497 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 1498 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 1499 }; 1500 }; 1501 1502 sdio { 1503 sdio_clk: sdio-clk { 1504 rockchip,pins = 1505 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 1506 }; 1507 1508 sdio_cmd: sdio-cmd { 1509 rockchip,pins = 1510 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 1511 }; 1512 1513 sdio_pwren: sdio-pwren { 1514 rockchip,pins = 1515 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 1516 }; 1517 1518 sdio_wrpt: sdio-wrpt { 1519 rockchip,pins = 1520 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 1521 }; 1522 1523 sdio_intn: sdio-intn { 1524 rockchip,pins = 1525 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 1526 }; 1527 1528 sdio_bus1: sdio-bus1 { 1529 rockchip,pins = 1530 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 1531 }; 1532 1533 sdio_bus4: sdio-bus4 { 1534 rockchip,pins = 1535 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 1536 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 1537 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 1538 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 1539 }; 1540 }; 1541 1542 spdif_in { 1543 spdif_in: spdif-in { 1544 rockchip,pins = 1545 <0 RK_PC2 1 &pcfg_pull_none>; 1546 }; 1547 }; 1548 1549 spdif_out { 1550 spdif_out: spdif-out { 1551 rockchip,pins = 1552 <0 RK_PC1 1 &pcfg_pull_none>; 1553 }; 1554 }; 1555 1556 spi0 { 1557 spi0_clk: spi0-clk { 1558 rockchip,pins = 1559 <2 RK_PA2 2 &pcfg_pull_up_4ma>; 1560 }; 1561 1562 spi0_csn0: spi0-csn0 { 1563 rockchip,pins = 1564 <2 RK_PA3 2 &pcfg_pull_up_4ma>; 1565 }; 1566 1567 spi0_miso: spi0-miso { 1568 rockchip,pins = 1569 <2 RK_PA0 2 &pcfg_pull_up_4ma>; 1570 }; 1571 1572 spi0_mosi: spi0-mosi { 1573 rockchip,pins = 1574 <2 RK_PA1 2 &pcfg_pull_up_4ma>; 1575 }; 1576 }; 1577 1578 spi1 { 1579 spi1_clk: spi1-clk { 1580 rockchip,pins = 1581 <3 RK_PB3 3 &pcfg_pull_up_4ma>; 1582 }; 1583 1584 spi1_csn0: spi1-csn0 { 1585 rockchip,pins = 1586 <3 RK_PB5 3 &pcfg_pull_up_4ma>; 1587 }; 1588 1589 spi1_miso: spi1-miso { 1590 rockchip,pins = 1591 <3 RK_PB2 3 &pcfg_pull_up_4ma>; 1592 }; 1593 1594 spi1_mosi: spi1-mosi { 1595 rockchip,pins = 1596 <3 RK_PB4 3 &pcfg_pull_up_4ma>; 1597 }; 1598 }; 1599 1600 spi1-m1 { 1601 spi1m1_miso: spi1m1-miso { 1602 rockchip,pins = 1603 <2 RK_PA4 2 &pcfg_pull_up_4ma>; 1604 }; 1605 1606 spi1m1_mosi: spi1m1-mosi { 1607 rockchip,pins = 1608 <2 RK_PA5 2 &pcfg_pull_up_4ma>; 1609 }; 1610 1611 spi1m1_clk: spi1m1-clk { 1612 rockchip,pins = 1613 <2 RK_PA7 2 &pcfg_pull_up_4ma>; 1614 }; 1615 1616 spi1m1_csn0: spi1m1-csn0 { 1617 rockchip,pins = 1618 <2 RK_PB1 2 &pcfg_pull_up_4ma>; 1619 }; 1620 }; 1621 1622 spi2 { 1623 spi2_clk: spi2-clk { 1624 rockchip,pins = 1625 <1 RK_PD0 3 &pcfg_pull_up_4ma>; 1626 }; 1627 1628 spi2_csn0: spi2-csn0 { 1629 rockchip,pins = 1630 <1 RK_PD1 3 &pcfg_pull_up_4ma>; 1631 }; 1632 1633 spi2_miso: spi2-miso { 1634 rockchip,pins = 1635 <1 RK_PC6 3 &pcfg_pull_up_4ma>; 1636 }; 1637 1638 spi2_mosi: spi2-mosi { 1639 rockchip,pins = 1640 <1 RK_PC7 3 &pcfg_pull_up_4ma>; 1641 }; 1642 }; 1643 1644 tsadc { 1645 tsadc_otp_pin: tsadc-otp-pin { 1646 rockchip,pins = 1647 <0 RK_PB2 0 &pcfg_pull_none>; 1648 }; 1649 1650 tsadc_otp_out: tsadc-otp-out { 1651 rockchip,pins = 1652 <0 RK_PB2 1 &pcfg_pull_none>; 1653 }; 1654 }; 1655 1656 uart0 { 1657 uart0_xfer: uart0-xfer { 1658 rockchip,pins = 1659 <2 RK_PA1 1 &pcfg_pull_up>, 1660 <2 RK_PA0 1 &pcfg_pull_up>; 1661 }; 1662 1663 uart0_cts: uart0-cts { 1664 rockchip,pins = 1665 <2 RK_PA2 1 &pcfg_pull_none>; 1666 }; 1667 1668 uart0_rts: uart0-rts { 1669 rockchip,pins = 1670 <2 RK_PA3 1 &pcfg_pull_none>; 1671 }; 1672 1673 uart0_rts_pin: uart0-rts-pin { 1674 rockchip,pins = 1675 <2 RK_PA3 0 &pcfg_pull_none>; 1676 }; 1677 }; 1678 1679 uart1 { 1680 uart1_xfer: uart1-xfer { 1681 rockchip,pins = 1682 <1 RK_PD1 1 &pcfg_pull_up>, 1683 <1 RK_PD0 1 &pcfg_pull_up>; 1684 }; 1685 1686 uart1_cts: uart1-cts { 1687 rockchip,pins = 1688 <1 RK_PC6 1 &pcfg_pull_none>; 1689 }; 1690 1691 uart1_rts: uart1-rts { 1692 rockchip,pins = 1693 <1 RK_PC7 1 &pcfg_pull_none>; 1694 }; 1695 }; 1696 1697 uart2-m0 { 1698 uart2m0_xfer: uart2m0-xfer { 1699 rockchip,pins = 1700 <1 RK_PC7 2 &pcfg_pull_up>, 1701 <1 RK_PC6 2 &pcfg_pull_up>; 1702 }; 1703 }; 1704 1705 uart2-m1 { 1706 uart2m1_xfer: uart2m1-xfer { 1707 rockchip,pins = 1708 <4 RK_PD3 2 &pcfg_pull_up>, 1709 <4 RK_PD2 2 &pcfg_pull_up>; 1710 }; 1711 }; 1712 1713 uart3 { 1714 uart3_xfer: uart3-xfer { 1715 rockchip,pins = 1716 <3 RK_PB5 4 &pcfg_pull_up>, 1717 <3 RK_PB4 4 &pcfg_pull_up>; 1718 }; 1719 }; 1720 1721 uart3-m1 { 1722 uart3m1_xfer: uart3m1-xfer { 1723 rockchip,pins = 1724 <0 RK_PC2 3 &pcfg_pull_up>, 1725 <0 RK_PC1 3 &pcfg_pull_up>; 1726 }; 1727 }; 1728 1729 uart4 { 1730 uart4_xfer: uart4-xfer { 1731 rockchip,pins = 1732 <4 RK_PB1 1 &pcfg_pull_up>, 1733 <4 RK_PB0 1 &pcfg_pull_up>; 1734 }; 1735 1736 uart4_cts: uart4-cts { 1737 rockchip,pins = 1738 <4 RK_PA6 1 &pcfg_pull_none>; 1739 }; 1740 1741 uart4_rts: uart4-rts { 1742 rockchip,pins = 1743 <4 RK_PA7 1 &pcfg_pull_none>; 1744 }; 1745 1746 uart4_rts_pin: uart4-rts-pin { 1747 rockchip,pins = 1748 <4 RK_PA7 0 &pcfg_pull_none>; 1749 }; 1750 }; 1751 }; 1752}; 1753