1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7#include <dt-bindings/clock/rk3308-cru.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3308"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 serial3 = &uart3; 31 serial4 = &uart4; 32 spi0 = &spi0; 33 spi1 = &spi1; 34 spi2 = &spi2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 clocks = <&cru ARMCLK>; 47 #cooling-cells = <2>; 48 dynamic-power-coefficient = <90>; 49 operating-points-v2 = <&cpu0_opp_table>; 50 cpu-idle-states = <&CPU_SLEEP>; 51 next-level-cache = <&l2>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 cpu-idle-states = <&CPU_SLEEP>; 61 next-level-cache = <&l2>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a35"; 67 reg = <0x0 0x2>; 68 enable-method = "psci"; 69 operating-points-v2 = <&cpu0_opp_table>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 next-level-cache = <&l2>; 72 }; 73 74 cpu3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a35"; 77 reg = <0x0 0x3>; 78 enable-method = "psci"; 79 operating-points-v2 = <&cpu0_opp_table>; 80 cpu-idle-states = <&CPU_SLEEP>; 81 next-level-cache = <&l2>; 82 }; 83 84 idle-states { 85 entry-method = "psci"; 86 87 CPU_SLEEP: cpu-sleep { 88 compatible = "arm,idle-state"; 89 local-timer-stop; 90 arm,psci-suspend-param = <0x0010000>; 91 entry-latency-us = <120>; 92 exit-latency-us = <250>; 93 min-residency-us = <900>; 94 }; 95 }; 96 97 l2: l2-cache { 98 compatible = "cache"; 99 }; 100 }; 101 102 cpu0_opp_table: cpu0-opp-table { 103 compatible = "operating-points-v2"; 104 opp-shared; 105 106 opp-408000000 { 107 opp-hz = /bits/ 64 <408000000>; 108 opp-microvolt = <950000 950000 1340000>; 109 clock-latency-ns = <40000>; 110 opp-suspend; 111 }; 112 opp-600000000 { 113 opp-hz = /bits/ 64 <600000000>; 114 opp-microvolt = <950000 950000 1340000>; 115 clock-latency-ns = <40000>; 116 }; 117 opp-816000000 { 118 opp-hz = /bits/ 64 <816000000>; 119 opp-microvolt = <1025000 1025000 1340000>; 120 clock-latency-ns = <40000>; 121 }; 122 opp-1008000000 { 123 opp-hz = /bits/ 64 <1008000000>; 124 opp-microvolt = <1125000 1125000 1340000>; 125 clock-latency-ns = <40000>; 126 }; 127 }; 128 129 arm-pmu { 130 compatible = "arm,cortex-a35-pmu"; 131 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 136 }; 137 138 mac_clkin: external-mac-clock { 139 compatible = "fixed-clock"; 140 clock-frequency = <50000000>; 141 clock-output-names = "mac_clkin"; 142 #clock-cells = <0>; 143 }; 144 145 psci { 146 compatible = "arm,psci-1.0"; 147 method = "smc"; 148 }; 149 150 timer { 151 compatible = "arm,armv8-timer"; 152 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 153 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 154 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 155 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 156 }; 157 158 xin24m: xin24m { 159 compatible = "fixed-clock"; 160 #clock-cells = <0>; 161 clock-frequency = <24000000>; 162 clock-output-names = "xin24m"; 163 }; 164 165 grf: grf@ff000000 { 166 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 167 reg = <0x0 0xff000000 0x0 0x10000>; 168 169 reboot-mode { 170 compatible = "syscon-reboot-mode"; 171 offset = <0x500>; 172 mode-bootloader = <BOOT_BL_DOWNLOAD>; 173 mode-loader = <BOOT_BL_DOWNLOAD>; 174 mode-normal = <BOOT_NORMAL>; 175 mode-recovery = <BOOT_RECOVERY>; 176 mode-fastboot = <BOOT_FASTBOOT>; 177 }; 178 }; 179 180 detect_grf: syscon@ff00b000 { 181 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; 182 reg = <0x0 0xff00b000 0x0 0x1000>; 183 #address-cells = <1>; 184 #size-cells = <1>; 185 }; 186 187 core_grf: syscon@ff00c000 { 188 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; 189 reg = <0x0 0xff00c000 0x0 0x1000>; 190 #address-cells = <1>; 191 #size-cells = <1>; 192 }; 193 194 i2c0: i2c@ff040000 { 195 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 196 reg = <0x0 0xff040000 0x0 0x1000>; 197 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 198 clock-names = "i2c", "pclk"; 199 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&i2c0_xfer>; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 status = "disabled"; 205 }; 206 207 i2c1: i2c@ff050000 { 208 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 209 reg = <0x0 0xff050000 0x0 0x1000>; 210 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 211 clock-names = "i2c", "pclk"; 212 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&i2c1_xfer>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 status = "disabled"; 218 }; 219 220 i2c2: i2c@ff060000 { 221 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 222 reg = <0x0 0xff060000 0x0 0x1000>; 223 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 224 clock-names = "i2c", "pclk"; 225 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&i2c2_xfer>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 status = "disabled"; 231 }; 232 233 i2c3: i2c@ff070000 { 234 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; 235 reg = <0x0 0xff070000 0x0 0x1000>; 236 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 237 clock-names = "i2c", "pclk"; 238 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 239 pinctrl-names = "default"; 240 pinctrl-0 = <&i2c3m0_xfer>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 status = "disabled"; 244 }; 245 246 wdt: watchdog@ff080000 { 247 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; 248 reg = <0x0 0xff080000 0x0 0x100>; 249 clocks = <&cru PCLK_WDT>; 250 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 251 status = "disabled"; 252 }; 253 254 uart0: serial@ff0a0000 { 255 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 256 reg = <0x0 0xff0a0000 0x0 0x100>; 257 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 259 clock-names = "baudclk", "apb_pclk"; 260 reg-shift = <2>; 261 reg-io-width = <4>; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 264 status = "disabled"; 265 }; 266 267 uart1: serial@ff0b0000 { 268 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 269 reg = <0x0 0xff0b0000 0x0 0x100>; 270 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 272 clock-names = "baudclk", "apb_pclk"; 273 reg-shift = <2>; 274 reg-io-width = <4>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 277 status = "disabled"; 278 }; 279 280 uart2: serial@ff0c0000 { 281 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 282 reg = <0x0 0xff0c0000 0x0 0x100>; 283 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 285 clock-names = "baudclk", "apb_pclk"; 286 reg-shift = <2>; 287 reg-io-width = <4>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&uart2m0_xfer>; 290 status = "disabled"; 291 }; 292 293 uart3: serial@ff0d0000 { 294 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 295 reg = <0x0 0xff0d0000 0x0 0x100>; 296 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 298 clock-names = "baudclk", "apb_pclk"; 299 reg-shift = <2>; 300 reg-io-width = <4>; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&uart3_xfer>; 303 status = "disabled"; 304 }; 305 306 uart4: serial@ff0e0000 { 307 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 308 reg = <0x0 0xff0e0000 0x0 0x100>; 309 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 311 clock-names = "baudclk", "apb_pclk"; 312 reg-shift = <2>; 313 reg-io-width = <4>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 316 status = "disabled"; 317 }; 318 319 spi0: spi@ff120000 { 320 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 321 reg = <0x0 0xff120000 0x0 0x1000>; 322 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 326 clock-names = "spiclk", "apb_pclk"; 327 dmas = <&dmac0 0>, <&dmac0 1>; 328 dma-names = "tx", "rx"; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; 331 status = "disabled"; 332 }; 333 334 spi1: spi@ff130000 { 335 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 336 reg = <0x0 0xff130000 0x0 0x1000>; 337 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 341 clock-names = "spiclk", "apb_pclk"; 342 dmas = <&dmac0 2>, <&dmac0 3>; 343 dma-names = "tx", "rx"; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; 346 status = "disabled"; 347 }; 348 349 spi2: spi@ff140000 { 350 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; 351 reg = <0x0 0xff140000 0x0 0x1000>; 352 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 356 clock-names = "spiclk", "apb_pclk"; 357 dmas = <&dmac1 16>, <&dmac1 17>; 358 dma-names = "tx", "rx"; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; 361 status = "disabled"; 362 }; 363 364 pwm8: pwm@ff160000 { 365 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 366 reg = <0x0 0xff160000 0x0 0x10>; 367 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 368 clock-names = "pwm", "pclk"; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pwm8_pin>; 371 #pwm-cells = <3>; 372 status = "disabled"; 373 }; 374 375 pwm9: pwm@ff160010 { 376 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 377 reg = <0x0 0xff160010 0x0 0x10>; 378 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 379 clock-names = "pwm", "pclk"; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&pwm9_pin>; 382 #pwm-cells = <3>; 383 status = "disabled"; 384 }; 385 386 pwm10: pwm@ff160020 { 387 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 388 reg = <0x0 0xff160020 0x0 0x10>; 389 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 390 clock-names = "pwm", "pclk"; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&pwm10_pin>; 393 #pwm-cells = <3>; 394 status = "disabled"; 395 }; 396 397 pwm11: pwm@ff160030 { 398 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 399 reg = <0x0 0xff160030 0x0 0x10>; 400 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 401 clock-names = "pwm", "pclk"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pwm11_pin>; 404 #pwm-cells = <3>; 405 status = "disabled"; 406 }; 407 408 pwm4: pwm@ff170000 { 409 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 410 reg = <0x0 0xff170000 0x0 0x10>; 411 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 412 clock-names = "pwm", "pclk"; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pwm4_pin>; 415 #pwm-cells = <3>; 416 status = "disabled"; 417 }; 418 419 pwm5: pwm@ff170010 { 420 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 421 reg = <0x0 0xff170010 0x0 0x10>; 422 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 423 clock-names = "pwm", "pclk"; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&pwm5_pin>; 426 #pwm-cells = <3>; 427 status = "disabled"; 428 }; 429 430 pwm6: pwm@ff170020 { 431 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 432 reg = <0x0 0xff170020 0x0 0x10>; 433 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 434 clock-names = "pwm", "pclk"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&pwm6_pin>; 437 #pwm-cells = <3>; 438 status = "disabled"; 439 }; 440 441 pwm7: pwm@ff170030 { 442 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 443 reg = <0x0 0xff170030 0x0 0x10>; 444 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 445 clock-names = "pwm", "pclk"; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&pwm7_pin>; 448 #pwm-cells = <3>; 449 status = "disabled"; 450 }; 451 452 pwm0: pwm@ff180000 { 453 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 454 reg = <0x0 0xff180000 0x0 0x10>; 455 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 456 clock-names = "pwm", "pclk"; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&pwm0_pin>; 459 #pwm-cells = <3>; 460 status = "disabled"; 461 }; 462 463 pwm1: pwm@ff180010 { 464 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 465 reg = <0x0 0xff180010 0x0 0x10>; 466 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 467 clock-names = "pwm", "pclk"; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pwm1_pin>; 470 #pwm-cells = <3>; 471 status = "disabled"; 472 }; 473 474 pwm2: pwm@ff180020 { 475 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 476 reg = <0x0 0xff180020 0x0 0x10>; 477 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 478 clock-names = "pwm", "pclk"; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pwm2_pin>; 481 #pwm-cells = <3>; 482 status = "disabled"; 483 }; 484 485 pwm3: pwm@ff180030 { 486 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 487 reg = <0x0 0xff180030 0x0 0x10>; 488 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 489 clock-names = "pwm", "pclk"; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pwm3_pin>; 492 #pwm-cells = <3>; 493 status = "disabled"; 494 }; 495 496 rktimer: rktimer@ff1a0000 { 497 compatible = "rockchip,rk3288-timer"; 498 reg = <0x0 0xff1a0000 0x0 0x20>; 499 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 501 clock-names = "pclk", "timer"; 502 }; 503 504 saradc: saradc@ff1e0000 { 505 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 506 reg = <0x0 0xff1e0000 0x0 0x100>; 507 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 509 clock-names = "saradc", "apb_pclk"; 510 #io-channel-cells = <1>; 511 resets = <&cru SRST_SARADC_P>; 512 reset-names = "saradc-apb"; 513 status = "disabled"; 514 }; 515 516 dmac0: dma-controller@ff2c0000 { 517 compatible = "arm,pl330", "arm,primecell"; 518 reg = <0x0 0xff2c0000 0x0 0x4000>; 519 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 521 arm,pl330-periph-burst; 522 clocks = <&cru ACLK_DMAC0>; 523 clock-names = "apb_pclk"; 524 #dma-cells = <1>; 525 }; 526 527 dmac1: dma-controller@ff2d0000 { 528 compatible = "arm,pl330", "arm,primecell"; 529 reg = <0x0 0xff2d0000 0x0 0x4000>; 530 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 532 arm,pl330-periph-burst; 533 clocks = <&cru ACLK_DMAC1>; 534 clock-names = "apb_pclk"; 535 #dma-cells = <1>; 536 }; 537 538 i2s_2ch_0: i2s@ff350000 { 539 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 540 reg = <0x0 0xff350000 0x0 0x1000>; 541 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; 543 clock-names = "i2s_clk", "i2s_hclk"; 544 dmas = <&dmac1 8>, <&dmac1 9>; 545 dma-names = "tx", "rx"; 546 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; 547 reset-names = "reset-m", "reset-h"; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&i2s_2ch_0_sclk 550 &i2s_2ch_0_lrck 551 &i2s_2ch_0_sdi 552 &i2s_2ch_0_sdo>; 553 status = "disabled"; 554 }; 555 556 i2s_2ch_1: i2s@ff360000 { 557 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 558 reg = <0x0 0xff360000 0x0 0x1000>; 559 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; 561 clock-names = "i2s_clk", "i2s_hclk"; 562 dmas = <&dmac1 11>; 563 dma-names = "rx"; 564 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; 565 reset-names = "reset-m", "reset-h"; 566 status = "disabled"; 567 }; 568 569 spdif_tx: spdif-tx@ff3a0000 { 570 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; 571 reg = <0x0 0xff3a0000 0x0 0x1000>; 572 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; 574 clock-names = "mclk", "hclk"; 575 dmas = <&dmac1 13>; 576 dma-names = "tx"; 577 pinctrl-names = "default"; 578 pinctrl-0 = <&spdif_out>; 579 status = "disabled"; 580 }; 581 582 sdmmc: mmc@ff480000 { 583 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 584 reg = <0x0 0xff480000 0x0 0x4000>; 585 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 586 bus-width = <4>; 587 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 588 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 589 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 590 fifo-depth = <0x100>; 591 max-frequency = <150000000>; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 594 status = "disabled"; 595 }; 596 597 emmc: mmc@ff490000 { 598 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 599 reg = <0x0 0xff490000 0x0 0x4000>; 600 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 601 bus-width = <8>; 602 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 603 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 604 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 605 fifo-depth = <0x100>; 606 max-frequency = <150000000>; 607 status = "disabled"; 608 }; 609 610 sdio: mmc@ff4a0000 { 611 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 612 reg = <0x0 0xff4a0000 0x0 0x4000>; 613 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 614 bus-width = <4>; 615 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 616 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 617 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 618 fifo-depth = <0x100>; 619 max-frequency = <150000000>; 620 pinctrl-names = "default"; 621 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 622 status = "disabled"; 623 }; 624 625 nfc: nand-controller@ff4b0000 { 626 compatible = "rockchip,rk3308-nfc", 627 "rockchip,rv1108-nfc"; 628 reg = <0x0 0xff4b0000 0x0 0x4000>; 629 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 631 clock-names = "ahb", "nfc"; 632 assigned-clocks = <&cru SCLK_NANDC>; 633 assigned-clock-rates = <150000000>; 634 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 635 &flash_rdn &flash_rdy &flash_wrn>; 636 pinctrl-names = "default"; 637 status = "disabled"; 638 }; 639 640 gmac: ethernet@ff4e0000 { 641 compatible = "rockchip,rk3308-gmac"; 642 reg = <0x0 0xff4e0000 0x0 0x10000>; 643 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 644 interrupt-names = "macirq"; 645 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, 646 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, 647 <&cru SCLK_MAC>, <&cru ACLK_MAC>, 648 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; 649 clock-names = "stmmaceth", "mac_clk_rx", 650 "mac_clk_tx", "clk_mac_ref", 651 "clk_mac_refout", "aclk_mac", 652 "pclk_mac", "clk_mac_speed"; 653 phy-mode = "rmii"; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 656 resets = <&cru SRST_MAC_A>; 657 reset-names = "stmmaceth"; 658 rockchip,grf = <&grf>; 659 status = "disabled"; 660 }; 661 662 cru: clock-controller@ff500000 { 663 compatible = "rockchip,rk3308-cru"; 664 reg = <0x0 0xff500000 0x0 0x1000>; 665 #clock-cells = <1>; 666 #reset-cells = <1>; 667 rockchip,grf = <&grf>; 668 669 assigned-clocks = <&cru SCLK_RTC32K>; 670 assigned-clock-rates = <32768>; 671 }; 672 673 gic: interrupt-controller@ff580000 { 674 compatible = "arm,gic-400"; 675 reg = <0x0 0xff581000 0x0 0x1000>, 676 <0x0 0xff582000 0x0 0x2000>, 677 <0x0 0xff584000 0x0 0x2000>, 678 <0x0 0xff586000 0x0 0x2000>; 679 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 680 #interrupt-cells = <3>; 681 interrupt-controller; 682 #address-cells = <0>; 683 }; 684 685 sram: sram@fff80000 { 686 compatible = "mmio-sram"; 687 reg = <0x0 0xfff80000 0x0 0x40000>; 688 ranges = <0 0x0 0xfff80000 0x40000>; 689 #address-cells = <1>; 690 #size-cells = <1>; 691 692 /* reserved for ddr dvfs and system suspend/resume */ 693 ddr-sram@0 { 694 reg = <0x0 0x8000>; 695 }; 696 697 /* reserved for vad audio buffer */ 698 vad_sram: vad-sram@8000 { 699 reg = <0x8000 0x38000>; 700 }; 701 }; 702 703 pinctrl: pinctrl { 704 compatible = "rockchip,rk3308-pinctrl"; 705 rockchip,grf = <&grf>; 706 #address-cells = <2>; 707 #size-cells = <2>; 708 ranges; 709 710 gpio0: gpio0@ff220000 { 711 compatible = "rockchip,gpio-bank"; 712 reg = <0x0 0xff220000 0x0 0x100>; 713 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&cru PCLK_GPIO0>; 715 gpio-controller; 716 #gpio-cells = <2>; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 }; 720 721 gpio1: gpio1@ff230000 { 722 compatible = "rockchip,gpio-bank"; 723 reg = <0x0 0xff230000 0x0 0x100>; 724 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&cru PCLK_GPIO1>; 726 gpio-controller; 727 #gpio-cells = <2>; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 732 gpio2: gpio2@ff240000 { 733 compatible = "rockchip,gpio-bank"; 734 reg = <0x0 0xff240000 0x0 0x100>; 735 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&cru PCLK_GPIO2>; 737 gpio-controller; 738 #gpio-cells = <2>; 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 }; 742 743 gpio3: gpio3@ff250000 { 744 compatible = "rockchip,gpio-bank"; 745 reg = <0x0 0xff250000 0x0 0x100>; 746 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&cru PCLK_GPIO3>; 748 gpio-controller; 749 #gpio-cells = <2>; 750 interrupt-controller; 751 #interrupt-cells = <2>; 752 }; 753 754 gpio4: gpio4@ff260000 { 755 compatible = "rockchip,gpio-bank"; 756 reg = <0x0 0xff260000 0x0 0x100>; 757 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&cru PCLK_GPIO4>; 759 gpio-controller; 760 #gpio-cells = <2>; 761 interrupt-controller; 762 #interrupt-cells = <2>; 763 }; 764 765 pcfg_pull_up: pcfg-pull-up { 766 bias-pull-up; 767 }; 768 769 pcfg_pull_down: pcfg-pull-down { 770 bias-pull-down; 771 }; 772 773 pcfg_pull_none: pcfg-pull-none { 774 bias-disable; 775 }; 776 777 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 778 bias-disable; 779 drive-strength = <2>; 780 }; 781 782 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 783 bias-pull-up; 784 drive-strength = <2>; 785 }; 786 787 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 788 bias-pull-up; 789 drive-strength = <4>; 790 }; 791 792 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 793 bias-disable; 794 drive-strength = <4>; 795 }; 796 797 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 798 bias-pull-down; 799 drive-strength = <4>; 800 }; 801 802 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 803 bias-disable; 804 drive-strength = <8>; 805 }; 806 807 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 808 bias-pull-up; 809 drive-strength = <8>; 810 }; 811 812 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 813 bias-disable; 814 drive-strength = <12>; 815 }; 816 817 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 818 bias-pull-up; 819 drive-strength = <12>; 820 }; 821 822 pcfg_pull_none_smt: pcfg-pull-none-smt { 823 bias-disable; 824 input-schmitt-enable; 825 }; 826 827 pcfg_output_high: pcfg-output-high { 828 output-high; 829 }; 830 831 pcfg_output_low: pcfg-output-low { 832 output-low; 833 }; 834 835 pcfg_input_high: pcfg-input-high { 836 bias-pull-up; 837 input-enable; 838 }; 839 840 pcfg_input: pcfg-input { 841 input-enable; 842 }; 843 844 emmc { 845 emmc_clk: emmc-clk { 846 rockchip,pins = 847 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 848 }; 849 850 emmc_cmd: emmc-cmd { 851 rockchip,pins = 852 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 853 }; 854 855 emmc_pwren: emmc-pwren { 856 rockchip,pins = 857 <3 RK_PB3 2 &pcfg_pull_none>; 858 }; 859 860 emmc_rstn: emmc-rstn { 861 rockchip,pins = 862 <3 RK_PB2 2 &pcfg_pull_none>; 863 }; 864 865 emmc_bus1: emmc-bus1 { 866 rockchip,pins = 867 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 868 }; 869 870 emmc_bus4: emmc-bus4 { 871 rockchip,pins = 872 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 873 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 874 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 875 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 876 }; 877 878 emmc_bus8: emmc-bus8 { 879 rockchip,pins = 880 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 881 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 882 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 883 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 884 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 885 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 886 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 887 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 888 }; 889 }; 890 891 flash { 892 flash_csn0: flash-csn0 { 893 rockchip,pins = 894 <3 RK_PB5 1 &pcfg_pull_none>; 895 }; 896 897 flash_rdy: flash-rdy { 898 rockchip,pins = 899 <3 RK_PB4 1 &pcfg_pull_none>; 900 }; 901 902 flash_ale: flash-ale { 903 rockchip,pins = 904 <3 RK_PB3 1 &pcfg_pull_none>; 905 }; 906 907 flash_cle: flash-cle { 908 rockchip,pins = 909 <3 RK_PB1 1 &pcfg_pull_none>; 910 }; 911 912 flash_wrn: flash-wrn { 913 rockchip,pins = 914 <3 RK_PB0 1 &pcfg_pull_none>; 915 }; 916 917 flash_rdn: flash-rdn { 918 rockchip,pins = 919 <3 RK_PB2 1 &pcfg_pull_none>; 920 }; 921 922 flash_bus8: flash-bus8 { 923 rockchip,pins = 924 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 925 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 926 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 927 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 928 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 929 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 930 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 931 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 932 }; 933 }; 934 935 gmac { 936 rmii_pins: rmii-pins { 937 rockchip,pins = 938 /* mac_txen */ 939 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 940 /* mac_txd1 */ 941 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 942 /* mac_txd0 */ 943 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 944 /* mac_rxd0 */ 945 <1 RK_PC4 3 &pcfg_pull_none>, 946 /* mac_rxd1 */ 947 <1 RK_PC5 3 &pcfg_pull_none>, 948 /* mac_rxer */ 949 <1 RK_PB7 3 &pcfg_pull_none>, 950 /* mac_rxdv */ 951 <1 RK_PC0 3 &pcfg_pull_none>, 952 /* mac_mdio */ 953 <1 RK_PB6 3 &pcfg_pull_none>, 954 /* mac_mdc */ 955 <1 RK_PB5 3 &pcfg_pull_none>; 956 }; 957 958 mac_refclk_12ma: mac-refclk-12ma { 959 rockchip,pins = 960 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 961 }; 962 963 mac_refclk: mac-refclk { 964 rockchip,pins = 965 <1 RK_PB4 3 &pcfg_pull_none>; 966 }; 967 }; 968 969 gmac-m1 { 970 rmiim1_pins: rmiim1-pins { 971 rockchip,pins = 972 /* mac_txen */ 973 <4 RK_PB7 2 &pcfg_pull_none_12ma>, 974 /* mac_txd1 */ 975 <4 RK_PA5 2 &pcfg_pull_none_12ma>, 976 /* mac_txd0 */ 977 <4 RK_PA4 2 &pcfg_pull_none_12ma>, 978 /* mac_rxd0 */ 979 <4 RK_PA2 2 &pcfg_pull_none>, 980 /* mac_rxd1 */ 981 <4 RK_PA3 2 &pcfg_pull_none>, 982 /* mac_rxer */ 983 <4 RK_PA0 2 &pcfg_pull_none>, 984 /* mac_rxdv */ 985 <4 RK_PA1 2 &pcfg_pull_none>, 986 /* mac_mdio */ 987 <4 RK_PB6 2 &pcfg_pull_none>, 988 /* mac_mdc */ 989 <4 RK_PB5 2 &pcfg_pull_none>; 990 }; 991 992 macm1_refclk_12ma: macm1-refclk-12ma { 993 rockchip,pins = 994 <4 RK_PB4 2 &pcfg_pull_none_12ma>; 995 }; 996 997 macm1_refclk: macm1-refclk { 998 rockchip,pins = 999 <4 RK_PB4 2 &pcfg_pull_none>; 1000 }; 1001 }; 1002 1003 i2c0 { 1004 i2c0_xfer: i2c0-xfer { 1005 rockchip,pins = 1006 <1 RK_PD0 2 &pcfg_pull_none_smt>, 1007 <1 RK_PD1 2 &pcfg_pull_none_smt>; 1008 }; 1009 }; 1010 1011 i2c1 { 1012 i2c1_xfer: i2c1-xfer { 1013 rockchip,pins = 1014 <0 RK_PB3 1 &pcfg_pull_none_smt>, 1015 <0 RK_PB4 1 &pcfg_pull_none_smt>; 1016 }; 1017 }; 1018 1019 i2c2 { 1020 i2c2_xfer: i2c2-xfer { 1021 rockchip,pins = 1022 <2 RK_PA2 3 &pcfg_pull_none_smt>, 1023 <2 RK_PA3 3 &pcfg_pull_none_smt>; 1024 }; 1025 }; 1026 1027 i2c3-m0 { 1028 i2c3m0_xfer: i2c3m0-xfer { 1029 rockchip,pins = 1030 <0 RK_PB7 2 &pcfg_pull_none_smt>, 1031 <0 RK_PC0 2 &pcfg_pull_none_smt>; 1032 }; 1033 }; 1034 1035 i2c3-m1 { 1036 i2c3m1_xfer: i2c3m1-xfer { 1037 rockchip,pins = 1038 <3 RK_PB4 2 &pcfg_pull_none_smt>, 1039 <3 RK_PB5 2 &pcfg_pull_none_smt>; 1040 }; 1041 }; 1042 1043 i2c3-m2 { 1044 i2c3m2_xfer: i2c3m2-xfer { 1045 rockchip,pins = 1046 <2 RK_PA1 3 &pcfg_pull_none_smt>, 1047 <2 RK_PA0 3 &pcfg_pull_none_smt>; 1048 }; 1049 }; 1050 1051 i2s_2ch_0 { 1052 i2s_2ch_0_mclk: i2s-2ch-0-mclk { 1053 rockchip,pins = 1054 <4 RK_PB4 1 &pcfg_pull_none>; 1055 }; 1056 1057 i2s_2ch_0_sclk: i2s-2ch-0-sclk { 1058 rockchip,pins = 1059 <4 RK_PB5 1 &pcfg_pull_none>; 1060 }; 1061 1062 i2s_2ch_0_lrck: i2s-2ch-0-lrck { 1063 rockchip,pins = 1064 <4 RK_PB6 1 &pcfg_pull_none>; 1065 }; 1066 1067 i2s_2ch_0_sdo: i2s-2ch-0-sdo { 1068 rockchip,pins = 1069 <4 RK_PB7 1 &pcfg_pull_none>; 1070 }; 1071 1072 i2s_2ch_0_sdi: i2s-2ch-0-sdi { 1073 rockchip,pins = 1074 <4 RK_PC0 1 &pcfg_pull_none>; 1075 }; 1076 }; 1077 1078 i2s_8ch_0 { 1079 i2s_8ch_0_mclk: i2s-8ch-0-mclk { 1080 rockchip,pins = 1081 <2 RK_PA4 1 &pcfg_pull_none>; 1082 }; 1083 1084 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { 1085 rockchip,pins = 1086 <2 RK_PA5 1 &pcfg_pull_none>; 1087 }; 1088 1089 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { 1090 rockchip,pins = 1091 <2 RK_PA6 1 &pcfg_pull_none>; 1092 }; 1093 1094 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { 1095 rockchip,pins = 1096 <2 RK_PA7 1 &pcfg_pull_none>; 1097 }; 1098 1099 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { 1100 rockchip,pins = 1101 <2 RK_PB0 1 &pcfg_pull_none>; 1102 }; 1103 1104 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { 1105 rockchip,pins = 1106 <2 RK_PB1 1 &pcfg_pull_none>; 1107 }; 1108 1109 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { 1110 rockchip,pins = 1111 <2 RK_PB2 1 &pcfg_pull_none>; 1112 }; 1113 1114 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { 1115 rockchip,pins = 1116 <2 RK_PB3 1 &pcfg_pull_none>; 1117 }; 1118 1119 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { 1120 rockchip,pins = 1121 <2 RK_PB4 1 &pcfg_pull_none>; 1122 }; 1123 1124 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { 1125 rockchip,pins = 1126 <2 RK_PB5 1 &pcfg_pull_none>; 1127 }; 1128 1129 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { 1130 rockchip,pins = 1131 <2 RK_PB6 1 &pcfg_pull_none>; 1132 }; 1133 1134 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { 1135 rockchip,pins = 1136 <2 RK_PB7 1 &pcfg_pull_none>; 1137 }; 1138 1139 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { 1140 rockchip,pins = 1141 <2 RK_PC0 1 &pcfg_pull_none>; 1142 }; 1143 }; 1144 1145 i2s_8ch_1_m0 { 1146 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { 1147 rockchip,pins = 1148 <1 RK_PA2 2 &pcfg_pull_none>; 1149 }; 1150 1151 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { 1152 rockchip,pins = 1153 <1 RK_PA3 2 &pcfg_pull_none>; 1154 }; 1155 1156 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { 1157 rockchip,pins = 1158 <1 RK_PA4 2 &pcfg_pull_none>; 1159 }; 1160 1161 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { 1162 rockchip,pins = 1163 <1 RK_PA5 2 &pcfg_pull_none>; 1164 }; 1165 1166 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { 1167 rockchip,pins = 1168 <1 RK_PA6 2 &pcfg_pull_none>; 1169 }; 1170 1171 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { 1172 rockchip,pins = 1173 <1 RK_PA7 2 &pcfg_pull_none>; 1174 }; 1175 1176 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { 1177 rockchip,pins = 1178 <1 RK_PB0 2 &pcfg_pull_none>; 1179 }; 1180 1181 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { 1182 rockchip,pins = 1183 <1 RK_PB1 2 &pcfg_pull_none>; 1184 }; 1185 1186 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { 1187 rockchip,pins = 1188 <1 RK_PB2 2 &pcfg_pull_none>; 1189 }; 1190 1191 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { 1192 rockchip,pins = 1193 <1 RK_PB3 2 &pcfg_pull_none>; 1194 }; 1195 }; 1196 1197 i2s_8ch_1_m1 { 1198 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { 1199 rockchip,pins = 1200 <1 RK_PB4 2 &pcfg_pull_none>; 1201 }; 1202 1203 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { 1204 rockchip,pins = 1205 <1 RK_PB5 2 &pcfg_pull_none>; 1206 }; 1207 1208 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { 1209 rockchip,pins = 1210 <1 RK_PB6 2 &pcfg_pull_none>; 1211 }; 1212 1213 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { 1214 rockchip,pins = 1215 <1 RK_PB7 2 &pcfg_pull_none>; 1216 }; 1217 1218 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { 1219 rockchip,pins = 1220 <1 RK_PC0 2 &pcfg_pull_none>; 1221 }; 1222 1223 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { 1224 rockchip,pins = 1225 <1 RK_PC1 2 &pcfg_pull_none>; 1226 }; 1227 1228 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { 1229 rockchip,pins = 1230 <1 RK_PC2 2 &pcfg_pull_none>; 1231 }; 1232 1233 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { 1234 rockchip,pins = 1235 <1 RK_PC3 2 &pcfg_pull_none>; 1236 }; 1237 1238 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { 1239 rockchip,pins = 1240 <1 RK_PC4 2 &pcfg_pull_none>; 1241 }; 1242 1243 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { 1244 rockchip,pins = 1245 <1 RK_PC5 2 &pcfg_pull_none>; 1246 }; 1247 }; 1248 1249 pdm_m0 { 1250 pdm_m0_clk: pdm-m0-clk { 1251 rockchip,pins = 1252 <1 RK_PA4 3 &pcfg_pull_none>; 1253 }; 1254 1255 pdm_m0_sdi0: pdm-m0-sdi0 { 1256 rockchip,pins = 1257 <1 RK_PB3 3 &pcfg_pull_none>; 1258 }; 1259 1260 pdm_m0_sdi1: pdm-m0-sdi1 { 1261 rockchip,pins = 1262 <1 RK_PB2 3 &pcfg_pull_none>; 1263 }; 1264 1265 pdm_m0_sdi2: pdm-m0-sdi2 { 1266 rockchip,pins = 1267 <1 RK_PB1 3 &pcfg_pull_none>; 1268 }; 1269 1270 pdm_m0_sdi3: pdm-m0-sdi3 { 1271 rockchip,pins = 1272 <1 RK_PB0 3 &pcfg_pull_none>; 1273 }; 1274 }; 1275 1276 pdm_m1 { 1277 pdm_m1_clk: pdm-m1-clk { 1278 rockchip,pins = 1279 <1 RK_PB6 4 &pcfg_pull_none>; 1280 }; 1281 1282 pdm_m1_sdi0: pdm-m1-sdi0 { 1283 rockchip,pins = 1284 <1 RK_PC5 4 &pcfg_pull_none>; 1285 }; 1286 1287 pdm_m1_sdi1: pdm-m1-sdi1 { 1288 rockchip,pins = 1289 <1 RK_PC4 4 &pcfg_pull_none>; 1290 }; 1291 1292 pdm_m1_sdi2: pdm-m1-sdi2 { 1293 rockchip,pins = 1294 <1 RK_PC3 4 &pcfg_pull_none>; 1295 }; 1296 1297 pdm_m1_sdi3: pdm-m1-sdi3 { 1298 rockchip,pins = 1299 <1 RK_PC2 4 &pcfg_pull_none>; 1300 }; 1301 }; 1302 1303 pdm_m2 { 1304 pdm_m2_clkm: pdm-m2-clkm { 1305 rockchip,pins = 1306 <2 RK_PA4 3 &pcfg_pull_none>; 1307 }; 1308 1309 pdm_m2_clk: pdm-m2-clk { 1310 rockchip,pins = 1311 <2 RK_PA6 2 &pcfg_pull_none>; 1312 }; 1313 1314 pdm_m2_sdi0: pdm-m2-sdi0 { 1315 rockchip,pins = 1316 <2 RK_PB5 2 &pcfg_pull_none>; 1317 }; 1318 1319 pdm_m2_sdi1: pdm-m2-sdi1 { 1320 rockchip,pins = 1321 <2 RK_PB6 2 &pcfg_pull_none>; 1322 }; 1323 1324 pdm_m2_sdi2: pdm-m2-sdi2 { 1325 rockchip,pins = 1326 <2 RK_PB7 2 &pcfg_pull_none>; 1327 }; 1328 1329 pdm_m2_sdi3: pdm-m2-sdi3 { 1330 rockchip,pins = 1331 <2 RK_PC0 2 &pcfg_pull_none>; 1332 }; 1333 }; 1334 1335 pwm0 { 1336 pwm0_pin: pwm0-pin { 1337 rockchip,pins = 1338 <0 RK_PB5 1 &pcfg_pull_none>; 1339 }; 1340 1341 pwm0_pin_pull_down: pwm0-pin-pull-down { 1342 rockchip,pins = 1343 <0 RK_PB5 1 &pcfg_pull_down>; 1344 }; 1345 }; 1346 1347 pwm1 { 1348 pwm1_pin: pwm1-pin { 1349 rockchip,pins = 1350 <0 RK_PB6 1 &pcfg_pull_none>; 1351 }; 1352 1353 pwm1_pin_pull_down: pwm1-pin-pull-down { 1354 rockchip,pins = 1355 <0 RK_PB6 1 &pcfg_pull_down>; 1356 }; 1357 }; 1358 1359 pwm2 { 1360 pwm2_pin: pwm2-pin { 1361 rockchip,pins = 1362 <0 RK_PB7 1 &pcfg_pull_none>; 1363 }; 1364 1365 pwm2_pin_pull_down: pwm2-pin-pull-down { 1366 rockchip,pins = 1367 <0 RK_PB7 1 &pcfg_pull_down>; 1368 }; 1369 }; 1370 1371 pwm3 { 1372 pwm3_pin: pwm3-pin { 1373 rockchip,pins = 1374 <0 RK_PC0 1 &pcfg_pull_none>; 1375 }; 1376 1377 pwm3_pin_pull_down: pwm3-pin-pull-down { 1378 rockchip,pins = 1379 <0 RK_PC0 1 &pcfg_pull_down>; 1380 }; 1381 }; 1382 1383 pwm4 { 1384 pwm4_pin: pwm4-pin { 1385 rockchip,pins = 1386 <0 RK_PA1 2 &pcfg_pull_none>; 1387 }; 1388 1389 pwm4_pin_pull_down: pwm4-pin-pull-down { 1390 rockchip,pins = 1391 <0 RK_PA1 2 &pcfg_pull_down>; 1392 }; 1393 }; 1394 1395 pwm5 { 1396 pwm5_pin: pwm5-pin { 1397 rockchip,pins = 1398 <0 RK_PC1 2 &pcfg_pull_none>; 1399 }; 1400 1401 pwm5_pin_pull_down: pwm5-pin-pull-down { 1402 rockchip,pins = 1403 <0 RK_PC1 2 &pcfg_pull_down>; 1404 }; 1405 }; 1406 1407 pwm6 { 1408 pwm6_pin: pwm6-pin { 1409 rockchip,pins = 1410 <0 RK_PC2 2 &pcfg_pull_none>; 1411 }; 1412 1413 pwm6_pin_pull_down: pwm6-pin-pull-down { 1414 rockchip,pins = 1415 <0 RK_PC2 2 &pcfg_pull_down>; 1416 }; 1417 }; 1418 1419 pwm7 { 1420 pwm7_pin: pwm7-pin { 1421 rockchip,pins = 1422 <2 RK_PB0 2 &pcfg_pull_none>; 1423 }; 1424 1425 pwm7_pin_pull_down: pwm7-pin-pull-down { 1426 rockchip,pins = 1427 <2 RK_PB0 2 &pcfg_pull_down>; 1428 }; 1429 }; 1430 1431 pwm8 { 1432 pwm8_pin: pwm8-pin { 1433 rockchip,pins = 1434 <2 RK_PB2 2 &pcfg_pull_none>; 1435 }; 1436 1437 pwm8_pin_pull_down: pwm8-pin-pull-down { 1438 rockchip,pins = 1439 <2 RK_PB2 2 &pcfg_pull_down>; 1440 }; 1441 }; 1442 1443 pwm9 { 1444 pwm9_pin: pwm9-pin { 1445 rockchip,pins = 1446 <2 RK_PB3 2 &pcfg_pull_none>; 1447 }; 1448 1449 pwm9_pin_pull_down: pwm9-pin-pull-down { 1450 rockchip,pins = 1451 <2 RK_PB3 2 &pcfg_pull_down>; 1452 }; 1453 }; 1454 1455 pwm10 { 1456 pwm10_pin: pwm10-pin { 1457 rockchip,pins = 1458 <2 RK_PB4 2 &pcfg_pull_none>; 1459 }; 1460 1461 pwm10_pin_pull_down: pwm10-pin-pull-down { 1462 rockchip,pins = 1463 <2 RK_PB4 2 &pcfg_pull_down>; 1464 }; 1465 }; 1466 1467 pwm11 { 1468 pwm11_pin: pwm11-pin { 1469 rockchip,pins = 1470 <2 RK_PC0 4 &pcfg_pull_none>; 1471 }; 1472 1473 pwm11_pin_pull_down: pwm11-pin-pull-down { 1474 rockchip,pins = 1475 <2 RK_PC0 4 &pcfg_pull_down>; 1476 }; 1477 }; 1478 1479 rtc { 1480 rtc_32k: rtc-32k { 1481 rockchip,pins = 1482 <0 RK_PC3 1 &pcfg_pull_none>; 1483 }; 1484 }; 1485 1486 sdmmc { 1487 sdmmc_clk: sdmmc-clk { 1488 rockchip,pins = 1489 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 1490 }; 1491 1492 sdmmc_cmd: sdmmc-cmd { 1493 rockchip,pins = 1494 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 1495 }; 1496 1497 sdmmc_det: sdmmc-det { 1498 rockchip,pins = 1499 <0 RK_PA3 1 &pcfg_pull_up_4ma>; 1500 }; 1501 1502 sdmmc_pwren: sdmmc-pwren { 1503 rockchip,pins = 1504 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 1505 }; 1506 1507 sdmmc_bus1: sdmmc-bus1 { 1508 rockchip,pins = 1509 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 1510 }; 1511 1512 sdmmc_bus4: sdmmc-bus4 { 1513 rockchip,pins = 1514 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 1515 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 1516 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 1517 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 1518 }; 1519 }; 1520 1521 sdio { 1522 sdio_clk: sdio-clk { 1523 rockchip,pins = 1524 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 1525 }; 1526 1527 sdio_cmd: sdio-cmd { 1528 rockchip,pins = 1529 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 1530 }; 1531 1532 sdio_pwren: sdio-pwren { 1533 rockchip,pins = 1534 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 1535 }; 1536 1537 sdio_wrpt: sdio-wrpt { 1538 rockchip,pins = 1539 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 1540 }; 1541 1542 sdio_intn: sdio-intn { 1543 rockchip,pins = 1544 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 1545 }; 1546 1547 sdio_bus1: sdio-bus1 { 1548 rockchip,pins = 1549 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 1550 }; 1551 1552 sdio_bus4: sdio-bus4 { 1553 rockchip,pins = 1554 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 1555 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 1556 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 1557 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 1558 }; 1559 }; 1560 1561 spdif_in { 1562 spdif_in: spdif-in { 1563 rockchip,pins = 1564 <0 RK_PC2 1 &pcfg_pull_none>; 1565 }; 1566 }; 1567 1568 spdif_out { 1569 spdif_out: spdif-out { 1570 rockchip,pins = 1571 <0 RK_PC1 1 &pcfg_pull_none>; 1572 }; 1573 }; 1574 1575 spi0 { 1576 spi0_clk: spi0-clk { 1577 rockchip,pins = 1578 <2 RK_PA2 2 &pcfg_pull_up_4ma>; 1579 }; 1580 1581 spi0_csn0: spi0-csn0 { 1582 rockchip,pins = 1583 <2 RK_PA3 2 &pcfg_pull_up_4ma>; 1584 }; 1585 1586 spi0_miso: spi0-miso { 1587 rockchip,pins = 1588 <2 RK_PA0 2 &pcfg_pull_up_4ma>; 1589 }; 1590 1591 spi0_mosi: spi0-mosi { 1592 rockchip,pins = 1593 <2 RK_PA1 2 &pcfg_pull_up_4ma>; 1594 }; 1595 }; 1596 1597 spi1 { 1598 spi1_clk: spi1-clk { 1599 rockchip,pins = 1600 <3 RK_PB3 3 &pcfg_pull_up_4ma>; 1601 }; 1602 1603 spi1_csn0: spi1-csn0 { 1604 rockchip,pins = 1605 <3 RK_PB5 3 &pcfg_pull_up_4ma>; 1606 }; 1607 1608 spi1_miso: spi1-miso { 1609 rockchip,pins = 1610 <3 RK_PB2 3 &pcfg_pull_up_4ma>; 1611 }; 1612 1613 spi1_mosi: spi1-mosi { 1614 rockchip,pins = 1615 <3 RK_PB4 3 &pcfg_pull_up_4ma>; 1616 }; 1617 }; 1618 1619 spi1-m1 { 1620 spi1m1_miso: spi1m1-miso { 1621 rockchip,pins = 1622 <2 RK_PA4 2 &pcfg_pull_up_4ma>; 1623 }; 1624 1625 spi1m1_mosi: spi1m1-mosi { 1626 rockchip,pins = 1627 <2 RK_PA5 2 &pcfg_pull_up_4ma>; 1628 }; 1629 1630 spi1m1_clk: spi1m1-clk { 1631 rockchip,pins = 1632 <2 RK_PA7 2 &pcfg_pull_up_4ma>; 1633 }; 1634 1635 spi1m1_csn0: spi1m1-csn0 { 1636 rockchip,pins = 1637 <2 RK_PB1 2 &pcfg_pull_up_4ma>; 1638 }; 1639 }; 1640 1641 spi2 { 1642 spi2_clk: spi2-clk { 1643 rockchip,pins = 1644 <1 RK_PD0 3 &pcfg_pull_up_4ma>; 1645 }; 1646 1647 spi2_csn0: spi2-csn0 { 1648 rockchip,pins = 1649 <1 RK_PD1 3 &pcfg_pull_up_4ma>; 1650 }; 1651 1652 spi2_miso: spi2-miso { 1653 rockchip,pins = 1654 <1 RK_PC6 3 &pcfg_pull_up_4ma>; 1655 }; 1656 1657 spi2_mosi: spi2-mosi { 1658 rockchip,pins = 1659 <1 RK_PC7 3 &pcfg_pull_up_4ma>; 1660 }; 1661 }; 1662 1663 tsadc { 1664 tsadc_otp_pin: tsadc-otp-pin { 1665 rockchip,pins = 1666 <0 RK_PB2 0 &pcfg_pull_none>; 1667 }; 1668 1669 tsadc_otp_out: tsadc-otp-out { 1670 rockchip,pins = 1671 <0 RK_PB2 1 &pcfg_pull_none>; 1672 }; 1673 }; 1674 1675 uart0 { 1676 uart0_xfer: uart0-xfer { 1677 rockchip,pins = 1678 <2 RK_PA1 1 &pcfg_pull_up>, 1679 <2 RK_PA0 1 &pcfg_pull_up>; 1680 }; 1681 1682 uart0_cts: uart0-cts { 1683 rockchip,pins = 1684 <2 RK_PA2 1 &pcfg_pull_none>; 1685 }; 1686 1687 uart0_rts: uart0-rts { 1688 rockchip,pins = 1689 <2 RK_PA3 1 &pcfg_pull_none>; 1690 }; 1691 1692 uart0_rts_pin: uart0-rts-pin { 1693 rockchip,pins = 1694 <2 RK_PA3 0 &pcfg_pull_none>; 1695 }; 1696 }; 1697 1698 uart1 { 1699 uart1_xfer: uart1-xfer { 1700 rockchip,pins = 1701 <1 RK_PD1 1 &pcfg_pull_up>, 1702 <1 RK_PD0 1 &pcfg_pull_up>; 1703 }; 1704 1705 uart1_cts: uart1-cts { 1706 rockchip,pins = 1707 <1 RK_PC6 1 &pcfg_pull_none>; 1708 }; 1709 1710 uart1_rts: uart1-rts { 1711 rockchip,pins = 1712 <1 RK_PC7 1 &pcfg_pull_none>; 1713 }; 1714 }; 1715 1716 uart2-m0 { 1717 uart2m0_xfer: uart2m0-xfer { 1718 rockchip,pins = 1719 <1 RK_PC7 2 &pcfg_pull_up>, 1720 <1 RK_PC6 2 &pcfg_pull_up>; 1721 }; 1722 }; 1723 1724 uart2-m1 { 1725 uart2m1_xfer: uart2m1-xfer { 1726 rockchip,pins = 1727 <4 RK_PD3 2 &pcfg_pull_up>, 1728 <4 RK_PD2 2 &pcfg_pull_up>; 1729 }; 1730 }; 1731 1732 uart3 { 1733 uart3_xfer: uart3-xfer { 1734 rockchip,pins = 1735 <3 RK_PB5 4 &pcfg_pull_up>, 1736 <3 RK_PB4 4 &pcfg_pull_up>; 1737 }; 1738 }; 1739 1740 uart3-m1 { 1741 uart3m1_xfer: uart3m1-xfer { 1742 rockchip,pins = 1743 <0 RK_PC2 3 &pcfg_pull_up>, 1744 <0 RK_PC1 3 &pcfg_pull_up>; 1745 }; 1746 }; 1747 1748 uart4 { 1749 uart4_xfer: uart4-xfer { 1750 rockchip,pins = 1751 <4 RK_PB1 1 &pcfg_pull_up>, 1752 <4 RK_PB0 1 &pcfg_pull_up>; 1753 }; 1754 1755 uart4_cts: uart4-cts { 1756 rockchip,pins = 1757 <4 RK_PA6 1 &pcfg_pull_none>; 1758 }; 1759 1760 uart4_rts: uart4-rts { 1761 rockchip,pins = 1762 <4 RK_PA7 1 &pcfg_pull_none>; 1763 }; 1764 1765 uart4_rts_pin: uart4-rts-pin { 1766 rockchip,pins = 1767 <4 RK_PA7 0 &pcfg_pull_none>; 1768 }; 1769 }; 1770 }; 1771}; 1772