1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 serial3 = &uart3; 32 serial4 = &uart4; 33 serial5 = &uart5; 34 spi0 = &spi0; 35 spi1 = &spi1; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a35"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 clocks = <&cru ARMCLK>; 48 #cooling-cells = <2>; 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 50 dynamic-power-coefficient = <90>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 #cooling-cells = <2>; 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 62 dynamic-power-coefficient = <90>; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 clocks = <&cru ARMCLK>; 72 #cooling-cells = <2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 74 dynamic-power-coefficient = <90>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 }; 77 78 cpu3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a35"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 #cooling-cells = <2>; 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 86 dynamic-power-coefficient = <90>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 102 CLUSTER_SLEEP: cluster-sleep { 103 compatible = "arm,idle-state"; 104 local-timer-stop; 105 arm,psci-suspend-param = <0x1010000>; 106 entry-latency-us = <400>; 107 exit-latency-us = <500>; 108 min-residency-us = <2000>; 109 }; 110 }; 111 }; 112 113 cpu0_opp_table: cpu0-opp-table { 114 compatible = "operating-points-v2"; 115 opp-shared; 116 117 opp-600000000 { 118 opp-hz = /bits/ 64 <600000000>; 119 opp-microvolt = <950000 950000 1350000>; 120 clock-latency-ns = <40000>; 121 opp-suspend; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1050000 1050000 1350000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1175000 1175000 1350000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1300000 1300000 1350000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1350000 1350000 1350000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a35-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vopb_out>, <&vopl_out>; 157 status = "disabled"; 158 }; 159 160 gmac_clkin: external-gmac-clock { 161 compatible = "fixed-clock"; 162 clock-frequency = <50000000>; 163 clock-output-names = "gmac_clkin"; 164 #clock-cells = <0>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 178 }; 179 180 thermal_zones: thermal-zones { 181 soc_thermal: soc-thermal { 182 polling-delay-passive = <20>; 183 polling-delay = <1000>; 184 sustainable-power = <750>; 185 thermal-sensors = <&tsadc 0>; 186 187 trips { 188 threshold: trip-point-0 { 189 temperature = <70000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 target: trip-point-1 { 195 temperature = <85000>; 196 hysteresis = <2000>; 197 type = "passive"; 198 }; 199 200 soc_crit: soc-crit { 201 temperature = <115000>; 202 hysteresis = <2000>; 203 type = "critical"; 204 }; 205 }; 206 207 cooling-maps { 208 map0 { 209 trip = <&target>; 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211 contribution = <4096>; 212 }; 213 214 map1 { 215 trip = <&target>; 216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 217 contribution = <4096>; 218 }; 219 }; 220 }; 221 222 gpu_thermal: gpu-thermal { 223 polling-delay-passive = <100>; /* milliseconds */ 224 polling-delay = <1000>; /* milliseconds */ 225 thermal-sensors = <&tsadc 1>; 226 }; 227 }; 228 229 xin24m: xin24m { 230 compatible = "fixed-clock"; 231 #clock-cells = <0>; 232 clock-frequency = <24000000>; 233 clock-output-names = "xin24m"; 234 }; 235 236 pmu: power-management@ff000000 { 237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 238 reg = <0x0 0xff000000 0x0 0x1000>; 239 240 power: power-controller { 241 compatible = "rockchip,px30-power-controller"; 242 #power-domain-cells = <1>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 /* These power domains are grouped by VD_LOGIC */ 247 pd_usb@PX30_PD_USB { 248 reg = <PX30_PD_USB>; 249 clocks = <&cru HCLK_HOST>, 250 <&cru HCLK_OTG>, 251 <&cru SCLK_OTG_ADP>; 252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 253 }; 254 pd_sdcard@PX30_PD_SDCARD { 255 reg = <PX30_PD_SDCARD>; 256 clocks = <&cru HCLK_SDMMC>, 257 <&cru SCLK_SDMMC>; 258 pm_qos = <&qos_sdmmc>; 259 }; 260 pd_gmac@PX30_PD_GMAC { 261 reg = <PX30_PD_GMAC>; 262 clocks = <&cru ACLK_GMAC>, 263 <&cru PCLK_GMAC>, 264 <&cru SCLK_MAC_REF>, 265 <&cru SCLK_GMAC_RX_TX>; 266 pm_qos = <&qos_gmac>; 267 }; 268 pd_mmc_nand@PX30_PD_MMC_NAND { 269 reg = <PX30_PD_MMC_NAND>; 270 clocks = <&cru HCLK_NANDC>, 271 <&cru HCLK_EMMC>, 272 <&cru HCLK_SDIO>, 273 <&cru HCLK_SFC>, 274 <&cru SCLK_EMMC>, 275 <&cru SCLK_NANDC>, 276 <&cru SCLK_SDIO>, 277 <&cru SCLK_SFC>; 278 pm_qos = <&qos_emmc>, <&qos_nand>, 279 <&qos_sdio>, <&qos_sfc>; 280 }; 281 pd_vpu@PX30_PD_VPU { 282 reg = <PX30_PD_VPU>; 283 clocks = <&cru ACLK_VPU>, 284 <&cru HCLK_VPU>, 285 <&cru SCLK_CORE_VPU>; 286 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 287 }; 288 pd_vo@PX30_PD_VO { 289 reg = <PX30_PD_VO>; 290 clocks = <&cru ACLK_RGA>, 291 <&cru ACLK_VOPB>, 292 <&cru ACLK_VOPL>, 293 <&cru DCLK_VOPB>, 294 <&cru DCLK_VOPL>, 295 <&cru HCLK_RGA>, 296 <&cru HCLK_VOPB>, 297 <&cru HCLK_VOPL>, 298 <&cru PCLK_MIPI_DSI>, 299 <&cru SCLK_RGA_CORE>, 300 <&cru SCLK_VOPB_PWM>; 301 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 302 <&qos_vop_m0>, <&qos_vop_m1>; 303 }; 304 pd_vi@PX30_PD_VI { 305 reg = <PX30_PD_VI>; 306 clocks = <&cru ACLK_CIF>, 307 <&cru ACLK_ISP>, 308 <&cru HCLK_CIF>, 309 <&cru HCLK_ISP>, 310 <&cru SCLK_ISP>; 311 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 312 <&qos_isp_wr>, <&qos_isp_m1>, 313 <&qos_vip>; 314 }; 315 pd_gpu@PX30_PD_GPU { 316 reg = <PX30_PD_GPU>; 317 clocks = <&cru SCLK_GPU>; 318 pm_qos = <&qos_gpu>; 319 }; 320 }; 321 }; 322 323 pmugrf: syscon@ff010000 { 324 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 325 reg = <0x0 0xff010000 0x0 0x1000>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 329 pmu_io_domains: io-domains { 330 compatible = "rockchip,px30-pmu-io-voltage-domain"; 331 status = "disabled"; 332 }; 333 334 reboot-mode { 335 compatible = "syscon-reboot-mode"; 336 offset = <0x200>; 337 mode-bootloader = <BOOT_BL_DOWNLOAD>; 338 mode-fastboot = <BOOT_FASTBOOT>; 339 mode-loader = <BOOT_BL_DOWNLOAD>; 340 mode-normal = <BOOT_NORMAL>; 341 mode-recovery = <BOOT_RECOVERY>; 342 }; 343 }; 344 345 uart0: serial@ff030000 { 346 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 347 reg = <0x0 0xff030000 0x0 0x100>; 348 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 350 clock-names = "baudclk", "apb_pclk"; 351 dmas = <&dmac 0>, <&dmac 1>; 352 dma-names = "tx", "rx"; 353 reg-shift = <2>; 354 reg-io-width = <4>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 357 status = "disabled"; 358 }; 359 360 i2s1_2ch: i2s@ff070000 { 361 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 362 reg = <0x0 0xff070000 0x0 0x1000>; 363 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 365 clock-names = "i2s_clk", "i2s_hclk"; 366 dmas = <&dmac 18>, <&dmac 19>; 367 dma-names = "tx", "rx"; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 370 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 371 #sound-dai-cells = <0>; 372 status = "disabled"; 373 }; 374 375 i2s2_2ch: i2s@ff080000 { 376 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 377 reg = <0x0 0xff080000 0x0 0x1000>; 378 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 380 clock-names = "i2s_clk", "i2s_hclk"; 381 dmas = <&dmac 20>, <&dmac 21>; 382 dma-names = "tx", "rx"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 385 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 386 #sound-dai-cells = <0>; 387 status = "disabled"; 388 }; 389 390 gic: interrupt-controller@ff131000 { 391 compatible = "arm,gic-400"; 392 #interrupt-cells = <3>; 393 #address-cells = <0>; 394 interrupt-controller; 395 reg = <0x0 0xff131000 0 0x1000>, 396 <0x0 0xff132000 0 0x2000>, 397 <0x0 0xff134000 0 0x2000>, 398 <0x0 0xff136000 0 0x2000>; 399 interrupts = <GIC_PPI 9 400 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 401 }; 402 403 grf: syscon@ff140000 { 404 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 405 reg = <0x0 0xff140000 0x0 0x1000>; 406 #address-cells = <1>; 407 #size-cells = <1>; 408 409 io_domains: io-domains { 410 compatible = "rockchip,px30-io-voltage-domain"; 411 status = "disabled"; 412 }; 413 414 lvds: lvds { 415 compatible = "rockchip,px30-lvds"; 416 phys = <&dsi_dphy>; 417 phy-names = "dphy"; 418 rockchip,grf = <&grf>; 419 rockchip,output = "lvds"; 420 status = "disabled"; 421 422 ports { 423 #address-cells = <1>; 424 #size-cells = <0>; 425 426 port@0 { 427 reg = <0>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 431 lvds_vopb_in: endpoint@0 { 432 reg = <0>; 433 remote-endpoint = <&vopb_out_lvds>; 434 }; 435 436 lvds_vopl_in: endpoint@1 { 437 reg = <1>; 438 remote-endpoint = <&vopl_out_lvds>; 439 }; 440 }; 441 }; 442 }; 443 }; 444 445 uart1: serial@ff158000 { 446 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 447 reg = <0x0 0xff158000 0x0 0x100>; 448 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 450 clock-names = "baudclk", "apb_pclk"; 451 dmas = <&dmac 2>, <&dmac 3>; 452 dma-names = "tx", "rx"; 453 reg-shift = <2>; 454 reg-io-width = <4>; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 457 status = "disabled"; 458 }; 459 460 uart2: serial@ff160000 { 461 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 462 reg = <0x0 0xff160000 0x0 0x100>; 463 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 465 clock-names = "baudclk", "apb_pclk"; 466 dmas = <&dmac 4>, <&dmac 5>; 467 dma-names = "tx", "rx"; 468 reg-shift = <2>; 469 reg-io-width = <4>; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&uart2m0_xfer>; 472 status = "disabled"; 473 }; 474 475 uart3: serial@ff168000 { 476 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 477 reg = <0x0 0xff168000 0x0 0x100>; 478 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 480 clock-names = "baudclk", "apb_pclk"; 481 dmas = <&dmac 6>, <&dmac 7>; 482 dma-names = "tx", "rx"; 483 reg-shift = <2>; 484 reg-io-width = <4>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 487 status = "disabled"; 488 }; 489 490 uart4: serial@ff170000 { 491 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 492 reg = <0x0 0xff170000 0x0 0x100>; 493 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 495 clock-names = "baudclk", "apb_pclk"; 496 dmas = <&dmac 8>, <&dmac 9>; 497 dma-names = "tx", "rx"; 498 reg-shift = <2>; 499 reg-io-width = <4>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 502 status = "disabled"; 503 }; 504 505 uart5: serial@ff178000 { 506 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 507 reg = <0x0 0xff178000 0x0 0x100>; 508 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 510 clock-names = "baudclk", "apb_pclk"; 511 dmas = <&dmac 10>, <&dmac 11>; 512 dma-names = "tx", "rx"; 513 reg-shift = <2>; 514 reg-io-width = <4>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 517 status = "disabled"; 518 }; 519 520 i2c0: i2c@ff180000 { 521 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 522 reg = <0x0 0xff180000 0x0 0x1000>; 523 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 524 clock-names = "i2c", "pclk"; 525 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&i2c0_xfer>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 status = "disabled"; 531 }; 532 533 i2c1: i2c@ff190000 { 534 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 535 reg = <0x0 0xff190000 0x0 0x1000>; 536 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 537 clock-names = "i2c", "pclk"; 538 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&i2c1_xfer>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 546 i2c2: i2c@ff1a0000 { 547 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 548 reg = <0x0 0xff1a0000 0x0 0x1000>; 549 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 550 clock-names = "i2c", "pclk"; 551 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&i2c2_xfer>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "disabled"; 557 }; 558 559 i2c3: i2c@ff1b0000 { 560 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 561 reg = <0x0 0xff1b0000 0x0 0x1000>; 562 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 563 clock-names = "i2c", "pclk"; 564 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&i2c3_xfer>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 spi0: spi@ff1d0000 { 573 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 574 reg = <0x0 0xff1d0000 0x0 0x1000>; 575 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 577 clock-names = "spiclk", "apb_pclk"; 578 dmas = <&dmac 12>, <&dmac 13>; 579 dma-names = "tx", "rx"; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 status = "disabled"; 585 }; 586 587 spi1: spi@ff1d8000 { 588 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 589 reg = <0x0 0xff1d8000 0x0 0x1000>; 590 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 592 clock-names = "spiclk", "apb_pclk"; 593 dmas = <&dmac 14>, <&dmac 15>; 594 dma-names = "tx", "rx"; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 }; 601 602 wdt: watchdog@ff1e0000 { 603 compatible = "snps,dw-wdt"; 604 reg = <0x0 0xff1e0000 0x0 0x100>; 605 clocks = <&cru PCLK_WDT_NS>; 606 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 607 status = "disabled"; 608 }; 609 610 pwm0: pwm@ff200000 { 611 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 612 reg = <0x0 0xff200000 0x0 0x10>; 613 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 614 clock-names = "pwm", "pclk"; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&pwm0_pin>; 617 #pwm-cells = <3>; 618 status = "disabled"; 619 }; 620 621 pwm1: pwm@ff200010 { 622 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 623 reg = <0x0 0xff200010 0x0 0x10>; 624 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 625 clock-names = "pwm", "pclk"; 626 pinctrl-names = "default"; 627 pinctrl-0 = <&pwm1_pin>; 628 #pwm-cells = <3>; 629 status = "disabled"; 630 }; 631 632 pwm2: pwm@ff200020 { 633 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 634 reg = <0x0 0xff200020 0x0 0x10>; 635 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 636 clock-names = "pwm", "pclk"; 637 pinctrl-names = "default"; 638 pinctrl-0 = <&pwm2_pin>; 639 #pwm-cells = <3>; 640 status = "disabled"; 641 }; 642 643 pwm3: pwm@ff200030 { 644 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 645 reg = <0x0 0xff200030 0x0 0x10>; 646 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 647 clock-names = "pwm", "pclk"; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&pwm3_pin>; 650 #pwm-cells = <3>; 651 status = "disabled"; 652 }; 653 654 pwm4: pwm@ff208000 { 655 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 656 reg = <0x0 0xff208000 0x0 0x10>; 657 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 658 clock-names = "pwm", "pclk"; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&pwm4_pin>; 661 #pwm-cells = <3>; 662 status = "disabled"; 663 }; 664 665 pwm5: pwm@ff208010 { 666 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 667 reg = <0x0 0xff208010 0x0 0x10>; 668 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 669 clock-names = "pwm", "pclk"; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&pwm5_pin>; 672 #pwm-cells = <3>; 673 status = "disabled"; 674 }; 675 676 pwm6: pwm@ff208020 { 677 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 678 reg = <0x0 0xff208020 0x0 0x10>; 679 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 680 clock-names = "pwm", "pclk"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&pwm6_pin>; 683 #pwm-cells = <3>; 684 status = "disabled"; 685 }; 686 687 pwm7: pwm@ff208030 { 688 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 689 reg = <0x0 0xff208030 0x0 0x10>; 690 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 691 clock-names = "pwm", "pclk"; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&pwm7_pin>; 694 #pwm-cells = <3>; 695 status = "disabled"; 696 }; 697 698 rktimer: timer@ff210000 { 699 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 700 reg = <0x0 0xff210000 0x0 0x1000>; 701 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 703 clock-names = "pclk", "timer"; 704 }; 705 706 amba: bus { 707 compatible = "simple-bus"; 708 #address-cells = <2>; 709 #size-cells = <2>; 710 ranges; 711 712 dmac: dmac@ff240000 { 713 compatible = "arm,pl330", "arm,primecell"; 714 reg = <0x0 0xff240000 0x0 0x4000>; 715 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 717 arm,pl330-periph-burst; 718 clocks = <&cru ACLK_DMAC>; 719 clock-names = "apb_pclk"; 720 #dma-cells = <1>; 721 }; 722 }; 723 724 tsadc: tsadc@ff280000 { 725 compatible = "rockchip,px30-tsadc"; 726 reg = <0x0 0xff280000 0x0 0x100>; 727 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 728 assigned-clocks = <&cru SCLK_TSADC>; 729 assigned-clock-rates = <50000>; 730 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 731 clock-names = "tsadc", "apb_pclk"; 732 resets = <&cru SRST_TSADC>; 733 reset-names = "tsadc-apb"; 734 rockchip,grf = <&grf>; 735 rockchip,hw-tshut-temp = <120000>; 736 pinctrl-names = "init", "default", "sleep"; 737 pinctrl-0 = <&tsadc_otp_pin>; 738 pinctrl-1 = <&tsadc_otp_out>; 739 pinctrl-2 = <&tsadc_otp_pin>; 740 #thermal-sensor-cells = <1>; 741 status = "disabled"; 742 }; 743 744 saradc: saradc@ff288000 { 745 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 746 reg = <0x0 0xff288000 0x0 0x100>; 747 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 748 #io-channel-cells = <1>; 749 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 750 clock-names = "saradc", "apb_pclk"; 751 resets = <&cru SRST_SARADC_P>; 752 reset-names = "saradc-apb"; 753 status = "disabled"; 754 }; 755 756 otp: nvmem@ff290000 { 757 compatible = "rockchip,px30-otp"; 758 reg = <0x0 0xff290000 0x0 0x4000>; 759 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 760 <&cru PCLK_OTP_PHY>; 761 clock-names = "otp", "apb_pclk", "phy"; 762 resets = <&cru SRST_OTP_PHY>; 763 reset-names = "phy"; 764 #address-cells = <1>; 765 #size-cells = <1>; 766 767 /* Data cells */ 768 cpu_id: id@7 { 769 reg = <0x07 0x10>; 770 }; 771 cpu_leakage: cpu-leakage@17 { 772 reg = <0x17 0x1>; 773 }; 774 performance: performance@1e { 775 reg = <0x1e 0x1>; 776 bits = <4 3>; 777 }; 778 }; 779 780 cru: clock-controller@ff2b0000 { 781 compatible = "rockchip,px30-cru"; 782 reg = <0x0 0xff2b0000 0x0 0x1000>; 783 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 784 clock-names = "xin24m", "gpll"; 785 rockchip,grf = <&grf>; 786 #clock-cells = <1>; 787 #reset-cells = <1>; 788 789 assigned-clocks = <&cru PLL_NPLL>, 790 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 791 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 792 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 793 794 assigned-clock-rates = <1188000000>, 795 <200000000>, <200000000>, 796 <150000000>, <150000000>, 797 <100000000>, <200000000>; 798 }; 799 800 pmucru: clock-controller@ff2bc000 { 801 compatible = "rockchip,px30-pmucru"; 802 reg = <0x0 0xff2bc000 0x0 0x1000>; 803 clocks = <&xin24m>; 804 clock-names = "xin24m"; 805 rockchip,grf = <&grf>; 806 #clock-cells = <1>; 807 #reset-cells = <1>; 808 809 assigned-clocks = 810 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 811 <&pmucru SCLK_WIFI_PMU>; 812 assigned-clock-rates = 813 <1200000000>, <100000000>, 814 <26000000>; 815 }; 816 817 usb2phy_grf: syscon@ff2c0000 { 818 compatible = "rockchip,px30-usb2phy-grf", "syscon", 819 "simple-mfd"; 820 reg = <0x0 0xff2c0000 0x0 0x10000>; 821 #address-cells = <1>; 822 #size-cells = <1>; 823 824 u2phy: usb2-phy@100 { 825 compatible = "rockchip,px30-usb2phy"; 826 reg = <0x100 0x20>; 827 clocks = <&pmucru SCLK_USBPHY_REF>; 828 clock-names = "phyclk"; 829 #clock-cells = <0>; 830 assigned-clocks = <&cru USB480M>; 831 assigned-clock-parents = <&u2phy>; 832 clock-output-names = "usb480m_phy"; 833 status = "disabled"; 834 835 u2phy_host: host-port { 836 #phy-cells = <0>; 837 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 838 interrupt-names = "linestate"; 839 status = "disabled"; 840 }; 841 842 u2phy_otg: otg-port { 843 #phy-cells = <0>; 844 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 847 interrupt-names = "otg-bvalid", "otg-id", 848 "linestate"; 849 status = "disabled"; 850 }; 851 }; 852 }; 853 854 dsi_dphy: phy@ff2e0000 { 855 compatible = "rockchip,px30-dsi-dphy"; 856 reg = <0x0 0xff2e0000 0x0 0x10000>; 857 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 858 clock-names = "ref", "pclk"; 859 resets = <&cru SRST_MIPIDSIPHY_P>; 860 reset-names = "apb"; 861 #phy-cells = <0>; 862 power-domains = <&power PX30_PD_VO>; 863 status = "disabled"; 864 }; 865 866 usb20_otg: usb@ff300000 { 867 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 868 "snps,dwc2"; 869 reg = <0x0 0xff300000 0x0 0x40000>; 870 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&cru HCLK_OTG>; 872 clock-names = "otg"; 873 dr_mode = "otg"; 874 g-np-tx-fifo-size = <16>; 875 g-rx-fifo-size = <280>; 876 g-tx-fifo-size = <256 128 128 64 32 16>; 877 phys = <&u2phy_otg>; 878 phy-names = "usb2-phy"; 879 power-domains = <&power PX30_PD_USB>; 880 status = "disabled"; 881 }; 882 883 usb_host0_ehci: usb@ff340000 { 884 compatible = "generic-ehci"; 885 reg = <0x0 0xff340000 0x0 0x10000>; 886 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&cru HCLK_HOST>; 888 phys = <&u2phy_host>; 889 phy-names = "usb"; 890 power-domains = <&power PX30_PD_USB>; 891 status = "disabled"; 892 }; 893 894 usb_host0_ohci: usb@ff350000 { 895 compatible = "generic-ohci"; 896 reg = <0x0 0xff350000 0x0 0x10000>; 897 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&cru HCLK_HOST>; 899 phys = <&u2phy_host>; 900 phy-names = "usb"; 901 power-domains = <&power PX30_PD_USB>; 902 status = "disabled"; 903 }; 904 905 gmac: ethernet@ff360000 { 906 compatible = "rockchip,px30-gmac"; 907 reg = <0x0 0xff360000 0x0 0x10000>; 908 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 909 interrupt-names = "macirq"; 910 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 911 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 912 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 913 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 914 clock-names = "stmmaceth", "mac_clk_rx", 915 "mac_clk_tx", "clk_mac_ref", 916 "clk_mac_refout", "aclk_mac", 917 "pclk_mac", "clk_mac_speed"; 918 rockchip,grf = <&grf>; 919 phy-mode = "rmii"; 920 pinctrl-names = "default"; 921 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 922 power-domains = <&power PX30_PD_GMAC>; 923 resets = <&cru SRST_GMAC_A>; 924 reset-names = "stmmaceth"; 925 status = "disabled"; 926 }; 927 928 sdmmc: mmc@ff370000 { 929 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 930 reg = <0x0 0xff370000 0x0 0x4000>; 931 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 933 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 934 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 935 bus-width = <4>; 936 fifo-depth = <0x100>; 937 max-frequency = <150000000>; 938 pinctrl-names = "default"; 939 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 940 power-domains = <&power PX30_PD_SDCARD>; 941 status = "disabled"; 942 }; 943 944 sdio: mmc@ff380000 { 945 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 946 reg = <0x0 0xff380000 0x0 0x4000>; 947 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 949 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 950 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 951 bus-width = <4>; 952 fifo-depth = <0x100>; 953 max-frequency = <150000000>; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 956 power-domains = <&power PX30_PD_MMC_NAND>; 957 status = "disabled"; 958 }; 959 960 emmc: mmc@ff390000 { 961 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 962 reg = <0x0 0xff390000 0x0 0x4000>; 963 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 965 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 966 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 967 bus-width = <8>; 968 fifo-depth = <0x100>; 969 max-frequency = <150000000>; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 972 power-domains = <&power PX30_PD_MMC_NAND>; 973 status = "disabled"; 974 }; 975 976 gpu: gpu@ff400000 { 977 compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 978 reg = <0x0 0xff400000 0x0 0x4000>; 979 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 982 interrupt-names = "job", "mmu", "gpu"; 983 clocks = <&cru SCLK_GPU>; 984 #cooling-cells = <2>; 985 power-domains = <&power PX30_PD_GPU>; 986 status = "disabled"; 987 }; 988 989 dsi: dsi@ff450000 { 990 compatible = "rockchip,px30-mipi-dsi"; 991 reg = <0x0 0xff450000 0x0 0x10000>; 992 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&cru PCLK_MIPI_DSI>; 994 clock-names = "pclk"; 995 phys = <&dsi_dphy>; 996 phy-names = "dphy"; 997 power-domains = <&power PX30_PD_VO>; 998 resets = <&cru SRST_MIPIDSI_HOST_P>; 999 reset-names = "apb"; 1000 rockchip,grf = <&grf>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 status = "disabled"; 1004 1005 ports { 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 1009 port@0 { 1010 reg = <0>; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 1014 dsi_in_vopb: endpoint@0 { 1015 reg = <0>; 1016 remote-endpoint = <&vopb_out_dsi>; 1017 }; 1018 1019 dsi_in_vopl: endpoint@1 { 1020 reg = <1>; 1021 remote-endpoint = <&vopl_out_dsi>; 1022 }; 1023 }; 1024 }; 1025 }; 1026 1027 vopb: vop@ff460000 { 1028 compatible = "rockchip,px30-vop-big"; 1029 reg = <0x0 0xff460000 0x0 0xefc>; 1030 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1032 <&cru HCLK_VOPB>; 1033 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1034 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1035 reset-names = "axi", "ahb", "dclk"; 1036 iommus = <&vopb_mmu>; 1037 power-domains = <&power PX30_PD_VO>; 1038 status = "disabled"; 1039 1040 vopb_out: port { 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 1044 vopb_out_dsi: endpoint@0 { 1045 reg = <0>; 1046 remote-endpoint = <&dsi_in_vopb>; 1047 }; 1048 1049 vopb_out_lvds: endpoint@1 { 1050 reg = <1>; 1051 remote-endpoint = <&lvds_vopb_in>; 1052 }; 1053 }; 1054 }; 1055 1056 vopb_mmu: iommu@ff460f00 { 1057 compatible = "rockchip,iommu"; 1058 reg = <0x0 0xff460f00 0x0 0x100>; 1059 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1060 interrupt-names = "vopb_mmu"; 1061 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1062 clock-names = "aclk", "iface"; 1063 power-domains = <&power PX30_PD_VO>; 1064 #iommu-cells = <0>; 1065 status = "disabled"; 1066 }; 1067 1068 vopl: vop@ff470000 { 1069 compatible = "rockchip,px30-vop-lit"; 1070 reg = <0x0 0xff470000 0x0 0xefc>; 1071 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1073 <&cru HCLK_VOPL>; 1074 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1075 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1076 reset-names = "axi", "ahb", "dclk"; 1077 iommus = <&vopl_mmu>; 1078 power-domains = <&power PX30_PD_VO>; 1079 status = "disabled"; 1080 1081 vopl_out: port { 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 1085 vopl_out_dsi: endpoint@0 { 1086 reg = <0>; 1087 remote-endpoint = <&dsi_in_vopl>; 1088 }; 1089 1090 vopl_out_lvds: endpoint@1 { 1091 reg = <1>; 1092 remote-endpoint = <&lvds_vopl_in>; 1093 }; 1094 }; 1095 }; 1096 1097 vopl_mmu: iommu@ff470f00 { 1098 compatible = "rockchip,iommu"; 1099 reg = <0x0 0xff470f00 0x0 0x100>; 1100 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1101 interrupt-names = "vopl_mmu"; 1102 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1103 clock-names = "aclk", "iface"; 1104 power-domains = <&power PX30_PD_VO>; 1105 #iommu-cells = <0>; 1106 status = "disabled"; 1107 }; 1108 1109 qos_gmac: qos@ff518000 { 1110 compatible = "syscon"; 1111 reg = <0x0 0xff518000 0x0 0x20>; 1112 }; 1113 1114 qos_gpu: qos@ff520000 { 1115 compatible = "syscon"; 1116 reg = <0x0 0xff520000 0x0 0x20>; 1117 }; 1118 1119 qos_sdmmc: qos@ff52c000 { 1120 compatible = "syscon"; 1121 reg = <0x0 0xff52c000 0x0 0x20>; 1122 }; 1123 1124 qos_emmc: qos@ff538000 { 1125 compatible = "syscon"; 1126 reg = <0x0 0xff538000 0x0 0x20>; 1127 }; 1128 1129 qos_nand: qos@ff538080 { 1130 compatible = "syscon"; 1131 reg = <0x0 0xff538080 0x0 0x20>; 1132 }; 1133 1134 qos_sdio: qos@ff538100 { 1135 compatible = "syscon"; 1136 reg = <0x0 0xff538100 0x0 0x20>; 1137 }; 1138 1139 qos_sfc: qos@ff538180 { 1140 compatible = "syscon"; 1141 reg = <0x0 0xff538180 0x0 0x20>; 1142 }; 1143 1144 qos_usb_host: qos@ff540000 { 1145 compatible = "syscon"; 1146 reg = <0x0 0xff540000 0x0 0x20>; 1147 }; 1148 1149 qos_usb_otg: qos@ff540080 { 1150 compatible = "syscon"; 1151 reg = <0x0 0xff540080 0x0 0x20>; 1152 }; 1153 1154 qos_isp_128: qos@ff548000 { 1155 compatible = "syscon"; 1156 reg = <0x0 0xff548000 0x0 0x20>; 1157 }; 1158 1159 qos_isp_rd: qos@ff548080 { 1160 compatible = "syscon"; 1161 reg = <0x0 0xff548080 0x0 0x20>; 1162 }; 1163 1164 qos_isp_wr: qos@ff548100 { 1165 compatible = "syscon"; 1166 reg = <0x0 0xff548100 0x0 0x20>; 1167 }; 1168 1169 qos_isp_m1: qos@ff548180 { 1170 compatible = "syscon"; 1171 reg = <0x0 0xff548180 0x0 0x20>; 1172 }; 1173 1174 qos_vip: qos@ff548200 { 1175 compatible = "syscon"; 1176 reg = <0x0 0xff548200 0x0 0x20>; 1177 }; 1178 1179 qos_rga_rd: qos@ff550000 { 1180 compatible = "syscon"; 1181 reg = <0x0 0xff550000 0x0 0x20>; 1182 }; 1183 1184 qos_rga_wr: qos@ff550080 { 1185 compatible = "syscon"; 1186 reg = <0x0 0xff550080 0x0 0x20>; 1187 }; 1188 1189 qos_vop_m0: qos@ff550100 { 1190 compatible = "syscon"; 1191 reg = <0x0 0xff550100 0x0 0x20>; 1192 }; 1193 1194 qos_vop_m1: qos@ff550180 { 1195 compatible = "syscon"; 1196 reg = <0x0 0xff550180 0x0 0x20>; 1197 }; 1198 1199 qos_vpu: qos@ff558000 { 1200 compatible = "syscon"; 1201 reg = <0x0 0xff558000 0x0 0x20>; 1202 }; 1203 1204 qos_vpu_r128: qos@ff558080 { 1205 compatible = "syscon"; 1206 reg = <0x0 0xff558080 0x0 0x20>; 1207 }; 1208 1209 pinctrl: pinctrl { 1210 compatible = "rockchip,px30-pinctrl"; 1211 rockchip,grf = <&grf>; 1212 rockchip,pmu = <&pmugrf>; 1213 #address-cells = <2>; 1214 #size-cells = <2>; 1215 ranges; 1216 1217 gpio0: gpio0@ff040000 { 1218 compatible = "rockchip,gpio-bank"; 1219 reg = <0x0 0xff040000 0x0 0x100>; 1220 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1221 clocks = <&pmucru PCLK_GPIO0_PMU>; 1222 gpio-controller; 1223 #gpio-cells = <2>; 1224 1225 interrupt-controller; 1226 #interrupt-cells = <2>; 1227 }; 1228 1229 gpio1: gpio1@ff250000 { 1230 compatible = "rockchip,gpio-bank"; 1231 reg = <0x0 0xff250000 0x0 0x100>; 1232 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1233 clocks = <&cru PCLK_GPIO1>; 1234 gpio-controller; 1235 #gpio-cells = <2>; 1236 1237 interrupt-controller; 1238 #interrupt-cells = <2>; 1239 }; 1240 1241 gpio2: gpio2@ff260000 { 1242 compatible = "rockchip,gpio-bank"; 1243 reg = <0x0 0xff260000 0x0 0x100>; 1244 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&cru PCLK_GPIO2>; 1246 gpio-controller; 1247 #gpio-cells = <2>; 1248 1249 interrupt-controller; 1250 #interrupt-cells = <2>; 1251 }; 1252 1253 gpio3: gpio3@ff270000 { 1254 compatible = "rockchip,gpio-bank"; 1255 reg = <0x0 0xff270000 0x0 0x100>; 1256 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&cru PCLK_GPIO3>; 1258 gpio-controller; 1259 #gpio-cells = <2>; 1260 1261 interrupt-controller; 1262 #interrupt-cells = <2>; 1263 }; 1264 1265 pcfg_pull_up: pcfg-pull-up { 1266 bias-pull-up; 1267 }; 1268 1269 pcfg_pull_down: pcfg-pull-down { 1270 bias-pull-down; 1271 }; 1272 1273 pcfg_pull_none: pcfg-pull-none { 1274 bias-disable; 1275 }; 1276 1277 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1278 bias-disable; 1279 drive-strength = <2>; 1280 }; 1281 1282 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1283 bias-pull-up; 1284 drive-strength = <2>; 1285 }; 1286 1287 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1288 bias-pull-up; 1289 drive-strength = <4>; 1290 }; 1291 1292 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1293 bias-disable; 1294 drive-strength = <4>; 1295 }; 1296 1297 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1298 bias-pull-down; 1299 drive-strength = <4>; 1300 }; 1301 1302 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1303 bias-disable; 1304 drive-strength = <8>; 1305 }; 1306 1307 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1308 bias-pull-up; 1309 drive-strength = <8>; 1310 }; 1311 1312 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1313 bias-disable; 1314 drive-strength = <12>; 1315 }; 1316 1317 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1318 bias-pull-up; 1319 drive-strength = <12>; 1320 }; 1321 1322 pcfg_pull_none_smt: pcfg-pull-none-smt { 1323 bias-disable; 1324 input-schmitt-enable; 1325 }; 1326 1327 pcfg_output_high: pcfg-output-high { 1328 output-high; 1329 }; 1330 1331 pcfg_output_low: pcfg-output-low { 1332 output-low; 1333 }; 1334 1335 pcfg_input_high: pcfg-input-high { 1336 bias-pull-up; 1337 input-enable; 1338 }; 1339 1340 pcfg_input: pcfg-input { 1341 input-enable; 1342 }; 1343 1344 i2c0 { 1345 i2c0_xfer: i2c0-xfer { 1346 rockchip,pins = 1347 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1348 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1349 }; 1350 }; 1351 1352 i2c1 { 1353 i2c1_xfer: i2c1-xfer { 1354 rockchip,pins = 1355 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1356 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1357 }; 1358 }; 1359 1360 i2c2 { 1361 i2c2_xfer: i2c2-xfer { 1362 rockchip,pins = 1363 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1364 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1365 }; 1366 }; 1367 1368 i2c3 { 1369 i2c3_xfer: i2c3-xfer { 1370 rockchip,pins = 1371 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1372 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1373 }; 1374 }; 1375 1376 tsadc { 1377 tsadc_otp_pin: tsadc-otp-pin { 1378 rockchip,pins = 1379 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1380 }; 1381 1382 tsadc_otp_out: tsadc-otp-out { 1383 rockchip,pins = 1384 <0 RK_PA6 1 &pcfg_pull_none>; 1385 }; 1386 }; 1387 1388 uart0 { 1389 uart0_xfer: uart0-xfer { 1390 rockchip,pins = 1391 <0 RK_PB2 1 &pcfg_pull_up>, 1392 <0 RK_PB3 1 &pcfg_pull_up>; 1393 }; 1394 1395 uart0_cts: uart0-cts { 1396 rockchip,pins = 1397 <0 RK_PB4 1 &pcfg_pull_none>; 1398 }; 1399 1400 uart0_rts: uart0-rts { 1401 rockchip,pins = 1402 <0 RK_PB5 1 &pcfg_pull_none>; 1403 }; 1404 }; 1405 1406 uart1 { 1407 uart1_xfer: uart1-xfer { 1408 rockchip,pins = 1409 <1 RK_PC1 1 &pcfg_pull_up>, 1410 <1 RK_PC0 1 &pcfg_pull_up>; 1411 }; 1412 1413 uart1_cts: uart1-cts { 1414 rockchip,pins = 1415 <1 RK_PC2 1 &pcfg_pull_none>; 1416 }; 1417 1418 uart1_rts: uart1-rts { 1419 rockchip,pins = 1420 <1 RK_PC3 1 &pcfg_pull_none>; 1421 }; 1422 }; 1423 1424 uart2-m0 { 1425 uart2m0_xfer: uart2m0-xfer { 1426 rockchip,pins = 1427 <1 RK_PD2 2 &pcfg_pull_up>, 1428 <1 RK_PD3 2 &pcfg_pull_up>; 1429 }; 1430 }; 1431 1432 uart2-m1 { 1433 uart2m1_xfer: uart2m1-xfer { 1434 rockchip,pins = 1435 <2 RK_PB4 2 &pcfg_pull_up>, 1436 <2 RK_PB6 2 &pcfg_pull_up>; 1437 }; 1438 }; 1439 1440 uart3-m0 { 1441 uart3m0_xfer: uart3m0-xfer { 1442 rockchip,pins = 1443 <0 RK_PC0 2 &pcfg_pull_up>, 1444 <0 RK_PC1 2 &pcfg_pull_up>; 1445 }; 1446 1447 uart3m0_cts: uart3m0-cts { 1448 rockchip,pins = 1449 <0 RK_PC2 2 &pcfg_pull_none>; 1450 }; 1451 1452 uart3m0_rts: uart3m0-rts { 1453 rockchip,pins = 1454 <0 RK_PC3 2 &pcfg_pull_none>; 1455 }; 1456 }; 1457 1458 uart3-m1 { 1459 uart3m1_xfer: uart3m1-xfer { 1460 rockchip,pins = 1461 <1 RK_PB6 2 &pcfg_pull_up>, 1462 <1 RK_PB7 2 &pcfg_pull_up>; 1463 }; 1464 1465 uart3m1_cts: uart3m1-cts { 1466 rockchip,pins = 1467 <1 RK_PB4 2 &pcfg_pull_none>; 1468 }; 1469 1470 uart3m1_rts: uart3m1-rts { 1471 rockchip,pins = 1472 <1 RK_PB5 2 &pcfg_pull_none>; 1473 }; 1474 }; 1475 1476 uart4 { 1477 uart4_xfer: uart4-xfer { 1478 rockchip,pins = 1479 <1 RK_PD4 2 &pcfg_pull_up>, 1480 <1 RK_PD5 2 &pcfg_pull_up>; 1481 }; 1482 1483 uart4_cts: uart4-cts { 1484 rockchip,pins = 1485 <1 RK_PD6 2 &pcfg_pull_none>; 1486 }; 1487 1488 uart4_rts: uart4-rts { 1489 rockchip,pins = 1490 <1 RK_PD7 2 &pcfg_pull_none>; 1491 }; 1492 }; 1493 1494 uart5 { 1495 uart5_xfer: uart5-xfer { 1496 rockchip,pins = 1497 <3 RK_PA2 4 &pcfg_pull_up>, 1498 <3 RK_PA1 4 &pcfg_pull_up>; 1499 }; 1500 1501 uart5_cts: uart5-cts { 1502 rockchip,pins = 1503 <3 RK_PA3 4 &pcfg_pull_none>; 1504 }; 1505 1506 uart5_rts: uart5-rts { 1507 rockchip,pins = 1508 <3 RK_PA5 4 &pcfg_pull_none>; 1509 }; 1510 }; 1511 1512 spi0 { 1513 spi0_clk: spi0-clk { 1514 rockchip,pins = 1515 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1516 }; 1517 1518 spi0_csn: spi0-csn { 1519 rockchip,pins = 1520 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1521 }; 1522 1523 spi0_miso: spi0-miso { 1524 rockchip,pins = 1525 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1526 }; 1527 1528 spi0_mosi: spi0-mosi { 1529 rockchip,pins = 1530 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1531 }; 1532 1533 spi0_clk_hs: spi0-clk-hs { 1534 rockchip,pins = 1535 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1536 }; 1537 1538 spi0_miso_hs: spi0-miso-hs { 1539 rockchip,pins = 1540 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1541 }; 1542 1543 spi0_mosi_hs: spi0-mosi-hs { 1544 rockchip,pins = 1545 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1546 }; 1547 }; 1548 1549 spi1 { 1550 spi1_clk: spi1-clk { 1551 rockchip,pins = 1552 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1553 }; 1554 1555 spi1_csn0: spi1-csn0 { 1556 rockchip,pins = 1557 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1558 }; 1559 1560 spi1_csn1: spi1-csn1 { 1561 rockchip,pins = 1562 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1563 }; 1564 1565 spi1_miso: spi1-miso { 1566 rockchip,pins = 1567 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1568 }; 1569 1570 spi1_mosi: spi1-mosi { 1571 rockchip,pins = 1572 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1573 }; 1574 1575 spi1_clk_hs: spi1-clk-hs { 1576 rockchip,pins = 1577 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1578 }; 1579 1580 spi1_miso_hs: spi1-miso-hs { 1581 rockchip,pins = 1582 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1583 }; 1584 1585 spi1_mosi_hs: spi1-mosi-hs { 1586 rockchip,pins = 1587 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1588 }; 1589 }; 1590 1591 pdm { 1592 pdm_clk0m0: pdm-clk0m0 { 1593 rockchip,pins = 1594 <3 RK_PC6 2 &pcfg_pull_none>; 1595 }; 1596 1597 pdm_clk0m1: pdm-clk0m1 { 1598 rockchip,pins = 1599 <2 RK_PC6 1 &pcfg_pull_none>; 1600 }; 1601 1602 pdm_clk1: pdm-clk1 { 1603 rockchip,pins = 1604 <3 RK_PC7 2 &pcfg_pull_none>; 1605 }; 1606 1607 pdm_sdi0m0: pdm-sdi0m0 { 1608 rockchip,pins = 1609 <3 RK_PD3 2 &pcfg_pull_none>; 1610 }; 1611 1612 pdm_sdi0m1: pdm-sdi0m1 { 1613 rockchip,pins = 1614 <2 RK_PC5 2 &pcfg_pull_none>; 1615 }; 1616 1617 pdm_sdi1: pdm-sdi1 { 1618 rockchip,pins = 1619 <3 RK_PD0 2 &pcfg_pull_none>; 1620 }; 1621 1622 pdm_sdi2: pdm-sdi2 { 1623 rockchip,pins = 1624 <3 RK_PD1 2 &pcfg_pull_none>; 1625 }; 1626 1627 pdm_sdi3: pdm-sdi3 { 1628 rockchip,pins = 1629 <3 RK_PD2 2 &pcfg_pull_none>; 1630 }; 1631 1632 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1633 rockchip,pins = 1634 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1635 }; 1636 1637 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1638 rockchip,pins = 1639 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1640 }; 1641 1642 pdm_clk1_sleep: pdm-clk1-sleep { 1643 rockchip,pins = 1644 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1645 }; 1646 1647 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1648 rockchip,pins = 1649 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1650 }; 1651 1652 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1653 rockchip,pins = 1654 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1655 }; 1656 1657 pdm_sdi1_sleep: pdm-sdi1-sleep { 1658 rockchip,pins = 1659 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1660 }; 1661 1662 pdm_sdi2_sleep: pdm-sdi2-sleep { 1663 rockchip,pins = 1664 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1665 }; 1666 1667 pdm_sdi3_sleep: pdm-sdi3-sleep { 1668 rockchip,pins = 1669 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1670 }; 1671 }; 1672 1673 i2s0 { 1674 i2s0_8ch_mclk: i2s0-8ch-mclk { 1675 rockchip,pins = 1676 <3 RK_PC1 2 &pcfg_pull_none>; 1677 }; 1678 1679 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1680 rockchip,pins = 1681 <3 RK_PC3 2 &pcfg_pull_none>; 1682 }; 1683 1684 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1685 rockchip,pins = 1686 <3 RK_PB4 2 &pcfg_pull_none>; 1687 }; 1688 1689 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1690 rockchip,pins = 1691 <3 RK_PC2 2 &pcfg_pull_none>; 1692 }; 1693 1694 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1695 rockchip,pins = 1696 <3 RK_PB5 2 &pcfg_pull_none>; 1697 }; 1698 1699 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1700 rockchip,pins = 1701 <3 RK_PC4 2 &pcfg_pull_none>; 1702 }; 1703 1704 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1705 rockchip,pins = 1706 <3 RK_PC0 2 &pcfg_pull_none>; 1707 }; 1708 1709 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1710 rockchip,pins = 1711 <3 RK_PB7 2 &pcfg_pull_none>; 1712 }; 1713 1714 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1715 rockchip,pins = 1716 <3 RK_PB6 2 &pcfg_pull_none>; 1717 }; 1718 1719 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1720 rockchip,pins = 1721 <3 RK_PC5 2 &pcfg_pull_none>; 1722 }; 1723 1724 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1725 rockchip,pins = 1726 <3 RK_PB3 2 &pcfg_pull_none>; 1727 }; 1728 1729 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1730 rockchip,pins = 1731 <3 RK_PB1 2 &pcfg_pull_none>; 1732 }; 1733 1734 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1735 rockchip,pins = 1736 <3 RK_PB0 2 &pcfg_pull_none>; 1737 }; 1738 }; 1739 1740 i2s1 { 1741 i2s1_2ch_mclk: i2s1-2ch-mclk { 1742 rockchip,pins = 1743 <2 RK_PC3 1 &pcfg_pull_none>; 1744 }; 1745 1746 i2s1_2ch_sclk: i2s1-2ch-sclk { 1747 rockchip,pins = 1748 <2 RK_PC2 1 &pcfg_pull_none>; 1749 }; 1750 1751 i2s1_2ch_lrck: i2s1-2ch-lrck { 1752 rockchip,pins = 1753 <2 RK_PC1 1 &pcfg_pull_none>; 1754 }; 1755 1756 i2s1_2ch_sdi: i2s1-2ch-sdi { 1757 rockchip,pins = 1758 <2 RK_PC5 1 &pcfg_pull_none>; 1759 }; 1760 1761 i2s1_2ch_sdo: i2s1-2ch-sdo { 1762 rockchip,pins = 1763 <2 RK_PC4 1 &pcfg_pull_none>; 1764 }; 1765 }; 1766 1767 i2s2 { 1768 i2s2_2ch_mclk: i2s2-2ch-mclk { 1769 rockchip,pins = 1770 <3 RK_PA1 2 &pcfg_pull_none>; 1771 }; 1772 1773 i2s2_2ch_sclk: i2s2-2ch-sclk { 1774 rockchip,pins = 1775 <3 RK_PA2 2 &pcfg_pull_none>; 1776 }; 1777 1778 i2s2_2ch_lrck: i2s2-2ch-lrck { 1779 rockchip,pins = 1780 <3 RK_PA3 2 &pcfg_pull_none>; 1781 }; 1782 1783 i2s2_2ch_sdi: i2s2-2ch-sdi { 1784 rockchip,pins = 1785 <3 RK_PA5 2 &pcfg_pull_none>; 1786 }; 1787 1788 i2s2_2ch_sdo: i2s2-2ch-sdo { 1789 rockchip,pins = 1790 <3 RK_PA7 2 &pcfg_pull_none>; 1791 }; 1792 }; 1793 1794 sdmmc { 1795 sdmmc_clk: sdmmc-clk { 1796 rockchip,pins = 1797 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1798 }; 1799 1800 sdmmc_cmd: sdmmc-cmd { 1801 rockchip,pins = 1802 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1803 }; 1804 1805 sdmmc_det: sdmmc-det { 1806 rockchip,pins = 1807 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1808 }; 1809 1810 sdmmc_bus1: sdmmc-bus1 { 1811 rockchip,pins = 1812 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1813 }; 1814 1815 sdmmc_bus4: sdmmc-bus4 { 1816 rockchip,pins = 1817 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1818 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1819 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1820 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1821 }; 1822 }; 1823 1824 sdio { 1825 sdio_clk: sdio-clk { 1826 rockchip,pins = 1827 <1 RK_PC5 1 &pcfg_pull_none>; 1828 }; 1829 1830 sdio_cmd: sdio-cmd { 1831 rockchip,pins = 1832 <1 RK_PC4 1 &pcfg_pull_up>; 1833 }; 1834 1835 sdio_bus4: sdio-bus4 { 1836 rockchip,pins = 1837 <1 RK_PC6 1 &pcfg_pull_up>, 1838 <1 RK_PC7 1 &pcfg_pull_up>, 1839 <1 RK_PD0 1 &pcfg_pull_up>, 1840 <1 RK_PD1 1 &pcfg_pull_up>; 1841 }; 1842 }; 1843 1844 emmc { 1845 emmc_clk: emmc-clk { 1846 rockchip,pins = 1847 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 1848 }; 1849 1850 emmc_cmd: emmc-cmd { 1851 rockchip,pins = 1852 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 1853 }; 1854 1855 emmc_rstnout: emmc-rstnout { 1856 rockchip,pins = 1857 <1 RK_PB3 2 &pcfg_pull_none>; 1858 }; 1859 1860 emmc_bus1: emmc-bus1 { 1861 rockchip,pins = 1862 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 1863 }; 1864 1865 emmc_bus4: emmc-bus4 { 1866 rockchip,pins = 1867 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1868 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1869 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1870 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 1871 }; 1872 1873 emmc_bus8: emmc-bus8 { 1874 rockchip,pins = 1875 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1876 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1877 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1878 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 1879 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 1880 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 1881 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 1882 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 1883 }; 1884 }; 1885 1886 flash { 1887 flash_cs0: flash-cs0 { 1888 rockchip,pins = 1889 <1 RK_PB0 1 &pcfg_pull_none>; 1890 }; 1891 1892 flash_rdy: flash-rdy { 1893 rockchip,pins = 1894 <1 RK_PB1 1 &pcfg_pull_none>; 1895 }; 1896 1897 flash_dqs: flash-dqs { 1898 rockchip,pins = 1899 <1 RK_PB2 1 &pcfg_pull_none>; 1900 }; 1901 1902 flash_ale: flash-ale { 1903 rockchip,pins = 1904 <1 RK_PB3 1 &pcfg_pull_none>; 1905 }; 1906 1907 flash_cle: flash-cle { 1908 rockchip,pins = 1909 <1 RK_PB4 1 &pcfg_pull_none>; 1910 }; 1911 1912 flash_wrn: flash-wrn { 1913 rockchip,pins = 1914 <1 RK_PB5 1 &pcfg_pull_none>; 1915 }; 1916 1917 flash_csl: flash-csl { 1918 rockchip,pins = 1919 <1 RK_PB6 1 &pcfg_pull_none>; 1920 }; 1921 1922 flash_rdn: flash-rdn { 1923 rockchip,pins = 1924 <1 RK_PB7 1 &pcfg_pull_none>; 1925 }; 1926 1927 flash_bus8: flash-bus8 { 1928 rockchip,pins = 1929 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 1930 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 1931 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 1932 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 1933 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 1934 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 1935 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 1936 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 1937 }; 1938 }; 1939 1940 lcdc { 1941 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1942 rockchip,pins = 1943 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 1944 }; 1945 1946 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1947 rockchip,pins = 1948 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 1949 }; 1950 1951 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1952 rockchip,pins = 1953 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 1954 }; 1955 1956 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1957 rockchip,pins = 1958 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 1959 }; 1960 1961 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1962 rockchip,pins = 1963 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1964 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1965 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1966 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1967 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1968 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1969 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1970 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1971 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1972 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1973 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1974 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 1975 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1976 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1977 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1978 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1979 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 1980 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 1981 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1982 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 1983 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 1984 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 1985 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 1986 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 1987 }; 1988 1989 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 1990 rockchip,pins = 1991 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1992 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1993 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1994 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1995 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1996 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1997 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1998 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1999 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2000 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2001 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2002 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2003 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2004 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2005 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2006 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2007 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2008 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2009 }; 2010 2011 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2012 rockchip,pins = 2013 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2014 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2015 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2016 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2017 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2018 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2019 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2020 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2021 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2022 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2023 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2024 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2025 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2026 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2027 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2028 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2029 }; 2030 2031 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2032 rockchip,pins = 2033 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2034 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2035 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2036 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2037 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2038 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2039 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2040 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2041 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2042 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2043 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2044 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2045 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2046 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2047 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2048 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2049 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2050 }; 2051 2052 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2053 rockchip,pins = 2054 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2055 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2056 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2057 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2058 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2059 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2060 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2061 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2062 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2063 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2064 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2065 }; 2066 2067 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2068 rockchip,pins = 2069 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2070 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2071 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2072 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2073 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2074 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2075 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2076 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2077 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2078 }; 2079 }; 2080 2081 pwm0 { 2082 pwm0_pin: pwm0-pin { 2083 rockchip,pins = 2084 <0 RK_PB7 1 &pcfg_pull_none>; 2085 }; 2086 }; 2087 2088 pwm1 { 2089 pwm1_pin: pwm1-pin { 2090 rockchip,pins = 2091 <0 RK_PC0 1 &pcfg_pull_none>; 2092 }; 2093 }; 2094 2095 pwm2 { 2096 pwm2_pin: pwm2-pin { 2097 rockchip,pins = 2098 <2 RK_PB5 1 &pcfg_pull_none>; 2099 }; 2100 }; 2101 2102 pwm3 { 2103 pwm3_pin: pwm3-pin { 2104 rockchip,pins = 2105 <0 RK_PC1 1 &pcfg_pull_none>; 2106 }; 2107 }; 2108 2109 pwm4 { 2110 pwm4_pin: pwm4-pin { 2111 rockchip,pins = 2112 <3 RK_PC2 3 &pcfg_pull_none>; 2113 }; 2114 }; 2115 2116 pwm5 { 2117 pwm5_pin: pwm5-pin { 2118 rockchip,pins = 2119 <3 RK_PC3 3 &pcfg_pull_none>; 2120 }; 2121 }; 2122 2123 pwm6 { 2124 pwm6_pin: pwm6-pin { 2125 rockchip,pins = 2126 <3 RK_PC4 3 &pcfg_pull_none>; 2127 }; 2128 }; 2129 2130 pwm7 { 2131 pwm7_pin: pwm7-pin { 2132 rockchip,pins = 2133 <3 RK_PC5 3 &pcfg_pull_none>; 2134 }; 2135 }; 2136 2137 gmac { 2138 rmii_pins: rmii-pins { 2139 rockchip,pins = 2140 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 2141 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 2142 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 2143 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 2144 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 2145 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 2146 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 2147 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 2148 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 2149 }; 2150 2151 mac_refclk_12ma: mac-refclk-12ma { 2152 rockchip,pins = 2153 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 2154 }; 2155 2156 mac_refclk: mac-refclk { 2157 rockchip,pins = 2158 <2 RK_PB2 2 &pcfg_pull_none>; 2159 }; 2160 }; 2161 2162 cif-m0 { 2163 cif_clkout_m0: cif-clkout-m0 { 2164 rockchip,pins = 2165 <2 RK_PB3 1 &pcfg_pull_none>; 2166 }; 2167 2168 dvp_d2d9_m0: dvp-d2d9-m0 { 2169 rockchip,pins = 2170 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 2171 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 2172 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 2173 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 2174 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 2175 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 2176 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 2177 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 2178 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 2179 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 2180 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 2181 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 2182 }; 2183 2184 dvp_d0d1_m0: dvp-d0d1-m0 { 2185 rockchip,pins = 2186 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 2187 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 2188 }; 2189 2190 dvp_d10d11_m0:d10-d11-m0 { 2191 rockchip,pins = 2192 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 2193 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 2194 }; 2195 }; 2196 2197 cif-m1 { 2198 cif_clkout_m1: cif-clkout-m1 { 2199 rockchip,pins = 2200 <3 RK_PD0 3 &pcfg_pull_none>; 2201 }; 2202 2203 dvp_d2d9_m1: dvp-d2d9-m1 { 2204 rockchip,pins = 2205 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 2206 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 2207 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 2208 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 2209 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 2210 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 2211 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 2212 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 2213 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 2214 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 2215 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 2216 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 2217 }; 2218 2219 dvp_d0d1_m1: dvp-d0d1-m1 { 2220 rockchip,pins = 2221 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 2222 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 2223 }; 2224 2225 dvp_d10d11_m1:d10-d11-m1 { 2226 rockchip,pins = 2227 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 2228 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 2229 }; 2230 }; 2231 2232 isp { 2233 isp_prelight: isp-prelight { 2234 rockchip,pins = 2235 <3 RK_PD1 4 &pcfg_pull_none>; 2236 }; 2237 }; 2238 }; 2239}; 2240