1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 serial3 = &uart3; 32 serial4 = &uart4; 33 serial5 = &uart5; 34 spi0 = &spi0; 35 spi1 = &spi1; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a35"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 clocks = <&cru ARMCLK>; 48 #cooling-cells = <2>; 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 50 dynamic-power-coefficient = <90>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 #cooling-cells = <2>; 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 62 dynamic-power-coefficient = <90>; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 clocks = <&cru ARMCLK>; 72 #cooling-cells = <2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 74 dynamic-power-coefficient = <90>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 }; 77 78 cpu3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a35"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 #cooling-cells = <2>; 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 86 dynamic-power-coefficient = <90>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 102 CLUSTER_SLEEP: cluster-sleep { 103 compatible = "arm,idle-state"; 104 local-timer-stop; 105 arm,psci-suspend-param = <0x1010000>; 106 entry-latency-us = <400>; 107 exit-latency-us = <500>; 108 min-residency-us = <2000>; 109 }; 110 }; 111 }; 112 113 cpu0_opp_table: opp-table-0 { 114 compatible = "operating-points-v2"; 115 opp-shared; 116 117 opp-600000000 { 118 opp-hz = /bits/ 64 <600000000>; 119 opp-microvolt = <950000 950000 1350000>; 120 clock-latency-ns = <40000>; 121 opp-suspend; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1050000 1050000 1350000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1175000 1175000 1350000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1300000 1300000 1350000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1350000 1350000 1350000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a35-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vopb_out>, <&vopl_out>; 157 status = "disabled"; 158 }; 159 160 gmac_clkin: external-gmac-clock { 161 compatible = "fixed-clock"; 162 clock-frequency = <50000000>; 163 clock-output-names = "gmac_clkin"; 164 #clock-cells = <0>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 178 }; 179 180 thermal_zones: thermal-zones { 181 soc_thermal: soc-thermal { 182 polling-delay-passive = <20>; 183 polling-delay = <1000>; 184 sustainable-power = <750>; 185 thermal-sensors = <&tsadc 0>; 186 187 trips { 188 threshold: trip-point-0 { 189 temperature = <70000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 target: trip-point-1 { 195 temperature = <85000>; 196 hysteresis = <2000>; 197 type = "passive"; 198 }; 199 200 soc_crit: soc-crit { 201 temperature = <115000>; 202 hysteresis = <2000>; 203 type = "critical"; 204 }; 205 }; 206 207 cooling-maps { 208 map0 { 209 trip = <&target>; 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211 contribution = <4096>; 212 }; 213 214 map1 { 215 trip = <&target>; 216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 217 contribution = <4096>; 218 }; 219 }; 220 }; 221 222 gpu_thermal: gpu-thermal { 223 polling-delay-passive = <100>; /* milliseconds */ 224 polling-delay = <1000>; /* milliseconds */ 225 thermal-sensors = <&tsadc 1>; 226 }; 227 }; 228 229 xin24m: xin24m { 230 compatible = "fixed-clock"; 231 #clock-cells = <0>; 232 clock-frequency = <24000000>; 233 clock-output-names = "xin24m"; 234 }; 235 236 pmu: power-management@ff000000 { 237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 238 reg = <0x0 0xff000000 0x0 0x1000>; 239 240 power: power-controller { 241 compatible = "rockchip,px30-power-controller"; 242 #power-domain-cells = <1>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 /* These power domains are grouped by VD_LOGIC */ 247 power-domain@PX30_PD_USB { 248 reg = <PX30_PD_USB>; 249 clocks = <&cru HCLK_HOST>, 250 <&cru HCLK_OTG>, 251 <&cru SCLK_OTG_ADP>; 252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 253 #power-domain-cells = <0>; 254 }; 255 power-domain@PX30_PD_SDCARD { 256 reg = <PX30_PD_SDCARD>; 257 clocks = <&cru HCLK_SDMMC>, 258 <&cru SCLK_SDMMC>; 259 pm_qos = <&qos_sdmmc>; 260 #power-domain-cells = <0>; 261 }; 262 power-domain@PX30_PD_GMAC { 263 reg = <PX30_PD_GMAC>; 264 clocks = <&cru ACLK_GMAC>, 265 <&cru PCLK_GMAC>, 266 <&cru SCLK_MAC_REF>, 267 <&cru SCLK_GMAC_RX_TX>; 268 pm_qos = <&qos_gmac>; 269 #power-domain-cells = <0>; 270 }; 271 power-domain@PX30_PD_MMC_NAND { 272 reg = <PX30_PD_MMC_NAND>; 273 clocks = <&cru HCLK_NANDC>, 274 <&cru HCLK_EMMC>, 275 <&cru HCLK_SDIO>, 276 <&cru HCLK_SFC>, 277 <&cru SCLK_EMMC>, 278 <&cru SCLK_NANDC>, 279 <&cru SCLK_SDIO>, 280 <&cru SCLK_SFC>; 281 pm_qos = <&qos_emmc>, <&qos_nand>, 282 <&qos_sdio>, <&qos_sfc>; 283 #power-domain-cells = <0>; 284 }; 285 power-domain@PX30_PD_VPU { 286 reg = <PX30_PD_VPU>; 287 clocks = <&cru ACLK_VPU>, 288 <&cru HCLK_VPU>, 289 <&cru SCLK_CORE_VPU>; 290 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 291 #power-domain-cells = <0>; 292 }; 293 power-domain@PX30_PD_VO { 294 reg = <PX30_PD_VO>; 295 clocks = <&cru ACLK_RGA>, 296 <&cru ACLK_VOPB>, 297 <&cru ACLK_VOPL>, 298 <&cru DCLK_VOPB>, 299 <&cru DCLK_VOPL>, 300 <&cru HCLK_RGA>, 301 <&cru HCLK_VOPB>, 302 <&cru HCLK_VOPL>, 303 <&cru PCLK_MIPI_DSI>, 304 <&cru SCLK_RGA_CORE>, 305 <&cru SCLK_VOPB_PWM>; 306 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 307 <&qos_vop_m0>, <&qos_vop_m1>; 308 #power-domain-cells = <0>; 309 }; 310 power-domain@PX30_PD_VI { 311 reg = <PX30_PD_VI>; 312 clocks = <&cru ACLK_CIF>, 313 <&cru ACLK_ISP>, 314 <&cru HCLK_CIF>, 315 <&cru HCLK_ISP>, 316 <&cru SCLK_ISP>; 317 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 318 <&qos_isp_wr>, <&qos_isp_m1>, 319 <&qos_vip>; 320 #power-domain-cells = <0>; 321 }; 322 power-domain@PX30_PD_GPU { 323 reg = <PX30_PD_GPU>; 324 clocks = <&cru SCLK_GPU>; 325 pm_qos = <&qos_gpu>; 326 #power-domain-cells = <0>; 327 }; 328 }; 329 }; 330 331 pmugrf: syscon@ff010000 { 332 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 333 reg = <0x0 0xff010000 0x0 0x1000>; 334 #address-cells = <1>; 335 #size-cells = <1>; 336 337 pmu_io_domains: io-domains { 338 compatible = "rockchip,px30-pmu-io-voltage-domain"; 339 status = "disabled"; 340 }; 341 342 reboot-mode { 343 compatible = "syscon-reboot-mode"; 344 offset = <0x200>; 345 mode-bootloader = <BOOT_BL_DOWNLOAD>; 346 mode-fastboot = <BOOT_FASTBOOT>; 347 mode-loader = <BOOT_BL_DOWNLOAD>; 348 mode-normal = <BOOT_NORMAL>; 349 mode-recovery = <BOOT_RECOVERY>; 350 }; 351 }; 352 353 uart0: serial@ff030000 { 354 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 355 reg = <0x0 0xff030000 0x0 0x100>; 356 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 358 clock-names = "baudclk", "apb_pclk"; 359 dmas = <&dmac 0>, <&dmac 1>; 360 dma-names = "tx", "rx"; 361 reg-shift = <2>; 362 reg-io-width = <4>; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 365 status = "disabled"; 366 }; 367 368 i2s0_8ch: i2s@ff060000 { 369 compatible = "rockchip,px30-i2s-tdm"; 370 reg = <0x0 0xff060000 0x0 0x1000>; 371 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>; 373 clock-names = "mclk_tx", "mclk_rx", "hclk"; 374 dmas = <&dmac 16>, <&dmac 17>; 375 dma-names = "tx", "rx"; 376 rockchip,grf = <&grf>; 377 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; 378 reset-names = "tx-m", "rx-m"; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx 381 &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx 382 &i2s0_8ch_sdo0 &i2s0_8ch_sdi0 383 &i2s0_8ch_sdo1 &i2s0_8ch_sdi1 384 &i2s0_8ch_sdo2 &i2s0_8ch_sdi2 385 &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>; 386 #sound-dai-cells = <0>; 387 status = "disabled"; 388 }; 389 390 i2s1_2ch: i2s@ff070000 { 391 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 392 reg = <0x0 0xff070000 0x0 0x1000>; 393 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 395 clock-names = "i2s_clk", "i2s_hclk"; 396 dmas = <&dmac 18>, <&dmac 19>; 397 dma-names = "tx", "rx"; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 400 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 401 #sound-dai-cells = <0>; 402 status = "disabled"; 403 }; 404 405 i2s2_2ch: i2s@ff080000 { 406 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 407 reg = <0x0 0xff080000 0x0 0x1000>; 408 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 410 clock-names = "i2s_clk", "i2s_hclk"; 411 dmas = <&dmac 20>, <&dmac 21>; 412 dma-names = "tx", "rx"; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 415 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 416 #sound-dai-cells = <0>; 417 status = "disabled"; 418 }; 419 420 gic: interrupt-controller@ff131000 { 421 compatible = "arm,gic-400"; 422 #interrupt-cells = <3>; 423 #address-cells = <0>; 424 interrupt-controller; 425 reg = <0x0 0xff131000 0 0x1000>, 426 <0x0 0xff132000 0 0x2000>, 427 <0x0 0xff134000 0 0x2000>, 428 <0x0 0xff136000 0 0x2000>; 429 interrupts = <GIC_PPI 9 430 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 431 }; 432 433 grf: syscon@ff140000 { 434 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 435 reg = <0x0 0xff140000 0x0 0x1000>; 436 #address-cells = <1>; 437 #size-cells = <1>; 438 439 io_domains: io-domains { 440 compatible = "rockchip,px30-io-voltage-domain"; 441 status = "disabled"; 442 }; 443 444 lvds: lvds { 445 compatible = "rockchip,px30-lvds"; 446 phys = <&dsi_dphy>; 447 phy-names = "dphy"; 448 rockchip,grf = <&grf>; 449 rockchip,output = "lvds"; 450 status = "disabled"; 451 452 ports { 453 #address-cells = <1>; 454 #size-cells = <0>; 455 456 port@0 { 457 reg = <0>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 461 lvds_vopb_in: endpoint@0 { 462 reg = <0>; 463 remote-endpoint = <&vopb_out_lvds>; 464 }; 465 466 lvds_vopl_in: endpoint@1 { 467 reg = <1>; 468 remote-endpoint = <&vopl_out_lvds>; 469 }; 470 }; 471 }; 472 }; 473 }; 474 475 uart1: serial@ff158000 { 476 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 477 reg = <0x0 0xff158000 0x0 0x100>; 478 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 480 clock-names = "baudclk", "apb_pclk"; 481 dmas = <&dmac 2>, <&dmac 3>; 482 dma-names = "tx", "rx"; 483 reg-shift = <2>; 484 reg-io-width = <4>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 487 status = "disabled"; 488 }; 489 490 uart2: serial@ff160000 { 491 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 492 reg = <0x0 0xff160000 0x0 0x100>; 493 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 495 clock-names = "baudclk", "apb_pclk"; 496 dmas = <&dmac 4>, <&dmac 5>; 497 dma-names = "tx", "rx"; 498 reg-shift = <2>; 499 reg-io-width = <4>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&uart2m0_xfer>; 502 status = "disabled"; 503 }; 504 505 uart3: serial@ff168000 { 506 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 507 reg = <0x0 0xff168000 0x0 0x100>; 508 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 510 clock-names = "baudclk", "apb_pclk"; 511 dmas = <&dmac 6>, <&dmac 7>; 512 dma-names = "tx", "rx"; 513 reg-shift = <2>; 514 reg-io-width = <4>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 517 status = "disabled"; 518 }; 519 520 uart4: serial@ff170000 { 521 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 522 reg = <0x0 0xff170000 0x0 0x100>; 523 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 525 clock-names = "baudclk", "apb_pclk"; 526 dmas = <&dmac 8>, <&dmac 9>; 527 dma-names = "tx", "rx"; 528 reg-shift = <2>; 529 reg-io-width = <4>; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 532 status = "disabled"; 533 }; 534 535 uart5: serial@ff178000 { 536 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 537 reg = <0x0 0xff178000 0x0 0x100>; 538 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 540 clock-names = "baudclk", "apb_pclk"; 541 dmas = <&dmac 10>, <&dmac 11>; 542 dma-names = "tx", "rx"; 543 reg-shift = <2>; 544 reg-io-width = <4>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 547 status = "disabled"; 548 }; 549 550 i2c0: i2c@ff180000 { 551 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 552 reg = <0x0 0xff180000 0x0 0x1000>; 553 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 554 clock-names = "i2c", "pclk"; 555 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&i2c0_xfer>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 status = "disabled"; 561 }; 562 563 i2c1: i2c@ff190000 { 564 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 565 reg = <0x0 0xff190000 0x0 0x1000>; 566 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 567 clock-names = "i2c", "pclk"; 568 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&i2c1_xfer>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 status = "disabled"; 574 }; 575 576 i2c2: i2c@ff1a0000 { 577 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 578 reg = <0x0 0xff1a0000 0x0 0x1000>; 579 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 580 clock-names = "i2c", "pclk"; 581 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&i2c2_xfer>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 status = "disabled"; 587 }; 588 589 i2c3: i2c@ff1b0000 { 590 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 591 reg = <0x0 0xff1b0000 0x0 0x1000>; 592 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 593 clock-names = "i2c", "pclk"; 594 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&i2c3_xfer>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 }; 601 602 spi0: spi@ff1d0000 { 603 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 604 reg = <0x0 0xff1d0000 0x0 0x1000>; 605 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 607 clock-names = "spiclk", "apb_pclk"; 608 dmas = <&dmac 12>, <&dmac 13>; 609 dma-names = "tx", "rx"; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 status = "disabled"; 615 }; 616 617 spi1: spi@ff1d8000 { 618 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 619 reg = <0x0 0xff1d8000 0x0 0x1000>; 620 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 622 clock-names = "spiclk", "apb_pclk"; 623 dmas = <&dmac 14>, <&dmac 15>; 624 dma-names = "tx", "rx"; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 status = "disabled"; 630 }; 631 632 wdt: watchdog@ff1e0000 { 633 compatible = "rockchip,px30-wdt", "snps,dw-wdt"; 634 reg = <0x0 0xff1e0000 0x0 0x100>; 635 clocks = <&cru PCLK_WDT_NS>; 636 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 637 status = "disabled"; 638 }; 639 640 pwm0: pwm@ff200000 { 641 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 642 reg = <0x0 0xff200000 0x0 0x10>; 643 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 644 clock-names = "pwm", "pclk"; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&pwm0_pin>; 647 #pwm-cells = <3>; 648 status = "disabled"; 649 }; 650 651 pwm1: pwm@ff200010 { 652 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 653 reg = <0x0 0xff200010 0x0 0x10>; 654 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 655 clock-names = "pwm", "pclk"; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&pwm1_pin>; 658 #pwm-cells = <3>; 659 status = "disabled"; 660 }; 661 662 pwm2: pwm@ff200020 { 663 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 664 reg = <0x0 0xff200020 0x0 0x10>; 665 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 666 clock-names = "pwm", "pclk"; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pwm2_pin>; 669 #pwm-cells = <3>; 670 status = "disabled"; 671 }; 672 673 pwm3: pwm@ff200030 { 674 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 675 reg = <0x0 0xff200030 0x0 0x10>; 676 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 677 clock-names = "pwm", "pclk"; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&pwm3_pin>; 680 #pwm-cells = <3>; 681 status = "disabled"; 682 }; 683 684 pwm4: pwm@ff208000 { 685 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 686 reg = <0x0 0xff208000 0x0 0x10>; 687 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 688 clock-names = "pwm", "pclk"; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&pwm4_pin>; 691 #pwm-cells = <3>; 692 status = "disabled"; 693 }; 694 695 pwm5: pwm@ff208010 { 696 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 697 reg = <0x0 0xff208010 0x0 0x10>; 698 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 699 clock-names = "pwm", "pclk"; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&pwm5_pin>; 702 #pwm-cells = <3>; 703 status = "disabled"; 704 }; 705 706 pwm6: pwm@ff208020 { 707 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 708 reg = <0x0 0xff208020 0x0 0x10>; 709 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 710 clock-names = "pwm", "pclk"; 711 pinctrl-names = "default"; 712 pinctrl-0 = <&pwm6_pin>; 713 #pwm-cells = <3>; 714 status = "disabled"; 715 }; 716 717 pwm7: pwm@ff208030 { 718 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 719 reg = <0x0 0xff208030 0x0 0x10>; 720 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 721 clock-names = "pwm", "pclk"; 722 pinctrl-names = "default"; 723 pinctrl-0 = <&pwm7_pin>; 724 #pwm-cells = <3>; 725 status = "disabled"; 726 }; 727 728 rktimer: timer@ff210000 { 729 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 730 reg = <0x0 0xff210000 0x0 0x1000>; 731 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 733 clock-names = "pclk", "timer"; 734 }; 735 736 dmac: dma-controller@ff240000 { 737 compatible = "arm,pl330", "arm,primecell"; 738 reg = <0x0 0xff240000 0x0 0x4000>; 739 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 741 arm,pl330-periph-burst; 742 clocks = <&cru ACLK_DMAC>; 743 clock-names = "apb_pclk"; 744 #dma-cells = <1>; 745 }; 746 747 tsadc: tsadc@ff280000 { 748 compatible = "rockchip,px30-tsadc"; 749 reg = <0x0 0xff280000 0x0 0x100>; 750 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 751 assigned-clocks = <&cru SCLK_TSADC>; 752 assigned-clock-rates = <50000>; 753 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 754 clock-names = "tsadc", "apb_pclk"; 755 resets = <&cru SRST_TSADC>; 756 reset-names = "tsadc-apb"; 757 rockchip,grf = <&grf>; 758 rockchip,hw-tshut-temp = <120000>; 759 pinctrl-names = "init", "default", "sleep"; 760 pinctrl-0 = <&tsadc_otp_pin>; 761 pinctrl-1 = <&tsadc_otp_out>; 762 pinctrl-2 = <&tsadc_otp_pin>; 763 #thermal-sensor-cells = <1>; 764 status = "disabled"; 765 }; 766 767 saradc: saradc@ff288000 { 768 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 769 reg = <0x0 0xff288000 0x0 0x100>; 770 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 771 #io-channel-cells = <1>; 772 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 773 clock-names = "saradc", "apb_pclk"; 774 resets = <&cru SRST_SARADC_P>; 775 reset-names = "saradc-apb"; 776 status = "disabled"; 777 }; 778 779 otp: nvmem@ff290000 { 780 compatible = "rockchip,px30-otp"; 781 reg = <0x0 0xff290000 0x0 0x4000>; 782 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 783 <&cru PCLK_OTP_PHY>; 784 clock-names = "otp", "apb_pclk", "phy"; 785 resets = <&cru SRST_OTP_PHY>; 786 reset-names = "phy"; 787 #address-cells = <1>; 788 #size-cells = <1>; 789 790 /* Data cells */ 791 cpu_id: id@7 { 792 reg = <0x07 0x10>; 793 }; 794 cpu_leakage: cpu-leakage@17 { 795 reg = <0x17 0x1>; 796 }; 797 performance: performance@1e { 798 reg = <0x1e 0x1>; 799 bits = <4 3>; 800 }; 801 }; 802 803 cru: clock-controller@ff2b0000 { 804 compatible = "rockchip,px30-cru"; 805 reg = <0x0 0xff2b0000 0x0 0x1000>; 806 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 807 clock-names = "xin24m", "gpll"; 808 rockchip,grf = <&grf>; 809 #clock-cells = <1>; 810 #reset-cells = <1>; 811 812 assigned-clocks = <&cru PLL_NPLL>, 813 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 814 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 815 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 816 817 assigned-clock-rates = <1188000000>, 818 <200000000>, <200000000>, 819 <150000000>, <150000000>, 820 <100000000>, <200000000>; 821 }; 822 823 pmucru: clock-controller@ff2bc000 { 824 compatible = "rockchip,px30-pmucru"; 825 reg = <0x0 0xff2bc000 0x0 0x1000>; 826 clocks = <&xin24m>; 827 clock-names = "xin24m"; 828 rockchip,grf = <&grf>; 829 #clock-cells = <1>; 830 #reset-cells = <1>; 831 832 assigned-clocks = 833 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 834 <&pmucru SCLK_WIFI_PMU>; 835 assigned-clock-rates = 836 <1200000000>, <100000000>, 837 <26000000>; 838 }; 839 840 usb2phy_grf: syscon@ff2c0000 { 841 compatible = "rockchip,px30-usb2phy-grf", "syscon", 842 "simple-mfd"; 843 reg = <0x0 0xff2c0000 0x0 0x10000>; 844 #address-cells = <1>; 845 #size-cells = <1>; 846 847 u2phy: usb2phy@100 { 848 compatible = "rockchip,px30-usb2phy"; 849 reg = <0x100 0x20>; 850 clocks = <&pmucru SCLK_USBPHY_REF>; 851 clock-names = "phyclk"; 852 #clock-cells = <0>; 853 assigned-clocks = <&cru USB480M>; 854 assigned-clock-parents = <&u2phy>; 855 clock-output-names = "usb480m_phy"; 856 status = "disabled"; 857 858 u2phy_host: host-port { 859 #phy-cells = <0>; 860 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 861 interrupt-names = "linestate"; 862 status = "disabled"; 863 }; 864 865 u2phy_otg: otg-port { 866 #phy-cells = <0>; 867 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 870 interrupt-names = "otg-bvalid", "otg-id", 871 "linestate"; 872 status = "disabled"; 873 }; 874 }; 875 }; 876 877 dsi_dphy: phy@ff2e0000 { 878 compatible = "rockchip,px30-dsi-dphy"; 879 reg = <0x0 0xff2e0000 0x0 0x10000>; 880 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 881 clock-names = "ref", "pclk"; 882 resets = <&cru SRST_MIPIDSIPHY_P>; 883 reset-names = "apb"; 884 #phy-cells = <0>; 885 power-domains = <&power PX30_PD_VO>; 886 status = "disabled"; 887 }; 888 889 csi_dphy: phy@ff2f0000 { 890 compatible = "rockchip,px30-csi-dphy"; 891 reg = <0x0 0xff2f0000 0x0 0x4000>; 892 clocks = <&cru PCLK_MIPICSIPHY>; 893 clock-names = "pclk"; 894 #phy-cells = <0>; 895 power-domains = <&power PX30_PD_VI>; 896 resets = <&cru SRST_MIPICSIPHY_P>; 897 reset-names = "apb"; 898 rockchip,grf = <&grf>; 899 status = "disabled"; 900 }; 901 902 usb20_otg: usb@ff300000 { 903 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 904 "snps,dwc2"; 905 reg = <0x0 0xff300000 0x0 0x40000>; 906 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&cru HCLK_OTG>; 908 clock-names = "otg"; 909 dr_mode = "otg"; 910 g-np-tx-fifo-size = <16>; 911 g-rx-fifo-size = <280>; 912 g-tx-fifo-size = <256 128 128 64 32 16>; 913 phys = <&u2phy_otg>; 914 phy-names = "usb2-phy"; 915 power-domains = <&power PX30_PD_USB>; 916 status = "disabled"; 917 }; 918 919 usb_host0_ehci: usb@ff340000 { 920 compatible = "generic-ehci"; 921 reg = <0x0 0xff340000 0x0 0x10000>; 922 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&cru HCLK_HOST>; 924 phys = <&u2phy_host>; 925 phy-names = "usb"; 926 power-domains = <&power PX30_PD_USB>; 927 status = "disabled"; 928 }; 929 930 usb_host0_ohci: usb@ff350000 { 931 compatible = "generic-ohci"; 932 reg = <0x0 0xff350000 0x0 0x10000>; 933 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&cru HCLK_HOST>; 935 phys = <&u2phy_host>; 936 phy-names = "usb"; 937 power-domains = <&power PX30_PD_USB>; 938 status = "disabled"; 939 }; 940 941 gmac: ethernet@ff360000 { 942 compatible = "rockchip,px30-gmac"; 943 reg = <0x0 0xff360000 0x0 0x10000>; 944 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 945 interrupt-names = "macirq"; 946 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 947 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 948 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 949 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 950 clock-names = "stmmaceth", "mac_clk_rx", 951 "mac_clk_tx", "clk_mac_ref", 952 "clk_mac_refout", "aclk_mac", 953 "pclk_mac", "clk_mac_speed"; 954 rockchip,grf = <&grf>; 955 phy-mode = "rmii"; 956 pinctrl-names = "default"; 957 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 958 power-domains = <&power PX30_PD_GMAC>; 959 resets = <&cru SRST_GMAC_A>; 960 reset-names = "stmmaceth"; 961 status = "disabled"; 962 }; 963 964 sdmmc: mmc@ff370000 { 965 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 966 reg = <0x0 0xff370000 0x0 0x4000>; 967 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 969 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 970 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 971 bus-width = <4>; 972 fifo-depth = <0x100>; 973 max-frequency = <150000000>; 974 pinctrl-names = "default"; 975 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 976 power-domains = <&power PX30_PD_SDCARD>; 977 status = "disabled"; 978 }; 979 980 sdio: mmc@ff380000 { 981 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 982 reg = <0x0 0xff380000 0x0 0x4000>; 983 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 985 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 986 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 987 bus-width = <4>; 988 fifo-depth = <0x100>; 989 max-frequency = <150000000>; 990 pinctrl-names = "default"; 991 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 992 power-domains = <&power PX30_PD_MMC_NAND>; 993 status = "disabled"; 994 }; 995 996 emmc: mmc@ff390000 { 997 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 998 reg = <0x0 0xff390000 0x0 0x4000>; 999 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 1001 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1002 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1003 bus-width = <8>; 1004 fifo-depth = <0x100>; 1005 max-frequency = <150000000>; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 1008 power-domains = <&power PX30_PD_MMC_NAND>; 1009 status = "disabled"; 1010 }; 1011 1012 sfc: spi@ff3a0000 { 1013 compatible = "rockchip,sfc"; 1014 reg = <0x0 0xff3a0000 0x0 0x4000>; 1015 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1017 clock-names = "clk_sfc", "hclk_sfc"; 1018 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; 1019 pinctrl-names = "default"; 1020 power-domains = <&power PX30_PD_MMC_NAND>; 1021 status = "disabled"; 1022 }; 1023 1024 nfc: nand-controller@ff3b0000 { 1025 compatible = "rockchip,px30-nfc"; 1026 reg = <0x0 0xff3b0000 0x0 0x4000>; 1027 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 1029 clock-names = "ahb", "nfc"; 1030 assigned-clocks = <&cru SCLK_NANDC>; 1031 assigned-clock-rates = <150000000>; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 1034 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; 1035 power-domains = <&power PX30_PD_MMC_NAND>; 1036 status = "disabled"; 1037 }; 1038 1039 gpu_opp_table: opp-table-1 { 1040 compatible = "operating-points-v2"; 1041 1042 opp-200000000 { 1043 opp-hz = /bits/ 64 <200000000>; 1044 opp-microvolt = <950000>; 1045 }; 1046 opp-300000000 { 1047 opp-hz = /bits/ 64 <300000000>; 1048 opp-microvolt = <975000>; 1049 }; 1050 opp-400000000 { 1051 opp-hz = /bits/ 64 <400000000>; 1052 opp-microvolt = <1050000>; 1053 }; 1054 opp-480000000 { 1055 opp-hz = /bits/ 64 <480000000>; 1056 opp-microvolt = <1125000>; 1057 }; 1058 }; 1059 1060 gpu: gpu@ff400000 { 1061 compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 1062 reg = <0x0 0xff400000 0x0 0x4000>; 1063 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1066 interrupt-names = "job", "mmu", "gpu"; 1067 clocks = <&cru SCLK_GPU>; 1068 #cooling-cells = <2>; 1069 power-domains = <&power PX30_PD_GPU>; 1070 operating-points-v2 = <&gpu_opp_table>; 1071 status = "disabled"; 1072 }; 1073 1074 vpu: video-codec@ff442000 { 1075 compatible = "rockchip,px30-vpu"; 1076 reg = <0x0 0xff442000 0x0 0x800>; 1077 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1079 interrupt-names = "vepu", "vdpu"; 1080 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1081 clock-names = "aclk", "hclk"; 1082 iommus = <&vpu_mmu>; 1083 power-domains = <&power PX30_PD_VPU>; 1084 }; 1085 1086 vpu_mmu: iommu@ff442800 { 1087 compatible = "rockchip,iommu"; 1088 reg = <0x0 0xff442800 0x0 0x100>; 1089 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1091 clock-names = "aclk", "iface"; 1092 #iommu-cells = <0>; 1093 power-domains = <&power PX30_PD_VPU>; 1094 }; 1095 1096 dsi: dsi@ff450000 { 1097 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"; 1098 reg = <0x0 0xff450000 0x0 0x10000>; 1099 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&cru PCLK_MIPI_DSI>; 1101 clock-names = "pclk"; 1102 phys = <&dsi_dphy>; 1103 phy-names = "dphy"; 1104 power-domains = <&power PX30_PD_VO>; 1105 resets = <&cru SRST_MIPIDSI_HOST_P>; 1106 reset-names = "apb"; 1107 rockchip,grf = <&grf>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 1112 ports { 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 1116 port@0 { 1117 reg = <0>; 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 1121 dsi_in_vopb: endpoint@0 { 1122 reg = <0>; 1123 remote-endpoint = <&vopb_out_dsi>; 1124 }; 1125 1126 dsi_in_vopl: endpoint@1 { 1127 reg = <1>; 1128 remote-endpoint = <&vopl_out_dsi>; 1129 }; 1130 }; 1131 }; 1132 }; 1133 1134 vopb: vop@ff460000 { 1135 compatible = "rockchip,px30-vop-big"; 1136 reg = <0x0 0xff460000 0x0 0xefc>; 1137 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1139 <&cru HCLK_VOPB>; 1140 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1141 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1142 reset-names = "axi", "ahb", "dclk"; 1143 iommus = <&vopb_mmu>; 1144 power-domains = <&power PX30_PD_VO>; 1145 status = "disabled"; 1146 1147 vopb_out: port { 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 1151 vopb_out_dsi: endpoint@0 { 1152 reg = <0>; 1153 remote-endpoint = <&dsi_in_vopb>; 1154 }; 1155 1156 vopb_out_lvds: endpoint@1 { 1157 reg = <1>; 1158 remote-endpoint = <&lvds_vopb_in>; 1159 }; 1160 }; 1161 }; 1162 1163 vopb_mmu: iommu@ff460f00 { 1164 compatible = "rockchip,iommu"; 1165 reg = <0x0 0xff460f00 0x0 0x100>; 1166 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1167 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1168 clock-names = "aclk", "iface"; 1169 power-domains = <&power PX30_PD_VO>; 1170 #iommu-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 vopl: vop@ff470000 { 1175 compatible = "rockchip,px30-vop-lit"; 1176 reg = <0x0 0xff470000 0x0 0xefc>; 1177 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1178 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1179 <&cru HCLK_VOPL>; 1180 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1181 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1182 reset-names = "axi", "ahb", "dclk"; 1183 iommus = <&vopl_mmu>; 1184 power-domains = <&power PX30_PD_VO>; 1185 status = "disabled"; 1186 1187 vopl_out: port { 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 1191 vopl_out_dsi: endpoint@0 { 1192 reg = <0>; 1193 remote-endpoint = <&dsi_in_vopl>; 1194 }; 1195 1196 vopl_out_lvds: endpoint@1 { 1197 reg = <1>; 1198 remote-endpoint = <&lvds_vopl_in>; 1199 }; 1200 }; 1201 }; 1202 1203 vopl_mmu: iommu@ff470f00 { 1204 compatible = "rockchip,iommu"; 1205 reg = <0x0 0xff470f00 0x0 0x100>; 1206 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1208 clock-names = "aclk", "iface"; 1209 power-domains = <&power PX30_PD_VO>; 1210 #iommu-cells = <0>; 1211 status = "disabled"; 1212 }; 1213 1214 isp: isp@ff4a0000 { 1215 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/ 1216 reg = <0x0 0xff4a0000 0x0 0x8000>; 1217 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1220 interrupt-names = "isp", "mi", "mipi"; 1221 clocks = <&cru SCLK_ISP>, 1222 <&cru ACLK_ISP>, 1223 <&cru HCLK_ISP>, 1224 <&cru PCLK_ISP>; 1225 clock-names = "isp", "aclk", "hclk", "pclk"; 1226 iommus = <&isp_mmu>; 1227 phys = <&csi_dphy>; 1228 phy-names = "dphy"; 1229 power-domains = <&power PX30_PD_VI>; 1230 status = "disabled"; 1231 1232 ports { 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 1236 port@0 { 1237 reg = <0>; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 }; 1241 }; 1242 }; 1243 1244 isp_mmu: iommu@ff4a8000 { 1245 compatible = "rockchip,iommu"; 1246 reg = <0x0 0xff4a8000 0x0 0x100>; 1247 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1248 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1249 clock-names = "aclk", "iface"; 1250 power-domains = <&power PX30_PD_VI>; 1251 rockchip,disable-mmu-reset; 1252 #iommu-cells = <0>; 1253 }; 1254 1255 qos_gmac: qos@ff518000 { 1256 compatible = "rockchip,px30-qos", "syscon"; 1257 reg = <0x0 0xff518000 0x0 0x20>; 1258 }; 1259 1260 qos_gpu: qos@ff520000 { 1261 compatible = "rockchip,px30-qos", "syscon"; 1262 reg = <0x0 0xff520000 0x0 0x20>; 1263 }; 1264 1265 qos_sdmmc: qos@ff52c000 { 1266 compatible = "rockchip,px30-qos", "syscon"; 1267 reg = <0x0 0xff52c000 0x0 0x20>; 1268 }; 1269 1270 qos_emmc: qos@ff538000 { 1271 compatible = "rockchip,px30-qos", "syscon"; 1272 reg = <0x0 0xff538000 0x0 0x20>; 1273 }; 1274 1275 qos_nand: qos@ff538080 { 1276 compatible = "rockchip,px30-qos", "syscon"; 1277 reg = <0x0 0xff538080 0x0 0x20>; 1278 }; 1279 1280 qos_sdio: qos@ff538100 { 1281 compatible = "rockchip,px30-qos", "syscon"; 1282 reg = <0x0 0xff538100 0x0 0x20>; 1283 }; 1284 1285 qos_sfc: qos@ff538180 { 1286 compatible = "rockchip,px30-qos", "syscon"; 1287 reg = <0x0 0xff538180 0x0 0x20>; 1288 }; 1289 1290 qos_usb_host: qos@ff540000 { 1291 compatible = "rockchip,px30-qos", "syscon"; 1292 reg = <0x0 0xff540000 0x0 0x20>; 1293 }; 1294 1295 qos_usb_otg: qos@ff540080 { 1296 compatible = "rockchip,px30-qos", "syscon"; 1297 reg = <0x0 0xff540080 0x0 0x20>; 1298 }; 1299 1300 qos_isp_128: qos@ff548000 { 1301 compatible = "rockchip,px30-qos", "syscon"; 1302 reg = <0x0 0xff548000 0x0 0x20>; 1303 }; 1304 1305 qos_isp_rd: qos@ff548080 { 1306 compatible = "rockchip,px30-qos", "syscon"; 1307 reg = <0x0 0xff548080 0x0 0x20>; 1308 }; 1309 1310 qos_isp_wr: qos@ff548100 { 1311 compatible = "rockchip,px30-qos", "syscon"; 1312 reg = <0x0 0xff548100 0x0 0x20>; 1313 }; 1314 1315 qos_isp_m1: qos@ff548180 { 1316 compatible = "rockchip,px30-qos", "syscon"; 1317 reg = <0x0 0xff548180 0x0 0x20>; 1318 }; 1319 1320 qos_vip: qos@ff548200 { 1321 compatible = "rockchip,px30-qos", "syscon"; 1322 reg = <0x0 0xff548200 0x0 0x20>; 1323 }; 1324 1325 qos_rga_rd: qos@ff550000 { 1326 compatible = "rockchip,px30-qos", "syscon"; 1327 reg = <0x0 0xff550000 0x0 0x20>; 1328 }; 1329 1330 qos_rga_wr: qos@ff550080 { 1331 compatible = "rockchip,px30-qos", "syscon"; 1332 reg = <0x0 0xff550080 0x0 0x20>; 1333 }; 1334 1335 qos_vop_m0: qos@ff550100 { 1336 compatible = "rockchip,px30-qos", "syscon"; 1337 reg = <0x0 0xff550100 0x0 0x20>; 1338 }; 1339 1340 qos_vop_m1: qos@ff550180 { 1341 compatible = "rockchip,px30-qos", "syscon"; 1342 reg = <0x0 0xff550180 0x0 0x20>; 1343 }; 1344 1345 qos_vpu: qos@ff558000 { 1346 compatible = "rockchip,px30-qos", "syscon"; 1347 reg = <0x0 0xff558000 0x0 0x20>; 1348 }; 1349 1350 qos_vpu_r128: qos@ff558080 { 1351 compatible = "rockchip,px30-qos", "syscon"; 1352 reg = <0x0 0xff558080 0x0 0x20>; 1353 }; 1354 1355 pinctrl: pinctrl { 1356 compatible = "rockchip,px30-pinctrl"; 1357 rockchip,grf = <&grf>; 1358 rockchip,pmu = <&pmugrf>; 1359 #address-cells = <2>; 1360 #size-cells = <2>; 1361 ranges; 1362 1363 gpio0: gpio@ff040000 { 1364 compatible = "rockchip,gpio-bank"; 1365 reg = <0x0 0xff040000 0x0 0x100>; 1366 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1367 clocks = <&pmucru PCLK_GPIO0_PMU>; 1368 gpio-controller; 1369 #gpio-cells = <2>; 1370 1371 interrupt-controller; 1372 #interrupt-cells = <2>; 1373 }; 1374 1375 gpio1: gpio@ff250000 { 1376 compatible = "rockchip,gpio-bank"; 1377 reg = <0x0 0xff250000 0x0 0x100>; 1378 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1379 clocks = <&cru PCLK_GPIO1>; 1380 gpio-controller; 1381 #gpio-cells = <2>; 1382 1383 interrupt-controller; 1384 #interrupt-cells = <2>; 1385 }; 1386 1387 gpio2: gpio@ff260000 { 1388 compatible = "rockchip,gpio-bank"; 1389 reg = <0x0 0xff260000 0x0 0x100>; 1390 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1391 clocks = <&cru PCLK_GPIO2>; 1392 gpio-controller; 1393 #gpio-cells = <2>; 1394 1395 interrupt-controller; 1396 #interrupt-cells = <2>; 1397 }; 1398 1399 gpio3: gpio@ff270000 { 1400 compatible = "rockchip,gpio-bank"; 1401 reg = <0x0 0xff270000 0x0 0x100>; 1402 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1403 clocks = <&cru PCLK_GPIO3>; 1404 gpio-controller; 1405 #gpio-cells = <2>; 1406 1407 interrupt-controller; 1408 #interrupt-cells = <2>; 1409 }; 1410 1411 pcfg_pull_up: pcfg-pull-up { 1412 bias-pull-up; 1413 }; 1414 1415 pcfg_pull_down: pcfg-pull-down { 1416 bias-pull-down; 1417 }; 1418 1419 pcfg_pull_none: pcfg-pull-none { 1420 bias-disable; 1421 }; 1422 1423 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1424 bias-disable; 1425 drive-strength = <2>; 1426 }; 1427 1428 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1429 bias-pull-up; 1430 drive-strength = <2>; 1431 }; 1432 1433 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1434 bias-pull-up; 1435 drive-strength = <4>; 1436 }; 1437 1438 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1439 bias-disable; 1440 drive-strength = <4>; 1441 }; 1442 1443 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1444 bias-pull-down; 1445 drive-strength = <4>; 1446 }; 1447 1448 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1449 bias-disable; 1450 drive-strength = <8>; 1451 }; 1452 1453 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1454 bias-pull-up; 1455 drive-strength = <8>; 1456 }; 1457 1458 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1459 bias-disable; 1460 drive-strength = <12>; 1461 }; 1462 1463 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1464 bias-pull-up; 1465 drive-strength = <12>; 1466 }; 1467 1468 pcfg_pull_none_smt: pcfg-pull-none-smt { 1469 bias-disable; 1470 input-schmitt-enable; 1471 }; 1472 1473 pcfg_output_high: pcfg-output-high { 1474 output-high; 1475 }; 1476 1477 pcfg_output_low: pcfg-output-low { 1478 output-low; 1479 }; 1480 1481 pcfg_input_high: pcfg-input-high { 1482 bias-pull-up; 1483 input-enable; 1484 }; 1485 1486 pcfg_input: pcfg-input { 1487 input-enable; 1488 }; 1489 1490 i2c0 { 1491 i2c0_xfer: i2c0-xfer { 1492 rockchip,pins = 1493 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1494 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1495 }; 1496 }; 1497 1498 i2c1 { 1499 i2c1_xfer: i2c1-xfer { 1500 rockchip,pins = 1501 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1502 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1503 }; 1504 }; 1505 1506 i2c2 { 1507 i2c2_xfer: i2c2-xfer { 1508 rockchip,pins = 1509 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1510 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1511 }; 1512 }; 1513 1514 i2c3 { 1515 i2c3_xfer: i2c3-xfer { 1516 rockchip,pins = 1517 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1518 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1519 }; 1520 }; 1521 1522 tsadc { 1523 tsadc_otp_pin: tsadc-otp-pin { 1524 rockchip,pins = 1525 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1526 }; 1527 1528 tsadc_otp_out: tsadc-otp-out { 1529 rockchip,pins = 1530 <0 RK_PA6 1 &pcfg_pull_none>; 1531 }; 1532 }; 1533 1534 uart0 { 1535 uart0_xfer: uart0-xfer { 1536 rockchip,pins = 1537 <0 RK_PB2 1 &pcfg_pull_up>, 1538 <0 RK_PB3 1 &pcfg_pull_up>; 1539 }; 1540 1541 uart0_cts: uart0-cts { 1542 rockchip,pins = 1543 <0 RK_PB4 1 &pcfg_pull_none>; 1544 }; 1545 1546 uart0_rts: uart0-rts { 1547 rockchip,pins = 1548 <0 RK_PB5 1 &pcfg_pull_none>; 1549 }; 1550 }; 1551 1552 uart1 { 1553 uart1_xfer: uart1-xfer { 1554 rockchip,pins = 1555 <1 RK_PC1 1 &pcfg_pull_up>, 1556 <1 RK_PC0 1 &pcfg_pull_up>; 1557 }; 1558 1559 uart1_cts: uart1-cts { 1560 rockchip,pins = 1561 <1 RK_PC2 1 &pcfg_pull_none>; 1562 }; 1563 1564 uart1_rts: uart1-rts { 1565 rockchip,pins = 1566 <1 RK_PC3 1 &pcfg_pull_none>; 1567 }; 1568 }; 1569 1570 uart2-m0 { 1571 uart2m0_xfer: uart2m0-xfer { 1572 rockchip,pins = 1573 <1 RK_PD2 2 &pcfg_pull_up>, 1574 <1 RK_PD3 2 &pcfg_pull_up>; 1575 }; 1576 }; 1577 1578 uart2-m1 { 1579 uart2m1_xfer: uart2m1-xfer { 1580 rockchip,pins = 1581 <2 RK_PB4 2 &pcfg_pull_up>, 1582 <2 RK_PB6 2 &pcfg_pull_up>; 1583 }; 1584 }; 1585 1586 uart3-m0 { 1587 uart3m0_xfer: uart3m0-xfer { 1588 rockchip,pins = 1589 <0 RK_PC0 2 &pcfg_pull_up>, 1590 <0 RK_PC1 2 &pcfg_pull_up>; 1591 }; 1592 1593 uart3m0_cts: uart3m0-cts { 1594 rockchip,pins = 1595 <0 RK_PC2 2 &pcfg_pull_none>; 1596 }; 1597 1598 uart3m0_rts: uart3m0-rts { 1599 rockchip,pins = 1600 <0 RK_PC3 2 &pcfg_pull_none>; 1601 }; 1602 }; 1603 1604 uart3-m1 { 1605 uart3m1_xfer: uart3m1-xfer { 1606 rockchip,pins = 1607 <1 RK_PB6 2 &pcfg_pull_up>, 1608 <1 RK_PB7 2 &pcfg_pull_up>; 1609 }; 1610 1611 uart3m1_cts: uart3m1-cts { 1612 rockchip,pins = 1613 <1 RK_PB4 2 &pcfg_pull_none>; 1614 }; 1615 1616 uart3m1_rts: uart3m1-rts { 1617 rockchip,pins = 1618 <1 RK_PB5 2 &pcfg_pull_none>; 1619 }; 1620 }; 1621 1622 uart4 { 1623 uart4_xfer: uart4-xfer { 1624 rockchip,pins = 1625 <1 RK_PD4 2 &pcfg_pull_up>, 1626 <1 RK_PD5 2 &pcfg_pull_up>; 1627 }; 1628 1629 uart4_cts: uart4-cts { 1630 rockchip,pins = 1631 <1 RK_PD6 2 &pcfg_pull_none>; 1632 }; 1633 1634 uart4_rts: uart4-rts { 1635 rockchip,pins = 1636 <1 RK_PD7 2 &pcfg_pull_none>; 1637 }; 1638 }; 1639 1640 uart5 { 1641 uart5_xfer: uart5-xfer { 1642 rockchip,pins = 1643 <3 RK_PA2 4 &pcfg_pull_up>, 1644 <3 RK_PA1 4 &pcfg_pull_up>; 1645 }; 1646 1647 uart5_cts: uart5-cts { 1648 rockchip,pins = 1649 <3 RK_PA3 4 &pcfg_pull_none>; 1650 }; 1651 1652 uart5_rts: uart5-rts { 1653 rockchip,pins = 1654 <3 RK_PA5 4 &pcfg_pull_none>; 1655 }; 1656 }; 1657 1658 spi0 { 1659 spi0_clk: spi0-clk { 1660 rockchip,pins = 1661 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1662 }; 1663 1664 spi0_csn: spi0-csn { 1665 rockchip,pins = 1666 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1667 }; 1668 1669 spi0_miso: spi0-miso { 1670 rockchip,pins = 1671 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1672 }; 1673 1674 spi0_mosi: spi0-mosi { 1675 rockchip,pins = 1676 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1677 }; 1678 1679 spi0_clk_hs: spi0-clk-hs { 1680 rockchip,pins = 1681 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1682 }; 1683 1684 spi0_miso_hs: spi0-miso-hs { 1685 rockchip,pins = 1686 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1687 }; 1688 1689 spi0_mosi_hs: spi0-mosi-hs { 1690 rockchip,pins = 1691 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1692 }; 1693 }; 1694 1695 spi1 { 1696 spi1_clk: spi1-clk { 1697 rockchip,pins = 1698 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1699 }; 1700 1701 spi1_csn0: spi1-csn0 { 1702 rockchip,pins = 1703 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1704 }; 1705 1706 spi1_csn1: spi1-csn1 { 1707 rockchip,pins = 1708 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1709 }; 1710 1711 spi1_miso: spi1-miso { 1712 rockchip,pins = 1713 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1714 }; 1715 1716 spi1_mosi: spi1-mosi { 1717 rockchip,pins = 1718 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1719 }; 1720 1721 spi1_clk_hs: spi1-clk-hs { 1722 rockchip,pins = 1723 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1724 }; 1725 1726 spi1_miso_hs: spi1-miso-hs { 1727 rockchip,pins = 1728 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1729 }; 1730 1731 spi1_mosi_hs: spi1-mosi-hs { 1732 rockchip,pins = 1733 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1734 }; 1735 }; 1736 1737 pdm { 1738 pdm_clk0m0: pdm-clk0m0 { 1739 rockchip,pins = 1740 <3 RK_PC6 2 &pcfg_pull_none>; 1741 }; 1742 1743 pdm_clk0m1: pdm-clk0m1 { 1744 rockchip,pins = 1745 <2 RK_PC6 1 &pcfg_pull_none>; 1746 }; 1747 1748 pdm_clk1: pdm-clk1 { 1749 rockchip,pins = 1750 <3 RK_PC7 2 &pcfg_pull_none>; 1751 }; 1752 1753 pdm_sdi0m0: pdm-sdi0m0 { 1754 rockchip,pins = 1755 <3 RK_PD3 2 &pcfg_pull_none>; 1756 }; 1757 1758 pdm_sdi0m1: pdm-sdi0m1 { 1759 rockchip,pins = 1760 <2 RK_PC5 2 &pcfg_pull_none>; 1761 }; 1762 1763 pdm_sdi1: pdm-sdi1 { 1764 rockchip,pins = 1765 <3 RK_PD0 2 &pcfg_pull_none>; 1766 }; 1767 1768 pdm_sdi2: pdm-sdi2 { 1769 rockchip,pins = 1770 <3 RK_PD1 2 &pcfg_pull_none>; 1771 }; 1772 1773 pdm_sdi3: pdm-sdi3 { 1774 rockchip,pins = 1775 <3 RK_PD2 2 &pcfg_pull_none>; 1776 }; 1777 1778 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1779 rockchip,pins = 1780 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1781 }; 1782 1783 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1784 rockchip,pins = 1785 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1786 }; 1787 1788 pdm_clk1_sleep: pdm-clk1-sleep { 1789 rockchip,pins = 1790 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1791 }; 1792 1793 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1794 rockchip,pins = 1795 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1796 }; 1797 1798 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1799 rockchip,pins = 1800 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1801 }; 1802 1803 pdm_sdi1_sleep: pdm-sdi1-sleep { 1804 rockchip,pins = 1805 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1806 }; 1807 1808 pdm_sdi2_sleep: pdm-sdi2-sleep { 1809 rockchip,pins = 1810 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1811 }; 1812 1813 pdm_sdi3_sleep: pdm-sdi3-sleep { 1814 rockchip,pins = 1815 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1816 }; 1817 }; 1818 1819 i2s0 { 1820 i2s0_8ch_mclk: i2s0-8ch-mclk { 1821 rockchip,pins = 1822 <3 RK_PC1 2 &pcfg_pull_none>; 1823 }; 1824 1825 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1826 rockchip,pins = 1827 <3 RK_PC3 2 &pcfg_pull_none>; 1828 }; 1829 1830 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1831 rockchip,pins = 1832 <3 RK_PB4 2 &pcfg_pull_none>; 1833 }; 1834 1835 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1836 rockchip,pins = 1837 <3 RK_PC2 2 &pcfg_pull_none>; 1838 }; 1839 1840 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1841 rockchip,pins = 1842 <3 RK_PB5 2 &pcfg_pull_none>; 1843 }; 1844 1845 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1846 rockchip,pins = 1847 <3 RK_PC4 2 &pcfg_pull_none>; 1848 }; 1849 1850 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1851 rockchip,pins = 1852 <3 RK_PC0 2 &pcfg_pull_none>; 1853 }; 1854 1855 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1856 rockchip,pins = 1857 <3 RK_PB7 2 &pcfg_pull_none>; 1858 }; 1859 1860 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1861 rockchip,pins = 1862 <3 RK_PB6 2 &pcfg_pull_none>; 1863 }; 1864 1865 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1866 rockchip,pins = 1867 <3 RK_PC5 2 &pcfg_pull_none>; 1868 }; 1869 1870 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1871 rockchip,pins = 1872 <3 RK_PB3 2 &pcfg_pull_none>; 1873 }; 1874 1875 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1876 rockchip,pins = 1877 <3 RK_PB1 2 &pcfg_pull_none>; 1878 }; 1879 1880 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1881 rockchip,pins = 1882 <3 RK_PB0 2 &pcfg_pull_none>; 1883 }; 1884 }; 1885 1886 i2s1 { 1887 i2s1_2ch_mclk: i2s1-2ch-mclk { 1888 rockchip,pins = 1889 <2 RK_PC3 1 &pcfg_pull_none>; 1890 }; 1891 1892 i2s1_2ch_sclk: i2s1-2ch-sclk { 1893 rockchip,pins = 1894 <2 RK_PC2 1 &pcfg_pull_none>; 1895 }; 1896 1897 i2s1_2ch_lrck: i2s1-2ch-lrck { 1898 rockchip,pins = 1899 <2 RK_PC1 1 &pcfg_pull_none>; 1900 }; 1901 1902 i2s1_2ch_sdi: i2s1-2ch-sdi { 1903 rockchip,pins = 1904 <2 RK_PC5 1 &pcfg_pull_none>; 1905 }; 1906 1907 i2s1_2ch_sdo: i2s1-2ch-sdo { 1908 rockchip,pins = 1909 <2 RK_PC4 1 &pcfg_pull_none>; 1910 }; 1911 }; 1912 1913 i2s2 { 1914 i2s2_2ch_mclk: i2s2-2ch-mclk { 1915 rockchip,pins = 1916 <3 RK_PA1 2 &pcfg_pull_none>; 1917 }; 1918 1919 i2s2_2ch_sclk: i2s2-2ch-sclk { 1920 rockchip,pins = 1921 <3 RK_PA2 2 &pcfg_pull_none>; 1922 }; 1923 1924 i2s2_2ch_lrck: i2s2-2ch-lrck { 1925 rockchip,pins = 1926 <3 RK_PA3 2 &pcfg_pull_none>; 1927 }; 1928 1929 i2s2_2ch_sdi: i2s2-2ch-sdi { 1930 rockchip,pins = 1931 <3 RK_PA5 2 &pcfg_pull_none>; 1932 }; 1933 1934 i2s2_2ch_sdo: i2s2-2ch-sdo { 1935 rockchip,pins = 1936 <3 RK_PA7 2 &pcfg_pull_none>; 1937 }; 1938 }; 1939 1940 sdmmc { 1941 sdmmc_clk: sdmmc-clk { 1942 rockchip,pins = 1943 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1944 }; 1945 1946 sdmmc_cmd: sdmmc-cmd { 1947 rockchip,pins = 1948 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1949 }; 1950 1951 sdmmc_det: sdmmc-det { 1952 rockchip,pins = 1953 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1954 }; 1955 1956 sdmmc_bus1: sdmmc-bus1 { 1957 rockchip,pins = 1958 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1959 }; 1960 1961 sdmmc_bus4: sdmmc-bus4 { 1962 rockchip,pins = 1963 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1964 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1965 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1966 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1967 }; 1968 }; 1969 1970 sdio { 1971 sdio_clk: sdio-clk { 1972 rockchip,pins = 1973 <1 RK_PC5 1 &pcfg_pull_none>; 1974 }; 1975 1976 sdio_cmd: sdio-cmd { 1977 rockchip,pins = 1978 <1 RK_PC4 1 &pcfg_pull_up>; 1979 }; 1980 1981 sdio_bus4: sdio-bus4 { 1982 rockchip,pins = 1983 <1 RK_PC6 1 &pcfg_pull_up>, 1984 <1 RK_PC7 1 &pcfg_pull_up>, 1985 <1 RK_PD0 1 &pcfg_pull_up>, 1986 <1 RK_PD1 1 &pcfg_pull_up>; 1987 }; 1988 }; 1989 1990 emmc { 1991 emmc_clk: emmc-clk { 1992 rockchip,pins = 1993 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 1994 }; 1995 1996 emmc_cmd: emmc-cmd { 1997 rockchip,pins = 1998 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 1999 }; 2000 2001 emmc_rstnout: emmc-rstnout { 2002 rockchip,pins = 2003 <1 RK_PB3 2 &pcfg_pull_none>; 2004 }; 2005 2006 emmc_bus1: emmc-bus1 { 2007 rockchip,pins = 2008 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 2009 }; 2010 2011 emmc_bus4: emmc-bus4 { 2012 rockchip,pins = 2013 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 2014 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 2015 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 2016 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 2017 }; 2018 2019 emmc_bus8: emmc-bus8 { 2020 rockchip,pins = 2021 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 2022 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 2023 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 2024 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 2025 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 2026 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 2027 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 2028 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 2029 }; 2030 }; 2031 2032 flash { 2033 flash_cs0: flash-cs0 { 2034 rockchip,pins = 2035 <1 RK_PB0 1 &pcfg_pull_none>; 2036 }; 2037 2038 flash_rdy: flash-rdy { 2039 rockchip,pins = 2040 <1 RK_PB1 1 &pcfg_pull_none>; 2041 }; 2042 2043 flash_dqs: flash-dqs { 2044 rockchip,pins = 2045 <1 RK_PB2 1 &pcfg_pull_none>; 2046 }; 2047 2048 flash_ale: flash-ale { 2049 rockchip,pins = 2050 <1 RK_PB3 1 &pcfg_pull_none>; 2051 }; 2052 2053 flash_cle: flash-cle { 2054 rockchip,pins = 2055 <1 RK_PB4 1 &pcfg_pull_none>; 2056 }; 2057 2058 flash_wrn: flash-wrn { 2059 rockchip,pins = 2060 <1 RK_PB5 1 &pcfg_pull_none>; 2061 }; 2062 2063 flash_csl: flash-csl { 2064 rockchip,pins = 2065 <1 RK_PB6 1 &pcfg_pull_none>; 2066 }; 2067 2068 flash_rdn: flash-rdn { 2069 rockchip,pins = 2070 <1 RK_PB7 1 &pcfg_pull_none>; 2071 }; 2072 2073 flash_bus8: flash-bus8 { 2074 rockchip,pins = 2075 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 2076 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 2077 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 2078 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 2079 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 2080 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 2081 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 2082 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 2083 }; 2084 }; 2085 2086 sfc { 2087 sfc_bus4: sfc-bus4 { 2088 rockchip,pins = 2089 <1 RK_PA0 3 &pcfg_pull_none>, 2090 <1 RK_PA1 3 &pcfg_pull_none>, 2091 <1 RK_PA2 3 &pcfg_pull_none>, 2092 <1 RK_PA3 3 &pcfg_pull_none>; 2093 }; 2094 2095 sfc_bus2: sfc-bus2 { 2096 rockchip,pins = 2097 <1 RK_PA0 3 &pcfg_pull_none>, 2098 <1 RK_PA1 3 &pcfg_pull_none>; 2099 }; 2100 2101 sfc_cs0: sfc-cs0 { 2102 rockchip,pins = 2103 <1 RK_PA4 3 &pcfg_pull_none>; 2104 }; 2105 2106 sfc_clk: sfc-clk { 2107 rockchip,pins = 2108 <1 RK_PB1 3 &pcfg_pull_none>; 2109 }; 2110 }; 2111 2112 lcdc { 2113 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 2114 rockchip,pins = 2115 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 2116 }; 2117 2118 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 2119 rockchip,pins = 2120 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 2121 }; 2122 2123 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 2124 rockchip,pins = 2125 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 2126 }; 2127 2128 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 2129 rockchip,pins = 2130 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 2131 }; 2132 2133 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 2134 rockchip,pins = 2135 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2136 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2137 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2138 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2139 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2140 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2141 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2142 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2143 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2144 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2145 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2146 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2147 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2148 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2149 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2150 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2151 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2152 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2153 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2154 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2155 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2156 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2157 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2158 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2159 }; 2160 2161 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 2162 rockchip,pins = 2163 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2164 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2165 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2166 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2167 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2168 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2169 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2170 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2171 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2172 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2173 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2174 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2175 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2176 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2177 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2178 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2179 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2180 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2181 }; 2182 2183 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2184 rockchip,pins = 2185 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2186 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2187 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2188 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2189 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2190 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2191 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2192 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2193 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2194 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2195 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2196 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2197 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2198 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2199 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2200 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2201 }; 2202 2203 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2204 rockchip,pins = 2205 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2206 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2207 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2208 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2209 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2210 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2211 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2212 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2213 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2214 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2215 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2216 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2217 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2218 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2219 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2220 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2221 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2222 }; 2223 2224 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2225 rockchip,pins = 2226 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2227 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2228 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2229 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2230 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2231 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2232 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2233 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2234 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2235 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2236 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2237 }; 2238 2239 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2240 rockchip,pins = 2241 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2242 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2243 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2244 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2245 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2246 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2247 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2248 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2249 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2250 }; 2251 }; 2252 2253 pwm0 { 2254 pwm0_pin: pwm0-pin { 2255 rockchip,pins = 2256 <0 RK_PB7 1 &pcfg_pull_none>; 2257 }; 2258 }; 2259 2260 pwm1 { 2261 pwm1_pin: pwm1-pin { 2262 rockchip,pins = 2263 <0 RK_PC0 1 &pcfg_pull_none>; 2264 }; 2265 }; 2266 2267 pwm2 { 2268 pwm2_pin: pwm2-pin { 2269 rockchip,pins = 2270 <2 RK_PB5 1 &pcfg_pull_none>; 2271 }; 2272 }; 2273 2274 pwm3 { 2275 pwm3_pin: pwm3-pin { 2276 rockchip,pins = 2277 <0 RK_PC1 1 &pcfg_pull_none>; 2278 }; 2279 }; 2280 2281 pwm4 { 2282 pwm4_pin: pwm4-pin { 2283 rockchip,pins = 2284 <3 RK_PC2 3 &pcfg_pull_none>; 2285 }; 2286 }; 2287 2288 pwm5 { 2289 pwm5_pin: pwm5-pin { 2290 rockchip,pins = 2291 <3 RK_PC3 3 &pcfg_pull_none>; 2292 }; 2293 }; 2294 2295 pwm6 { 2296 pwm6_pin: pwm6-pin { 2297 rockchip,pins = 2298 <3 RK_PC4 3 &pcfg_pull_none>; 2299 }; 2300 }; 2301 2302 pwm7 { 2303 pwm7_pin: pwm7-pin { 2304 rockchip,pins = 2305 <3 RK_PC5 3 &pcfg_pull_none>; 2306 }; 2307 }; 2308 2309 gmac { 2310 rmii_pins: rmii-pins { 2311 rockchip,pins = 2312 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 2313 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 2314 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 2315 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 2316 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 2317 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 2318 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 2319 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 2320 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 2321 }; 2322 2323 mac_refclk_12ma: mac-refclk-12ma { 2324 rockchip,pins = 2325 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 2326 }; 2327 2328 mac_refclk: mac-refclk { 2329 rockchip,pins = 2330 <2 RK_PB2 2 &pcfg_pull_none>; 2331 }; 2332 }; 2333 2334 cif-m0 { 2335 cif_clkout_m0: cif-clkout-m0 { 2336 rockchip,pins = 2337 <2 RK_PB3 1 &pcfg_pull_none>; 2338 }; 2339 2340 dvp_d2d9_m0: dvp-d2d9-m0 { 2341 rockchip,pins = 2342 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 2343 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 2344 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 2345 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 2346 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 2347 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 2348 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 2349 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 2350 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 2351 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 2352 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 2353 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 2354 }; 2355 2356 dvp_d0d1_m0: dvp-d0d1-m0 { 2357 rockchip,pins = 2358 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 2359 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 2360 }; 2361 2362 dvp_d10d11_m0:d10-d11-m0 { 2363 rockchip,pins = 2364 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 2365 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 2366 }; 2367 }; 2368 2369 cif-m1 { 2370 cif_clkout_m1: cif-clkout-m1 { 2371 rockchip,pins = 2372 <3 RK_PD0 3 &pcfg_pull_none>; 2373 }; 2374 2375 dvp_d2d9_m1: dvp-d2d9-m1 { 2376 rockchip,pins = 2377 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 2378 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 2379 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 2380 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 2381 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 2382 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 2383 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 2384 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 2385 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 2386 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 2387 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 2388 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 2389 }; 2390 2391 dvp_d0d1_m1: dvp-d0d1-m1 { 2392 rockchip,pins = 2393 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 2394 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 2395 }; 2396 2397 dvp_d10d11_m1:d10-d11-m1 { 2398 rockchip,pins = 2399 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 2400 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 2401 }; 2402 }; 2403 2404 isp { 2405 isp_prelight: isp-prelight { 2406 rockchip,pins = 2407 <3 RK_PD1 4 &pcfg_pull_none>; 2408 }; 2409 }; 2410 }; 2411}; 2412