1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 serial3 = &uart3; 32 serial4 = &uart4; 33 serial5 = &uart5; 34 spi0 = &spi0; 35 spi1 = &spi1; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a35"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 clocks = <&cru ARMCLK>; 48 #cooling-cells = <2>; 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 50 dynamic-power-coefficient = <90>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 #cooling-cells = <2>; 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 62 dynamic-power-coefficient = <90>; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 clocks = <&cru ARMCLK>; 72 #cooling-cells = <2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 74 dynamic-power-coefficient = <90>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 }; 77 78 cpu3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a35"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 #cooling-cells = <2>; 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 86 dynamic-power-coefficient = <90>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 102 CLUSTER_SLEEP: cluster-sleep { 103 compatible = "arm,idle-state"; 104 local-timer-stop; 105 arm,psci-suspend-param = <0x1010000>; 106 entry-latency-us = <400>; 107 exit-latency-us = <500>; 108 min-residency-us = <2000>; 109 }; 110 }; 111 }; 112 113 cpu0_opp_table: cpu0-opp-table { 114 compatible = "operating-points-v2"; 115 opp-shared; 116 117 opp-600000000 { 118 opp-hz = /bits/ 64 <600000000>; 119 opp-microvolt = <950000 950000 1350000>; 120 clock-latency-ns = <40000>; 121 opp-suspend; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1050000 1050000 1350000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1175000 1175000 1350000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1300000 1300000 1350000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1350000 1350000 1350000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vopb_out>, <&vopl_out>; 157 status = "disabled"; 158 }; 159 160 gmac_clkin: external-gmac-clock { 161 compatible = "fixed-clock"; 162 clock-frequency = <50000000>; 163 clock-output-names = "gmac_clkin"; 164 #clock-cells = <0>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 178 }; 179 180 thermal_zones: thermal-zones { 181 soc_thermal: soc-thermal { 182 polling-delay-passive = <20>; 183 polling-delay = <1000>; 184 sustainable-power = <750>; 185 thermal-sensors = <&tsadc 0>; 186 187 trips { 188 threshold: trip-point-0 { 189 temperature = <70000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 target: trip-point-1 { 195 temperature = <85000>; 196 hysteresis = <2000>; 197 type = "passive"; 198 }; 199 200 soc_crit: soc-crit { 201 temperature = <115000>; 202 hysteresis = <2000>; 203 type = "critical"; 204 }; 205 }; 206 207 cooling-maps { 208 map0 { 209 trip = <&target>; 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211 contribution = <4096>; 212 }; 213 214 map1 { 215 trip = <&target>; 216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 217 contribution = <4096>; 218 }; 219 }; 220 }; 221 222 gpu_thermal: gpu-thermal { 223 polling-delay-passive = <100>; /* milliseconds */ 224 polling-delay = <1000>; /* milliseconds */ 225 thermal-sensors = <&tsadc 1>; 226 }; 227 }; 228 229 xin24m: xin24m { 230 compatible = "fixed-clock"; 231 #clock-cells = <0>; 232 clock-frequency = <24000000>; 233 clock-output-names = "xin24m"; 234 }; 235 236 pmu: power-management@ff000000 { 237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 238 reg = <0x0 0xff000000 0x0 0x1000>; 239 240 power: power-controller { 241 compatible = "rockchip,px30-power-controller"; 242 #power-domain-cells = <1>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 /* These power domains are grouped by VD_LOGIC */ 247 pd_usb@PX30_PD_USB { 248 reg = <PX30_PD_USB>; 249 clocks = <&cru HCLK_HOST>, 250 <&cru HCLK_OTG>, 251 <&cru SCLK_OTG_ADP>; 252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 253 }; 254 pd_sdcard@PX30_PD_SDCARD { 255 reg = <PX30_PD_SDCARD>; 256 clocks = <&cru HCLK_SDMMC>, 257 <&cru SCLK_SDMMC>; 258 pm_qos = <&qos_sdmmc>; 259 }; 260 pd_gmac@PX30_PD_GMAC { 261 reg = <PX30_PD_GMAC>; 262 clocks = <&cru ACLK_GMAC>, 263 <&cru PCLK_GMAC>, 264 <&cru SCLK_MAC_REF>, 265 <&cru SCLK_GMAC_RX_TX>; 266 pm_qos = <&qos_gmac>; 267 }; 268 pd_mmc_nand@PX30_PD_MMC_NAND { 269 reg = <PX30_PD_MMC_NAND>; 270 clocks = <&cru HCLK_NANDC>, 271 <&cru HCLK_EMMC>, 272 <&cru HCLK_SDIO>, 273 <&cru HCLK_SFC>, 274 <&cru SCLK_EMMC>, 275 <&cru SCLK_NANDC>, 276 <&cru SCLK_SDIO>, 277 <&cru SCLK_SFC>; 278 pm_qos = <&qos_emmc>, <&qos_nand>, 279 <&qos_sdio>, <&qos_sfc>; 280 }; 281 pd_vpu@PX30_PD_VPU { 282 reg = <PX30_PD_VPU>; 283 clocks = <&cru ACLK_VPU>, 284 <&cru HCLK_VPU>, 285 <&cru SCLK_CORE_VPU>; 286 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 287 }; 288 pd_vo@PX30_PD_VO { 289 reg = <PX30_PD_VO>; 290 clocks = <&cru ACLK_RGA>, 291 <&cru ACLK_VOPB>, 292 <&cru ACLK_VOPL>, 293 <&cru DCLK_VOPB>, 294 <&cru DCLK_VOPL>, 295 <&cru HCLK_RGA>, 296 <&cru HCLK_VOPB>, 297 <&cru HCLK_VOPL>, 298 <&cru PCLK_MIPI_DSI>, 299 <&cru SCLK_RGA_CORE>, 300 <&cru SCLK_VOPB_PWM>; 301 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 302 <&qos_vop_m0>, <&qos_vop_m1>; 303 }; 304 pd_vi@PX30_PD_VI { 305 reg = <PX30_PD_VI>; 306 clocks = <&cru ACLK_CIF>, 307 <&cru ACLK_ISP>, 308 <&cru HCLK_CIF>, 309 <&cru HCLK_ISP>, 310 <&cru SCLK_ISP>; 311 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 312 <&qos_isp_wr>, <&qos_isp_m1>, 313 <&qos_vip>; 314 }; 315 pd_gpu@PX30_PD_GPU { 316 reg = <PX30_PD_GPU>; 317 clocks = <&cru SCLK_GPU>; 318 pm_qos = <&qos_gpu>; 319 }; 320 }; 321 }; 322 323 pmugrf: syscon@ff010000 { 324 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 325 reg = <0x0 0xff010000 0x0 0x1000>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 329 pmu_io_domains: io-domains { 330 compatible = "rockchip,px30-pmu-io-voltage-domain"; 331 status = "disabled"; 332 }; 333 334 reboot-mode { 335 compatible = "syscon-reboot-mode"; 336 offset = <0x200>; 337 mode-bootloader = <BOOT_BL_DOWNLOAD>; 338 mode-fastboot = <BOOT_FASTBOOT>; 339 mode-loader = <BOOT_BL_DOWNLOAD>; 340 mode-normal = <BOOT_NORMAL>; 341 mode-recovery = <BOOT_RECOVERY>; 342 }; 343 }; 344 345 uart0: serial@ff030000 { 346 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 347 reg = <0x0 0xff030000 0x0 0x100>; 348 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 350 clock-names = "baudclk", "apb_pclk"; 351 dmas = <&dmac 0>, <&dmac 1>; 352 dma-names = "tx", "rx"; 353 reg-shift = <2>; 354 reg-io-width = <4>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 357 status = "disabled"; 358 }; 359 360 i2s1_2ch: i2s@ff070000 { 361 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 362 reg = <0x0 0xff070000 0x0 0x1000>; 363 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 365 clock-names = "i2s_clk", "i2s_hclk"; 366 dmas = <&dmac 18>, <&dmac 19>; 367 dma-names = "tx", "rx"; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 370 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 371 #sound-dai-cells = <0>; 372 status = "disabled"; 373 }; 374 375 i2s2_2ch: i2s@ff080000 { 376 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 377 reg = <0x0 0xff080000 0x0 0x1000>; 378 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 380 clock-names = "i2s_clk", "i2s_hclk"; 381 dmas = <&dmac 20>, <&dmac 21>; 382 dma-names = "tx", "rx"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 385 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 386 #sound-dai-cells = <0>; 387 status = "disabled"; 388 }; 389 390 gic: interrupt-controller@ff131000 { 391 compatible = "arm,gic-400"; 392 #interrupt-cells = <3>; 393 #address-cells = <0>; 394 interrupt-controller; 395 reg = <0x0 0xff131000 0 0x1000>, 396 <0x0 0xff132000 0 0x2000>, 397 <0x0 0xff134000 0 0x2000>, 398 <0x0 0xff136000 0 0x2000>; 399 interrupts = <GIC_PPI 9 400 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 401 }; 402 403 grf: syscon@ff140000 { 404 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 405 reg = <0x0 0xff140000 0x0 0x1000>; 406 #address-cells = <1>; 407 #size-cells = <1>; 408 409 io_domains: io-domains { 410 compatible = "rockchip,px30-io-voltage-domain"; 411 status = "disabled"; 412 }; 413 414 lvds: lvds { 415 compatible = "rockchip,px30-lvds"; 416 phys = <&dsi_dphy>; 417 phy-names = "dphy"; 418 rockchip,grf = <&grf>; 419 rockchip,output = "lvds"; 420 status = "disabled"; 421 422 ports { 423 #address-cells = <1>; 424 #size-cells = <0>; 425 426 port@0 { 427 reg = <0>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 431 lvds_vopb_in: endpoint@0 { 432 reg = <0>; 433 remote-endpoint = <&vopb_out_lvds>; 434 }; 435 436 lvds_vopl_in: endpoint@1 { 437 reg = <1>; 438 remote-endpoint = <&vopl_out_lvds>; 439 }; 440 }; 441 }; 442 }; 443 }; 444 445 uart1: serial@ff158000 { 446 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 447 reg = <0x0 0xff158000 0x0 0x100>; 448 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 450 clock-names = "baudclk", "apb_pclk"; 451 dmas = <&dmac 2>, <&dmac 3>; 452 dma-names = "tx", "rx"; 453 reg-shift = <2>; 454 reg-io-width = <4>; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 457 status = "disabled"; 458 }; 459 460 uart2: serial@ff160000 { 461 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 462 reg = <0x0 0xff160000 0x0 0x100>; 463 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 465 clock-names = "baudclk", "apb_pclk"; 466 dmas = <&dmac 4>, <&dmac 5>; 467 dma-names = "tx", "rx"; 468 reg-shift = <2>; 469 reg-io-width = <4>; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&uart2m0_xfer>; 472 status = "disabled"; 473 }; 474 475 uart3: serial@ff168000 { 476 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 477 reg = <0x0 0xff168000 0x0 0x100>; 478 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 480 clock-names = "baudclk", "apb_pclk"; 481 dmas = <&dmac 6>, <&dmac 7>; 482 dma-names = "tx", "rx"; 483 reg-shift = <2>; 484 reg-io-width = <4>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 487 status = "disabled"; 488 }; 489 490 uart4: serial@ff170000 { 491 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 492 reg = <0x0 0xff170000 0x0 0x100>; 493 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 495 clock-names = "baudclk", "apb_pclk"; 496 dmas = <&dmac 8>, <&dmac 9>; 497 dma-names = "tx", "rx"; 498 reg-shift = <2>; 499 reg-io-width = <4>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 502 status = "disabled"; 503 }; 504 505 uart5: serial@ff178000 { 506 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 507 reg = <0x0 0xff178000 0x0 0x100>; 508 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 510 clock-names = "baudclk", "apb_pclk"; 511 dmas = <&dmac 10>, <&dmac 11>; 512 dma-names = "tx", "rx"; 513 reg-shift = <2>; 514 reg-io-width = <4>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 517 status = "disabled"; 518 }; 519 520 i2c0: i2c@ff180000 { 521 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 522 reg = <0x0 0xff180000 0x0 0x1000>; 523 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 524 clock-names = "i2c", "pclk"; 525 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&i2c0_xfer>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 status = "disabled"; 531 }; 532 533 i2c1: i2c@ff190000 { 534 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 535 reg = <0x0 0xff190000 0x0 0x1000>; 536 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 537 clock-names = "i2c", "pclk"; 538 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&i2c1_xfer>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 546 i2c2: i2c@ff1a0000 { 547 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 548 reg = <0x0 0xff1a0000 0x0 0x1000>; 549 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 550 clock-names = "i2c", "pclk"; 551 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&i2c2_xfer>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "disabled"; 557 }; 558 559 i2c3: i2c@ff1b0000 { 560 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 561 reg = <0x0 0xff1b0000 0x0 0x1000>; 562 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 563 clock-names = "i2c", "pclk"; 564 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&i2c3_xfer>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 spi0: spi@ff1d0000 { 573 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 574 reg = <0x0 0xff1d0000 0x0 0x1000>; 575 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 577 clock-names = "spiclk", "apb_pclk"; 578 dmas = <&dmac 12>, <&dmac 13>; 579 dma-names = "tx", "rx"; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 status = "disabled"; 585 }; 586 587 spi1: spi@ff1d8000 { 588 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 589 reg = <0x0 0xff1d8000 0x0 0x1000>; 590 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 592 clock-names = "spiclk", "apb_pclk"; 593 dmas = <&dmac 14>, <&dmac 15>; 594 dma-names = "tx", "rx"; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 }; 601 602 wdt: watchdog@ff1e0000 { 603 compatible = "snps,dw-wdt"; 604 reg = <0x0 0xff1e0000 0x0 0x100>; 605 clocks = <&cru PCLK_WDT_NS>; 606 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 607 status = "disabled"; 608 }; 609 610 pwm0: pwm@ff200000 { 611 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 612 reg = <0x0 0xff200000 0x0 0x10>; 613 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 614 clock-names = "pwm", "pclk"; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&pwm0_pin>; 617 #pwm-cells = <3>; 618 status = "disabled"; 619 }; 620 621 pwm1: pwm@ff200010 { 622 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 623 reg = <0x0 0xff200010 0x0 0x10>; 624 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 625 clock-names = "pwm", "pclk"; 626 pinctrl-names = "default"; 627 pinctrl-0 = <&pwm1_pin>; 628 #pwm-cells = <3>; 629 status = "disabled"; 630 }; 631 632 pwm2: pwm@ff200020 { 633 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 634 reg = <0x0 0xff200020 0x0 0x10>; 635 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 636 clock-names = "pwm", "pclk"; 637 pinctrl-names = "default"; 638 pinctrl-0 = <&pwm2_pin>; 639 #pwm-cells = <3>; 640 status = "disabled"; 641 }; 642 643 pwm3: pwm@ff200030 { 644 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 645 reg = <0x0 0xff200030 0x0 0x10>; 646 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 647 clock-names = "pwm", "pclk"; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&pwm3_pin>; 650 #pwm-cells = <3>; 651 status = "disabled"; 652 }; 653 654 pwm4: pwm@ff208000 { 655 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 656 reg = <0x0 0xff208000 0x0 0x10>; 657 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 658 clock-names = "pwm", "pclk"; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&pwm4_pin>; 661 #pwm-cells = <3>; 662 status = "disabled"; 663 }; 664 665 pwm5: pwm@ff208010 { 666 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 667 reg = <0x0 0xff208010 0x0 0x10>; 668 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 669 clock-names = "pwm", "pclk"; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&pwm5_pin>; 672 #pwm-cells = <3>; 673 status = "disabled"; 674 }; 675 676 pwm6: pwm@ff208020 { 677 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 678 reg = <0x0 0xff208020 0x0 0x10>; 679 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 680 clock-names = "pwm", "pclk"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&pwm6_pin>; 683 #pwm-cells = <3>; 684 status = "disabled"; 685 }; 686 687 pwm7: pwm@ff208030 { 688 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 689 reg = <0x0 0xff208030 0x0 0x10>; 690 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 691 clock-names = "pwm", "pclk"; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&pwm7_pin>; 694 #pwm-cells = <3>; 695 status = "disabled"; 696 }; 697 698 rktimer: timer@ff210000 { 699 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 700 reg = <0x0 0xff210000 0x0 0x1000>; 701 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 703 clock-names = "pclk", "timer"; 704 }; 705 706 amba: bus { 707 compatible = "simple-bus"; 708 #address-cells = <2>; 709 #size-cells = <2>; 710 ranges; 711 712 dmac: dmac@ff240000 { 713 compatible = "arm,pl330", "arm,primecell"; 714 reg = <0x0 0xff240000 0x0 0x4000>; 715 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&cru ACLK_DMAC>; 718 clock-names = "apb_pclk"; 719 #dma-cells = <1>; 720 }; 721 }; 722 723 tsadc: tsadc@ff280000 { 724 compatible = "rockchip,px30-tsadc"; 725 reg = <0x0 0xff280000 0x0 0x100>; 726 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 727 assigned-clocks = <&cru SCLK_TSADC>; 728 assigned-clock-rates = <50000>; 729 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 730 clock-names = "tsadc", "apb_pclk"; 731 resets = <&cru SRST_TSADC>; 732 reset-names = "tsadc-apb"; 733 rockchip,grf = <&grf>; 734 rockchip,hw-tshut-temp = <120000>; 735 pinctrl-names = "init", "default", "sleep"; 736 pinctrl-0 = <&tsadc_otp_gpio>; 737 pinctrl-1 = <&tsadc_otp_out>; 738 pinctrl-2 = <&tsadc_otp_gpio>; 739 #thermal-sensor-cells = <1>; 740 status = "disabled"; 741 }; 742 743 saradc: saradc@ff288000 { 744 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 745 reg = <0x0 0xff288000 0x0 0x100>; 746 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 747 #io-channel-cells = <1>; 748 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 749 clock-names = "saradc", "apb_pclk"; 750 resets = <&cru SRST_SARADC_P>; 751 reset-names = "saradc-apb"; 752 status = "disabled"; 753 }; 754 755 otp: nvmem@ff290000 { 756 compatible = "rockchip,px30-otp"; 757 reg = <0x0 0xff290000 0x0 0x4000>; 758 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 759 <&cru PCLK_OTP_PHY>; 760 clock-names = "otp", "apb_pclk", "phy"; 761 resets = <&cru SRST_OTP_PHY>; 762 reset-names = "phy"; 763 #address-cells = <1>; 764 #size-cells = <1>; 765 766 /* Data cells */ 767 cpu_id: id@7 { 768 reg = <0x07 0x10>; 769 }; 770 cpu_leakage: cpu-leakage@17 { 771 reg = <0x17 0x1>; 772 }; 773 performance: performance@1e { 774 reg = <0x1e 0x1>; 775 bits = <4 3>; 776 }; 777 }; 778 779 cru: clock-controller@ff2b0000 { 780 compatible = "rockchip,px30-cru"; 781 reg = <0x0 0xff2b0000 0x0 0x1000>; 782 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 783 clock-names = "xin24m", "gpll"; 784 rockchip,grf = <&grf>; 785 #clock-cells = <1>; 786 #reset-cells = <1>; 787 788 assigned-clocks = <&cru PLL_NPLL>, 789 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 790 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 791 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 792 793 assigned-clock-rates = <1188000000>, 794 <200000000>, <200000000>, 795 <150000000>, <150000000>, 796 <100000000>, <200000000>; 797 }; 798 799 pmucru: clock-controller@ff2bc000 { 800 compatible = "rockchip,px30-pmucru"; 801 reg = <0x0 0xff2bc000 0x0 0x1000>; 802 clocks = <&xin24m>; 803 clock-names = "xin24m"; 804 rockchip,grf = <&grf>; 805 #clock-cells = <1>; 806 #reset-cells = <1>; 807 808 assigned-clocks = 809 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 810 <&pmucru SCLK_WIFI_PMU>; 811 assigned-clock-rates = 812 <1200000000>, <100000000>, 813 <26000000>; 814 }; 815 816 usb2phy_grf: syscon@ff2c0000 { 817 compatible = "rockchip,px30-usb2phy-grf", "syscon", 818 "simple-mfd"; 819 reg = <0x0 0xff2c0000 0x0 0x10000>; 820 #address-cells = <1>; 821 #size-cells = <1>; 822 823 u2phy: usb2-phy@100 { 824 compatible = "rockchip,px30-usb2phy"; 825 reg = <0x100 0x20>; 826 clocks = <&pmucru SCLK_USBPHY_REF>; 827 clock-names = "phyclk"; 828 #clock-cells = <0>; 829 assigned-clocks = <&cru USB480M>; 830 assigned-clock-parents = <&u2phy>; 831 clock-output-names = "usb480m_phy"; 832 status = "disabled"; 833 834 u2phy_host: host-port { 835 #phy-cells = <0>; 836 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 837 interrupt-names = "linestate"; 838 status = "disabled"; 839 }; 840 841 u2phy_otg: otg-port { 842 #phy-cells = <0>; 843 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-names = "otg-bvalid", "otg-id", 847 "linestate"; 848 status = "disabled"; 849 }; 850 }; 851 }; 852 853 dsi_dphy: phy@ff2e0000 { 854 compatible = "rockchip,px30-dsi-dphy"; 855 reg = <0x0 0xff2e0000 0x0 0x10000>; 856 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 857 clock-names = "ref", "pclk"; 858 resets = <&cru SRST_MIPIDSIPHY_P>; 859 reset-names = "apb"; 860 #phy-cells = <0>; 861 power-domains = <&power PX30_PD_VO>; 862 status = "disabled"; 863 }; 864 865 usb20_otg: usb@ff300000 { 866 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 867 "snps,dwc2"; 868 reg = <0x0 0xff300000 0x0 0x40000>; 869 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&cru HCLK_OTG>; 871 clock-names = "otg"; 872 dr_mode = "otg"; 873 g-np-tx-fifo-size = <16>; 874 g-rx-fifo-size = <280>; 875 g-tx-fifo-size = <256 128 128 64 32 16>; 876 phys = <&u2phy_otg>; 877 phy-names = "usb2-phy"; 878 power-domains = <&power PX30_PD_USB>; 879 status = "disabled"; 880 }; 881 882 usb_host0_ehci: usb@ff340000 { 883 compatible = "generic-ehci"; 884 reg = <0x0 0xff340000 0x0 0x10000>; 885 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&cru HCLK_HOST>; 887 phys = <&u2phy_host>; 888 phy-names = "usb"; 889 power-domains = <&power PX30_PD_USB>; 890 status = "disabled"; 891 }; 892 893 usb_host0_ohci: usb@ff350000 { 894 compatible = "generic-ohci"; 895 reg = <0x0 0xff350000 0x0 0x10000>; 896 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&cru HCLK_HOST>; 898 phys = <&u2phy_host>; 899 phy-names = "usb"; 900 power-domains = <&power PX30_PD_USB>; 901 status = "disabled"; 902 }; 903 904 gmac: ethernet@ff360000 { 905 compatible = "rockchip,px30-gmac"; 906 reg = <0x0 0xff360000 0x0 0x10000>; 907 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 908 interrupt-names = "macirq"; 909 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 910 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 911 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 912 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 913 clock-names = "stmmaceth", "mac_clk_rx", 914 "mac_clk_tx", "clk_mac_ref", 915 "clk_mac_refout", "aclk_mac", 916 "pclk_mac", "clk_mac_speed"; 917 rockchip,grf = <&grf>; 918 phy-mode = "rmii"; 919 pinctrl-names = "default"; 920 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 921 power-domains = <&power PX30_PD_GMAC>; 922 resets = <&cru SRST_GMAC_A>; 923 reset-names = "stmmaceth"; 924 status = "disabled"; 925 }; 926 927 sdmmc: mmc@ff370000 { 928 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 929 reg = <0x0 0xff370000 0x0 0x4000>; 930 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 932 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 933 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 934 fifo-depth = <0x100>; 935 max-frequency = <150000000>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 938 power-domains = <&power PX30_PD_SDCARD>; 939 status = "disabled"; 940 }; 941 942 sdio: mmc@ff380000 { 943 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 944 reg = <0x0 0xff380000 0x0 0x4000>; 945 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 947 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 948 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 949 fifo-depth = <0x100>; 950 max-frequency = <150000000>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 953 power-domains = <&power PX30_PD_MMC_NAND>; 954 status = "disabled"; 955 }; 956 957 emmc: mmc@ff390000 { 958 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 959 reg = <0x0 0xff390000 0x0 0x4000>; 960 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 962 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 963 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 964 fifo-depth = <0x100>; 965 max-frequency = <150000000>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 968 power-domains = <&power PX30_PD_MMC_NAND>; 969 status = "disabled"; 970 }; 971 972 gpu: gpu@ff400000 { 973 compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 974 reg = <0x0 0xff400000 0x0 0x4000>; 975 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 978 interrupt-names = "job", "mmu", "gpu"; 979 clocks = <&cru SCLK_GPU>; 980 #cooling-cells = <2>; 981 power-domains = <&power PX30_PD_GPU>; 982 status = "disabled"; 983 }; 984 985 dsi: dsi@ff450000 { 986 compatible = "rockchip,px30-mipi-dsi"; 987 reg = <0x0 0xff450000 0x0 0x10000>; 988 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&cru PCLK_MIPI_DSI>; 990 clock-names = "pclk"; 991 phys = <&dsi_dphy>; 992 phy-names = "dphy"; 993 power-domains = <&power PX30_PD_VO>; 994 resets = <&cru SRST_MIPIDSI_HOST_P>; 995 reset-names = "apb"; 996 rockchip,grf = <&grf>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 status = "disabled"; 1000 1001 ports { 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 1005 port@0 { 1006 reg = <0>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 1010 dsi_in_vopb: endpoint@0 { 1011 reg = <0>; 1012 remote-endpoint = <&vopb_out_dsi>; 1013 }; 1014 1015 dsi_in_vopl: endpoint@1 { 1016 reg = <1>; 1017 remote-endpoint = <&vopl_out_dsi>; 1018 }; 1019 }; 1020 }; 1021 }; 1022 1023 vopb: vop@ff460000 { 1024 compatible = "rockchip,px30-vop-big"; 1025 reg = <0x0 0xff460000 0x0 0xefc>; 1026 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1028 <&cru HCLK_VOPB>; 1029 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1030 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1031 reset-names = "axi", "ahb", "dclk"; 1032 iommus = <&vopb_mmu>; 1033 power-domains = <&power PX30_PD_VO>; 1034 status = "disabled"; 1035 1036 vopb_out: port { 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 1040 vopb_out_dsi: endpoint@0 { 1041 reg = <0>; 1042 remote-endpoint = <&dsi_in_vopb>; 1043 }; 1044 1045 vopb_out_lvds: endpoint@1 { 1046 reg = <1>; 1047 remote-endpoint = <&lvds_vopb_in>; 1048 }; 1049 }; 1050 }; 1051 1052 vopb_mmu: iommu@ff460f00 { 1053 compatible = "rockchip,iommu"; 1054 reg = <0x0 0xff460f00 0x0 0x100>; 1055 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1056 interrupt-names = "vopb_mmu"; 1057 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1058 clock-names = "aclk", "iface"; 1059 power-domains = <&power PX30_PD_VO>; 1060 #iommu-cells = <0>; 1061 status = "disabled"; 1062 }; 1063 1064 vopl: vop@ff470000 { 1065 compatible = "rockchip,px30-vop-lit"; 1066 reg = <0x0 0xff470000 0x0 0xefc>; 1067 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1069 <&cru HCLK_VOPL>; 1070 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1071 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1072 reset-names = "axi", "ahb", "dclk"; 1073 iommus = <&vopl_mmu>; 1074 power-domains = <&power PX30_PD_VO>; 1075 status = "disabled"; 1076 1077 vopl_out: port { 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 1081 vopl_out_dsi: endpoint@0 { 1082 reg = <0>; 1083 remote-endpoint = <&dsi_in_vopl>; 1084 }; 1085 1086 vopl_out_lvds: endpoint@1 { 1087 reg = <1>; 1088 remote-endpoint = <&lvds_vopl_in>; 1089 }; 1090 }; 1091 }; 1092 1093 vopl_mmu: iommu@ff470f00 { 1094 compatible = "rockchip,iommu"; 1095 reg = <0x0 0xff470f00 0x0 0x100>; 1096 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1097 interrupt-names = "vopl_mmu"; 1098 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1099 clock-names = "aclk", "iface"; 1100 power-domains = <&power PX30_PD_VO>; 1101 #iommu-cells = <0>; 1102 status = "disabled"; 1103 }; 1104 1105 qos_gmac: qos@ff518000 { 1106 compatible = "syscon"; 1107 reg = <0x0 0xff518000 0x0 0x20>; 1108 }; 1109 1110 qos_gpu: qos@ff520000 { 1111 compatible = "syscon"; 1112 reg = <0x0 0xff520000 0x0 0x20>; 1113 }; 1114 1115 qos_sdmmc: qos@ff52c000 { 1116 compatible = "syscon"; 1117 reg = <0x0 0xff52c000 0x0 0x20>; 1118 }; 1119 1120 qos_emmc: qos@ff538000 { 1121 compatible = "syscon"; 1122 reg = <0x0 0xff538000 0x0 0x20>; 1123 }; 1124 1125 qos_nand: qos@ff538080 { 1126 compatible = "syscon"; 1127 reg = <0x0 0xff538080 0x0 0x20>; 1128 }; 1129 1130 qos_sdio: qos@ff538100 { 1131 compatible = "syscon"; 1132 reg = <0x0 0xff538100 0x0 0x20>; 1133 }; 1134 1135 qos_sfc: qos@ff538180 { 1136 compatible = "syscon"; 1137 reg = <0x0 0xff538180 0x0 0x20>; 1138 }; 1139 1140 qos_usb_host: qos@ff540000 { 1141 compatible = "syscon"; 1142 reg = <0x0 0xff540000 0x0 0x20>; 1143 }; 1144 1145 qos_usb_otg: qos@ff540080 { 1146 compatible = "syscon"; 1147 reg = <0x0 0xff540080 0x0 0x20>; 1148 }; 1149 1150 qos_isp_128: qos@ff548000 { 1151 compatible = "syscon"; 1152 reg = <0x0 0xff548000 0x0 0x20>; 1153 }; 1154 1155 qos_isp_rd: qos@ff548080 { 1156 compatible = "syscon"; 1157 reg = <0x0 0xff548080 0x0 0x20>; 1158 }; 1159 1160 qos_isp_wr: qos@ff548100 { 1161 compatible = "syscon"; 1162 reg = <0x0 0xff548100 0x0 0x20>; 1163 }; 1164 1165 qos_isp_m1: qos@ff548180 { 1166 compatible = "syscon"; 1167 reg = <0x0 0xff548180 0x0 0x20>; 1168 }; 1169 1170 qos_vip: qos@ff548200 { 1171 compatible = "syscon"; 1172 reg = <0x0 0xff548200 0x0 0x20>; 1173 }; 1174 1175 qos_rga_rd: qos@ff550000 { 1176 compatible = "syscon"; 1177 reg = <0x0 0xff550000 0x0 0x20>; 1178 }; 1179 1180 qos_rga_wr: qos@ff550080 { 1181 compatible = "syscon"; 1182 reg = <0x0 0xff550080 0x0 0x20>; 1183 }; 1184 1185 qos_vop_m0: qos@ff550100 { 1186 compatible = "syscon"; 1187 reg = <0x0 0xff550100 0x0 0x20>; 1188 }; 1189 1190 qos_vop_m1: qos@ff550180 { 1191 compatible = "syscon"; 1192 reg = <0x0 0xff550180 0x0 0x20>; 1193 }; 1194 1195 qos_vpu: qos@ff558000 { 1196 compatible = "syscon"; 1197 reg = <0x0 0xff558000 0x0 0x20>; 1198 }; 1199 1200 qos_vpu_r128: qos@ff558080 { 1201 compatible = "syscon"; 1202 reg = <0x0 0xff558080 0x0 0x20>; 1203 }; 1204 1205 pinctrl: pinctrl { 1206 compatible = "rockchip,px30-pinctrl"; 1207 rockchip,grf = <&grf>; 1208 rockchip,pmu = <&pmugrf>; 1209 #address-cells = <2>; 1210 #size-cells = <2>; 1211 ranges; 1212 1213 gpio0: gpio0@ff040000 { 1214 compatible = "rockchip,gpio-bank"; 1215 reg = <0x0 0xff040000 0x0 0x100>; 1216 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1217 clocks = <&pmucru PCLK_GPIO0_PMU>; 1218 gpio-controller; 1219 #gpio-cells = <2>; 1220 1221 interrupt-controller; 1222 #interrupt-cells = <2>; 1223 }; 1224 1225 gpio1: gpio1@ff250000 { 1226 compatible = "rockchip,gpio-bank"; 1227 reg = <0x0 0xff250000 0x0 0x100>; 1228 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&cru PCLK_GPIO1>; 1230 gpio-controller; 1231 #gpio-cells = <2>; 1232 1233 interrupt-controller; 1234 #interrupt-cells = <2>; 1235 }; 1236 1237 gpio2: gpio2@ff260000 { 1238 compatible = "rockchip,gpio-bank"; 1239 reg = <0x0 0xff260000 0x0 0x100>; 1240 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1241 clocks = <&cru PCLK_GPIO2>; 1242 gpio-controller; 1243 #gpio-cells = <2>; 1244 1245 interrupt-controller; 1246 #interrupt-cells = <2>; 1247 }; 1248 1249 gpio3: gpio3@ff270000 { 1250 compatible = "rockchip,gpio-bank"; 1251 reg = <0x0 0xff270000 0x0 0x100>; 1252 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1253 clocks = <&cru PCLK_GPIO3>; 1254 gpio-controller; 1255 #gpio-cells = <2>; 1256 1257 interrupt-controller; 1258 #interrupt-cells = <2>; 1259 }; 1260 1261 pcfg_pull_up: pcfg-pull-up { 1262 bias-pull-up; 1263 }; 1264 1265 pcfg_pull_down: pcfg-pull-down { 1266 bias-pull-down; 1267 }; 1268 1269 pcfg_pull_none: pcfg-pull-none { 1270 bias-disable; 1271 }; 1272 1273 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1274 bias-disable; 1275 drive-strength = <2>; 1276 }; 1277 1278 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1279 bias-pull-up; 1280 drive-strength = <2>; 1281 }; 1282 1283 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1284 bias-pull-up; 1285 drive-strength = <4>; 1286 }; 1287 1288 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1289 bias-disable; 1290 drive-strength = <4>; 1291 }; 1292 1293 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1294 bias-pull-down; 1295 drive-strength = <4>; 1296 }; 1297 1298 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1299 bias-disable; 1300 drive-strength = <8>; 1301 }; 1302 1303 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1304 bias-pull-up; 1305 drive-strength = <8>; 1306 }; 1307 1308 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1309 bias-disable; 1310 drive-strength = <12>; 1311 }; 1312 1313 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1314 bias-pull-up; 1315 drive-strength = <12>; 1316 }; 1317 1318 pcfg_pull_none_smt: pcfg-pull-none-smt { 1319 bias-disable; 1320 input-schmitt-enable; 1321 }; 1322 1323 pcfg_output_high: pcfg-output-high { 1324 output-high; 1325 }; 1326 1327 pcfg_output_low: pcfg-output-low { 1328 output-low; 1329 }; 1330 1331 pcfg_input_high: pcfg-input-high { 1332 bias-pull-up; 1333 input-enable; 1334 }; 1335 1336 pcfg_input: pcfg-input { 1337 input-enable; 1338 }; 1339 1340 i2c0 { 1341 i2c0_xfer: i2c0-xfer { 1342 rockchip,pins = 1343 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1344 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1345 }; 1346 }; 1347 1348 i2c1 { 1349 i2c1_xfer: i2c1-xfer { 1350 rockchip,pins = 1351 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1352 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1353 }; 1354 }; 1355 1356 i2c2 { 1357 i2c2_xfer: i2c2-xfer { 1358 rockchip,pins = 1359 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1360 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1361 }; 1362 }; 1363 1364 i2c3 { 1365 i2c3_xfer: i2c3-xfer { 1366 rockchip,pins = 1367 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1368 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1369 }; 1370 }; 1371 1372 tsadc { 1373 tsadc_otp_gpio: tsadc-otp-gpio { 1374 rockchip,pins = 1375 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1376 }; 1377 1378 tsadc_otp_out: tsadc-otp-out { 1379 rockchip,pins = 1380 <0 RK_PA6 1 &pcfg_pull_none>; 1381 }; 1382 }; 1383 1384 uart0 { 1385 uart0_xfer: uart0-xfer { 1386 rockchip,pins = 1387 <0 RK_PB2 1 &pcfg_pull_up>, 1388 <0 RK_PB3 1 &pcfg_pull_up>; 1389 }; 1390 1391 uart0_cts: uart0-cts { 1392 rockchip,pins = 1393 <0 RK_PB4 1 &pcfg_pull_none>; 1394 }; 1395 1396 uart0_rts: uart0-rts { 1397 rockchip,pins = 1398 <0 RK_PB5 1 &pcfg_pull_none>; 1399 }; 1400 }; 1401 1402 uart1 { 1403 uart1_xfer: uart1-xfer { 1404 rockchip,pins = 1405 <1 RK_PC1 1 &pcfg_pull_up>, 1406 <1 RK_PC0 1 &pcfg_pull_up>; 1407 }; 1408 1409 uart1_cts: uart1-cts { 1410 rockchip,pins = 1411 <1 RK_PC2 1 &pcfg_pull_none>; 1412 }; 1413 1414 uart1_rts: uart1-rts { 1415 rockchip,pins = 1416 <1 RK_PC3 1 &pcfg_pull_none>; 1417 }; 1418 }; 1419 1420 uart2-m0 { 1421 uart2m0_xfer: uart2m0-xfer { 1422 rockchip,pins = 1423 <1 RK_PD2 2 &pcfg_pull_up>, 1424 <1 RK_PD3 2 &pcfg_pull_up>; 1425 }; 1426 }; 1427 1428 uart2-m1 { 1429 uart2m1_xfer: uart2m1-xfer { 1430 rockchip,pins = 1431 <2 RK_PB4 2 &pcfg_pull_up>, 1432 <2 RK_PB6 2 &pcfg_pull_up>; 1433 }; 1434 }; 1435 1436 uart3-m0 { 1437 uart3m0_xfer: uart3m0-xfer { 1438 rockchip,pins = 1439 <0 RK_PC0 2 &pcfg_pull_up>, 1440 <0 RK_PC1 2 &pcfg_pull_up>; 1441 }; 1442 1443 uart3m0_cts: uart3m0-cts { 1444 rockchip,pins = 1445 <0 RK_PC2 2 &pcfg_pull_none>; 1446 }; 1447 1448 uart3m0_rts: uart3m0-rts { 1449 rockchip,pins = 1450 <0 RK_PC3 2 &pcfg_pull_none>; 1451 }; 1452 }; 1453 1454 uart3-m1 { 1455 uart3m1_xfer: uart3m1-xfer { 1456 rockchip,pins = 1457 <1 RK_PB6 2 &pcfg_pull_up>, 1458 <1 RK_PB7 2 &pcfg_pull_up>; 1459 }; 1460 1461 uart3m1_cts: uart3m1-cts { 1462 rockchip,pins = 1463 <1 RK_PB4 2 &pcfg_pull_none>; 1464 }; 1465 1466 uart3m1_rts: uart3m1-rts { 1467 rockchip,pins = 1468 <1 RK_PB5 2 &pcfg_pull_none>; 1469 }; 1470 }; 1471 1472 uart4 { 1473 uart4_xfer: uart4-xfer { 1474 rockchip,pins = 1475 <1 RK_PD4 2 &pcfg_pull_up>, 1476 <1 RK_PD5 2 &pcfg_pull_up>; 1477 }; 1478 1479 uart4_cts: uart4-cts { 1480 rockchip,pins = 1481 <1 RK_PD6 2 &pcfg_pull_none>; 1482 }; 1483 1484 uart4_rts: uart4-rts { 1485 rockchip,pins = 1486 <1 RK_PD7 2 &pcfg_pull_none>; 1487 }; 1488 }; 1489 1490 uart5 { 1491 uart5_xfer: uart5-xfer { 1492 rockchip,pins = 1493 <3 RK_PA2 4 &pcfg_pull_up>, 1494 <3 RK_PA1 4 &pcfg_pull_up>; 1495 }; 1496 1497 uart5_cts: uart5-cts { 1498 rockchip,pins = 1499 <3 RK_PA3 4 &pcfg_pull_none>; 1500 }; 1501 1502 uart5_rts: uart5-rts { 1503 rockchip,pins = 1504 <3 RK_PA5 4 &pcfg_pull_none>; 1505 }; 1506 }; 1507 1508 spi0 { 1509 spi0_clk: spi0-clk { 1510 rockchip,pins = 1511 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1512 }; 1513 1514 spi0_csn: spi0-csn { 1515 rockchip,pins = 1516 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1517 }; 1518 1519 spi0_miso: spi0-miso { 1520 rockchip,pins = 1521 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1522 }; 1523 1524 spi0_mosi: spi0-mosi { 1525 rockchip,pins = 1526 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1527 }; 1528 1529 spi0_clk_hs: spi0-clk-hs { 1530 rockchip,pins = 1531 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1532 }; 1533 1534 spi0_miso_hs: spi0-miso-hs { 1535 rockchip,pins = 1536 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1537 }; 1538 1539 spi0_mosi_hs: spi0-mosi-hs { 1540 rockchip,pins = 1541 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1542 }; 1543 }; 1544 1545 spi1 { 1546 spi1_clk: spi1-clk { 1547 rockchip,pins = 1548 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1549 }; 1550 1551 spi1_csn0: spi1-csn0 { 1552 rockchip,pins = 1553 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1554 }; 1555 1556 spi1_csn1: spi1-csn1 { 1557 rockchip,pins = 1558 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1559 }; 1560 1561 spi1_miso: spi1-miso { 1562 rockchip,pins = 1563 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1564 }; 1565 1566 spi1_mosi: spi1-mosi { 1567 rockchip,pins = 1568 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1569 }; 1570 1571 spi1_clk_hs: spi1-clk-hs { 1572 rockchip,pins = 1573 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1574 }; 1575 1576 spi1_miso_hs: spi1-miso-hs { 1577 rockchip,pins = 1578 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1579 }; 1580 1581 spi1_mosi_hs: spi1-mosi-hs { 1582 rockchip,pins = 1583 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1584 }; 1585 }; 1586 1587 pdm { 1588 pdm_clk0m0: pdm-clk0m0 { 1589 rockchip,pins = 1590 <3 RK_PC6 2 &pcfg_pull_none>; 1591 }; 1592 1593 pdm_clk0m1: pdm-clk0m1 { 1594 rockchip,pins = 1595 <2 RK_PC6 1 &pcfg_pull_none>; 1596 }; 1597 1598 pdm_clk1: pdm-clk1 { 1599 rockchip,pins = 1600 <3 RK_PC7 2 &pcfg_pull_none>; 1601 }; 1602 1603 pdm_sdi0m0: pdm-sdi0m0 { 1604 rockchip,pins = 1605 <3 RK_PD3 2 &pcfg_pull_none>; 1606 }; 1607 1608 pdm_sdi0m1: pdm-sdi0m1 { 1609 rockchip,pins = 1610 <2 RK_PC5 2 &pcfg_pull_none>; 1611 }; 1612 1613 pdm_sdi1: pdm-sdi1 { 1614 rockchip,pins = 1615 <3 RK_PD0 2 &pcfg_pull_none>; 1616 }; 1617 1618 pdm_sdi2: pdm-sdi2 { 1619 rockchip,pins = 1620 <3 RK_PD1 2 &pcfg_pull_none>; 1621 }; 1622 1623 pdm_sdi3: pdm-sdi3 { 1624 rockchip,pins = 1625 <3 RK_PD2 2 &pcfg_pull_none>; 1626 }; 1627 1628 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1629 rockchip,pins = 1630 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1631 }; 1632 1633 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1634 rockchip,pins = 1635 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1636 }; 1637 1638 pdm_clk1_sleep: pdm-clk1-sleep { 1639 rockchip,pins = 1640 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1641 }; 1642 1643 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1644 rockchip,pins = 1645 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1646 }; 1647 1648 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1649 rockchip,pins = 1650 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1651 }; 1652 1653 pdm_sdi1_sleep: pdm-sdi1-sleep { 1654 rockchip,pins = 1655 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1656 }; 1657 1658 pdm_sdi2_sleep: pdm-sdi2-sleep { 1659 rockchip,pins = 1660 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1661 }; 1662 1663 pdm_sdi3_sleep: pdm-sdi3-sleep { 1664 rockchip,pins = 1665 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1666 }; 1667 }; 1668 1669 i2s0 { 1670 i2s0_8ch_mclk: i2s0-8ch-mclk { 1671 rockchip,pins = 1672 <3 RK_PC1 2 &pcfg_pull_none>; 1673 }; 1674 1675 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1676 rockchip,pins = 1677 <3 RK_PC3 2 &pcfg_pull_none>; 1678 }; 1679 1680 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1681 rockchip,pins = 1682 <3 RK_PB4 2 &pcfg_pull_none>; 1683 }; 1684 1685 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1686 rockchip,pins = 1687 <3 RK_PC2 2 &pcfg_pull_none>; 1688 }; 1689 1690 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1691 rockchip,pins = 1692 <3 RK_PB5 2 &pcfg_pull_none>; 1693 }; 1694 1695 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1696 rockchip,pins = 1697 <3 RK_PC4 2 &pcfg_pull_none>; 1698 }; 1699 1700 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1701 rockchip,pins = 1702 <3 RK_PC0 2 &pcfg_pull_none>; 1703 }; 1704 1705 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1706 rockchip,pins = 1707 <3 RK_PB7 2 &pcfg_pull_none>; 1708 }; 1709 1710 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1711 rockchip,pins = 1712 <3 RK_PB6 2 &pcfg_pull_none>; 1713 }; 1714 1715 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1716 rockchip,pins = 1717 <3 RK_PC5 2 &pcfg_pull_none>; 1718 }; 1719 1720 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1721 rockchip,pins = 1722 <3 RK_PB3 2 &pcfg_pull_none>; 1723 }; 1724 1725 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1726 rockchip,pins = 1727 <3 RK_PB1 2 &pcfg_pull_none>; 1728 }; 1729 1730 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1731 rockchip,pins = 1732 <3 RK_PB0 2 &pcfg_pull_none>; 1733 }; 1734 }; 1735 1736 i2s1 { 1737 i2s1_2ch_mclk: i2s1-2ch-mclk { 1738 rockchip,pins = 1739 <2 RK_PC3 1 &pcfg_pull_none>; 1740 }; 1741 1742 i2s1_2ch_sclk: i2s1-2ch-sclk { 1743 rockchip,pins = 1744 <2 RK_PC2 1 &pcfg_pull_none>; 1745 }; 1746 1747 i2s1_2ch_lrck: i2s1-2ch-lrck { 1748 rockchip,pins = 1749 <2 RK_PC1 1 &pcfg_pull_none>; 1750 }; 1751 1752 i2s1_2ch_sdi: i2s1-2ch-sdi { 1753 rockchip,pins = 1754 <2 RK_PC5 1 &pcfg_pull_none>; 1755 }; 1756 1757 i2s1_2ch_sdo: i2s1-2ch-sdo { 1758 rockchip,pins = 1759 <2 RK_PC4 1 &pcfg_pull_none>; 1760 }; 1761 }; 1762 1763 i2s2 { 1764 i2s2_2ch_mclk: i2s2-2ch-mclk { 1765 rockchip,pins = 1766 <3 RK_PA1 2 &pcfg_pull_none>; 1767 }; 1768 1769 i2s2_2ch_sclk: i2s2-2ch-sclk { 1770 rockchip,pins = 1771 <3 RK_PA2 2 &pcfg_pull_none>; 1772 }; 1773 1774 i2s2_2ch_lrck: i2s2-2ch-lrck { 1775 rockchip,pins = 1776 <3 RK_PA3 2 &pcfg_pull_none>; 1777 }; 1778 1779 i2s2_2ch_sdi: i2s2-2ch-sdi { 1780 rockchip,pins = 1781 <3 RK_PA5 2 &pcfg_pull_none>; 1782 }; 1783 1784 i2s2_2ch_sdo: i2s2-2ch-sdo { 1785 rockchip,pins = 1786 <3 RK_PA7 2 &pcfg_pull_none>; 1787 }; 1788 }; 1789 1790 sdmmc { 1791 sdmmc_clk: sdmmc-clk { 1792 rockchip,pins = 1793 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1794 }; 1795 1796 sdmmc_cmd: sdmmc-cmd { 1797 rockchip,pins = 1798 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1799 }; 1800 1801 sdmmc_det: sdmmc-det { 1802 rockchip,pins = 1803 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1804 }; 1805 1806 sdmmc_bus1: sdmmc-bus1 { 1807 rockchip,pins = 1808 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1809 }; 1810 1811 sdmmc_bus4: sdmmc-bus4 { 1812 rockchip,pins = 1813 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1814 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1815 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1816 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1817 }; 1818 }; 1819 1820 sdio { 1821 sdio_clk: sdio-clk { 1822 rockchip,pins = 1823 <1 RK_PC5 1 &pcfg_pull_none>; 1824 }; 1825 1826 sdio_cmd: sdio-cmd { 1827 rockchip,pins = 1828 <1 RK_PC4 1 &pcfg_pull_up>; 1829 }; 1830 1831 sdio_bus4: sdio-bus4 { 1832 rockchip,pins = 1833 <1 RK_PC6 1 &pcfg_pull_up>, 1834 <1 RK_PC7 1 &pcfg_pull_up>, 1835 <1 RK_PD0 1 &pcfg_pull_up>, 1836 <1 RK_PD1 1 &pcfg_pull_up>; 1837 }; 1838 }; 1839 1840 emmc { 1841 emmc_clk: emmc-clk { 1842 rockchip,pins = 1843 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 1844 }; 1845 1846 emmc_cmd: emmc-cmd { 1847 rockchip,pins = 1848 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 1849 }; 1850 1851 emmc_rstnout: emmc-rstnout { 1852 rockchip,pins = 1853 <1 RK_PB3 2 &pcfg_pull_none>; 1854 }; 1855 1856 emmc_bus1: emmc-bus1 { 1857 rockchip,pins = 1858 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 1859 }; 1860 1861 emmc_bus4: emmc-bus4 { 1862 rockchip,pins = 1863 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1864 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1865 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1866 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 1867 }; 1868 1869 emmc_bus8: emmc-bus8 { 1870 rockchip,pins = 1871 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1872 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1873 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1874 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 1875 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 1876 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 1877 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 1878 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 1879 }; 1880 }; 1881 1882 flash { 1883 flash_cs0: flash-cs0 { 1884 rockchip,pins = 1885 <1 RK_PB0 1 &pcfg_pull_none>; 1886 }; 1887 1888 flash_rdy: flash-rdy { 1889 rockchip,pins = 1890 <1 RK_PB1 1 &pcfg_pull_none>; 1891 }; 1892 1893 flash_dqs: flash-dqs { 1894 rockchip,pins = 1895 <1 RK_PB2 1 &pcfg_pull_none>; 1896 }; 1897 1898 flash_ale: flash-ale { 1899 rockchip,pins = 1900 <1 RK_PB3 1 &pcfg_pull_none>; 1901 }; 1902 1903 flash_cle: flash-cle { 1904 rockchip,pins = 1905 <1 RK_PB4 1 &pcfg_pull_none>; 1906 }; 1907 1908 flash_wrn: flash-wrn { 1909 rockchip,pins = 1910 <1 RK_PB5 1 &pcfg_pull_none>; 1911 }; 1912 1913 flash_csl: flash-csl { 1914 rockchip,pins = 1915 <1 RK_PB6 1 &pcfg_pull_none>; 1916 }; 1917 1918 flash_rdn: flash-rdn { 1919 rockchip,pins = 1920 <1 RK_PB7 1 &pcfg_pull_none>; 1921 }; 1922 1923 flash_bus8: flash-bus8 { 1924 rockchip,pins = 1925 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 1926 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 1927 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 1928 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 1929 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 1930 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 1931 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 1932 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 1933 }; 1934 }; 1935 1936 lcdc { 1937 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1938 rockchip,pins = 1939 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 1940 }; 1941 1942 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1943 rockchip,pins = 1944 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 1945 }; 1946 1947 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1948 rockchip,pins = 1949 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 1950 }; 1951 1952 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1953 rockchip,pins = 1954 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 1955 }; 1956 1957 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1958 rockchip,pins = 1959 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1960 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1961 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1962 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1963 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1964 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1965 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1966 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1967 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1968 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1969 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1970 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 1971 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1972 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1973 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1974 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1975 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 1976 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 1977 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1978 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 1979 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 1980 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 1981 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 1982 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 1983 }; 1984 1985 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 1986 rockchip,pins = 1987 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1988 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1989 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1990 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1991 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1992 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1993 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1994 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1995 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1996 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1997 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1998 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 1999 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2000 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2001 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2002 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2003 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2004 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2005 }; 2006 2007 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2008 rockchip,pins = 2009 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2010 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2011 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2012 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2013 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2014 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2015 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2016 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2017 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2018 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2019 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2020 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2021 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2022 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2023 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2024 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2025 }; 2026 2027 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2028 rockchip,pins = 2029 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2030 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2031 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2032 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2033 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2034 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2035 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2036 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2037 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2038 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2039 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2040 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2041 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2042 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2043 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2044 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2045 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2046 }; 2047 2048 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2049 rockchip,pins = 2050 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2051 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2052 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2053 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2054 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2055 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2056 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2057 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2058 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2059 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2060 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2061 }; 2062 2063 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2064 rockchip,pins = 2065 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2066 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2067 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2068 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2069 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2070 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2071 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2072 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2073 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2074 }; 2075 }; 2076 2077 pwm0 { 2078 pwm0_pin: pwm0-pin { 2079 rockchip,pins = 2080 <0 RK_PB7 1 &pcfg_pull_none>; 2081 }; 2082 }; 2083 2084 pwm1 { 2085 pwm1_pin: pwm1-pin { 2086 rockchip,pins = 2087 <0 RK_PC0 1 &pcfg_pull_none>; 2088 }; 2089 }; 2090 2091 pwm2 { 2092 pwm2_pin: pwm2-pin { 2093 rockchip,pins = 2094 <2 RK_PB5 1 &pcfg_pull_none>; 2095 }; 2096 }; 2097 2098 pwm3 { 2099 pwm3_pin: pwm3-pin { 2100 rockchip,pins = 2101 <0 RK_PC1 1 &pcfg_pull_none>; 2102 }; 2103 }; 2104 2105 pwm4 { 2106 pwm4_pin: pwm4-pin { 2107 rockchip,pins = 2108 <3 RK_PC2 3 &pcfg_pull_none>; 2109 }; 2110 }; 2111 2112 pwm5 { 2113 pwm5_pin: pwm5-pin { 2114 rockchip,pins = 2115 <3 RK_PC3 3 &pcfg_pull_none>; 2116 }; 2117 }; 2118 2119 pwm6 { 2120 pwm6_pin: pwm6-pin { 2121 rockchip,pins = 2122 <3 RK_PC4 3 &pcfg_pull_none>; 2123 }; 2124 }; 2125 2126 pwm7 { 2127 pwm7_pin: pwm7-pin { 2128 rockchip,pins = 2129 <3 RK_PC5 3 &pcfg_pull_none>; 2130 }; 2131 }; 2132 2133 gmac { 2134 rmii_pins: rmii-pins { 2135 rockchip,pins = 2136 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 2137 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 2138 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 2139 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 2140 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 2141 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 2142 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 2143 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 2144 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 2145 }; 2146 2147 mac_refclk_12ma: mac-refclk-12ma { 2148 rockchip,pins = 2149 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 2150 }; 2151 2152 mac_refclk: mac-refclk { 2153 rockchip,pins = 2154 <2 RK_PB2 2 &pcfg_pull_none>; 2155 }; 2156 }; 2157 2158 cif-m0 { 2159 cif_clkout_m0: cif-clkout-m0 { 2160 rockchip,pins = 2161 <2 RK_PB3 1 &pcfg_pull_none>; 2162 }; 2163 2164 dvp_d2d9_m0: dvp-d2d9-m0 { 2165 rockchip,pins = 2166 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 2167 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 2168 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 2169 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 2170 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 2171 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 2172 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 2173 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 2174 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 2175 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 2176 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 2177 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 2178 }; 2179 2180 dvp_d0d1_m0: dvp-d0d1-m0 { 2181 rockchip,pins = 2182 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 2183 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 2184 }; 2185 2186 dvp_d10d11_m0:d10-d11-m0 { 2187 rockchip,pins = 2188 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 2189 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 2190 }; 2191 }; 2192 2193 cif-m1 { 2194 cif_clkout_m1: cif-clkout-m1 { 2195 rockchip,pins = 2196 <3 RK_PD0 3 &pcfg_pull_none>; 2197 }; 2198 2199 dvp_d2d9_m1: dvp-d2d9-m1 { 2200 rockchip,pins = 2201 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 2202 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 2203 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 2204 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 2205 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 2206 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 2207 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 2208 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 2209 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 2210 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 2211 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 2212 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 2213 }; 2214 2215 dvp_d0d1_m1: dvp-d0d1-m1 { 2216 rockchip,pins = 2217 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 2218 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 2219 }; 2220 2221 dvp_d10d11_m1:d10-d11-m1 { 2222 rockchip,pins = 2223 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 2224 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 2225 }; 2226 }; 2227 2228 isp { 2229 isp_prelight: isp-prelight { 2230 rockchip,pins = 2231 <3 RK_PD1 4 &pcfg_pull_none>; 2232 }; 2233 }; 2234 }; 2235}; 2236