1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13 14/ { 15 compatible = "rockchip,px30"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 serial3 = &uart3; 31 serial4 = &uart4; 32 serial5 = &uart5; 33 spi0 = &spi0; 34 spi1 = &spi1; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 clocks = <&cru ARMCLK>; 47 #cooling-cells = <2>; 48 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 49 dynamic-power-coefficient = <90>; 50 operating-points-v2 = <&cpu0_opp_table>; 51 }; 52 53 cpu1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a35"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 clocks = <&cru ARMCLK>; 59 #cooling-cells = <2>; 60 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 61 dynamic-power-coefficient = <90>; 62 operating-points-v2 = <&cpu0_opp_table>; 63 }; 64 65 cpu2: cpu@2 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a35"; 68 reg = <0x0 0x2>; 69 enable-method = "psci"; 70 clocks = <&cru ARMCLK>; 71 #cooling-cells = <2>; 72 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 73 dynamic-power-coefficient = <90>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 }; 76 77 cpu3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a35"; 80 reg = <0x0 0x3>; 81 enable-method = "psci"; 82 clocks = <&cru ARMCLK>; 83 #cooling-cells = <2>; 84 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 85 dynamic-power-coefficient = <90>; 86 operating-points-v2 = <&cpu0_opp_table>; 87 }; 88 89 idle-states { 90 entry-method = "psci"; 91 92 CPU_SLEEP: cpu-sleep { 93 compatible = "arm,idle-state"; 94 local-timer-stop; 95 arm,psci-suspend-param = <0x0010000>; 96 entry-latency-us = <120>; 97 exit-latency-us = <250>; 98 min-residency-us = <900>; 99 }; 100 101 CLUSTER_SLEEP: cluster-sleep { 102 compatible = "arm,idle-state"; 103 local-timer-stop; 104 arm,psci-suspend-param = <0x1010000>; 105 entry-latency-us = <400>; 106 exit-latency-us = <500>; 107 min-residency-us = <2000>; 108 }; 109 }; 110 }; 111 112 cpu0_opp_table: cpu0-opp-table { 113 compatible = "operating-points-v2"; 114 opp-shared; 115 116 opp-408000000 { 117 opp-hz = /bits/ 64 <408000000>; 118 opp-microvolt = <950000 950000 1350000>; 119 clock-latency-ns = <40000>; 120 opp-suspend; 121 }; 122 opp-600000000 { 123 opp-hz = /bits/ 64 <600000000>; 124 opp-microvolt = <950000 950000 1350000>; 125 clock-latency-ns = <40000>; 126 }; 127 opp-816000000 { 128 opp-hz = /bits/ 64 <816000000>; 129 opp-microvolt = <1050000 1050000 1350000>; 130 clock-latency-ns = <40000>; 131 }; 132 opp-1008000000 { 133 opp-hz = /bits/ 64 <1008000000>; 134 opp-microvolt = <1175000 1175000 1350000>; 135 clock-latency-ns = <40000>; 136 }; 137 opp-1200000000 { 138 opp-hz = /bits/ 64 <1200000000>; 139 opp-microvolt = <1300000 1300000 1350000>; 140 clock-latency-ns = <40000>; 141 }; 142 opp-1296000000 { 143 opp-hz = /bits/ 64 <1296000000>; 144 opp-microvolt = <1350000 1350000 1350000>; 145 clock-latency-ns = <40000>; 146 }; 147 }; 148 149 arm-pmu { 150 compatible = "arm,cortex-a53-pmu"; 151 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 155 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 156 }; 157 158 display_subsystem: display-subsystem { 159 compatible = "rockchip,display-subsystem"; 160 ports = <&vopb_out>, <&vopl_out>; 161 status = "disabled"; 162 }; 163 164 firmware { 165 optee { 166 compatible = "linaro,optee-tz"; 167 method = "smc"; 168 }; 169 }; 170 171 gmac_clkin: external-gmac-clock { 172 compatible = "fixed-clock"; 173 clock-frequency = <50000000>; 174 clock-output-names = "gmac_clkin"; 175 #clock-cells = <0>; 176 }; 177 178 psci { 179 compatible = "arm,psci-1.0"; 180 method = "smc"; 181 }; 182 183 timer { 184 compatible = "arm,armv8-timer"; 185 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 186 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 187 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 188 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 189 }; 190 191 xin24m: xin24m { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <24000000>; 195 clock-output-names = "xin24m"; 196 }; 197 198 pmu: power-management@ff000000 { 199 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 200 reg = <0x0 0xff000000 0x0 0x1000>; 201 202 power: power-controller { 203 compatible = "rockchip,px30-power-controller"; 204 #power-domain-cells = <1>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 /* These power domains are grouped by VD_LOGIC */ 209 pd_usb@PX30_PD_USB { 210 reg = <PX30_PD_USB>; 211 clocks = <&cru HCLK_HOST>, 212 <&cru HCLK_OTG>, 213 <&cru SCLK_OTG_ADP>; 214 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 215 }; 216 pd_sdcard@PX30_PD_SDCARD { 217 reg = <PX30_PD_SDCARD>; 218 clocks = <&cru HCLK_SDMMC>, 219 <&cru SCLK_SDMMC>; 220 pm_qos = <&qos_sdmmc>; 221 }; 222 pd_gmac@PX30_PD_GMAC { 223 reg = <PX30_PD_GMAC>; 224 clocks = <&cru ACLK_GMAC>, 225 <&cru PCLK_GMAC>, 226 <&cru SCLK_MAC_REF>, 227 <&cru SCLK_GMAC_RX_TX>; 228 pm_qos = <&qos_gmac>; 229 }; 230 pd_mmc_nand@PX30_PD_MMC_NAND { 231 reg = <PX30_PD_MMC_NAND>; 232 clocks = <&cru HCLK_NANDC>, 233 <&cru HCLK_EMMC>, 234 <&cru HCLK_SDIO>, 235 <&cru HCLK_SFC>, 236 <&cru SCLK_EMMC>, 237 <&cru SCLK_NANDC>, 238 <&cru SCLK_SDIO>, 239 <&cru SCLK_SFC>; 240 pm_qos = <&qos_emmc>, <&qos_nand>, 241 <&qos_sdio>, <&qos_sfc>; 242 }; 243 pd_vpu@PX30_PD_VPU { 244 reg = <PX30_PD_VPU>; 245 clocks = <&cru ACLK_VPU>, 246 <&cru HCLK_VPU>, 247 <&cru SCLK_CORE_VPU>; 248 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 249 }; 250 pd_vo@PX30_PD_VO { 251 reg = <PX30_PD_VO>; 252 clocks = <&cru ACLK_RGA>, 253 <&cru ACLK_VOPB>, 254 <&cru ACLK_VOPL>, 255 <&cru DCLK_VOPB>, 256 <&cru DCLK_VOPL>, 257 <&cru HCLK_RGA>, 258 <&cru HCLK_VOPB>, 259 <&cru HCLK_VOPL>, 260 <&cru PCLK_MIPI_DSI>, 261 <&cru SCLK_RGA_CORE>, 262 <&cru SCLK_VOPB_PWM>; 263 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 264 <&qos_vop_m0>, <&qos_vop_m1>; 265 }; 266 pd_vi@PX30_PD_VI { 267 reg = <PX30_PD_VI>; 268 clocks = <&cru ACLK_CIF>, 269 <&cru ACLK_ISP>, 270 <&cru HCLK_CIF>, 271 <&cru HCLK_ISP>, 272 <&cru SCLK_ISP>; 273 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 274 <&qos_isp_wr>, <&qos_isp_m1>, 275 <&qos_vip>; 276 }; 277 pd_gpu@PX30_PD_GPU { 278 reg = <PX30_PD_GPU>; 279 clocks = <&cru SCLK_GPU>; 280 pm_qos = <&qos_gpu>; 281 }; 282 }; 283 }; 284 285 pmugrf: syscon@ff010000 { 286 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 287 reg = <0x0 0xff010000 0x0 0x1000>; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 291 pmu_io_domains: io-domains { 292 compatible = "rockchip,px30-pmu-io-voltage-domain"; 293 status = "disabled"; 294 }; 295 296 reboot-mode { 297 compatible = "syscon-reboot-mode"; 298 offset = <0x200>; 299 mode-bootloader = <BOOT_BL_DOWNLOAD>; 300 mode-fastboot = <BOOT_FASTBOOT>; 301 mode-loader = <BOOT_BL_DOWNLOAD>; 302 mode-normal = <BOOT_NORMAL>; 303 mode-recovery = <BOOT_RECOVERY>; 304 }; 305 }; 306 307 uart0: serial@ff030000 { 308 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 309 reg = <0x0 0xff030000 0x0 0x100>; 310 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 312 clock-names = "baudclk", "apb_pclk"; 313 dmas = <&dmac 0>, <&dmac 1>; 314 dma-names = "tx", "rx"; 315 reg-shift = <2>; 316 reg-io-width = <4>; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 319 status = "disabled"; 320 }; 321 322 i2s1_2ch: i2s@ff070000 { 323 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 324 reg = <0x0 0xff070000 0x0 0x1000>; 325 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 327 clock-names = "i2s_clk", "i2s_hclk"; 328 dmas = <&dmac 18>, <&dmac 19>; 329 dma-names = "tx", "rx"; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 332 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 333 #sound-dai-cells = <0>; 334 status = "disabled"; 335 }; 336 337 i2s2_2ch: i2s@ff080000 { 338 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 339 reg = <0x0 0xff080000 0x0 0x1000>; 340 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 342 clock-names = "i2s_clk", "i2s_hclk"; 343 dmas = <&dmac 20>, <&dmac 21>; 344 dma-names = "tx", "rx"; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 347 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 348 #sound-dai-cells = <0>; 349 status = "disabled"; 350 }; 351 352 gic: interrupt-controller@ff131000 { 353 compatible = "arm,gic-400"; 354 #interrupt-cells = <3>; 355 #address-cells = <0>; 356 interrupt-controller; 357 reg = <0x0 0xff131000 0 0x1000>, 358 <0x0 0xff132000 0 0x2000>, 359 <0x0 0xff134000 0 0x2000>, 360 <0x0 0xff136000 0 0x2000>; 361 interrupts = <GIC_PPI 9 362 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 363 }; 364 365 grf: syscon@ff140000 { 366 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 367 reg = <0x0 0xff140000 0x0 0x1000>; 368 #address-cells = <1>; 369 #size-cells = <1>; 370 371 io_domains: io-domains { 372 compatible = "rockchip,px30-io-voltage-domain"; 373 status = "disabled"; 374 }; 375 }; 376 377 uart1: serial@ff158000 { 378 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 379 reg = <0x0 0xff158000 0x0 0x100>; 380 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 382 clock-names = "baudclk", "apb_pclk"; 383 dmas = <&dmac 2>, <&dmac 3>; 384 dma-names = "tx", "rx"; 385 reg-shift = <2>; 386 reg-io-width = <4>; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 389 status = "disabled"; 390 }; 391 392 uart2: serial@ff160000 { 393 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 394 reg = <0x0 0xff160000 0x0 0x100>; 395 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 397 clock-names = "baudclk", "apb_pclk"; 398 dmas = <&dmac 4>, <&dmac 5>; 399 dma-names = "tx", "rx"; 400 reg-shift = <2>; 401 reg-io-width = <4>; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&uart2m0_xfer>; 404 status = "disabled"; 405 }; 406 407 uart3: serial@ff168000 { 408 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 409 reg = <0x0 0xff168000 0x0 0x100>; 410 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 412 clock-names = "baudclk", "apb_pclk"; 413 dmas = <&dmac 6>, <&dmac 7>; 414 dma-names = "tx", "rx"; 415 reg-shift = <2>; 416 reg-io-width = <4>; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 419 status = "disabled"; 420 }; 421 422 uart4: serial@ff170000 { 423 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 424 reg = <0x0 0xff170000 0x0 0x100>; 425 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 427 clock-names = "baudclk", "apb_pclk"; 428 dmas = <&dmac 8>, <&dmac 9>; 429 dma-names = "tx", "rx"; 430 reg-shift = <2>; 431 reg-io-width = <4>; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 434 status = "disabled"; 435 }; 436 437 uart5: serial@ff178000 { 438 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 439 reg = <0x0 0xff178000 0x0 0x100>; 440 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 442 clock-names = "baudclk", "apb_pclk"; 443 dmas = <&dmac 10>, <&dmac 11>; 444 dma-names = "tx", "rx"; 445 reg-shift = <2>; 446 reg-io-width = <4>; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 449 status = "disabled"; 450 }; 451 452 i2c0: i2c@ff180000 { 453 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 454 reg = <0x0 0xff180000 0x0 0x1000>; 455 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 456 clock-names = "i2c", "pclk"; 457 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&i2c0_xfer>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 status = "disabled"; 463 }; 464 465 i2c1: i2c@ff190000 { 466 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 467 reg = <0x0 0xff190000 0x0 0x1000>; 468 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 469 clock-names = "i2c", "pclk"; 470 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&i2c1_xfer>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 status = "disabled"; 476 }; 477 478 i2c2: i2c@ff1a0000 { 479 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 480 reg = <0x0 0xff1a0000 0x0 0x1000>; 481 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 482 clock-names = "i2c", "pclk"; 483 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&i2c2_xfer>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 status = "disabled"; 489 }; 490 491 i2c3: i2c@ff1b0000 { 492 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 493 reg = <0x0 0xff1b0000 0x0 0x1000>; 494 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 495 clock-names = "i2c", "pclk"; 496 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 497 pinctrl-names = "default"; 498 pinctrl-0 = <&i2c3_xfer>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 status = "disabled"; 502 }; 503 504 spi0: spi@ff1d0000 { 505 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 506 reg = <0x0 0xff1d0000 0x0 0x1000>; 507 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 509 clock-names = "spiclk", "apb_pclk"; 510 dmas = <&dmac 12>, <&dmac 13>; 511 dma-names = "tx", "rx"; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 status = "disabled"; 517 }; 518 519 spi1: spi@ff1d8000 { 520 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 521 reg = <0x0 0xff1d8000 0x0 0x1000>; 522 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 524 clock-names = "spiclk", "apb_pclk"; 525 dmas = <&dmac 14>, <&dmac 15>; 526 dma-names = "tx", "rx"; 527 pinctrl-names = "default"; 528 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 status = "disabled"; 532 }; 533 534 wdt: watchdog@ff1e0000 { 535 compatible = "snps,dw-wdt"; 536 reg = <0x0 0xff1e0000 0x0 0x100>; 537 clocks = <&cru PCLK_WDT_NS>; 538 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 539 status = "disabled"; 540 }; 541 542 pwm0: pwm@ff200000 { 543 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 544 reg = <0x0 0xff200000 0x0 0x10>; 545 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 546 clock-names = "pwm", "pclk"; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&pwm0_pin>; 549 #pwm-cells = <3>; 550 status = "disabled"; 551 }; 552 553 pwm1: pwm@ff200010 { 554 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 555 reg = <0x0 0xff200010 0x0 0x10>; 556 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 557 clock-names = "pwm", "pclk"; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&pwm1_pin>; 560 #pwm-cells = <3>; 561 status = "disabled"; 562 }; 563 564 pwm2: pwm@ff200020 { 565 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 566 reg = <0x0 0xff200020 0x0 0x10>; 567 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 568 clock-names = "pwm", "pclk"; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pwm2_pin>; 571 #pwm-cells = <3>; 572 status = "disabled"; 573 }; 574 575 pwm3: pwm@ff200030 { 576 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 577 reg = <0x0 0xff200030 0x0 0x10>; 578 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 579 clock-names = "pwm", "pclk"; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&pwm3_pin>; 582 #pwm-cells = <3>; 583 status = "disabled"; 584 }; 585 586 pwm4: pwm@ff208000 { 587 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 588 reg = <0x0 0xff208000 0x0 0x10>; 589 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 590 clock-names = "pwm", "pclk"; 591 pinctrl-names = "default"; 592 pinctrl-0 = <&pwm4_pin>; 593 #pwm-cells = <3>; 594 status = "disabled"; 595 }; 596 597 pwm5: pwm@ff208010 { 598 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 599 reg = <0x0 0xff208010 0x0 0x10>; 600 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 601 clock-names = "pwm", "pclk"; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&pwm5_pin>; 604 #pwm-cells = <3>; 605 status = "disabled"; 606 }; 607 608 pwm6: pwm@ff208020 { 609 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 610 reg = <0x0 0xff208020 0x0 0x10>; 611 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 612 clock-names = "pwm", "pclk"; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&pwm6_pin>; 615 #pwm-cells = <3>; 616 status = "disabled"; 617 }; 618 619 pwm7: pwm@ff208030 { 620 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 621 reg = <0x0 0xff208030 0x0 0x10>; 622 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 623 clock-names = "pwm", "pclk"; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&pwm7_pin>; 626 #pwm-cells = <3>; 627 status = "disabled"; 628 }; 629 630 rktimer: timer@ff210000 { 631 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 632 reg = <0x0 0xff210000 0x0 0x1000>; 633 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 635 clock-names = "pclk", "timer"; 636 }; 637 638 amba { 639 compatible = "simple-bus"; 640 #address-cells = <2>; 641 #size-cells = <2>; 642 ranges; 643 644 dmac: dmac@ff240000 { 645 compatible = "arm,pl330", "arm,primecell"; 646 reg = <0x0 0xff240000 0x0 0x4000>; 647 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&cru ACLK_DMAC>; 650 clock-names = "apb_pclk"; 651 #dma-cells = <1>; 652 }; 653 }; 654 655 saradc: saradc@ff288000 { 656 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 657 reg = <0x0 0xff288000 0x0 0x100>; 658 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 659 #io-channel-cells = <1>; 660 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 661 clock-names = "saradc", "apb_pclk"; 662 resets = <&cru SRST_SARADC_P>; 663 reset-names = "saradc-apb"; 664 status = "disabled"; 665 }; 666 667 cru: clock-controller@ff2b0000 { 668 compatible = "rockchip,px30-cru"; 669 reg = <0x0 0xff2b0000 0x0 0x1000>; 670 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 671 clock-names = "xin24m", "gpll"; 672 rockchip,grf = <&grf>; 673 #clock-cells = <1>; 674 #reset-cells = <1>; 675 676 assigned-clocks = <&cru PLL_NPLL>, 677 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 678 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 679 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 680 681 assigned-clock-rates = <1188000000>, 682 <200000000>, <200000000>, 683 <150000000>, <150000000>, 684 <100000000>, <200000000>; 685 }; 686 687 pmucru: clock-controller@ff2bc000 { 688 compatible = "rockchip,px30-pmucru"; 689 reg = <0x0 0xff2bc000 0x0 0x1000>; 690 clocks = <&xin24m>; 691 clock-names = "xin24m"; 692 rockchip,grf = <&grf>; 693 #clock-cells = <1>; 694 #reset-cells = <1>; 695 696 assigned-clocks = 697 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 698 <&pmucru SCLK_WIFI_PMU>; 699 assigned-clock-rates = 700 <1200000000>, <100000000>, 701 <26000000>; 702 }; 703 704 usb20_otg: usb@ff300000 { 705 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 706 "snps,dwc2"; 707 reg = <0x0 0xff300000 0x0 0x40000>; 708 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cru HCLK_OTG>; 710 clock-names = "otg"; 711 dr_mode = "otg"; 712 g-np-tx-fifo-size = <16>; 713 g-rx-fifo-size = <280>; 714 g-tx-fifo-size = <256 128 128 64 32 16>; 715 g-use-dma; 716 power-domains = <&power PX30_PD_USB>; 717 status = "disabled"; 718 }; 719 720 usb_host0_ehci: usb@ff340000 { 721 compatible = "generic-ehci"; 722 reg = <0x0 0xff340000 0x0 0x10000>; 723 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&cru HCLK_HOST>; 725 clock-names = "usbhost"; 726 power-domains = <&power PX30_PD_USB>; 727 status = "disabled"; 728 }; 729 730 usb_host0_ohci: usb@ff350000 { 731 compatible = "generic-ohci"; 732 reg = <0x0 0xff350000 0x0 0x10000>; 733 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&cru HCLK_HOST>; 735 clock-names = "usbhost"; 736 power-domains = <&power PX30_PD_USB>; 737 status = "disabled"; 738 }; 739 740 gmac: ethernet@ff360000 { 741 compatible = "rockchip,px30-gmac"; 742 reg = <0x0 0xff360000 0x0 0x10000>; 743 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 744 interrupt-names = "macirq"; 745 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 746 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 747 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 748 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 749 clock-names = "stmmaceth", "mac_clk_rx", 750 "mac_clk_tx", "clk_mac_ref", 751 "clk_mac_refout", "aclk_mac", 752 "pclk_mac", "clk_mac_speed"; 753 rockchip,grf = <&grf>; 754 phy-mode = "rmii"; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 757 power-domains = <&power PX30_PD_GMAC>; 758 resets = <&cru SRST_GMAC_A>; 759 reset-names = "stmmaceth"; 760 status = "disabled"; 761 }; 762 763 sdmmc: dwmmc@ff370000 { 764 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 765 reg = <0x0 0xff370000 0x0 0x4000>; 766 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 768 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 769 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 770 fifo-depth = <0x100>; 771 max-frequency = <150000000>; 772 pinctrl-names = "default"; 773 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 774 power-domains = <&power PX30_PD_SDCARD>; 775 status = "disabled"; 776 }; 777 778 sdio: dwmmc@ff380000 { 779 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 780 reg = <0x0 0xff380000 0x0 0x4000>; 781 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 783 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 784 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 785 fifo-depth = <0x100>; 786 max-frequency = <150000000>; 787 pinctrl-names = "default"; 788 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 789 power-domains = <&power PX30_PD_MMC_NAND>; 790 status = "disabled"; 791 }; 792 793 emmc: dwmmc@ff390000 { 794 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 795 reg = <0x0 0xff390000 0x0 0x4000>; 796 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 798 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 799 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 800 fifo-depth = <0x100>; 801 max-frequency = <150000000>; 802 pinctrl-names = "default"; 803 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 804 power-domains = <&power PX30_PD_MMC_NAND>; 805 status = "disabled"; 806 }; 807 808 vopb: vop@ff460000 { 809 compatible = "rockchip,px30-vop-big"; 810 reg = <0x0 0xff460000 0x0 0xefc>; 811 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 813 <&cru HCLK_VOPB>; 814 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 815 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 816 reset-names = "axi", "ahb", "dclk"; 817 iommus = <&vopb_mmu>; 818 power-domains = <&power PX30_PD_VO>; 819 rockchip,grf = <&grf>; 820 status = "disabled"; 821 822 vopb_out: port { 823 #address-cells = <1>; 824 #size-cells = <0>; 825 }; 826 }; 827 828 vopb_mmu: iommu@ff460f00 { 829 compatible = "rockchip,iommu"; 830 reg = <0x0 0xff460f00 0x0 0x100>; 831 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 832 interrupt-names = "vopb_mmu"; 833 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 834 clock-names = "aclk", "iface"; 835 power-domains = <&power PX30_PD_VO>; 836 #iommu-cells = <0>; 837 status = "disabled"; 838 }; 839 840 vopl: vop@ff470000 { 841 compatible = "rockchip,px30-vop-lit"; 842 reg = <0x0 0xff470000 0x0 0xefc>; 843 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 845 <&cru HCLK_VOPL>; 846 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 847 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 848 reset-names = "axi", "ahb", "dclk"; 849 iommus = <&vopl_mmu>; 850 power-domains = <&power PX30_PD_VO>; 851 rockchip,grf = <&grf>; 852 status = "disabled"; 853 854 vopl_out: port { 855 #address-cells = <1>; 856 #size-cells = <0>; 857 }; 858 }; 859 860 vopl_mmu: iommu@ff470f00 { 861 compatible = "rockchip,iommu"; 862 reg = <0x0 0xff470f00 0x0 0x100>; 863 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 864 interrupt-names = "vopl_mmu"; 865 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 866 clock-names = "aclk", "iface"; 867 power-domains = <&power PX30_PD_VO>; 868 #iommu-cells = <0>; 869 status = "disabled"; 870 }; 871 872 qos_gmac: qos@ff518000 { 873 compatible = "syscon"; 874 reg = <0x0 0xff518000 0x0 0x20>; 875 }; 876 877 qos_gpu: qos@ff520000 { 878 compatible = "syscon"; 879 reg = <0x0 0xff520000 0x0 0x20>; 880 }; 881 882 qos_sdmmc: qos@ff52c000 { 883 compatible = "syscon"; 884 reg = <0x0 0xff52c000 0x0 0x20>; 885 }; 886 887 qos_emmc: qos@ff538000 { 888 compatible = "syscon"; 889 reg = <0x0 0xff538000 0x0 0x20>; 890 }; 891 892 qos_nand: qos@ff538080 { 893 compatible = "syscon"; 894 reg = <0x0 0xff538080 0x0 0x20>; 895 }; 896 897 qos_sdio: qos@ff538100 { 898 compatible = "syscon"; 899 reg = <0x0 0xff538100 0x0 0x20>; 900 }; 901 902 qos_sfc: qos@ff538180 { 903 compatible = "syscon"; 904 reg = <0x0 0xff538180 0x0 0x20>; 905 }; 906 907 qos_usb_host: qos@ff540000 { 908 compatible = "syscon"; 909 reg = <0x0 0xff540000 0x0 0x20>; 910 }; 911 912 qos_usb_otg: qos@ff540080 { 913 compatible = "syscon"; 914 reg = <0x0 0xff540080 0x0 0x20>; 915 }; 916 917 qos_isp_128: qos@ff548000 { 918 compatible = "syscon"; 919 reg = <0x0 0xff548000 0x0 0x20>; 920 }; 921 922 qos_isp_rd: qos@ff548080 { 923 compatible = "syscon"; 924 reg = <0x0 0xff548080 0x0 0x20>; 925 }; 926 927 qos_isp_wr: qos@ff548100 { 928 compatible = "syscon"; 929 reg = <0x0 0xff548100 0x0 0x20>; 930 }; 931 932 qos_isp_m1: qos@ff548180 { 933 compatible = "syscon"; 934 reg = <0x0 0xff548180 0x0 0x20>; 935 }; 936 937 qos_vip: qos@ff548200 { 938 compatible = "syscon"; 939 reg = <0x0 0xff548200 0x0 0x20>; 940 }; 941 942 qos_rga_rd: qos@ff550000 { 943 compatible = "syscon"; 944 reg = <0x0 0xff550000 0x0 0x20>; 945 }; 946 947 qos_rga_wr: qos@ff550080 { 948 compatible = "syscon"; 949 reg = <0x0 0xff550080 0x0 0x20>; 950 }; 951 952 qos_vop_m0: qos@ff550100 { 953 compatible = "syscon"; 954 reg = <0x0 0xff550100 0x0 0x20>; 955 }; 956 957 qos_vop_m1: qos@ff550180 { 958 compatible = "syscon"; 959 reg = <0x0 0xff550180 0x0 0x20>; 960 }; 961 962 qos_vpu: qos@ff558000 { 963 compatible = "syscon"; 964 reg = <0x0 0xff558000 0x0 0x20>; 965 }; 966 967 qos_vpu_r128: qos@ff558080 { 968 compatible = "syscon"; 969 reg = <0x0 0xff558080 0x0 0x20>; 970 }; 971 972 pinctrl: pinctrl { 973 compatible = "rockchip,px30-pinctrl"; 974 rockchip,grf = <&grf>; 975 rockchip,pmu = <&pmugrf>; 976 #address-cells = <2>; 977 #size-cells = <2>; 978 ranges; 979 980 gpio0: gpio0@ff040000 { 981 compatible = "rockchip,gpio-bank"; 982 reg = <0x0 0xff040000 0x0 0x100>; 983 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&pmucru PCLK_GPIO0_PMU>; 985 gpio-controller; 986 #gpio-cells = <2>; 987 988 interrupt-controller; 989 #interrupt-cells = <2>; 990 }; 991 992 gpio1: gpio1@ff250000 { 993 compatible = "rockchip,gpio-bank"; 994 reg = <0x0 0xff250000 0x0 0x100>; 995 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&cru PCLK_GPIO1>; 997 gpio-controller; 998 #gpio-cells = <2>; 999 1000 interrupt-controller; 1001 #interrupt-cells = <2>; 1002 }; 1003 1004 gpio2: gpio2@ff260000 { 1005 compatible = "rockchip,gpio-bank"; 1006 reg = <0x0 0xff260000 0x0 0x100>; 1007 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&cru PCLK_GPIO2>; 1009 gpio-controller; 1010 #gpio-cells = <2>; 1011 1012 interrupt-controller; 1013 #interrupt-cells = <2>; 1014 }; 1015 1016 gpio3: gpio3@ff270000 { 1017 compatible = "rockchip,gpio-bank"; 1018 reg = <0x0 0xff270000 0x0 0x100>; 1019 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&cru PCLK_GPIO3>; 1021 gpio-controller; 1022 #gpio-cells = <2>; 1023 1024 interrupt-controller; 1025 #interrupt-cells = <2>; 1026 }; 1027 1028 pcfg_pull_up: pcfg-pull-up { 1029 bias-pull-up; 1030 }; 1031 1032 pcfg_pull_down: pcfg-pull-down { 1033 bias-pull-down; 1034 }; 1035 1036 pcfg_pull_none: pcfg-pull-none { 1037 bias-disable; 1038 }; 1039 1040 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1041 bias-disable; 1042 drive-strength = <2>; 1043 }; 1044 1045 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1046 bias-pull-up; 1047 drive-strength = <2>; 1048 }; 1049 1050 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1051 bias-pull-up; 1052 drive-strength = <4>; 1053 }; 1054 1055 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1056 bias-disable; 1057 drive-strength = <4>; 1058 }; 1059 1060 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1061 bias-pull-down; 1062 drive-strength = <4>; 1063 }; 1064 1065 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1066 bias-disable; 1067 drive-strength = <8>; 1068 }; 1069 1070 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1071 bias-pull-up; 1072 drive-strength = <8>; 1073 }; 1074 1075 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1076 bias-disable; 1077 drive-strength = <12>; 1078 }; 1079 1080 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1081 bias-pull-up; 1082 drive-strength = <12>; 1083 }; 1084 1085 pcfg_pull_none_smt: pcfg-pull-none-smt { 1086 bias-disable; 1087 input-schmitt-enable; 1088 }; 1089 1090 pcfg_output_high: pcfg-output-high { 1091 output-high; 1092 }; 1093 1094 pcfg_output_low: pcfg-output-low { 1095 output-low; 1096 }; 1097 1098 pcfg_input_high: pcfg-input-high { 1099 bias-pull-up; 1100 input-enable; 1101 }; 1102 1103 pcfg_input: pcfg-input { 1104 input-enable; 1105 }; 1106 1107 i2c0 { 1108 i2c0_xfer: i2c0-xfer { 1109 rockchip,pins = 1110 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1111 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1112 }; 1113 }; 1114 1115 i2c1 { 1116 i2c1_xfer: i2c1-xfer { 1117 rockchip,pins = 1118 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1119 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1120 }; 1121 }; 1122 1123 i2c2 { 1124 i2c2_xfer: i2c2-xfer { 1125 rockchip,pins = 1126 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1127 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1128 }; 1129 }; 1130 1131 i2c3 { 1132 i2c3_xfer: i2c3-xfer { 1133 rockchip,pins = 1134 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1135 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1136 }; 1137 }; 1138 1139 tsadc { 1140 tsadc_otp_gpio: tsadc-otp-gpio { 1141 rockchip,pins = 1142 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1143 }; 1144 1145 tsadc_otp_out: tsadc-otp-out { 1146 rockchip,pins = 1147 <0 RK_PA6 1 &pcfg_pull_none>; 1148 }; 1149 }; 1150 1151 uart0 { 1152 uart0_xfer: uart0-xfer { 1153 rockchip,pins = 1154 <0 RK_PB2 1 &pcfg_pull_up>, 1155 <0 RK_PB3 1 &pcfg_pull_up>; 1156 }; 1157 1158 uart0_cts: uart0-cts { 1159 rockchip,pins = 1160 <0 RK_PB4 1 &pcfg_pull_none>; 1161 }; 1162 1163 uart0_rts: uart0-rts { 1164 rockchip,pins = 1165 <0 RK_PB5 1 &pcfg_pull_none>; 1166 }; 1167 }; 1168 1169 uart1 { 1170 uart1_xfer: uart1-xfer { 1171 rockchip,pins = 1172 <1 RK_PC1 1 &pcfg_pull_up>, 1173 <1 RK_PC0 1 &pcfg_pull_up>; 1174 }; 1175 1176 uart1_cts: uart1-cts { 1177 rockchip,pins = 1178 <1 RK_PC2 1 &pcfg_pull_none>; 1179 }; 1180 1181 uart1_rts: uart1-rts { 1182 rockchip,pins = 1183 <1 RK_PC3 1 &pcfg_pull_none>; 1184 }; 1185 }; 1186 1187 uart2-m0 { 1188 uart2m0_xfer: uart2m0-xfer { 1189 rockchip,pins = 1190 <1 RK_PD2 2 &pcfg_pull_up>, 1191 <1 RK_PD3 2 &pcfg_pull_up>; 1192 }; 1193 }; 1194 1195 uart2-m1 { 1196 uart2m1_xfer: uart2m1-xfer { 1197 rockchip,pins = 1198 <2 RK_PB4 2 &pcfg_pull_up>, 1199 <2 RK_PB6 2 &pcfg_pull_up>; 1200 }; 1201 }; 1202 1203 uart3-m0 { 1204 uart3m0_xfer: uart3m0-xfer { 1205 rockchip,pins = 1206 <0 RK_PC0 2 &pcfg_pull_up>, 1207 <0 RK_PC1 2 &pcfg_pull_up>; 1208 }; 1209 1210 uart3m0_cts: uart3m0-cts { 1211 rockchip,pins = 1212 <0 RK_PC2 2 &pcfg_pull_none>; 1213 }; 1214 1215 uart3m0_rts: uart3m0-rts { 1216 rockchip,pins = 1217 <0 RK_PC3 2 &pcfg_pull_none>; 1218 }; 1219 }; 1220 1221 uart3-m1 { 1222 uart3m1_xfer: uart3m1-xfer { 1223 rockchip,pins = 1224 <1 RK_PB6 2 &pcfg_pull_up>, 1225 <1 RK_PB7 2 &pcfg_pull_up>; 1226 }; 1227 1228 uart3m1_cts: uart3m1-cts { 1229 rockchip,pins = 1230 <1 RK_PB4 2 &pcfg_pull_none>; 1231 }; 1232 1233 uart3m1_rts: uart3m1-rts { 1234 rockchip,pins = 1235 <1 RK_PB5 2 &pcfg_pull_none>; 1236 }; 1237 }; 1238 1239 uart4 { 1240 uart4_xfer: uart4-xfer { 1241 rockchip,pins = 1242 <1 RK_PD4 2 &pcfg_pull_up>, 1243 <1 RK_PD5 2 &pcfg_pull_up>; 1244 }; 1245 1246 uart4_cts: uart4-cts { 1247 rockchip,pins = 1248 <1 RK_PD6 2 &pcfg_pull_none>; 1249 }; 1250 1251 uart4_rts: uart4-rts { 1252 rockchip,pins = 1253 <1 RK_PD7 2 &pcfg_pull_none>; 1254 }; 1255 }; 1256 1257 uart5 { 1258 uart5_xfer: uart5-xfer { 1259 rockchip,pins = 1260 <3 RK_PA2 4 &pcfg_pull_up>, 1261 <3 RK_PA1 4 &pcfg_pull_up>; 1262 }; 1263 1264 uart5_cts: uart5-cts { 1265 rockchip,pins = 1266 <3 RK_PA3 4 &pcfg_pull_none>; 1267 }; 1268 1269 uart5_rts: uart5-rts { 1270 rockchip,pins = 1271 <3 RK_PA5 4 &pcfg_pull_none>; 1272 }; 1273 }; 1274 1275 spi0 { 1276 spi0_clk: spi0-clk { 1277 rockchip,pins = 1278 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1279 }; 1280 1281 spi0_csn: spi0-csn { 1282 rockchip,pins = 1283 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1284 }; 1285 1286 spi0_miso: spi0-miso { 1287 rockchip,pins = 1288 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1289 }; 1290 1291 spi0_mosi: spi0-mosi { 1292 rockchip,pins = 1293 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1294 }; 1295 1296 spi0_clk_hs: spi0-clk-hs { 1297 rockchip,pins = 1298 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1299 }; 1300 1301 spi0_miso_hs: spi0-miso-hs { 1302 rockchip,pins = 1303 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1304 }; 1305 1306 spi0_mosi_hs: spi0-mosi-hs { 1307 rockchip,pins = 1308 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1309 }; 1310 }; 1311 1312 spi1 { 1313 spi1_clk: spi1-clk { 1314 rockchip,pins = 1315 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1316 }; 1317 1318 spi1_csn0: spi1-csn0 { 1319 rockchip,pins = 1320 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1321 }; 1322 1323 spi1_csn1: spi1-csn1 { 1324 rockchip,pins = 1325 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1326 }; 1327 1328 spi1_miso: spi1-miso { 1329 rockchip,pins = 1330 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1331 }; 1332 1333 spi1_mosi: spi1-mosi { 1334 rockchip,pins = 1335 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1336 }; 1337 1338 spi1_clk_hs: spi1-clk-hs { 1339 rockchip,pins = 1340 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1341 }; 1342 1343 spi1_miso_hs: spi1-miso-hs { 1344 rockchip,pins = 1345 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1346 }; 1347 1348 spi1_mosi_hs: spi1-mosi-hs { 1349 rockchip,pins = 1350 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1351 }; 1352 }; 1353 1354 pdm { 1355 pdm_clk0m0: pdm-clk0m0 { 1356 rockchip,pins = 1357 <3 RK_PC6 2 &pcfg_pull_none>; 1358 }; 1359 1360 pdm_clk0m1: pdm-clk0m1 { 1361 rockchip,pins = 1362 <2 RK_PC6 1 &pcfg_pull_none>; 1363 }; 1364 1365 pdm_clk1: pdm-clk1 { 1366 rockchip,pins = 1367 <3 RK_PC7 2 &pcfg_pull_none>; 1368 }; 1369 1370 pdm_sdi0m0: pdm-sdi0m0 { 1371 rockchip,pins = 1372 <3 RK_PD3 2 &pcfg_pull_none>; 1373 }; 1374 1375 pdm_sdi0m1: pdm-sdi0m1 { 1376 rockchip,pins = 1377 <2 RK_PC5 2 &pcfg_pull_none>; 1378 }; 1379 1380 pdm_sdi1: pdm-sdi1 { 1381 rockchip,pins = 1382 <3 RK_PD0 2 &pcfg_pull_none>; 1383 }; 1384 1385 pdm_sdi2: pdm-sdi2 { 1386 rockchip,pins = 1387 <3 RK_PD1 2 &pcfg_pull_none>; 1388 }; 1389 1390 pdm_sdi3: pdm-sdi3 { 1391 rockchip,pins = 1392 <3 RK_PD2 2 &pcfg_pull_none>; 1393 }; 1394 1395 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1396 rockchip,pins = 1397 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1398 }; 1399 1400 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1401 rockchip,pins = 1402 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1403 }; 1404 1405 pdm_clk1_sleep: pdm-clk1-sleep { 1406 rockchip,pins = 1407 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1408 }; 1409 1410 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1411 rockchip,pins = 1412 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1413 }; 1414 1415 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1416 rockchip,pins = 1417 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1418 }; 1419 1420 pdm_sdi1_sleep: pdm-sdi1-sleep { 1421 rockchip,pins = 1422 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1423 }; 1424 1425 pdm_sdi2_sleep: pdm-sdi2-sleep { 1426 rockchip,pins = 1427 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1428 }; 1429 1430 pdm_sdi3_sleep: pdm-sdi3-sleep { 1431 rockchip,pins = 1432 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1433 }; 1434 }; 1435 1436 i2s0 { 1437 i2s0_8ch_mclk: i2s0-8ch-mclk { 1438 rockchip,pins = 1439 <3 RK_PC1 2 &pcfg_pull_none>; 1440 }; 1441 1442 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1443 rockchip,pins = 1444 <3 RK_PC3 2 &pcfg_pull_none>; 1445 }; 1446 1447 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1448 rockchip,pins = 1449 <3 RK_PB4 2 &pcfg_pull_none>; 1450 }; 1451 1452 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1453 rockchip,pins = 1454 <3 RK_PC2 2 &pcfg_pull_none>; 1455 }; 1456 1457 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1458 rockchip,pins = 1459 <3 RK_PB5 2 &pcfg_pull_none>; 1460 }; 1461 1462 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1463 rockchip,pins = 1464 <3 RK_PC4 2 &pcfg_pull_none>; 1465 }; 1466 1467 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1468 rockchip,pins = 1469 <3 RK_PC0 2 &pcfg_pull_none>; 1470 }; 1471 1472 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1473 rockchip,pins = 1474 <3 RK_PB7 2 &pcfg_pull_none>; 1475 }; 1476 1477 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1478 rockchip,pins = 1479 <3 RK_PB6 2 &pcfg_pull_none>; 1480 }; 1481 1482 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1483 rockchip,pins = 1484 <3 RK_PC5 2 &pcfg_pull_none>; 1485 }; 1486 1487 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1488 rockchip,pins = 1489 <3 RK_PB3 2 &pcfg_pull_none>; 1490 }; 1491 1492 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1493 rockchip,pins = 1494 <3 RK_PB1 2 &pcfg_pull_none>; 1495 }; 1496 1497 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1498 rockchip,pins = 1499 <3 RK_PB0 2 &pcfg_pull_none>; 1500 }; 1501 }; 1502 1503 i2s1 { 1504 i2s1_2ch_mclk: i2s1-2ch-mclk { 1505 rockchip,pins = 1506 <2 RK_PC3 1 &pcfg_pull_none>; 1507 }; 1508 1509 i2s1_2ch_sclk: i2s1-2ch-sclk { 1510 rockchip,pins = 1511 <2 RK_PC2 1 &pcfg_pull_none>; 1512 }; 1513 1514 i2s1_2ch_lrck: i2s1-2ch-lrck { 1515 rockchip,pins = 1516 <2 RK_PC1 1 &pcfg_pull_none>; 1517 }; 1518 1519 i2s1_2ch_sdi: i2s1-2ch-sdi { 1520 rockchip,pins = 1521 <2 RK_PC5 1 &pcfg_pull_none>; 1522 }; 1523 1524 i2s1_2ch_sdo: i2s1-2ch-sdo { 1525 rockchip,pins = 1526 <2 RK_PC4 1 &pcfg_pull_none>; 1527 }; 1528 }; 1529 1530 i2s2 { 1531 i2s2_2ch_mclk: i2s2-2ch-mclk { 1532 rockchip,pins = 1533 <3 RK_PA1 2 &pcfg_pull_none>; 1534 }; 1535 1536 i2s2_2ch_sclk: i2s2-2ch-sclk { 1537 rockchip,pins = 1538 <3 RK_PA2 2 &pcfg_pull_none>; 1539 }; 1540 1541 i2s2_2ch_lrck: i2s2-2ch-lrck { 1542 rockchip,pins = 1543 <3 RK_PA3 2 &pcfg_pull_none>; 1544 }; 1545 1546 i2s2_2ch_sdi: i2s2-2ch-sdi { 1547 rockchip,pins = 1548 <3 RK_PA5 2 &pcfg_pull_none>; 1549 }; 1550 1551 i2s2_2ch_sdo: i2s2-2ch-sdo { 1552 rockchip,pins = 1553 <3 RK_PA7 2 &pcfg_pull_none>; 1554 }; 1555 }; 1556 1557 sdmmc { 1558 sdmmc_clk: sdmmc-clk { 1559 rockchip,pins = 1560 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1561 }; 1562 1563 sdmmc_cmd: sdmmc-cmd { 1564 rockchip,pins = 1565 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1566 }; 1567 1568 sdmmc_det: sdmmc-det { 1569 rockchip,pins = 1570 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1571 }; 1572 1573 sdmmc_bus1: sdmmc-bus1 { 1574 rockchip,pins = 1575 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1576 }; 1577 1578 sdmmc_bus4: sdmmc-bus4 { 1579 rockchip,pins = 1580 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1581 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1582 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1583 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1584 }; 1585 }; 1586 1587 sdio { 1588 sdio_clk: sdio-clk { 1589 rockchip,pins = 1590 <1 RK_PC5 1 &pcfg_pull_none>; 1591 }; 1592 1593 sdio_cmd: sdio-cmd { 1594 rockchip,pins = 1595 <1 RK_PC4 1 &pcfg_pull_up>; 1596 }; 1597 1598 sdio_bus4: sdio-bus4 { 1599 rockchip,pins = 1600 <1 RK_PC6 1 &pcfg_pull_up>, 1601 <1 RK_PC7 1 &pcfg_pull_up>, 1602 <1 RK_PD0 1 &pcfg_pull_up>, 1603 <1 RK_PD1 1 &pcfg_pull_up>; 1604 }; 1605 }; 1606 1607 emmc { 1608 emmc_clk: emmc-clk { 1609 rockchip,pins = 1610 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 1611 }; 1612 1613 emmc_cmd: emmc-cmd { 1614 rockchip,pins = 1615 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 1616 }; 1617 1618 emmc_rstnout: emmc-rstnout { 1619 rockchip,pins = 1620 <1 RK_PB3 2 &pcfg_pull_none>; 1621 }; 1622 1623 emmc_bus1: emmc-bus1 { 1624 rockchip,pins = 1625 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 1626 }; 1627 1628 emmc_bus4: emmc-bus4 { 1629 rockchip,pins = 1630 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1631 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1632 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1633 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 1634 }; 1635 1636 emmc_bus8: emmc-bus8 { 1637 rockchip,pins = 1638 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1639 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1640 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1641 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 1642 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 1643 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 1644 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 1645 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 1646 }; 1647 }; 1648 1649 flash { 1650 flash_cs0: flash-cs0 { 1651 rockchip,pins = 1652 <1 RK_PB0 1 &pcfg_pull_none>; 1653 }; 1654 1655 flash_rdy: flash-rdy { 1656 rockchip,pins = 1657 <1 RK_PB1 1 &pcfg_pull_none>; 1658 }; 1659 1660 flash_dqs: flash-dqs { 1661 rockchip,pins = 1662 <1 RK_PB2 1 &pcfg_pull_none>; 1663 }; 1664 1665 flash_ale: flash-ale { 1666 rockchip,pins = 1667 <1 RK_PB3 1 &pcfg_pull_none>; 1668 }; 1669 1670 flash_cle: flash-cle { 1671 rockchip,pins = 1672 <1 RK_PB4 1 &pcfg_pull_none>; 1673 }; 1674 1675 flash_wrn: flash-wrn { 1676 rockchip,pins = 1677 <1 RK_PB5 1 &pcfg_pull_none>; 1678 }; 1679 1680 flash_csl: flash-csl { 1681 rockchip,pins = 1682 <1 RK_PB6 1 &pcfg_pull_none>; 1683 }; 1684 1685 flash_rdn: flash-rdn { 1686 rockchip,pins = 1687 <1 RK_PB7 1 &pcfg_pull_none>; 1688 }; 1689 1690 flash_bus8: flash-bus8 { 1691 rockchip,pins = 1692 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 1693 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 1694 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 1695 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 1696 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 1697 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 1698 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 1699 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 1700 }; 1701 }; 1702 1703 lcdc { 1704 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1705 rockchip,pins = 1706 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 1707 }; 1708 1709 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1710 rockchip,pins = 1711 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 1712 }; 1713 1714 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1715 rockchip,pins = 1716 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 1717 }; 1718 1719 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1720 rockchip,pins = 1721 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 1722 }; 1723 1724 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1725 rockchip,pins = 1726 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1727 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1728 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1729 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1730 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1731 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1732 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1733 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1734 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1735 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1736 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1737 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 1738 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1739 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1740 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1741 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1742 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 1743 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 1744 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1745 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 1746 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 1747 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 1748 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 1749 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 1750 }; 1751 1752 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 1753 rockchip,pins = 1754 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1755 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1756 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1757 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1758 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1759 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1760 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1761 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1762 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1763 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1764 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1765 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 1766 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1767 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1768 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1769 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1770 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1771 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 1772 }; 1773 1774 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 1775 rockchip,pins = 1776 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1777 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1778 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1779 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1780 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1781 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1782 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1783 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1784 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1785 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1786 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1787 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 1788 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1789 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1790 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1791 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 1792 }; 1793 1794 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 1795 rockchip,pins = 1796 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1797 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1798 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1799 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1800 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1801 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1802 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1803 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1804 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1805 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 1806 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 1807 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1808 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 1809 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 1810 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 1811 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 1812 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 1813 }; 1814 1815 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 1816 rockchip,pins = 1817 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1818 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1819 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1820 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1821 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1822 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1823 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1824 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1825 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1826 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1827 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 1828 }; 1829 1830 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 1831 rockchip,pins = 1832 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1833 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1834 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1835 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1836 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1837 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1838 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1839 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1840 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 1841 }; 1842 }; 1843 1844 pwm0 { 1845 pwm0_pin: pwm0-pin { 1846 rockchip,pins = 1847 <0 RK_PB7 1 &pcfg_pull_none>; 1848 }; 1849 }; 1850 1851 pwm1 { 1852 pwm1_pin: pwm1-pin { 1853 rockchip,pins = 1854 <0 RK_PC0 1 &pcfg_pull_none>; 1855 }; 1856 }; 1857 1858 pwm2 { 1859 pwm2_pin: pwm2-pin { 1860 rockchip,pins = 1861 <2 RK_PB5 1 &pcfg_pull_none>; 1862 }; 1863 }; 1864 1865 pwm3 { 1866 pwm3_pin: pwm3-pin { 1867 rockchip,pins = 1868 <0 RK_PC1 1 &pcfg_pull_none>; 1869 }; 1870 }; 1871 1872 pwm4 { 1873 pwm4_pin: pwm4-pin { 1874 rockchip,pins = 1875 <3 RK_PC2 3 &pcfg_pull_none>; 1876 }; 1877 }; 1878 1879 pwm5 { 1880 pwm5_pin: pwm5-pin { 1881 rockchip,pins = 1882 <3 RK_PC3 3 &pcfg_pull_none>; 1883 }; 1884 }; 1885 1886 pwm6 { 1887 pwm6_pin: pwm6-pin { 1888 rockchip,pins = 1889 <3 RK_PC4 3 &pcfg_pull_none>; 1890 }; 1891 }; 1892 1893 pwm7 { 1894 pwm7_pin: pwm7-pin { 1895 rockchip,pins = 1896 <3 RK_PC5 3 &pcfg_pull_none>; 1897 }; 1898 }; 1899 1900 gmac { 1901 rmii_pins: rmii-pins { 1902 rockchip,pins = 1903 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 1904 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 1905 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 1906 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 1907 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 1908 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 1909 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 1910 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 1911 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 1912 }; 1913 1914 mac_refclk_12ma: mac-refclk-12ma { 1915 rockchip,pins = 1916 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 1917 }; 1918 1919 mac_refclk: mac-refclk { 1920 rockchip,pins = 1921 <2 RK_PB2 2 &pcfg_pull_none>; 1922 }; 1923 }; 1924 1925 cif-m0 { 1926 cif_clkout_m0: cif-clkout-m0 { 1927 rockchip,pins = 1928 <2 RK_PB3 1 &pcfg_pull_none>; 1929 }; 1930 1931 dvp_d2d9_m0: dvp-d2d9-m0 { 1932 rockchip,pins = 1933 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 1934 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 1935 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 1936 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 1937 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 1938 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 1939 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 1940 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 1941 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 1942 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 1943 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 1944 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 1945 }; 1946 1947 dvp_d0d1_m0: dvp-d0d1-m0 { 1948 rockchip,pins = 1949 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 1950 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 1951 }; 1952 1953 dvp_d10d11_m0:d10-d11-m0 { 1954 rockchip,pins = 1955 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 1956 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 1957 }; 1958 }; 1959 1960 cif-m1 { 1961 cif_clkout_m1: cif-clkout-m1 { 1962 rockchip,pins = 1963 <3 RK_PD0 3 &pcfg_pull_none>; 1964 }; 1965 1966 dvp_d2d9_m1: dvp-d2d9-m1 { 1967 rockchip,pins = 1968 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 1969 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 1970 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 1971 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 1972 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 1973 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 1974 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 1975 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 1976 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 1977 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 1978 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 1979 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 1980 }; 1981 1982 dvp_d0d1_m1: dvp-d0d1-m1 { 1983 rockchip,pins = 1984 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 1985 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 1986 }; 1987 1988 dvp_d10d11_m1:d10-d11-m1 { 1989 rockchip,pins = 1990 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 1991 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 1992 }; 1993 }; 1994 1995 isp { 1996 isp_prelight: isp-prelight { 1997 rockchip,pins = 1998 <3 RK_PD1 4 &pcfg_pull_none>; 1999 }; 2000 }; 2001 }; 2002}; 2003