1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 serial3 = &uart3; 32 serial4 = &uart4; 33 serial5 = &uart5; 34 spi0 = &spi0; 35 spi1 = &spi1; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a35"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 clocks = <&cru ARMCLK>; 48 #cooling-cells = <2>; 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 50 dynamic-power-coefficient = <90>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 #cooling-cells = <2>; 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 62 dynamic-power-coefficient = <90>; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 clocks = <&cru ARMCLK>; 72 #cooling-cells = <2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 74 dynamic-power-coefficient = <90>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 }; 77 78 cpu3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a35"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 #cooling-cells = <2>; 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 86 dynamic-power-coefficient = <90>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 102 CLUSTER_SLEEP: cluster-sleep { 103 compatible = "arm,idle-state"; 104 local-timer-stop; 105 arm,psci-suspend-param = <0x1010000>; 106 entry-latency-us = <400>; 107 exit-latency-us = <500>; 108 min-residency-us = <2000>; 109 }; 110 }; 111 }; 112 113 cpu0_opp_table: cpu0-opp-table { 114 compatible = "operating-points-v2"; 115 opp-shared; 116 117 opp-600000000 { 118 opp-hz = /bits/ 64 <600000000>; 119 opp-microvolt = <950000 950000 1350000>; 120 clock-latency-ns = <40000>; 121 opp-suspend; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1050000 1050000 1350000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1175000 1175000 1350000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1300000 1300000 1350000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1350000 1350000 1350000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vopb_out>, <&vopl_out>; 157 status = "disabled"; 158 }; 159 160 gmac_clkin: external-gmac-clock { 161 compatible = "fixed-clock"; 162 clock-frequency = <50000000>; 163 clock-output-names = "gmac_clkin"; 164 #clock-cells = <0>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 178 }; 179 180 thermal_zones: thermal-zones { 181 soc_thermal: soc-thermal { 182 polling-delay-passive = <20>; 183 polling-delay = <1000>; 184 sustainable-power = <750>; 185 thermal-sensors = <&tsadc 0>; 186 187 trips { 188 threshold: trip-point-0 { 189 temperature = <70000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 target: trip-point-1 { 195 temperature = <85000>; 196 hysteresis = <2000>; 197 type = "passive"; 198 }; 199 200 soc_crit: soc-crit { 201 temperature = <115000>; 202 hysteresis = <2000>; 203 type = "critical"; 204 }; 205 }; 206 207 cooling-maps { 208 map0 { 209 trip = <&target>; 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211 contribution = <4096>; 212 }; 213 214 map1 { 215 trip = <&target>; 216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 217 contribution = <4096>; 218 }; 219 }; 220 }; 221 222 gpu_thermal: gpu-thermal { 223 polling-delay-passive = <100>; /* milliseconds */ 224 polling-delay = <1000>; /* milliseconds */ 225 thermal-sensors = <&tsadc 1>; 226 }; 227 }; 228 229 xin24m: xin24m { 230 compatible = "fixed-clock"; 231 #clock-cells = <0>; 232 clock-frequency = <24000000>; 233 clock-output-names = "xin24m"; 234 }; 235 236 pmu: power-management@ff000000 { 237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 238 reg = <0x0 0xff000000 0x0 0x1000>; 239 240 power: power-controller { 241 compatible = "rockchip,px30-power-controller"; 242 #power-domain-cells = <1>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 /* These power domains are grouped by VD_LOGIC */ 247 pd_usb@PX30_PD_USB { 248 reg = <PX30_PD_USB>; 249 clocks = <&cru HCLK_HOST>, 250 <&cru HCLK_OTG>, 251 <&cru SCLK_OTG_ADP>; 252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 253 }; 254 pd_sdcard@PX30_PD_SDCARD { 255 reg = <PX30_PD_SDCARD>; 256 clocks = <&cru HCLK_SDMMC>, 257 <&cru SCLK_SDMMC>; 258 pm_qos = <&qos_sdmmc>; 259 }; 260 pd_gmac@PX30_PD_GMAC { 261 reg = <PX30_PD_GMAC>; 262 clocks = <&cru ACLK_GMAC>, 263 <&cru PCLK_GMAC>, 264 <&cru SCLK_MAC_REF>, 265 <&cru SCLK_GMAC_RX_TX>; 266 pm_qos = <&qos_gmac>; 267 }; 268 pd_mmc_nand@PX30_PD_MMC_NAND { 269 reg = <PX30_PD_MMC_NAND>; 270 clocks = <&cru HCLK_NANDC>, 271 <&cru HCLK_EMMC>, 272 <&cru HCLK_SDIO>, 273 <&cru HCLK_SFC>, 274 <&cru SCLK_EMMC>, 275 <&cru SCLK_NANDC>, 276 <&cru SCLK_SDIO>, 277 <&cru SCLK_SFC>; 278 pm_qos = <&qos_emmc>, <&qos_nand>, 279 <&qos_sdio>, <&qos_sfc>; 280 }; 281 pd_vpu@PX30_PD_VPU { 282 reg = <PX30_PD_VPU>; 283 clocks = <&cru ACLK_VPU>, 284 <&cru HCLK_VPU>, 285 <&cru SCLK_CORE_VPU>; 286 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 287 }; 288 pd_vo@PX30_PD_VO { 289 reg = <PX30_PD_VO>; 290 clocks = <&cru ACLK_RGA>, 291 <&cru ACLK_VOPB>, 292 <&cru ACLK_VOPL>, 293 <&cru DCLK_VOPB>, 294 <&cru DCLK_VOPL>, 295 <&cru HCLK_RGA>, 296 <&cru HCLK_VOPB>, 297 <&cru HCLK_VOPL>, 298 <&cru PCLK_MIPI_DSI>, 299 <&cru SCLK_RGA_CORE>, 300 <&cru SCLK_VOPB_PWM>; 301 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 302 <&qos_vop_m0>, <&qos_vop_m1>; 303 }; 304 pd_vi@PX30_PD_VI { 305 reg = <PX30_PD_VI>; 306 clocks = <&cru ACLK_CIF>, 307 <&cru ACLK_ISP>, 308 <&cru HCLK_CIF>, 309 <&cru HCLK_ISP>, 310 <&cru SCLK_ISP>; 311 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 312 <&qos_isp_wr>, <&qos_isp_m1>, 313 <&qos_vip>; 314 }; 315 pd_gpu@PX30_PD_GPU { 316 reg = <PX30_PD_GPU>; 317 clocks = <&cru SCLK_GPU>; 318 pm_qos = <&qos_gpu>; 319 }; 320 }; 321 }; 322 323 pmugrf: syscon@ff010000 { 324 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 325 reg = <0x0 0xff010000 0x0 0x1000>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 329 pmu_io_domains: io-domains { 330 compatible = "rockchip,px30-pmu-io-voltage-domain"; 331 status = "disabled"; 332 }; 333 334 reboot-mode { 335 compatible = "syscon-reboot-mode"; 336 offset = <0x200>; 337 mode-bootloader = <BOOT_BL_DOWNLOAD>; 338 mode-fastboot = <BOOT_FASTBOOT>; 339 mode-loader = <BOOT_BL_DOWNLOAD>; 340 mode-normal = <BOOT_NORMAL>; 341 mode-recovery = <BOOT_RECOVERY>; 342 }; 343 }; 344 345 uart0: serial@ff030000 { 346 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 347 reg = <0x0 0xff030000 0x0 0x100>; 348 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 350 clock-names = "baudclk", "apb_pclk"; 351 dmas = <&dmac 0>, <&dmac 1>; 352 dma-names = "tx", "rx"; 353 reg-shift = <2>; 354 reg-io-width = <4>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 357 status = "disabled"; 358 }; 359 360 i2s1_2ch: i2s@ff070000 { 361 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 362 reg = <0x0 0xff070000 0x0 0x1000>; 363 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 365 clock-names = "i2s_clk", "i2s_hclk"; 366 dmas = <&dmac 18>, <&dmac 19>; 367 dma-names = "tx", "rx"; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 370 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 371 #sound-dai-cells = <0>; 372 status = "disabled"; 373 }; 374 375 i2s2_2ch: i2s@ff080000 { 376 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 377 reg = <0x0 0xff080000 0x0 0x1000>; 378 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 380 clock-names = "i2s_clk", "i2s_hclk"; 381 dmas = <&dmac 20>, <&dmac 21>; 382 dma-names = "tx", "rx"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 385 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 386 #sound-dai-cells = <0>; 387 status = "disabled"; 388 }; 389 390 gic: interrupt-controller@ff131000 { 391 compatible = "arm,gic-400"; 392 #interrupt-cells = <3>; 393 #address-cells = <0>; 394 interrupt-controller; 395 reg = <0x0 0xff131000 0 0x1000>, 396 <0x0 0xff132000 0 0x2000>, 397 <0x0 0xff134000 0 0x2000>, 398 <0x0 0xff136000 0 0x2000>; 399 interrupts = <GIC_PPI 9 400 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 401 }; 402 403 grf: syscon@ff140000 { 404 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 405 reg = <0x0 0xff140000 0x0 0x1000>; 406 #address-cells = <1>; 407 #size-cells = <1>; 408 409 io_domains: io-domains { 410 compatible = "rockchip,px30-io-voltage-domain"; 411 status = "disabled"; 412 }; 413 414 lvds: lvds { 415 compatible = "rockchip,px30-lvds"; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 phys = <&dsi_dphy>; 419 phy-names = "dphy"; 420 rockchip,grf = <&grf>; 421 rockchip,output = "lvds"; 422 status = "disabled"; 423 424 port@0 { 425 reg = <0>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 429 lvds_vopb_in: endpoint@0 { 430 reg = <0>; 431 remote-endpoint = <&vopb_out_lvds>; 432 }; 433 434 lvds_vopl_in: endpoint@1 { 435 reg = <1>; 436 remote-endpoint = <&vopl_out_lvds>; 437 }; 438 }; 439 }; 440 }; 441 442 uart1: serial@ff158000 { 443 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 444 reg = <0x0 0xff158000 0x0 0x100>; 445 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 447 clock-names = "baudclk", "apb_pclk"; 448 dmas = <&dmac 2>, <&dmac 3>; 449 dma-names = "tx", "rx"; 450 reg-shift = <2>; 451 reg-io-width = <4>; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 454 status = "disabled"; 455 }; 456 457 uart2: serial@ff160000 { 458 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 459 reg = <0x0 0xff160000 0x0 0x100>; 460 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 462 clock-names = "baudclk", "apb_pclk"; 463 dmas = <&dmac 4>, <&dmac 5>; 464 dma-names = "tx", "rx"; 465 reg-shift = <2>; 466 reg-io-width = <4>; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&uart2m0_xfer>; 469 status = "disabled"; 470 }; 471 472 uart3: serial@ff168000 { 473 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 474 reg = <0x0 0xff168000 0x0 0x100>; 475 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 477 clock-names = "baudclk", "apb_pclk"; 478 dmas = <&dmac 6>, <&dmac 7>; 479 dma-names = "tx", "rx"; 480 reg-shift = <2>; 481 reg-io-width = <4>; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 484 status = "disabled"; 485 }; 486 487 uart4: serial@ff170000 { 488 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 489 reg = <0x0 0xff170000 0x0 0x100>; 490 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 492 clock-names = "baudclk", "apb_pclk"; 493 dmas = <&dmac 8>, <&dmac 9>; 494 dma-names = "tx", "rx"; 495 reg-shift = <2>; 496 reg-io-width = <4>; 497 pinctrl-names = "default"; 498 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 499 status = "disabled"; 500 }; 501 502 uart5: serial@ff178000 { 503 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 504 reg = <0x0 0xff178000 0x0 0x100>; 505 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 507 clock-names = "baudclk", "apb_pclk"; 508 dmas = <&dmac 10>, <&dmac 11>; 509 dma-names = "tx", "rx"; 510 reg-shift = <2>; 511 reg-io-width = <4>; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 514 status = "disabled"; 515 }; 516 517 i2c0: i2c@ff180000 { 518 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 519 reg = <0x0 0xff180000 0x0 0x1000>; 520 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 521 clock-names = "i2c", "pclk"; 522 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 523 pinctrl-names = "default"; 524 pinctrl-0 = <&i2c0_xfer>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 status = "disabled"; 528 }; 529 530 i2c1: i2c@ff190000 { 531 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 532 reg = <0x0 0xff190000 0x0 0x1000>; 533 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 534 clock-names = "i2c", "pclk"; 535 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&i2c1_xfer>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 status = "disabled"; 541 }; 542 543 i2c2: i2c@ff1a0000 { 544 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 545 reg = <0x0 0xff1a0000 0x0 0x1000>; 546 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 547 clock-names = "i2c", "pclk"; 548 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 549 pinctrl-names = "default"; 550 pinctrl-0 = <&i2c2_xfer>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 status = "disabled"; 554 }; 555 556 i2c3: i2c@ff1b0000 { 557 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 558 reg = <0x0 0xff1b0000 0x0 0x1000>; 559 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 560 clock-names = "i2c", "pclk"; 561 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&i2c3_xfer>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 status = "disabled"; 567 }; 568 569 spi0: spi@ff1d0000 { 570 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 571 reg = <0x0 0xff1d0000 0x0 0x1000>; 572 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 574 clock-names = "spiclk", "apb_pclk"; 575 dmas = <&dmac 12>, <&dmac 13>; 576 dma-names = "tx", "rx"; 577 pinctrl-names = "default"; 578 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 status = "disabled"; 582 }; 583 584 spi1: spi@ff1d8000 { 585 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 586 reg = <0x0 0xff1d8000 0x0 0x1000>; 587 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 589 clock-names = "spiclk", "apb_pclk"; 590 dmas = <&dmac 14>, <&dmac 15>; 591 dma-names = "tx", "rx"; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 status = "disabled"; 597 }; 598 599 wdt: watchdog@ff1e0000 { 600 compatible = "snps,dw-wdt"; 601 reg = <0x0 0xff1e0000 0x0 0x100>; 602 clocks = <&cru PCLK_WDT_NS>; 603 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 604 status = "disabled"; 605 }; 606 607 pwm0: pwm@ff200000 { 608 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 609 reg = <0x0 0xff200000 0x0 0x10>; 610 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 611 clock-names = "pwm", "pclk"; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&pwm0_pin>; 614 #pwm-cells = <3>; 615 status = "disabled"; 616 }; 617 618 pwm1: pwm@ff200010 { 619 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 620 reg = <0x0 0xff200010 0x0 0x10>; 621 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 622 clock-names = "pwm", "pclk"; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&pwm1_pin>; 625 #pwm-cells = <3>; 626 status = "disabled"; 627 }; 628 629 pwm2: pwm@ff200020 { 630 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 631 reg = <0x0 0xff200020 0x0 0x10>; 632 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 633 clock-names = "pwm", "pclk"; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&pwm2_pin>; 636 #pwm-cells = <3>; 637 status = "disabled"; 638 }; 639 640 pwm3: pwm@ff200030 { 641 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 642 reg = <0x0 0xff200030 0x0 0x10>; 643 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 644 clock-names = "pwm", "pclk"; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&pwm3_pin>; 647 #pwm-cells = <3>; 648 status = "disabled"; 649 }; 650 651 pwm4: pwm@ff208000 { 652 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 653 reg = <0x0 0xff208000 0x0 0x10>; 654 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 655 clock-names = "pwm", "pclk"; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&pwm4_pin>; 658 #pwm-cells = <3>; 659 status = "disabled"; 660 }; 661 662 pwm5: pwm@ff208010 { 663 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 664 reg = <0x0 0xff208010 0x0 0x10>; 665 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 666 clock-names = "pwm", "pclk"; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pwm5_pin>; 669 #pwm-cells = <3>; 670 status = "disabled"; 671 }; 672 673 pwm6: pwm@ff208020 { 674 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 675 reg = <0x0 0xff208020 0x0 0x10>; 676 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 677 clock-names = "pwm", "pclk"; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&pwm6_pin>; 680 #pwm-cells = <3>; 681 status = "disabled"; 682 }; 683 684 pwm7: pwm@ff208030 { 685 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 686 reg = <0x0 0xff208030 0x0 0x10>; 687 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 688 clock-names = "pwm", "pclk"; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&pwm7_pin>; 691 #pwm-cells = <3>; 692 status = "disabled"; 693 }; 694 695 rktimer: timer@ff210000 { 696 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 697 reg = <0x0 0xff210000 0x0 0x1000>; 698 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 700 clock-names = "pclk", "timer"; 701 }; 702 703 amba { 704 compatible = "simple-bus"; 705 #address-cells = <2>; 706 #size-cells = <2>; 707 ranges; 708 709 dmac: dmac@ff240000 { 710 compatible = "arm,pl330", "arm,primecell"; 711 reg = <0x0 0xff240000 0x0 0x4000>; 712 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&cru ACLK_DMAC>; 715 clock-names = "apb_pclk"; 716 #dma-cells = <1>; 717 }; 718 }; 719 720 tsadc: tsadc@ff280000 { 721 compatible = "rockchip,px30-tsadc"; 722 reg = <0x0 0xff280000 0x0 0x100>; 723 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 724 assigned-clocks = <&cru SCLK_TSADC>; 725 assigned-clock-rates = <50000>; 726 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 727 clock-names = "tsadc", "apb_pclk"; 728 resets = <&cru SRST_TSADC>; 729 reset-names = "tsadc-apb"; 730 rockchip,grf = <&grf>; 731 rockchip,hw-tshut-temp = <120000>; 732 pinctrl-names = "init", "default", "sleep"; 733 pinctrl-0 = <&tsadc_otp_gpio>; 734 pinctrl-1 = <&tsadc_otp_out>; 735 pinctrl-2 = <&tsadc_otp_gpio>; 736 #thermal-sensor-cells = <1>; 737 status = "disabled"; 738 }; 739 740 saradc: saradc@ff288000 { 741 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 742 reg = <0x0 0xff288000 0x0 0x100>; 743 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 744 #io-channel-cells = <1>; 745 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 746 clock-names = "saradc", "apb_pclk"; 747 resets = <&cru SRST_SARADC_P>; 748 reset-names = "saradc-apb"; 749 status = "disabled"; 750 }; 751 752 otp: nvmem@ff290000 { 753 compatible = "rockchip,px30-otp"; 754 reg = <0x0 0xff290000 0x0 0x4000>; 755 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 756 <&cru PCLK_OTP_PHY>; 757 clock-names = "otp", "apb_pclk", "phy"; 758 resets = <&cru SRST_OTP_PHY>; 759 reset-names = "phy"; 760 #address-cells = <1>; 761 #size-cells = <1>; 762 763 /* Data cells */ 764 cpu_id: id@7 { 765 reg = <0x07 0x10>; 766 }; 767 cpu_leakage: cpu-leakage@17 { 768 reg = <0x17 0x1>; 769 }; 770 performance: performance@1e { 771 reg = <0x1e 0x1>; 772 bits = <4 3>; 773 }; 774 }; 775 776 cru: clock-controller@ff2b0000 { 777 compatible = "rockchip,px30-cru"; 778 reg = <0x0 0xff2b0000 0x0 0x1000>; 779 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 780 clock-names = "xin24m", "gpll"; 781 rockchip,grf = <&grf>; 782 #clock-cells = <1>; 783 #reset-cells = <1>; 784 785 assigned-clocks = <&cru PLL_NPLL>, 786 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 787 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 788 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 789 790 assigned-clock-rates = <1188000000>, 791 <200000000>, <200000000>, 792 <150000000>, <150000000>, 793 <100000000>, <200000000>; 794 }; 795 796 pmucru: clock-controller@ff2bc000 { 797 compatible = "rockchip,px30-pmucru"; 798 reg = <0x0 0xff2bc000 0x0 0x1000>; 799 clocks = <&xin24m>; 800 clock-names = "xin24m"; 801 rockchip,grf = <&grf>; 802 #clock-cells = <1>; 803 #reset-cells = <1>; 804 805 assigned-clocks = 806 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 807 <&pmucru SCLK_WIFI_PMU>; 808 assigned-clock-rates = 809 <1200000000>, <100000000>, 810 <26000000>; 811 }; 812 813 usb2phy_grf: syscon@ff2c0000 { 814 compatible = "rockchip,px30-usb2phy-grf", "syscon", 815 "simple-mfd"; 816 reg = <0x0 0xff2c0000 0x0 0x10000>; 817 #address-cells = <1>; 818 #size-cells = <1>; 819 820 u2phy: usb2-phy@100 { 821 compatible = "rockchip,px30-usb2phy"; 822 reg = <0x100 0x20>; 823 clocks = <&pmucru SCLK_USBPHY_REF>; 824 clock-names = "phyclk"; 825 #clock-cells = <0>; 826 assigned-clocks = <&cru USB480M>; 827 assigned-clock-parents = <&u2phy>; 828 clock-output-names = "usb480m_phy"; 829 status = "disabled"; 830 831 u2phy_host: host-port { 832 #phy-cells = <0>; 833 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 834 interrupt-names = "linestate"; 835 status = "disabled"; 836 }; 837 838 u2phy_otg: otg-port { 839 #phy-cells = <0>; 840 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 843 interrupt-names = "otg-bvalid", "otg-id", 844 "linestate"; 845 status = "disabled"; 846 }; 847 }; 848 }; 849 850 dsi_dphy: phy@ff2e0000 { 851 compatible = "rockchip,px30-dsi-dphy"; 852 reg = <0x0 0xff2e0000 0x0 0x10000>; 853 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 854 clock-names = "ref", "pclk"; 855 resets = <&cru SRST_MIPIDSIPHY_P>; 856 reset-names = "apb"; 857 #phy-cells = <0>; 858 power-domains = <&power PX30_PD_VO>; 859 status = "disabled"; 860 }; 861 862 usb20_otg: usb@ff300000 { 863 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 864 "snps,dwc2"; 865 reg = <0x0 0xff300000 0x0 0x40000>; 866 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&cru HCLK_OTG>; 868 clock-names = "otg"; 869 dr_mode = "otg"; 870 g-np-tx-fifo-size = <16>; 871 g-rx-fifo-size = <280>; 872 g-tx-fifo-size = <256 128 128 64 32 16>; 873 g-use-dma; 874 phys = <&u2phy_otg>; 875 phy-names = "usb2-phy"; 876 power-domains = <&power PX30_PD_USB>; 877 status = "disabled"; 878 }; 879 880 usb_host0_ehci: usb@ff340000 { 881 compatible = "generic-ehci"; 882 reg = <0x0 0xff340000 0x0 0x10000>; 883 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&cru HCLK_HOST>; 885 clock-names = "usbhost"; 886 phys = <&u2phy_host>; 887 phy-names = "usb"; 888 power-domains = <&power PX30_PD_USB>; 889 status = "disabled"; 890 }; 891 892 usb_host0_ohci: usb@ff350000 { 893 compatible = "generic-ohci"; 894 reg = <0x0 0xff350000 0x0 0x10000>; 895 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&cru HCLK_HOST>; 897 clock-names = "usbhost"; 898 phys = <&u2phy_host>; 899 phy-names = "usb"; 900 power-domains = <&power PX30_PD_USB>; 901 status = "disabled"; 902 }; 903 904 gmac: ethernet@ff360000 { 905 compatible = "rockchip,px30-gmac"; 906 reg = <0x0 0xff360000 0x0 0x10000>; 907 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 908 interrupt-names = "macirq"; 909 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 910 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 911 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 912 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 913 clock-names = "stmmaceth", "mac_clk_rx", 914 "mac_clk_tx", "clk_mac_ref", 915 "clk_mac_refout", "aclk_mac", 916 "pclk_mac", "clk_mac_speed"; 917 rockchip,grf = <&grf>; 918 phy-mode = "rmii"; 919 pinctrl-names = "default"; 920 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 921 power-domains = <&power PX30_PD_GMAC>; 922 resets = <&cru SRST_GMAC_A>; 923 reset-names = "stmmaceth"; 924 status = "disabled"; 925 }; 926 927 sdmmc: mmc@ff370000 { 928 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 929 reg = <0x0 0xff370000 0x0 0x4000>; 930 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 932 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 933 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 934 fifo-depth = <0x100>; 935 max-frequency = <150000000>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 938 power-domains = <&power PX30_PD_SDCARD>; 939 status = "disabled"; 940 }; 941 942 sdio: mmc@ff380000 { 943 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 944 reg = <0x0 0xff380000 0x0 0x4000>; 945 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 947 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 948 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 949 fifo-depth = <0x100>; 950 max-frequency = <150000000>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 953 power-domains = <&power PX30_PD_MMC_NAND>; 954 status = "disabled"; 955 }; 956 957 emmc: mmc@ff390000 { 958 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 959 reg = <0x0 0xff390000 0x0 0x4000>; 960 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 962 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 963 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 964 fifo-depth = <0x100>; 965 max-frequency = <150000000>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 968 power-domains = <&power PX30_PD_MMC_NAND>; 969 status = "disabled"; 970 }; 971 972 gpu: gpu@ff400000 { 973 compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 974 reg = <0x0 0xff400000 0x0 0x4000>; 975 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 978 interrupt-names = "job", "mmu", "gpu"; 979 clocks = <&cru SCLK_GPU>; 980 #cooling-cells = <2>; 981 power-domains = <&power PX30_PD_GPU>; 982 status = "disabled"; 983 }; 984 985 dsi: dsi@ff450000 { 986 compatible = "rockchip,px30-mipi-dsi"; 987 reg = <0x0 0xff450000 0x0 0x10000>; 988 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&cru PCLK_MIPI_DSI>; 990 clock-names = "pclk"; 991 phys = <&dsi_dphy>; 992 phy-names = "dphy"; 993 power-domains = <&power PX30_PD_VO>; 994 resets = <&cru SRST_MIPIDSI_HOST_P>; 995 reset-names = "apb"; 996 rockchip,grf = <&grf>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 status = "disabled"; 1000 1001 ports { 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 1005 port@0 { 1006 reg = <0>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 1010 dsi_in_vopb: endpoint@0 { 1011 reg = <0>; 1012 remote-endpoint = <&vopb_out_dsi>; 1013 }; 1014 1015 dsi_in_vopl: endpoint@1 { 1016 reg = <1>; 1017 remote-endpoint = <&vopl_out_dsi>; 1018 }; 1019 }; 1020 }; 1021 }; 1022 1023 vopb: vop@ff460000 { 1024 compatible = "rockchip,px30-vop-big"; 1025 reg = <0x0 0xff460000 0x0 0xefc>; 1026 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1028 <&cru HCLK_VOPB>; 1029 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1030 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1031 reset-names = "axi", "ahb", "dclk"; 1032 iommus = <&vopb_mmu>; 1033 power-domains = <&power PX30_PD_VO>; 1034 rockchip,grf = <&grf>; 1035 status = "disabled"; 1036 1037 vopb_out: port { 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 1041 vopb_out_dsi: endpoint@0 { 1042 reg = <0>; 1043 remote-endpoint = <&dsi_in_vopb>; 1044 }; 1045 1046 vopb_out_lvds: endpoint@1 { 1047 reg = <1>; 1048 remote-endpoint = <&lvds_vopb_in>; 1049 }; 1050 }; 1051 }; 1052 1053 vopb_mmu: iommu@ff460f00 { 1054 compatible = "rockchip,iommu"; 1055 reg = <0x0 0xff460f00 0x0 0x100>; 1056 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1057 interrupt-names = "vopb_mmu"; 1058 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1059 clock-names = "aclk", "iface"; 1060 power-domains = <&power PX30_PD_VO>; 1061 #iommu-cells = <0>; 1062 status = "disabled"; 1063 }; 1064 1065 vopl: vop@ff470000 { 1066 compatible = "rockchip,px30-vop-lit"; 1067 reg = <0x0 0xff470000 0x0 0xefc>; 1068 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1069 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1070 <&cru HCLK_VOPL>; 1071 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1072 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1073 reset-names = "axi", "ahb", "dclk"; 1074 iommus = <&vopl_mmu>; 1075 power-domains = <&power PX30_PD_VO>; 1076 rockchip,grf = <&grf>; 1077 status = "disabled"; 1078 1079 vopl_out: port { 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 1083 vopl_out_dsi: endpoint@0 { 1084 reg = <0>; 1085 remote-endpoint = <&dsi_in_vopl>; 1086 }; 1087 1088 vopl_out_lvds: endpoint@1 { 1089 reg = <1>; 1090 remote-endpoint = <&lvds_vopl_in>; 1091 }; 1092 }; 1093 }; 1094 1095 vopl_mmu: iommu@ff470f00 { 1096 compatible = "rockchip,iommu"; 1097 reg = <0x0 0xff470f00 0x0 0x100>; 1098 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1099 interrupt-names = "vopl_mmu"; 1100 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1101 clock-names = "aclk", "iface"; 1102 power-domains = <&power PX30_PD_VO>; 1103 #iommu-cells = <0>; 1104 status = "disabled"; 1105 }; 1106 1107 qos_gmac: qos@ff518000 { 1108 compatible = "syscon"; 1109 reg = <0x0 0xff518000 0x0 0x20>; 1110 }; 1111 1112 qos_gpu: qos@ff520000 { 1113 compatible = "syscon"; 1114 reg = <0x0 0xff520000 0x0 0x20>; 1115 }; 1116 1117 qos_sdmmc: qos@ff52c000 { 1118 compatible = "syscon"; 1119 reg = <0x0 0xff52c000 0x0 0x20>; 1120 }; 1121 1122 qos_emmc: qos@ff538000 { 1123 compatible = "syscon"; 1124 reg = <0x0 0xff538000 0x0 0x20>; 1125 }; 1126 1127 qos_nand: qos@ff538080 { 1128 compatible = "syscon"; 1129 reg = <0x0 0xff538080 0x0 0x20>; 1130 }; 1131 1132 qos_sdio: qos@ff538100 { 1133 compatible = "syscon"; 1134 reg = <0x0 0xff538100 0x0 0x20>; 1135 }; 1136 1137 qos_sfc: qos@ff538180 { 1138 compatible = "syscon"; 1139 reg = <0x0 0xff538180 0x0 0x20>; 1140 }; 1141 1142 qos_usb_host: qos@ff540000 { 1143 compatible = "syscon"; 1144 reg = <0x0 0xff540000 0x0 0x20>; 1145 }; 1146 1147 qos_usb_otg: qos@ff540080 { 1148 compatible = "syscon"; 1149 reg = <0x0 0xff540080 0x0 0x20>; 1150 }; 1151 1152 qos_isp_128: qos@ff548000 { 1153 compatible = "syscon"; 1154 reg = <0x0 0xff548000 0x0 0x20>; 1155 }; 1156 1157 qos_isp_rd: qos@ff548080 { 1158 compatible = "syscon"; 1159 reg = <0x0 0xff548080 0x0 0x20>; 1160 }; 1161 1162 qos_isp_wr: qos@ff548100 { 1163 compatible = "syscon"; 1164 reg = <0x0 0xff548100 0x0 0x20>; 1165 }; 1166 1167 qos_isp_m1: qos@ff548180 { 1168 compatible = "syscon"; 1169 reg = <0x0 0xff548180 0x0 0x20>; 1170 }; 1171 1172 qos_vip: qos@ff548200 { 1173 compatible = "syscon"; 1174 reg = <0x0 0xff548200 0x0 0x20>; 1175 }; 1176 1177 qos_rga_rd: qos@ff550000 { 1178 compatible = "syscon"; 1179 reg = <0x0 0xff550000 0x0 0x20>; 1180 }; 1181 1182 qos_rga_wr: qos@ff550080 { 1183 compatible = "syscon"; 1184 reg = <0x0 0xff550080 0x0 0x20>; 1185 }; 1186 1187 qos_vop_m0: qos@ff550100 { 1188 compatible = "syscon"; 1189 reg = <0x0 0xff550100 0x0 0x20>; 1190 }; 1191 1192 qos_vop_m1: qos@ff550180 { 1193 compatible = "syscon"; 1194 reg = <0x0 0xff550180 0x0 0x20>; 1195 }; 1196 1197 qos_vpu: qos@ff558000 { 1198 compatible = "syscon"; 1199 reg = <0x0 0xff558000 0x0 0x20>; 1200 }; 1201 1202 qos_vpu_r128: qos@ff558080 { 1203 compatible = "syscon"; 1204 reg = <0x0 0xff558080 0x0 0x20>; 1205 }; 1206 1207 pinctrl: pinctrl { 1208 compatible = "rockchip,px30-pinctrl"; 1209 rockchip,grf = <&grf>; 1210 rockchip,pmu = <&pmugrf>; 1211 #address-cells = <2>; 1212 #size-cells = <2>; 1213 ranges; 1214 1215 gpio0: gpio0@ff040000 { 1216 compatible = "rockchip,gpio-bank"; 1217 reg = <0x0 0xff040000 0x0 0x100>; 1218 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1219 clocks = <&pmucru PCLK_GPIO0_PMU>; 1220 gpio-controller; 1221 #gpio-cells = <2>; 1222 1223 interrupt-controller; 1224 #interrupt-cells = <2>; 1225 }; 1226 1227 gpio1: gpio1@ff250000 { 1228 compatible = "rockchip,gpio-bank"; 1229 reg = <0x0 0xff250000 0x0 0x100>; 1230 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&cru PCLK_GPIO1>; 1232 gpio-controller; 1233 #gpio-cells = <2>; 1234 1235 interrupt-controller; 1236 #interrupt-cells = <2>; 1237 }; 1238 1239 gpio2: gpio2@ff260000 { 1240 compatible = "rockchip,gpio-bank"; 1241 reg = <0x0 0xff260000 0x0 0x100>; 1242 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1243 clocks = <&cru PCLK_GPIO2>; 1244 gpio-controller; 1245 #gpio-cells = <2>; 1246 1247 interrupt-controller; 1248 #interrupt-cells = <2>; 1249 }; 1250 1251 gpio3: gpio3@ff270000 { 1252 compatible = "rockchip,gpio-bank"; 1253 reg = <0x0 0xff270000 0x0 0x100>; 1254 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&cru PCLK_GPIO3>; 1256 gpio-controller; 1257 #gpio-cells = <2>; 1258 1259 interrupt-controller; 1260 #interrupt-cells = <2>; 1261 }; 1262 1263 pcfg_pull_up: pcfg-pull-up { 1264 bias-pull-up; 1265 }; 1266 1267 pcfg_pull_down: pcfg-pull-down { 1268 bias-pull-down; 1269 }; 1270 1271 pcfg_pull_none: pcfg-pull-none { 1272 bias-disable; 1273 }; 1274 1275 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1276 bias-disable; 1277 drive-strength = <2>; 1278 }; 1279 1280 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1281 bias-pull-up; 1282 drive-strength = <2>; 1283 }; 1284 1285 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1286 bias-pull-up; 1287 drive-strength = <4>; 1288 }; 1289 1290 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1291 bias-disable; 1292 drive-strength = <4>; 1293 }; 1294 1295 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1296 bias-pull-down; 1297 drive-strength = <4>; 1298 }; 1299 1300 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1301 bias-disable; 1302 drive-strength = <8>; 1303 }; 1304 1305 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1306 bias-pull-up; 1307 drive-strength = <8>; 1308 }; 1309 1310 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1311 bias-disable; 1312 drive-strength = <12>; 1313 }; 1314 1315 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1316 bias-pull-up; 1317 drive-strength = <12>; 1318 }; 1319 1320 pcfg_pull_none_smt: pcfg-pull-none-smt { 1321 bias-disable; 1322 input-schmitt-enable; 1323 }; 1324 1325 pcfg_output_high: pcfg-output-high { 1326 output-high; 1327 }; 1328 1329 pcfg_output_low: pcfg-output-low { 1330 output-low; 1331 }; 1332 1333 pcfg_input_high: pcfg-input-high { 1334 bias-pull-up; 1335 input-enable; 1336 }; 1337 1338 pcfg_input: pcfg-input { 1339 input-enable; 1340 }; 1341 1342 i2c0 { 1343 i2c0_xfer: i2c0-xfer { 1344 rockchip,pins = 1345 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1346 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1347 }; 1348 }; 1349 1350 i2c1 { 1351 i2c1_xfer: i2c1-xfer { 1352 rockchip,pins = 1353 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1354 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1355 }; 1356 }; 1357 1358 i2c2 { 1359 i2c2_xfer: i2c2-xfer { 1360 rockchip,pins = 1361 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1362 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1363 }; 1364 }; 1365 1366 i2c3 { 1367 i2c3_xfer: i2c3-xfer { 1368 rockchip,pins = 1369 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1370 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1371 }; 1372 }; 1373 1374 tsadc { 1375 tsadc_otp_gpio: tsadc-otp-gpio { 1376 rockchip,pins = 1377 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1378 }; 1379 1380 tsadc_otp_out: tsadc-otp-out { 1381 rockchip,pins = 1382 <0 RK_PA6 1 &pcfg_pull_none>; 1383 }; 1384 }; 1385 1386 uart0 { 1387 uart0_xfer: uart0-xfer { 1388 rockchip,pins = 1389 <0 RK_PB2 1 &pcfg_pull_up>, 1390 <0 RK_PB3 1 &pcfg_pull_up>; 1391 }; 1392 1393 uart0_cts: uart0-cts { 1394 rockchip,pins = 1395 <0 RK_PB4 1 &pcfg_pull_none>; 1396 }; 1397 1398 uart0_rts: uart0-rts { 1399 rockchip,pins = 1400 <0 RK_PB5 1 &pcfg_pull_none>; 1401 }; 1402 }; 1403 1404 uart1 { 1405 uart1_xfer: uart1-xfer { 1406 rockchip,pins = 1407 <1 RK_PC1 1 &pcfg_pull_up>, 1408 <1 RK_PC0 1 &pcfg_pull_up>; 1409 }; 1410 1411 uart1_cts: uart1-cts { 1412 rockchip,pins = 1413 <1 RK_PC2 1 &pcfg_pull_none>; 1414 }; 1415 1416 uart1_rts: uart1-rts { 1417 rockchip,pins = 1418 <1 RK_PC3 1 &pcfg_pull_none>; 1419 }; 1420 }; 1421 1422 uart2-m0 { 1423 uart2m0_xfer: uart2m0-xfer { 1424 rockchip,pins = 1425 <1 RK_PD2 2 &pcfg_pull_up>, 1426 <1 RK_PD3 2 &pcfg_pull_up>; 1427 }; 1428 }; 1429 1430 uart2-m1 { 1431 uart2m1_xfer: uart2m1-xfer { 1432 rockchip,pins = 1433 <2 RK_PB4 2 &pcfg_pull_up>, 1434 <2 RK_PB6 2 &pcfg_pull_up>; 1435 }; 1436 }; 1437 1438 uart3-m0 { 1439 uart3m0_xfer: uart3m0-xfer { 1440 rockchip,pins = 1441 <0 RK_PC0 2 &pcfg_pull_up>, 1442 <0 RK_PC1 2 &pcfg_pull_up>; 1443 }; 1444 1445 uart3m0_cts: uart3m0-cts { 1446 rockchip,pins = 1447 <0 RK_PC2 2 &pcfg_pull_none>; 1448 }; 1449 1450 uart3m0_rts: uart3m0-rts { 1451 rockchip,pins = 1452 <0 RK_PC3 2 &pcfg_pull_none>; 1453 }; 1454 }; 1455 1456 uart3-m1 { 1457 uart3m1_xfer: uart3m1-xfer { 1458 rockchip,pins = 1459 <1 RK_PB6 2 &pcfg_pull_up>, 1460 <1 RK_PB7 2 &pcfg_pull_up>; 1461 }; 1462 1463 uart3m1_cts: uart3m1-cts { 1464 rockchip,pins = 1465 <1 RK_PB4 2 &pcfg_pull_none>; 1466 }; 1467 1468 uart3m1_rts: uart3m1-rts { 1469 rockchip,pins = 1470 <1 RK_PB5 2 &pcfg_pull_none>; 1471 }; 1472 }; 1473 1474 uart4 { 1475 uart4_xfer: uart4-xfer { 1476 rockchip,pins = 1477 <1 RK_PD4 2 &pcfg_pull_up>, 1478 <1 RK_PD5 2 &pcfg_pull_up>; 1479 }; 1480 1481 uart4_cts: uart4-cts { 1482 rockchip,pins = 1483 <1 RK_PD6 2 &pcfg_pull_none>; 1484 }; 1485 1486 uart4_rts: uart4-rts { 1487 rockchip,pins = 1488 <1 RK_PD7 2 &pcfg_pull_none>; 1489 }; 1490 }; 1491 1492 uart5 { 1493 uart5_xfer: uart5-xfer { 1494 rockchip,pins = 1495 <3 RK_PA2 4 &pcfg_pull_up>, 1496 <3 RK_PA1 4 &pcfg_pull_up>; 1497 }; 1498 1499 uart5_cts: uart5-cts { 1500 rockchip,pins = 1501 <3 RK_PA3 4 &pcfg_pull_none>; 1502 }; 1503 1504 uart5_rts: uart5-rts { 1505 rockchip,pins = 1506 <3 RK_PA5 4 &pcfg_pull_none>; 1507 }; 1508 }; 1509 1510 spi0 { 1511 spi0_clk: spi0-clk { 1512 rockchip,pins = 1513 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1514 }; 1515 1516 spi0_csn: spi0-csn { 1517 rockchip,pins = 1518 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1519 }; 1520 1521 spi0_miso: spi0-miso { 1522 rockchip,pins = 1523 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1524 }; 1525 1526 spi0_mosi: spi0-mosi { 1527 rockchip,pins = 1528 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1529 }; 1530 1531 spi0_clk_hs: spi0-clk-hs { 1532 rockchip,pins = 1533 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1534 }; 1535 1536 spi0_miso_hs: spi0-miso-hs { 1537 rockchip,pins = 1538 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1539 }; 1540 1541 spi0_mosi_hs: spi0-mosi-hs { 1542 rockchip,pins = 1543 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1544 }; 1545 }; 1546 1547 spi1 { 1548 spi1_clk: spi1-clk { 1549 rockchip,pins = 1550 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1551 }; 1552 1553 spi1_csn0: spi1-csn0 { 1554 rockchip,pins = 1555 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1556 }; 1557 1558 spi1_csn1: spi1-csn1 { 1559 rockchip,pins = 1560 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1561 }; 1562 1563 spi1_miso: spi1-miso { 1564 rockchip,pins = 1565 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1566 }; 1567 1568 spi1_mosi: spi1-mosi { 1569 rockchip,pins = 1570 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1571 }; 1572 1573 spi1_clk_hs: spi1-clk-hs { 1574 rockchip,pins = 1575 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1576 }; 1577 1578 spi1_miso_hs: spi1-miso-hs { 1579 rockchip,pins = 1580 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1581 }; 1582 1583 spi1_mosi_hs: spi1-mosi-hs { 1584 rockchip,pins = 1585 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1586 }; 1587 }; 1588 1589 pdm { 1590 pdm_clk0m0: pdm-clk0m0 { 1591 rockchip,pins = 1592 <3 RK_PC6 2 &pcfg_pull_none>; 1593 }; 1594 1595 pdm_clk0m1: pdm-clk0m1 { 1596 rockchip,pins = 1597 <2 RK_PC6 1 &pcfg_pull_none>; 1598 }; 1599 1600 pdm_clk1: pdm-clk1 { 1601 rockchip,pins = 1602 <3 RK_PC7 2 &pcfg_pull_none>; 1603 }; 1604 1605 pdm_sdi0m0: pdm-sdi0m0 { 1606 rockchip,pins = 1607 <3 RK_PD3 2 &pcfg_pull_none>; 1608 }; 1609 1610 pdm_sdi0m1: pdm-sdi0m1 { 1611 rockchip,pins = 1612 <2 RK_PC5 2 &pcfg_pull_none>; 1613 }; 1614 1615 pdm_sdi1: pdm-sdi1 { 1616 rockchip,pins = 1617 <3 RK_PD0 2 &pcfg_pull_none>; 1618 }; 1619 1620 pdm_sdi2: pdm-sdi2 { 1621 rockchip,pins = 1622 <3 RK_PD1 2 &pcfg_pull_none>; 1623 }; 1624 1625 pdm_sdi3: pdm-sdi3 { 1626 rockchip,pins = 1627 <3 RK_PD2 2 &pcfg_pull_none>; 1628 }; 1629 1630 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1631 rockchip,pins = 1632 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1633 }; 1634 1635 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1636 rockchip,pins = 1637 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1638 }; 1639 1640 pdm_clk1_sleep: pdm-clk1-sleep { 1641 rockchip,pins = 1642 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1643 }; 1644 1645 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1646 rockchip,pins = 1647 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1648 }; 1649 1650 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1651 rockchip,pins = 1652 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1653 }; 1654 1655 pdm_sdi1_sleep: pdm-sdi1-sleep { 1656 rockchip,pins = 1657 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1658 }; 1659 1660 pdm_sdi2_sleep: pdm-sdi2-sleep { 1661 rockchip,pins = 1662 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1663 }; 1664 1665 pdm_sdi3_sleep: pdm-sdi3-sleep { 1666 rockchip,pins = 1667 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1668 }; 1669 }; 1670 1671 i2s0 { 1672 i2s0_8ch_mclk: i2s0-8ch-mclk { 1673 rockchip,pins = 1674 <3 RK_PC1 2 &pcfg_pull_none>; 1675 }; 1676 1677 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1678 rockchip,pins = 1679 <3 RK_PC3 2 &pcfg_pull_none>; 1680 }; 1681 1682 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1683 rockchip,pins = 1684 <3 RK_PB4 2 &pcfg_pull_none>; 1685 }; 1686 1687 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1688 rockchip,pins = 1689 <3 RK_PC2 2 &pcfg_pull_none>; 1690 }; 1691 1692 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1693 rockchip,pins = 1694 <3 RK_PB5 2 &pcfg_pull_none>; 1695 }; 1696 1697 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1698 rockchip,pins = 1699 <3 RK_PC4 2 &pcfg_pull_none>; 1700 }; 1701 1702 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1703 rockchip,pins = 1704 <3 RK_PC0 2 &pcfg_pull_none>; 1705 }; 1706 1707 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1708 rockchip,pins = 1709 <3 RK_PB7 2 &pcfg_pull_none>; 1710 }; 1711 1712 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1713 rockchip,pins = 1714 <3 RK_PB6 2 &pcfg_pull_none>; 1715 }; 1716 1717 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1718 rockchip,pins = 1719 <3 RK_PC5 2 &pcfg_pull_none>; 1720 }; 1721 1722 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1723 rockchip,pins = 1724 <3 RK_PB3 2 &pcfg_pull_none>; 1725 }; 1726 1727 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1728 rockchip,pins = 1729 <3 RK_PB1 2 &pcfg_pull_none>; 1730 }; 1731 1732 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1733 rockchip,pins = 1734 <3 RK_PB0 2 &pcfg_pull_none>; 1735 }; 1736 }; 1737 1738 i2s1 { 1739 i2s1_2ch_mclk: i2s1-2ch-mclk { 1740 rockchip,pins = 1741 <2 RK_PC3 1 &pcfg_pull_none>; 1742 }; 1743 1744 i2s1_2ch_sclk: i2s1-2ch-sclk { 1745 rockchip,pins = 1746 <2 RK_PC2 1 &pcfg_pull_none>; 1747 }; 1748 1749 i2s1_2ch_lrck: i2s1-2ch-lrck { 1750 rockchip,pins = 1751 <2 RK_PC1 1 &pcfg_pull_none>; 1752 }; 1753 1754 i2s1_2ch_sdi: i2s1-2ch-sdi { 1755 rockchip,pins = 1756 <2 RK_PC5 1 &pcfg_pull_none>; 1757 }; 1758 1759 i2s1_2ch_sdo: i2s1-2ch-sdo { 1760 rockchip,pins = 1761 <2 RK_PC4 1 &pcfg_pull_none>; 1762 }; 1763 }; 1764 1765 i2s2 { 1766 i2s2_2ch_mclk: i2s2-2ch-mclk { 1767 rockchip,pins = 1768 <3 RK_PA1 2 &pcfg_pull_none>; 1769 }; 1770 1771 i2s2_2ch_sclk: i2s2-2ch-sclk { 1772 rockchip,pins = 1773 <3 RK_PA2 2 &pcfg_pull_none>; 1774 }; 1775 1776 i2s2_2ch_lrck: i2s2-2ch-lrck { 1777 rockchip,pins = 1778 <3 RK_PA3 2 &pcfg_pull_none>; 1779 }; 1780 1781 i2s2_2ch_sdi: i2s2-2ch-sdi { 1782 rockchip,pins = 1783 <3 RK_PA5 2 &pcfg_pull_none>; 1784 }; 1785 1786 i2s2_2ch_sdo: i2s2-2ch-sdo { 1787 rockchip,pins = 1788 <3 RK_PA7 2 &pcfg_pull_none>; 1789 }; 1790 }; 1791 1792 sdmmc { 1793 sdmmc_clk: sdmmc-clk { 1794 rockchip,pins = 1795 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1796 }; 1797 1798 sdmmc_cmd: sdmmc-cmd { 1799 rockchip,pins = 1800 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1801 }; 1802 1803 sdmmc_det: sdmmc-det { 1804 rockchip,pins = 1805 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1806 }; 1807 1808 sdmmc_bus1: sdmmc-bus1 { 1809 rockchip,pins = 1810 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1811 }; 1812 1813 sdmmc_bus4: sdmmc-bus4 { 1814 rockchip,pins = 1815 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1816 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1817 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1818 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1819 }; 1820 }; 1821 1822 sdio { 1823 sdio_clk: sdio-clk { 1824 rockchip,pins = 1825 <1 RK_PC5 1 &pcfg_pull_none>; 1826 }; 1827 1828 sdio_cmd: sdio-cmd { 1829 rockchip,pins = 1830 <1 RK_PC4 1 &pcfg_pull_up>; 1831 }; 1832 1833 sdio_bus4: sdio-bus4 { 1834 rockchip,pins = 1835 <1 RK_PC6 1 &pcfg_pull_up>, 1836 <1 RK_PC7 1 &pcfg_pull_up>, 1837 <1 RK_PD0 1 &pcfg_pull_up>, 1838 <1 RK_PD1 1 &pcfg_pull_up>; 1839 }; 1840 }; 1841 1842 emmc { 1843 emmc_clk: emmc-clk { 1844 rockchip,pins = 1845 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 1846 }; 1847 1848 emmc_cmd: emmc-cmd { 1849 rockchip,pins = 1850 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 1851 }; 1852 1853 emmc_rstnout: emmc-rstnout { 1854 rockchip,pins = 1855 <1 RK_PB3 2 &pcfg_pull_none>; 1856 }; 1857 1858 emmc_bus1: emmc-bus1 { 1859 rockchip,pins = 1860 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 1861 }; 1862 1863 emmc_bus4: emmc-bus4 { 1864 rockchip,pins = 1865 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1866 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1867 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1868 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 1869 }; 1870 1871 emmc_bus8: emmc-bus8 { 1872 rockchip,pins = 1873 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1874 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1875 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1876 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 1877 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 1878 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 1879 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 1880 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 1881 }; 1882 }; 1883 1884 flash { 1885 flash_cs0: flash-cs0 { 1886 rockchip,pins = 1887 <1 RK_PB0 1 &pcfg_pull_none>; 1888 }; 1889 1890 flash_rdy: flash-rdy { 1891 rockchip,pins = 1892 <1 RK_PB1 1 &pcfg_pull_none>; 1893 }; 1894 1895 flash_dqs: flash-dqs { 1896 rockchip,pins = 1897 <1 RK_PB2 1 &pcfg_pull_none>; 1898 }; 1899 1900 flash_ale: flash-ale { 1901 rockchip,pins = 1902 <1 RK_PB3 1 &pcfg_pull_none>; 1903 }; 1904 1905 flash_cle: flash-cle { 1906 rockchip,pins = 1907 <1 RK_PB4 1 &pcfg_pull_none>; 1908 }; 1909 1910 flash_wrn: flash-wrn { 1911 rockchip,pins = 1912 <1 RK_PB5 1 &pcfg_pull_none>; 1913 }; 1914 1915 flash_csl: flash-csl { 1916 rockchip,pins = 1917 <1 RK_PB6 1 &pcfg_pull_none>; 1918 }; 1919 1920 flash_rdn: flash-rdn { 1921 rockchip,pins = 1922 <1 RK_PB7 1 &pcfg_pull_none>; 1923 }; 1924 1925 flash_bus8: flash-bus8 { 1926 rockchip,pins = 1927 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 1928 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 1929 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 1930 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 1931 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 1932 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 1933 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 1934 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 1935 }; 1936 }; 1937 1938 lcdc { 1939 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1940 rockchip,pins = 1941 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 1942 }; 1943 1944 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1945 rockchip,pins = 1946 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 1947 }; 1948 1949 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1950 rockchip,pins = 1951 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 1952 }; 1953 1954 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1955 rockchip,pins = 1956 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 1957 }; 1958 1959 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1960 rockchip,pins = 1961 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1962 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1963 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1964 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1965 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1966 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1967 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1968 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1969 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1970 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1971 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1972 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 1973 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1974 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1975 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1976 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1977 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 1978 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 1979 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1980 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 1981 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 1982 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 1983 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 1984 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 1985 }; 1986 1987 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 1988 rockchip,pins = 1989 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1990 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1991 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1992 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1993 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1994 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1995 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1996 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1997 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1998 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1999 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2000 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2001 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2002 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2003 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2004 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2005 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2006 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2007 }; 2008 2009 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2010 rockchip,pins = 2011 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2012 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2013 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2014 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2015 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2016 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2017 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2018 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2019 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2020 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2021 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2022 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2023 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2024 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2025 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2026 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2027 }; 2028 2029 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2030 rockchip,pins = 2031 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2032 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2033 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2034 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2035 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2036 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2037 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2038 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2039 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2040 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2041 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2042 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2043 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2044 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2045 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2046 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2047 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2048 }; 2049 2050 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2051 rockchip,pins = 2052 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2053 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2054 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2055 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2056 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2057 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2058 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2059 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2060 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2061 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2062 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2063 }; 2064 2065 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2066 rockchip,pins = 2067 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2068 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2069 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2070 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2071 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2072 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2073 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2074 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2075 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2076 }; 2077 }; 2078 2079 pwm0 { 2080 pwm0_pin: pwm0-pin { 2081 rockchip,pins = 2082 <0 RK_PB7 1 &pcfg_pull_none>; 2083 }; 2084 }; 2085 2086 pwm1 { 2087 pwm1_pin: pwm1-pin { 2088 rockchip,pins = 2089 <0 RK_PC0 1 &pcfg_pull_none>; 2090 }; 2091 }; 2092 2093 pwm2 { 2094 pwm2_pin: pwm2-pin { 2095 rockchip,pins = 2096 <2 RK_PB5 1 &pcfg_pull_none>; 2097 }; 2098 }; 2099 2100 pwm3 { 2101 pwm3_pin: pwm3-pin { 2102 rockchip,pins = 2103 <0 RK_PC1 1 &pcfg_pull_none>; 2104 }; 2105 }; 2106 2107 pwm4 { 2108 pwm4_pin: pwm4-pin { 2109 rockchip,pins = 2110 <3 RK_PC2 3 &pcfg_pull_none>; 2111 }; 2112 }; 2113 2114 pwm5 { 2115 pwm5_pin: pwm5-pin { 2116 rockchip,pins = 2117 <3 RK_PC3 3 &pcfg_pull_none>; 2118 }; 2119 }; 2120 2121 pwm6 { 2122 pwm6_pin: pwm6-pin { 2123 rockchip,pins = 2124 <3 RK_PC4 3 &pcfg_pull_none>; 2125 }; 2126 }; 2127 2128 pwm7 { 2129 pwm7_pin: pwm7-pin { 2130 rockchip,pins = 2131 <3 RK_PC5 3 &pcfg_pull_none>; 2132 }; 2133 }; 2134 2135 gmac { 2136 rmii_pins: rmii-pins { 2137 rockchip,pins = 2138 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 2139 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 2140 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 2141 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 2142 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 2143 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 2144 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 2145 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 2146 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 2147 }; 2148 2149 mac_refclk_12ma: mac-refclk-12ma { 2150 rockchip,pins = 2151 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 2152 }; 2153 2154 mac_refclk: mac-refclk { 2155 rockchip,pins = 2156 <2 RK_PB2 2 &pcfg_pull_none>; 2157 }; 2158 }; 2159 2160 cif-m0 { 2161 cif_clkout_m0: cif-clkout-m0 { 2162 rockchip,pins = 2163 <2 RK_PB3 1 &pcfg_pull_none>; 2164 }; 2165 2166 dvp_d2d9_m0: dvp-d2d9-m0 { 2167 rockchip,pins = 2168 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 2169 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 2170 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 2171 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 2172 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 2173 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 2174 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 2175 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 2176 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 2177 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 2178 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 2179 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 2180 }; 2181 2182 dvp_d0d1_m0: dvp-d0d1-m0 { 2183 rockchip,pins = 2184 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 2185 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 2186 }; 2187 2188 dvp_d10d11_m0:d10-d11-m0 { 2189 rockchip,pins = 2190 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 2191 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 2192 }; 2193 }; 2194 2195 cif-m1 { 2196 cif_clkout_m1: cif-clkout-m1 { 2197 rockchip,pins = 2198 <3 RK_PD0 3 &pcfg_pull_none>; 2199 }; 2200 2201 dvp_d2d9_m1: dvp-d2d9-m1 { 2202 rockchip,pins = 2203 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 2204 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 2205 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 2206 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 2207 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 2208 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 2209 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 2210 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 2211 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 2212 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 2213 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 2214 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 2215 }; 2216 2217 dvp_d0d1_m1: dvp-d0d1-m1 { 2218 rockchip,pins = 2219 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 2220 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 2221 }; 2222 2223 dvp_d10d11_m1:d10-d11-m1 { 2224 rockchip,pins = 2225 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 2226 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 2227 }; 2228 }; 2229 2230 isp { 2231 isp_prelight: isp-prelight { 2232 rockchip,pins = 2233 <3 RK_PD1 4 &pcfg_pull_none>; 2234 }; 2235 }; 2236 }; 2237}; 2238