1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/px30-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/power/px30-power.h>
12#include <dt-bindings/soc/rockchip,boot-mode.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	compatible = "rockchip,px30";
17
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		ethernet0 = &gmac;
24		i2c0 = &i2c0;
25		i2c1 = &i2c1;
26		i2c2 = &i2c2;
27		i2c3 = &i2c3;
28		serial0 = &uart0;
29		serial1 = &uart1;
30		serial2 = &uart2;
31		serial3 = &uart3;
32		serial4 = &uart4;
33		serial5 = &uart5;
34		spi0 = &spi0;
35		spi1 = &spi1;
36	};
37
38	cpus {
39		#address-cells = <2>;
40		#size-cells = <0>;
41
42		cpu0: cpu@0 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a35";
45			reg = <0x0 0x0>;
46			enable-method = "psci";
47			clocks = <&cru ARMCLK>;
48			#cooling-cells = <2>;
49			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
50			dynamic-power-coefficient = <90>;
51			operating-points-v2 = <&cpu0_opp_table>;
52		};
53
54		cpu1: cpu@1 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a35";
57			reg = <0x0 0x1>;
58			enable-method = "psci";
59			clocks = <&cru ARMCLK>;
60			#cooling-cells = <2>;
61			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
62			dynamic-power-coefficient = <90>;
63			operating-points-v2 = <&cpu0_opp_table>;
64		};
65
66		cpu2: cpu@2 {
67			device_type = "cpu";
68			compatible = "arm,cortex-a35";
69			reg = <0x0 0x2>;
70			enable-method = "psci";
71			clocks = <&cru ARMCLK>;
72			#cooling-cells = <2>;
73			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
74			dynamic-power-coefficient = <90>;
75			operating-points-v2 = <&cpu0_opp_table>;
76		};
77
78		cpu3: cpu@3 {
79			device_type = "cpu";
80			compatible = "arm,cortex-a35";
81			reg = <0x0 0x3>;
82			enable-method = "psci";
83			clocks = <&cru ARMCLK>;
84			#cooling-cells = <2>;
85			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86			dynamic-power-coefficient = <90>;
87			operating-points-v2 = <&cpu0_opp_table>;
88		};
89
90		idle-states {
91			entry-method = "psci";
92
93			CPU_SLEEP: cpu-sleep {
94				compatible = "arm,idle-state";
95				local-timer-stop;
96				arm,psci-suspend-param = <0x0010000>;
97				entry-latency-us = <120>;
98				exit-latency-us = <250>;
99				min-residency-us = <900>;
100			};
101
102			CLUSTER_SLEEP: cluster-sleep {
103				compatible = "arm,idle-state";
104				local-timer-stop;
105				arm,psci-suspend-param = <0x1010000>;
106				entry-latency-us = <400>;
107				exit-latency-us = <500>;
108				min-residency-us = <2000>;
109			};
110		};
111	};
112
113	cpu0_opp_table: opp-table-0 {
114		compatible = "operating-points-v2";
115		opp-shared;
116
117		opp-600000000 {
118			opp-hz = /bits/ 64 <600000000>;
119			opp-microvolt = <950000 950000 1350000>;
120			clock-latency-ns = <40000>;
121			opp-suspend;
122		};
123		opp-816000000 {
124			opp-hz = /bits/ 64 <816000000>;
125			opp-microvolt = <1050000 1050000 1350000>;
126			clock-latency-ns = <40000>;
127		};
128		opp-1008000000 {
129			opp-hz = /bits/ 64 <1008000000>;
130			opp-microvolt = <1175000 1175000 1350000>;
131			clock-latency-ns = <40000>;
132		};
133		opp-1200000000 {
134			opp-hz = /bits/ 64 <1200000000>;
135			opp-microvolt = <1300000 1300000 1350000>;
136			clock-latency-ns = <40000>;
137		};
138		opp-1296000000 {
139			opp-hz = /bits/ 64 <1296000000>;
140			opp-microvolt = <1350000 1350000 1350000>;
141			clock-latency-ns = <40000>;
142		};
143	};
144
145	arm-pmu {
146		compatible = "arm,cortex-a35-pmu";
147		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
148			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
149			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
150			     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
151		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
152	};
153
154	display_subsystem: display-subsystem {
155		compatible = "rockchip,display-subsystem";
156		ports = <&vopb_out>, <&vopl_out>;
157		status = "disabled";
158	};
159
160	gmac_clkin: external-gmac-clock {
161		compatible = "fixed-clock";
162		clock-frequency = <50000000>;
163		clock-output-names = "gmac_clkin";
164		#clock-cells = <0>;
165	};
166
167	psci {
168		compatible = "arm,psci-1.0";
169		method = "smc";
170	};
171
172	timer {
173		compatible = "arm,armv8-timer";
174		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
177			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
178	};
179
180	thermal_zones: thermal-zones {
181		soc_thermal: soc-thermal {
182			polling-delay-passive = <20>;
183			polling-delay = <1000>;
184			sustainable-power = <750>;
185			thermal-sensors = <&tsadc 0>;
186
187			trips {
188				threshold: trip-point-0 {
189					temperature = <70000>;
190					hysteresis = <2000>;
191					type = "passive";
192				};
193
194				target: trip-point-1 {
195					temperature = <85000>;
196					hysteresis = <2000>;
197					type = "passive";
198				};
199
200				soc_crit: soc-crit {
201					temperature = <115000>;
202					hysteresis = <2000>;
203					type = "critical";
204				};
205			};
206
207			cooling-maps {
208				map0 {
209					trip = <&target>;
210					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211					contribution = <4096>;
212				};
213			};
214		};
215
216		gpu_thermal: gpu-thermal {
217			polling-delay-passive = <100>; /* milliseconds */
218			polling-delay = <1000>; /* milliseconds */
219			thermal-sensors = <&tsadc 1>;
220
221			trips {
222				gpu_threshold: gpu-threshold {
223					temperature = <70000>;
224					hysteresis = <2000>;
225					type = "passive";
226				};
227
228				gpu_target: gpu-target {
229					temperature = <85000>;
230					hysteresis = <2000>;
231					type = "passive";
232				};
233
234				gpu_crit: gpu-crit {
235					temperature = <115000>;
236					hysteresis = <2000>;
237					type = "critical";
238				};
239			};
240
241			cooling-maps {
242				map0 {
243					trip = <&gpu_target>;
244					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
245				};
246			};
247		};
248	};
249
250	xin24m: xin24m {
251		compatible = "fixed-clock";
252		#clock-cells = <0>;
253		clock-frequency = <24000000>;
254		clock-output-names = "xin24m";
255	};
256
257	pmu: power-management@ff000000 {
258		compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
259		reg = <0x0 0xff000000 0x0 0x1000>;
260
261		power: power-controller {
262			compatible = "rockchip,px30-power-controller";
263			#power-domain-cells = <1>;
264			#address-cells = <1>;
265			#size-cells = <0>;
266
267			/* These power domains are grouped by VD_LOGIC */
268			power-domain@PX30_PD_USB {
269				reg = <PX30_PD_USB>;
270				clocks = <&cru HCLK_HOST>,
271					 <&cru HCLK_OTG>,
272					 <&cru SCLK_OTG_ADP>;
273				pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
274				#power-domain-cells = <0>;
275			};
276			power-domain@PX30_PD_SDCARD {
277				reg = <PX30_PD_SDCARD>;
278				clocks = <&cru HCLK_SDMMC>,
279					 <&cru SCLK_SDMMC>;
280				pm_qos = <&qos_sdmmc>;
281				#power-domain-cells = <0>;
282			};
283			power-domain@PX30_PD_GMAC {
284				reg = <PX30_PD_GMAC>;
285				clocks = <&cru ACLK_GMAC>,
286					 <&cru PCLK_GMAC>,
287					 <&cru SCLK_MAC_REF>,
288					 <&cru SCLK_GMAC_RX_TX>;
289				pm_qos = <&qos_gmac>;
290				#power-domain-cells = <0>;
291			};
292			power-domain@PX30_PD_MMC_NAND {
293				reg = <PX30_PD_MMC_NAND>;
294				clocks = <&cru HCLK_NANDC>,
295					 <&cru HCLK_EMMC>,
296					 <&cru HCLK_SDIO>,
297					 <&cru HCLK_SFC>,
298					 <&cru SCLK_EMMC>,
299					 <&cru SCLK_NANDC>,
300					 <&cru SCLK_SDIO>,
301					 <&cru SCLK_SFC>;
302				pm_qos = <&qos_emmc>, <&qos_nand>,
303					 <&qos_sdio>, <&qos_sfc>;
304				#power-domain-cells = <0>;
305			};
306			power-domain@PX30_PD_VPU {
307				reg = <PX30_PD_VPU>;
308				clocks = <&cru ACLK_VPU>,
309					 <&cru HCLK_VPU>,
310					 <&cru SCLK_CORE_VPU>;
311				pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
312				#power-domain-cells = <0>;
313			};
314			power-domain@PX30_PD_VO {
315				reg = <PX30_PD_VO>;
316				clocks = <&cru ACLK_RGA>,
317					 <&cru ACLK_VOPB>,
318					 <&cru ACLK_VOPL>,
319					 <&cru DCLK_VOPB>,
320					 <&cru DCLK_VOPL>,
321					 <&cru HCLK_RGA>,
322					 <&cru HCLK_VOPB>,
323					 <&cru HCLK_VOPL>,
324					 <&cru PCLK_MIPI_DSI>,
325					 <&cru SCLK_RGA_CORE>,
326					 <&cru SCLK_VOPB_PWM>;
327				pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
328					 <&qos_vop_m0>, <&qos_vop_m1>;
329				#power-domain-cells = <0>;
330			};
331			power-domain@PX30_PD_VI {
332				reg = <PX30_PD_VI>;
333				clocks = <&cru ACLK_CIF>,
334					 <&cru ACLK_ISP>,
335					 <&cru HCLK_CIF>,
336					 <&cru HCLK_ISP>,
337					 <&cru SCLK_ISP>;
338				pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
339					 <&qos_isp_wr>, <&qos_isp_m1>,
340					 <&qos_vip>;
341				#power-domain-cells = <0>;
342			};
343			power-domain@PX30_PD_GPU {
344				reg = <PX30_PD_GPU>;
345				clocks = <&cru SCLK_GPU>;
346				pm_qos = <&qos_gpu>;
347				#power-domain-cells = <0>;
348			};
349		};
350	};
351
352	pmugrf: syscon@ff010000 {
353		compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
354		reg = <0x0 0xff010000 0x0 0x1000>;
355		#address-cells = <1>;
356		#size-cells = <1>;
357
358		pmu_io_domains: io-domains {
359			compatible = "rockchip,px30-pmu-io-voltage-domain";
360			status = "disabled";
361		};
362
363		reboot-mode {
364			compatible = "syscon-reboot-mode";
365			offset = <0x200>;
366			mode-bootloader = <BOOT_BL_DOWNLOAD>;
367			mode-fastboot = <BOOT_FASTBOOT>;
368			mode-loader = <BOOT_BL_DOWNLOAD>;
369			mode-normal = <BOOT_NORMAL>;
370			mode-recovery = <BOOT_RECOVERY>;
371		};
372	};
373
374	uart0: serial@ff030000 {
375		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
376		reg = <0x0 0xff030000 0x0 0x100>;
377		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
378		clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
379		clock-names = "baudclk", "apb_pclk";
380		dmas = <&dmac 0>, <&dmac 1>;
381		dma-names = "tx", "rx";
382		reg-shift = <2>;
383		reg-io-width = <4>;
384		pinctrl-names = "default";
385		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
386		status = "disabled";
387	};
388
389	i2s0_8ch: i2s@ff060000 {
390		compatible = "rockchip,px30-i2s-tdm";
391		reg = <0x0 0xff060000 0x0 0x1000>;
392		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
393		clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
394		clock-names = "mclk_tx", "mclk_rx", "hclk";
395		dmas = <&dmac 16>, <&dmac 17>;
396		dma-names = "tx", "rx";
397		rockchip,grf = <&grf>;
398		resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
399		reset-names = "tx-m", "rx-m";
400		pinctrl-names = "default";
401		pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
402			     &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx
403			     &i2s0_8ch_sdo0 &i2s0_8ch_sdi0
404			     &i2s0_8ch_sdo1 &i2s0_8ch_sdi1
405			     &i2s0_8ch_sdo2 &i2s0_8ch_sdi2
406			     &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;
407		#sound-dai-cells = <0>;
408		status = "disabled";
409	};
410
411	i2s1_2ch: i2s@ff070000 {
412		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
413		reg = <0x0 0xff070000 0x0 0x1000>;
414		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
415		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
416		clock-names = "i2s_clk", "i2s_hclk";
417		dmas = <&dmac 18>, <&dmac 19>;
418		dma-names = "tx", "rx";
419		pinctrl-names = "default";
420		pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
421			     &i2s1_2ch_sdi &i2s1_2ch_sdo>;
422		#sound-dai-cells = <0>;
423		status = "disabled";
424	};
425
426	i2s2_2ch: i2s@ff080000 {
427		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
428		reg = <0x0 0xff080000 0x0 0x1000>;
429		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
430		clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
431		clock-names = "i2s_clk", "i2s_hclk";
432		dmas = <&dmac 20>, <&dmac 21>;
433		dma-names = "tx", "rx";
434		pinctrl-names = "default";
435		pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
436			     &i2s2_2ch_sdi &i2s2_2ch_sdo>;
437		#sound-dai-cells = <0>;
438		status = "disabled";
439	};
440
441	gic: interrupt-controller@ff131000 {
442		compatible = "arm,gic-400";
443		#interrupt-cells = <3>;
444		#address-cells = <0>;
445		interrupt-controller;
446		reg = <0x0 0xff131000 0 0x1000>,
447		      <0x0 0xff132000 0 0x2000>,
448		      <0x0 0xff134000 0 0x2000>,
449		      <0x0 0xff136000 0 0x2000>;
450		interrupts = <GIC_PPI 9
451		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
452	};
453
454	grf: syscon@ff140000 {
455		compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
456		reg = <0x0 0xff140000 0x0 0x1000>;
457		#address-cells = <1>;
458		#size-cells = <1>;
459
460		io_domains: io-domains {
461			compatible = "rockchip,px30-io-voltage-domain";
462			status = "disabled";
463		};
464
465		lvds: lvds {
466			compatible = "rockchip,px30-lvds";
467			phys = <&dsi_dphy>;
468			phy-names = "dphy";
469			rockchip,grf = <&grf>;
470			rockchip,output = "lvds";
471			status = "disabled";
472
473			ports {
474				#address-cells = <1>;
475				#size-cells = <0>;
476
477				lvds_in: port@0 {
478					reg = <0>;
479					#address-cells = <1>;
480					#size-cells = <0>;
481
482					lvds_vopb_in: endpoint@0 {
483						reg = <0>;
484						remote-endpoint = <&vopb_out_lvds>;
485					};
486
487					lvds_vopl_in: endpoint@1 {
488						reg = <1>;
489						remote-endpoint = <&vopl_out_lvds>;
490					};
491				};
492
493				lvds_out: port@1 {
494					reg = <1>;
495				};
496			};
497		};
498	};
499
500	uart1: serial@ff158000 {
501		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
502		reg = <0x0 0xff158000 0x0 0x100>;
503		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
504		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
505		clock-names = "baudclk", "apb_pclk";
506		dmas = <&dmac 2>, <&dmac 3>;
507		dma-names = "tx", "rx";
508		reg-shift = <2>;
509		reg-io-width = <4>;
510		pinctrl-names = "default";
511		pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
512		status = "disabled";
513	};
514
515	uart2: serial@ff160000 {
516		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
517		reg = <0x0 0xff160000 0x0 0x100>;
518		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
519		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
520		clock-names = "baudclk", "apb_pclk";
521		dmas = <&dmac 4>, <&dmac 5>;
522		dma-names = "tx", "rx";
523		reg-shift = <2>;
524		reg-io-width = <4>;
525		pinctrl-names = "default";
526		pinctrl-0 = <&uart2m0_xfer>;
527		status = "disabled";
528	};
529
530	uart3: serial@ff168000 {
531		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
532		reg = <0x0 0xff168000 0x0 0x100>;
533		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
534		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
535		clock-names = "baudclk", "apb_pclk";
536		dmas = <&dmac 6>, <&dmac 7>;
537		dma-names = "tx", "rx";
538		reg-shift = <2>;
539		reg-io-width = <4>;
540		pinctrl-names = "default";
541		pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
542		status = "disabled";
543	};
544
545	uart4: serial@ff170000 {
546		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
547		reg = <0x0 0xff170000 0x0 0x100>;
548		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
549		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
550		clock-names = "baudclk", "apb_pclk";
551		dmas = <&dmac 8>, <&dmac 9>;
552		dma-names = "tx", "rx";
553		reg-shift = <2>;
554		reg-io-width = <4>;
555		pinctrl-names = "default";
556		pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
557		status = "disabled";
558	};
559
560	uart5: serial@ff178000 {
561		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
562		reg = <0x0 0xff178000 0x0 0x100>;
563		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
564		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
565		clock-names = "baudclk", "apb_pclk";
566		dmas = <&dmac 10>, <&dmac 11>;
567		dma-names = "tx", "rx";
568		reg-shift = <2>;
569		reg-io-width = <4>;
570		pinctrl-names = "default";
571		pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
572		status = "disabled";
573	};
574
575	i2c0: i2c@ff180000 {
576		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
577		reg = <0x0 0xff180000 0x0 0x1000>;
578		clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
579		clock-names = "i2c", "pclk";
580		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
581		pinctrl-names = "default";
582		pinctrl-0 = <&i2c0_xfer>;
583		#address-cells = <1>;
584		#size-cells = <0>;
585		status = "disabled";
586	};
587
588	i2c1: i2c@ff190000 {
589		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
590		reg = <0x0 0xff190000 0x0 0x1000>;
591		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
592		clock-names = "i2c", "pclk";
593		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
594		pinctrl-names = "default";
595		pinctrl-0 = <&i2c1_xfer>;
596		#address-cells = <1>;
597		#size-cells = <0>;
598		status = "disabled";
599	};
600
601	i2c2: i2c@ff1a0000 {
602		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
603		reg = <0x0 0xff1a0000 0x0 0x1000>;
604		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
605		clock-names = "i2c", "pclk";
606		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
607		pinctrl-names = "default";
608		pinctrl-0 = <&i2c2_xfer>;
609		#address-cells = <1>;
610		#size-cells = <0>;
611		status = "disabled";
612	};
613
614	i2c3: i2c@ff1b0000 {
615		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
616		reg = <0x0 0xff1b0000 0x0 0x1000>;
617		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
618		clock-names = "i2c", "pclk";
619		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
620		pinctrl-names = "default";
621		pinctrl-0 = <&i2c3_xfer>;
622		#address-cells = <1>;
623		#size-cells = <0>;
624		status = "disabled";
625	};
626
627	spi0: spi@ff1d0000 {
628		compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
629		reg = <0x0 0xff1d0000 0x0 0x1000>;
630		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
631		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
632		clock-names = "spiclk", "apb_pclk";
633		dmas = <&dmac 12>, <&dmac 13>;
634		dma-names = "tx", "rx";
635		pinctrl-names = "default";
636		pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
637		#address-cells = <1>;
638		#size-cells = <0>;
639		status = "disabled";
640	};
641
642	spi1: spi@ff1d8000 {
643		compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
644		reg = <0x0 0xff1d8000 0x0 0x1000>;
645		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
646		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
647		clock-names = "spiclk", "apb_pclk";
648		dmas = <&dmac 14>, <&dmac 15>;
649		dma-names = "tx", "rx";
650		pinctrl-names = "default";
651		pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
652		#address-cells = <1>;
653		#size-cells = <0>;
654		status = "disabled";
655	};
656
657	wdt: watchdog@ff1e0000 {
658		compatible = "rockchip,px30-wdt", "snps,dw-wdt";
659		reg = <0x0 0xff1e0000 0x0 0x100>;
660		clocks = <&cru PCLK_WDT_NS>;
661		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
662		status = "disabled";
663	};
664
665	pwm0: pwm@ff200000 {
666		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
667		reg = <0x0 0xff200000 0x0 0x10>;
668		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
669		clock-names = "pwm", "pclk";
670		pinctrl-names = "default";
671		pinctrl-0 = <&pwm0_pin>;
672		#pwm-cells = <3>;
673		status = "disabled";
674	};
675
676	pwm1: pwm@ff200010 {
677		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
678		reg = <0x0 0xff200010 0x0 0x10>;
679		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
680		clock-names = "pwm", "pclk";
681		pinctrl-names = "default";
682		pinctrl-0 = <&pwm1_pin>;
683		#pwm-cells = <3>;
684		status = "disabled";
685	};
686
687	pwm2: pwm@ff200020 {
688		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
689		reg = <0x0 0xff200020 0x0 0x10>;
690		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
691		clock-names = "pwm", "pclk";
692		pinctrl-names = "default";
693		pinctrl-0 = <&pwm2_pin>;
694		#pwm-cells = <3>;
695		status = "disabled";
696	};
697
698	pwm3: pwm@ff200030 {
699		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
700		reg = <0x0 0xff200030 0x0 0x10>;
701		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
702		clock-names = "pwm", "pclk";
703		pinctrl-names = "default";
704		pinctrl-0 = <&pwm3_pin>;
705		#pwm-cells = <3>;
706		status = "disabled";
707	};
708
709	pwm4: pwm@ff208000 {
710		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
711		reg = <0x0 0xff208000 0x0 0x10>;
712		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
713		clock-names = "pwm", "pclk";
714		pinctrl-names = "default";
715		pinctrl-0 = <&pwm4_pin>;
716		#pwm-cells = <3>;
717		status = "disabled";
718	};
719
720	pwm5: pwm@ff208010 {
721		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
722		reg = <0x0 0xff208010 0x0 0x10>;
723		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
724		clock-names = "pwm", "pclk";
725		pinctrl-names = "default";
726		pinctrl-0 = <&pwm5_pin>;
727		#pwm-cells = <3>;
728		status = "disabled";
729	};
730
731	pwm6: pwm@ff208020 {
732		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
733		reg = <0x0 0xff208020 0x0 0x10>;
734		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
735		clock-names = "pwm", "pclk";
736		pinctrl-names = "default";
737		pinctrl-0 = <&pwm6_pin>;
738		#pwm-cells = <3>;
739		status = "disabled";
740	};
741
742	pwm7: pwm@ff208030 {
743		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
744		reg = <0x0 0xff208030 0x0 0x10>;
745		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
746		clock-names = "pwm", "pclk";
747		pinctrl-names = "default";
748		pinctrl-0 = <&pwm7_pin>;
749		#pwm-cells = <3>;
750		status = "disabled";
751	};
752
753	rktimer: timer@ff210000 {
754		compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
755		reg = <0x0 0xff210000 0x0 0x1000>;
756		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
757		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
758		clock-names = "pclk", "timer";
759	};
760
761	dmac: dma-controller@ff240000 {
762		compatible = "arm,pl330", "arm,primecell";
763		reg = <0x0 0xff240000 0x0 0x4000>;
764		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
765			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
766		arm,pl330-periph-burst;
767		clocks = <&cru ACLK_DMAC>;
768		clock-names = "apb_pclk";
769		#dma-cells = <1>;
770	};
771
772	tsadc: tsadc@ff280000 {
773		compatible = "rockchip,px30-tsadc";
774		reg = <0x0 0xff280000 0x0 0x100>;
775		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
776		assigned-clocks = <&cru SCLK_TSADC>;
777		assigned-clock-rates = <50000>;
778		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
779		clock-names = "tsadc", "apb_pclk";
780		resets = <&cru SRST_TSADC>;
781		reset-names = "tsadc-apb";
782		rockchip,grf = <&grf>;
783		rockchip,hw-tshut-temp = <120000>;
784		pinctrl-names = "init", "default", "sleep";
785		pinctrl-0 = <&tsadc_otp_pin>;
786		pinctrl-1 = <&tsadc_otp_out>;
787		pinctrl-2 = <&tsadc_otp_pin>;
788		#thermal-sensor-cells = <1>;
789		status = "disabled";
790	};
791
792	saradc: saradc@ff288000 {
793		compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
794		reg = <0x0 0xff288000 0x0 0x100>;
795		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
796		#io-channel-cells = <1>;
797		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
798		clock-names = "saradc", "apb_pclk";
799		resets = <&cru SRST_SARADC_P>;
800		reset-names = "saradc-apb";
801		status = "disabled";
802	};
803
804	otp: nvmem@ff290000 {
805		compatible = "rockchip,px30-otp";
806		reg = <0x0 0xff290000 0x0 0x4000>;
807		clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
808			 <&cru PCLK_OTP_PHY>;
809		clock-names = "otp", "apb_pclk", "phy";
810		resets = <&cru SRST_OTP_PHY>;
811		reset-names = "phy";
812		#address-cells = <1>;
813		#size-cells = <1>;
814
815		/* Data cells */
816		cpu_id: id@7 {
817			reg = <0x07 0x10>;
818		};
819		cpu_leakage: cpu-leakage@17 {
820			reg = <0x17 0x1>;
821		};
822		performance: performance@1e {
823			reg = <0x1e 0x1>;
824			bits = <4 3>;
825		};
826	};
827
828	cru: clock-controller@ff2b0000 {
829		compatible = "rockchip,px30-cru";
830		reg = <0x0 0xff2b0000 0x0 0x1000>;
831		clocks = <&xin24m>, <&pmucru PLL_GPLL>;
832		clock-names = "xin24m", "gpll";
833		rockchip,grf = <&grf>;
834		#clock-cells = <1>;
835		#reset-cells = <1>;
836
837		assigned-clocks = <&cru PLL_NPLL>,
838			<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
839			<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
840			<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
841
842		assigned-clock-rates = <1188000000>,
843			<200000000>, <200000000>,
844			<150000000>, <150000000>,
845			<100000000>, <200000000>;
846	};
847
848	pmucru: clock-controller@ff2bc000 {
849		compatible = "rockchip,px30-pmucru";
850		reg = <0x0 0xff2bc000 0x0 0x1000>;
851		clocks = <&xin24m>;
852		clock-names = "xin24m";
853		rockchip,grf = <&grf>;
854		#clock-cells = <1>;
855		#reset-cells = <1>;
856
857		assigned-clocks =
858			<&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
859			<&pmucru SCLK_WIFI_PMU>;
860		assigned-clock-rates =
861			<1200000000>, <100000000>,
862			<26000000>;
863	};
864
865	usb2phy_grf: syscon@ff2c0000 {
866		compatible = "rockchip,px30-usb2phy-grf", "syscon",
867			     "simple-mfd";
868		reg = <0x0 0xff2c0000 0x0 0x10000>;
869		#address-cells = <1>;
870		#size-cells = <1>;
871
872		u2phy: usb2phy@100 {
873			compatible = "rockchip,px30-usb2phy";
874			reg = <0x100 0x20>;
875			clocks = <&pmucru SCLK_USBPHY_REF>;
876			clock-names = "phyclk";
877			#clock-cells = <0>;
878			assigned-clocks = <&cru USB480M>;
879			assigned-clock-parents = <&u2phy>;
880			clock-output-names = "usb480m_phy";
881			status = "disabled";
882
883			u2phy_host: host-port {
884				#phy-cells = <0>;
885				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
886				interrupt-names = "linestate";
887				status = "disabled";
888			};
889
890			u2phy_otg: otg-port {
891				#phy-cells = <0>;
892				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
893					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
894					     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
895				interrupt-names = "otg-bvalid", "otg-id",
896						  "linestate";
897				status = "disabled";
898			};
899		};
900	};
901
902	dsi_dphy: phy@ff2e0000 {
903		compatible = "rockchip,px30-dsi-dphy";
904		reg = <0x0 0xff2e0000 0x0 0x10000>;
905		clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
906		clock-names = "ref", "pclk";
907		resets = <&cru SRST_MIPIDSIPHY_P>;
908		reset-names = "apb";
909		#phy-cells = <0>;
910		power-domains = <&power PX30_PD_VO>;
911		status = "disabled";
912	};
913
914	csi_dphy: phy@ff2f0000 {
915		compatible = "rockchip,px30-csi-dphy";
916		reg = <0x0 0xff2f0000 0x0 0x4000>;
917		clocks = <&cru PCLK_MIPICSIPHY>;
918		clock-names = "pclk";
919		#phy-cells = <0>;
920		power-domains = <&power PX30_PD_VI>;
921		resets = <&cru SRST_MIPICSIPHY_P>;
922		reset-names = "apb";
923		rockchip,grf = <&grf>;
924		status = "disabled";
925	};
926
927	usb20_otg: usb@ff300000 {
928		compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
929			     "snps,dwc2";
930		reg = <0x0 0xff300000 0x0 0x40000>;
931		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
932		clocks = <&cru HCLK_OTG>;
933		clock-names = "otg";
934		dr_mode = "otg";
935		g-np-tx-fifo-size = <16>;
936		g-rx-fifo-size = <280>;
937		g-tx-fifo-size = <256 128 128 64 32 16>;
938		phys = <&u2phy_otg>;
939		phy-names = "usb2-phy";
940		power-domains = <&power PX30_PD_USB>;
941		status = "disabled";
942	};
943
944	usb_host0_ehci: usb@ff340000 {
945		compatible = "generic-ehci";
946		reg = <0x0 0xff340000 0x0 0x10000>;
947		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
948		clocks = <&cru HCLK_HOST>;
949		phys = <&u2phy_host>;
950		phy-names = "usb";
951		power-domains = <&power PX30_PD_USB>;
952		status = "disabled";
953	};
954
955	usb_host0_ohci: usb@ff350000 {
956		compatible = "generic-ohci";
957		reg = <0x0 0xff350000 0x0 0x10000>;
958		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
959		clocks = <&cru HCLK_HOST>;
960		phys = <&u2phy_host>;
961		phy-names = "usb";
962		power-domains = <&power PX30_PD_USB>;
963		status = "disabled";
964	};
965
966	gmac: ethernet@ff360000 {
967		compatible = "rockchip,px30-gmac";
968		reg = <0x0 0xff360000 0x0 0x10000>;
969		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
970		interrupt-names = "macirq";
971		clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
972			 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
973			 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
974			 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
975		clock-names = "stmmaceth", "mac_clk_rx",
976			      "mac_clk_tx", "clk_mac_ref",
977			      "clk_mac_refout", "aclk_mac",
978			      "pclk_mac", "clk_mac_speed";
979		rockchip,grf = <&grf>;
980		phy-mode = "rmii";
981		pinctrl-names = "default";
982		pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
983		power-domains = <&power PX30_PD_GMAC>;
984		resets = <&cru SRST_GMAC_A>;
985		reset-names = "stmmaceth";
986		status = "disabled";
987	};
988
989	sdmmc: mmc@ff370000 {
990		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
991		reg = <0x0 0xff370000 0x0 0x4000>;
992		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
993		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
994			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
995		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
996		bus-width = <4>;
997		fifo-depth = <0x100>;
998		max-frequency = <150000000>;
999		pinctrl-names = "default";
1000		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1001		power-domains = <&power PX30_PD_SDCARD>;
1002		status = "disabled";
1003	};
1004
1005	sdio: mmc@ff380000 {
1006		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1007		reg = <0x0 0xff380000 0x0 0x4000>;
1008		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1009		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1010			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1011		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1012		bus-width = <4>;
1013		fifo-depth = <0x100>;
1014		max-frequency = <150000000>;
1015		pinctrl-names = "default";
1016		pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1017		power-domains = <&power PX30_PD_MMC_NAND>;
1018		status = "disabled";
1019	};
1020
1021	emmc: mmc@ff390000 {
1022		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1023		reg = <0x0 0xff390000 0x0 0x4000>;
1024		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1025		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1026			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1027		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1028		bus-width = <8>;
1029		fifo-depth = <0x100>;
1030		max-frequency = <150000000>;
1031		pinctrl-names = "default";
1032		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1033		power-domains = <&power PX30_PD_MMC_NAND>;
1034		status = "disabled";
1035	};
1036
1037	sfc: spi@ff3a0000 {
1038		compatible = "rockchip,sfc";
1039		reg = <0x0 0xff3a0000 0x0 0x4000>;
1040		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1041		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1042		clock-names = "clk_sfc", "hclk_sfc";
1043		pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1044		pinctrl-names = "default";
1045		power-domains = <&power PX30_PD_MMC_NAND>;
1046		status = "disabled";
1047	};
1048
1049	nfc: nand-controller@ff3b0000 {
1050		compatible = "rockchip,px30-nfc";
1051		reg = <0x0 0xff3b0000 0x0 0x4000>;
1052		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1053		clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1054		clock-names = "ahb", "nfc";
1055		assigned-clocks = <&cru SCLK_NANDC>;
1056		assigned-clock-rates = <150000000>;
1057		pinctrl-names = "default";
1058		pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1059			     &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
1060		power-domains = <&power PX30_PD_MMC_NAND>;
1061		status = "disabled";
1062	};
1063
1064	gpu_opp_table: opp-table-1 {
1065		compatible = "operating-points-v2";
1066
1067		opp-200000000 {
1068			opp-hz = /bits/ 64 <200000000>;
1069			opp-microvolt = <950000>;
1070		};
1071		opp-300000000 {
1072			opp-hz = /bits/ 64 <300000000>;
1073			opp-microvolt = <975000>;
1074		};
1075		opp-400000000 {
1076			opp-hz = /bits/ 64 <400000000>;
1077			opp-microvolt = <1050000>;
1078		};
1079		opp-480000000 {
1080			opp-hz = /bits/ 64 <480000000>;
1081			opp-microvolt = <1125000>;
1082		};
1083	};
1084
1085	gpu: gpu@ff400000 {
1086		compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1087		reg = <0x0 0xff400000 0x0 0x4000>;
1088		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1089			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1090			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1091		interrupt-names = "job", "mmu", "gpu";
1092		clocks = <&cru SCLK_GPU>;
1093		#cooling-cells = <2>;
1094		power-domains = <&power PX30_PD_GPU>;
1095		operating-points-v2 = <&gpu_opp_table>;
1096		status = "disabled";
1097	};
1098
1099	vpu: video-codec@ff442000 {
1100		compatible = "rockchip,px30-vpu";
1101		reg = <0x0 0xff442000 0x0 0x800>;
1102		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1103			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1104		interrupt-names = "vepu", "vdpu";
1105		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1106		clock-names = "aclk", "hclk";
1107		iommus = <&vpu_mmu>;
1108		power-domains = <&power PX30_PD_VPU>;
1109	};
1110
1111	vpu_mmu: iommu@ff442800 {
1112		compatible = "rockchip,iommu";
1113		reg = <0x0 0xff442800 0x0 0x100>;
1114		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1115		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1116		clock-names = "aclk", "iface";
1117		#iommu-cells = <0>;
1118		power-domains = <&power PX30_PD_VPU>;
1119	};
1120
1121	dsi: dsi@ff450000 {
1122		compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
1123		reg = <0x0 0xff450000 0x0 0x10000>;
1124		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1125		clocks = <&cru PCLK_MIPI_DSI>;
1126		clock-names = "pclk";
1127		phys = <&dsi_dphy>;
1128		phy-names = "dphy";
1129		power-domains = <&power PX30_PD_VO>;
1130		resets = <&cru SRST_MIPIDSI_HOST_P>;
1131		reset-names = "apb";
1132		rockchip,grf = <&grf>;
1133		#address-cells = <1>;
1134		#size-cells = <0>;
1135		status = "disabled";
1136
1137		ports {
1138			#address-cells = <1>;
1139			#size-cells = <0>;
1140
1141			dsi_in: port@0 {
1142				reg = <0>;
1143				#address-cells = <1>;
1144				#size-cells = <0>;
1145
1146				dsi_in_vopb: endpoint@0 {
1147					reg = <0>;
1148					remote-endpoint = <&vopb_out_dsi>;
1149				};
1150
1151				dsi_in_vopl: endpoint@1 {
1152					reg = <1>;
1153					remote-endpoint = <&vopl_out_dsi>;
1154				};
1155			};
1156
1157			dsi_out: port@1 {
1158				reg = <1>;
1159			};
1160		};
1161	};
1162
1163	vopb: vop@ff460000 {
1164		compatible = "rockchip,px30-vop-big";
1165		reg = <0x0 0xff460000 0x0 0xefc>;
1166		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1167		clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1168			 <&cru HCLK_VOPB>;
1169		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1170		resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1171		reset-names = "axi", "ahb", "dclk";
1172		iommus = <&vopb_mmu>;
1173		power-domains = <&power PX30_PD_VO>;
1174		status = "disabled";
1175
1176		vopb_out: port {
1177			#address-cells = <1>;
1178			#size-cells = <0>;
1179
1180			vopb_out_dsi: endpoint@0 {
1181				reg = <0>;
1182				remote-endpoint = <&dsi_in_vopb>;
1183			};
1184
1185			vopb_out_lvds: endpoint@1 {
1186				reg = <1>;
1187				remote-endpoint = <&lvds_vopb_in>;
1188			};
1189		};
1190	};
1191
1192	vopb_mmu: iommu@ff460f00 {
1193		compatible = "rockchip,iommu";
1194		reg = <0x0 0xff460f00 0x0 0x100>;
1195		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1196		clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1197		clock-names = "aclk", "iface";
1198		power-domains = <&power PX30_PD_VO>;
1199		#iommu-cells = <0>;
1200		status = "disabled";
1201	};
1202
1203	vopl: vop@ff470000 {
1204		compatible = "rockchip,px30-vop-lit";
1205		reg = <0x0 0xff470000 0x0 0xefc>;
1206		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1207		clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1208			 <&cru HCLK_VOPL>;
1209		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1210		resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1211		reset-names = "axi", "ahb", "dclk";
1212		iommus = <&vopl_mmu>;
1213		power-domains = <&power PX30_PD_VO>;
1214		status = "disabled";
1215
1216		vopl_out: port {
1217			#address-cells = <1>;
1218			#size-cells = <0>;
1219
1220			vopl_out_dsi: endpoint@0 {
1221				reg = <0>;
1222				remote-endpoint = <&dsi_in_vopl>;
1223			};
1224
1225			vopl_out_lvds: endpoint@1 {
1226				reg = <1>;
1227				remote-endpoint = <&lvds_vopl_in>;
1228			};
1229		};
1230	};
1231
1232	vopl_mmu: iommu@ff470f00 {
1233		compatible = "rockchip,iommu";
1234		reg = <0x0 0xff470f00 0x0 0x100>;
1235		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1236		clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1237		clock-names = "aclk", "iface";
1238		power-domains = <&power PX30_PD_VO>;
1239		#iommu-cells = <0>;
1240		status = "disabled";
1241	};
1242
1243	isp: isp@ff4a0000 {
1244		compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1245		reg = <0x0 0xff4a0000 0x0 0x8000>;
1246		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1247			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1248			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1249		interrupt-names = "isp", "mi", "mipi";
1250		clocks = <&cru SCLK_ISP>,
1251			 <&cru ACLK_ISP>,
1252			 <&cru HCLK_ISP>,
1253			 <&cru PCLK_ISP>;
1254		clock-names = "isp", "aclk", "hclk", "pclk";
1255		iommus = <&isp_mmu>;
1256		phys = <&csi_dphy>;
1257		phy-names = "dphy";
1258		power-domains = <&power PX30_PD_VI>;
1259		status = "disabled";
1260
1261		ports {
1262			#address-cells = <1>;
1263			#size-cells = <0>;
1264
1265			port@0 {
1266				reg = <0>;
1267				#address-cells = <1>;
1268				#size-cells = <0>;
1269			};
1270		};
1271	};
1272
1273	isp_mmu: iommu@ff4a8000 {
1274		compatible = "rockchip,iommu";
1275		reg = <0x0 0xff4a8000 0x0 0x100>;
1276		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1277		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1278		clock-names = "aclk", "iface";
1279		power-domains = <&power PX30_PD_VI>;
1280		rockchip,disable-mmu-reset;
1281		#iommu-cells = <0>;
1282	};
1283
1284	qos_gmac: qos@ff518000 {
1285		compatible = "rockchip,px30-qos", "syscon";
1286		reg = <0x0 0xff518000 0x0 0x20>;
1287	};
1288
1289	qos_gpu: qos@ff520000 {
1290		compatible = "rockchip,px30-qos", "syscon";
1291		reg = <0x0 0xff520000 0x0 0x20>;
1292	};
1293
1294	qos_sdmmc: qos@ff52c000 {
1295		compatible = "rockchip,px30-qos", "syscon";
1296		reg = <0x0 0xff52c000 0x0 0x20>;
1297	};
1298
1299	qos_emmc: qos@ff538000 {
1300		compatible = "rockchip,px30-qos", "syscon";
1301		reg = <0x0 0xff538000 0x0 0x20>;
1302	};
1303
1304	qos_nand: qos@ff538080 {
1305		compatible = "rockchip,px30-qos", "syscon";
1306		reg = <0x0 0xff538080 0x0 0x20>;
1307	};
1308
1309	qos_sdio: qos@ff538100 {
1310		compatible = "rockchip,px30-qos", "syscon";
1311		reg = <0x0 0xff538100 0x0 0x20>;
1312	};
1313
1314	qos_sfc: qos@ff538180 {
1315		compatible = "rockchip,px30-qos", "syscon";
1316		reg = <0x0 0xff538180 0x0 0x20>;
1317	};
1318
1319	qos_usb_host: qos@ff540000 {
1320		compatible = "rockchip,px30-qos", "syscon";
1321		reg = <0x0 0xff540000 0x0 0x20>;
1322	};
1323
1324	qos_usb_otg: qos@ff540080 {
1325		compatible = "rockchip,px30-qos", "syscon";
1326		reg = <0x0 0xff540080 0x0 0x20>;
1327	};
1328
1329	qos_isp_128: qos@ff548000 {
1330		compatible = "rockchip,px30-qos", "syscon";
1331		reg = <0x0 0xff548000 0x0 0x20>;
1332	};
1333
1334	qos_isp_rd: qos@ff548080 {
1335		compatible = "rockchip,px30-qos", "syscon";
1336		reg = <0x0 0xff548080 0x0 0x20>;
1337	};
1338
1339	qos_isp_wr: qos@ff548100 {
1340		compatible = "rockchip,px30-qos", "syscon";
1341		reg = <0x0 0xff548100 0x0 0x20>;
1342	};
1343
1344	qos_isp_m1: qos@ff548180 {
1345		compatible = "rockchip,px30-qos", "syscon";
1346		reg = <0x0 0xff548180 0x0 0x20>;
1347	};
1348
1349	qos_vip: qos@ff548200 {
1350		compatible = "rockchip,px30-qos", "syscon";
1351		reg = <0x0 0xff548200 0x0 0x20>;
1352	};
1353
1354	qos_rga_rd: qos@ff550000 {
1355		compatible = "rockchip,px30-qos", "syscon";
1356		reg = <0x0 0xff550000 0x0 0x20>;
1357	};
1358
1359	qos_rga_wr: qos@ff550080 {
1360		compatible = "rockchip,px30-qos", "syscon";
1361		reg = <0x0 0xff550080 0x0 0x20>;
1362	};
1363
1364	qos_vop_m0: qos@ff550100 {
1365		compatible = "rockchip,px30-qos", "syscon";
1366		reg = <0x0 0xff550100 0x0 0x20>;
1367	};
1368
1369	qos_vop_m1: qos@ff550180 {
1370		compatible = "rockchip,px30-qos", "syscon";
1371		reg = <0x0 0xff550180 0x0 0x20>;
1372	};
1373
1374	qos_vpu: qos@ff558000 {
1375		compatible = "rockchip,px30-qos", "syscon";
1376		reg = <0x0 0xff558000 0x0 0x20>;
1377	};
1378
1379	qos_vpu_r128: qos@ff558080 {
1380		compatible = "rockchip,px30-qos", "syscon";
1381		reg = <0x0 0xff558080 0x0 0x20>;
1382	};
1383
1384	pinctrl: pinctrl {
1385		compatible = "rockchip,px30-pinctrl";
1386		rockchip,grf = <&grf>;
1387		rockchip,pmu = <&pmugrf>;
1388		#address-cells = <2>;
1389		#size-cells = <2>;
1390		ranges;
1391
1392		gpio0: gpio@ff040000 {
1393			compatible = "rockchip,gpio-bank";
1394			reg = <0x0 0xff040000 0x0 0x100>;
1395			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1396			clocks = <&pmucru PCLK_GPIO0_PMU>;
1397			gpio-controller;
1398			#gpio-cells = <2>;
1399
1400			interrupt-controller;
1401			#interrupt-cells = <2>;
1402		};
1403
1404		gpio1: gpio@ff250000 {
1405			compatible = "rockchip,gpio-bank";
1406			reg = <0x0 0xff250000 0x0 0x100>;
1407			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1408			clocks = <&cru PCLK_GPIO1>;
1409			gpio-controller;
1410			#gpio-cells = <2>;
1411
1412			interrupt-controller;
1413			#interrupt-cells = <2>;
1414		};
1415
1416		gpio2: gpio@ff260000 {
1417			compatible = "rockchip,gpio-bank";
1418			reg = <0x0 0xff260000 0x0 0x100>;
1419			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1420			clocks = <&cru PCLK_GPIO2>;
1421			gpio-controller;
1422			#gpio-cells = <2>;
1423
1424			interrupt-controller;
1425			#interrupt-cells = <2>;
1426		};
1427
1428		gpio3: gpio@ff270000 {
1429			compatible = "rockchip,gpio-bank";
1430			reg = <0x0 0xff270000 0x0 0x100>;
1431			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1432			clocks = <&cru PCLK_GPIO3>;
1433			gpio-controller;
1434			#gpio-cells = <2>;
1435
1436			interrupt-controller;
1437			#interrupt-cells = <2>;
1438		};
1439
1440		pcfg_pull_up: pcfg-pull-up {
1441			bias-pull-up;
1442		};
1443
1444		pcfg_pull_down: pcfg-pull-down {
1445			bias-pull-down;
1446		};
1447
1448		pcfg_pull_none: pcfg-pull-none {
1449			bias-disable;
1450		};
1451
1452		pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1453			bias-disable;
1454			drive-strength = <2>;
1455		};
1456
1457		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1458			bias-pull-up;
1459			drive-strength = <2>;
1460		};
1461
1462		pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1463			bias-pull-up;
1464			drive-strength = <4>;
1465		};
1466
1467		pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1468			bias-disable;
1469			drive-strength = <4>;
1470		};
1471
1472		pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1473			bias-pull-down;
1474			drive-strength = <4>;
1475		};
1476
1477		pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1478			bias-disable;
1479			drive-strength = <8>;
1480		};
1481
1482		pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1483			bias-pull-up;
1484			drive-strength = <8>;
1485		};
1486
1487		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1488			bias-disable;
1489			drive-strength = <12>;
1490		};
1491
1492		pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1493			bias-pull-up;
1494			drive-strength = <12>;
1495		};
1496
1497		pcfg_pull_none_smt: pcfg-pull-none-smt {
1498			bias-disable;
1499			input-schmitt-enable;
1500		};
1501
1502		pcfg_output_high: pcfg-output-high {
1503			output-high;
1504		};
1505
1506		pcfg_output_low: pcfg-output-low {
1507			output-low;
1508		};
1509
1510		pcfg_input_high: pcfg-input-high {
1511			bias-pull-up;
1512			input-enable;
1513		};
1514
1515		pcfg_input: pcfg-input {
1516			input-enable;
1517		};
1518
1519		i2c0 {
1520			i2c0_xfer: i2c0-xfer {
1521				rockchip,pins =
1522					<0 RK_PB0 1 &pcfg_pull_none_smt>,
1523					<0 RK_PB1 1 &pcfg_pull_none_smt>;
1524			};
1525		};
1526
1527		i2c1 {
1528			i2c1_xfer: i2c1-xfer {
1529				rockchip,pins =
1530					<0 RK_PC2 1 &pcfg_pull_none_smt>,
1531					<0 RK_PC3 1 &pcfg_pull_none_smt>;
1532			};
1533		};
1534
1535		i2c2 {
1536			i2c2_xfer: i2c2-xfer {
1537				rockchip,pins =
1538					<2 RK_PB7 2 &pcfg_pull_none_smt>,
1539					<2 RK_PC0 2 &pcfg_pull_none_smt>;
1540			};
1541		};
1542
1543		i2c3 {
1544			i2c3_xfer: i2c3-xfer {
1545				rockchip,pins =
1546					<1 RK_PB4 4 &pcfg_pull_none_smt>,
1547					<1 RK_PB5 4 &pcfg_pull_none_smt>;
1548			};
1549		};
1550
1551		tsadc {
1552			tsadc_otp_pin: tsadc-otp-pin {
1553				rockchip,pins =
1554					<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1555			};
1556
1557			tsadc_otp_out: tsadc-otp-out {
1558				rockchip,pins =
1559					<0 RK_PA6 1 &pcfg_pull_none>;
1560			};
1561		};
1562
1563		uart0 {
1564			uart0_xfer: uart0-xfer {
1565				rockchip,pins =
1566					<0 RK_PB2 1 &pcfg_pull_up>,
1567					<0 RK_PB3 1 &pcfg_pull_up>;
1568			};
1569
1570			uart0_cts: uart0-cts {
1571				rockchip,pins =
1572					<0 RK_PB4 1 &pcfg_pull_none>;
1573			};
1574
1575			uart0_rts: uart0-rts {
1576				rockchip,pins =
1577					<0 RK_PB5 1 &pcfg_pull_none>;
1578			};
1579		};
1580
1581		uart1 {
1582			uart1_xfer: uart1-xfer {
1583				rockchip,pins =
1584					<1 RK_PC1 1 &pcfg_pull_up>,
1585					<1 RK_PC0 1 &pcfg_pull_up>;
1586			};
1587
1588			uart1_cts: uart1-cts {
1589				rockchip,pins =
1590					<1 RK_PC2 1 &pcfg_pull_none>;
1591			};
1592
1593			uart1_rts: uart1-rts {
1594				rockchip,pins =
1595					<1 RK_PC3 1 &pcfg_pull_none>;
1596			};
1597		};
1598
1599		uart2-m0 {
1600			uart2m0_xfer: uart2m0-xfer {
1601				rockchip,pins =
1602					<1 RK_PD2 2 &pcfg_pull_up>,
1603					<1 RK_PD3 2 &pcfg_pull_up>;
1604			};
1605		};
1606
1607		uart2-m1 {
1608			uart2m1_xfer: uart2m1-xfer {
1609				rockchip,pins =
1610					<2 RK_PB4 2 &pcfg_pull_up>,
1611					<2 RK_PB6 2 &pcfg_pull_up>;
1612			};
1613		};
1614
1615		uart3-m0 {
1616			uart3m0_xfer: uart3m0-xfer {
1617				rockchip,pins =
1618					<0 RK_PC0 2 &pcfg_pull_up>,
1619					<0 RK_PC1 2 &pcfg_pull_up>;
1620			};
1621
1622			uart3m0_cts: uart3m0-cts {
1623				rockchip,pins =
1624					<0 RK_PC2 2 &pcfg_pull_none>;
1625			};
1626
1627			uart3m0_rts: uart3m0-rts {
1628				rockchip,pins =
1629					<0 RK_PC3 2 &pcfg_pull_none>;
1630			};
1631		};
1632
1633		uart3-m1 {
1634			uart3m1_xfer: uart3m1-xfer {
1635				rockchip,pins =
1636					<1 RK_PB6 2 &pcfg_pull_up>,
1637					<1 RK_PB7 2 &pcfg_pull_up>;
1638			};
1639
1640			uart3m1_cts: uart3m1-cts {
1641				rockchip,pins =
1642					<1 RK_PB4 2 &pcfg_pull_none>;
1643			};
1644
1645			uart3m1_rts: uart3m1-rts {
1646				rockchip,pins =
1647					<1 RK_PB5 2 &pcfg_pull_none>;
1648			};
1649		};
1650
1651		uart4 {
1652			uart4_xfer: uart4-xfer {
1653				rockchip,pins =
1654					<1 RK_PD4 2 &pcfg_pull_up>,
1655					<1 RK_PD5 2 &pcfg_pull_up>;
1656			};
1657
1658			uart4_cts: uart4-cts {
1659				rockchip,pins =
1660					<1 RK_PD6 2 &pcfg_pull_none>;
1661			};
1662
1663			uart4_rts: uart4-rts {
1664				rockchip,pins =
1665					<1 RK_PD7 2 &pcfg_pull_none>;
1666			};
1667		};
1668
1669		uart5 {
1670			uart5_xfer: uart5-xfer {
1671				rockchip,pins =
1672					<3 RK_PA2 4 &pcfg_pull_up>,
1673					<3 RK_PA1 4 &pcfg_pull_up>;
1674			};
1675
1676			uart5_cts: uart5-cts {
1677				rockchip,pins =
1678					<3 RK_PA3 4 &pcfg_pull_none>;
1679			};
1680
1681			uart5_rts: uart5-rts {
1682				rockchip,pins =
1683					<3 RK_PA5 4 &pcfg_pull_none>;
1684			};
1685		};
1686
1687		spi0 {
1688			spi0_clk: spi0-clk {
1689				rockchip,pins =
1690					<1 RK_PB7 3 &pcfg_pull_up_4ma>;
1691			};
1692
1693			spi0_csn: spi0-csn {
1694				rockchip,pins =
1695					<1 RK_PB6 3 &pcfg_pull_up_4ma>;
1696			};
1697
1698			spi0_miso: spi0-miso {
1699				rockchip,pins =
1700					<1 RK_PB5 3 &pcfg_pull_up_4ma>;
1701			};
1702
1703			spi0_mosi: spi0-mosi {
1704				rockchip,pins =
1705					<1 RK_PB4 3 &pcfg_pull_up_4ma>;
1706			};
1707
1708			spi0_clk_hs: spi0-clk-hs {
1709				rockchip,pins =
1710					<1 RK_PB7 3 &pcfg_pull_up_8ma>;
1711			};
1712
1713			spi0_miso_hs: spi0-miso-hs {
1714				rockchip,pins =
1715					<1 RK_PB5 3 &pcfg_pull_up_8ma>;
1716			};
1717
1718			spi0_mosi_hs: spi0-mosi-hs {
1719				rockchip,pins =
1720					<1 RK_PB4 3 &pcfg_pull_up_8ma>;
1721			};
1722		};
1723
1724		spi1 {
1725			spi1_clk: spi1-clk {
1726				rockchip,pins =
1727					<3 RK_PB7 4 &pcfg_pull_up_4ma>;
1728			};
1729
1730			spi1_csn0: spi1-csn0 {
1731				rockchip,pins =
1732					<3 RK_PB1 4 &pcfg_pull_up_4ma>;
1733			};
1734
1735			spi1_csn1: spi1-csn1 {
1736				rockchip,pins =
1737					<3 RK_PB2 2 &pcfg_pull_up_4ma>;
1738			};
1739
1740			spi1_miso: spi1-miso {
1741				rockchip,pins =
1742					<3 RK_PB6 4 &pcfg_pull_up_4ma>;
1743			};
1744
1745			spi1_mosi: spi1-mosi {
1746				rockchip,pins =
1747					<3 RK_PB4 4 &pcfg_pull_up_4ma>;
1748			};
1749
1750			spi1_clk_hs: spi1-clk-hs {
1751				rockchip,pins =
1752					<3 RK_PB7 4 &pcfg_pull_up_8ma>;
1753			};
1754
1755			spi1_miso_hs: spi1-miso-hs {
1756				rockchip,pins =
1757					<3 RK_PB6 4 &pcfg_pull_up_8ma>;
1758			};
1759
1760			spi1_mosi_hs: spi1-mosi-hs {
1761				rockchip,pins =
1762					<3 RK_PB4 4 &pcfg_pull_up_8ma>;
1763			};
1764		};
1765
1766		pdm {
1767			pdm_clk0m0: pdm-clk0m0 {
1768				rockchip,pins =
1769					<3 RK_PC6 2 &pcfg_pull_none>;
1770			};
1771
1772			pdm_clk0m1: pdm-clk0m1 {
1773				rockchip,pins =
1774					<2 RK_PC6 1 &pcfg_pull_none>;
1775			};
1776
1777			pdm_clk1: pdm-clk1 {
1778				rockchip,pins =
1779					<3 RK_PC7 2 &pcfg_pull_none>;
1780			};
1781
1782			pdm_sdi0m0: pdm-sdi0m0 {
1783				rockchip,pins =
1784					<3 RK_PD3 2 &pcfg_pull_none>;
1785			};
1786
1787			pdm_sdi0m1: pdm-sdi0m1 {
1788				rockchip,pins =
1789					<2 RK_PC5 2 &pcfg_pull_none>;
1790			};
1791
1792			pdm_sdi1: pdm-sdi1 {
1793				rockchip,pins =
1794					<3 RK_PD0 2 &pcfg_pull_none>;
1795			};
1796
1797			pdm_sdi2: pdm-sdi2 {
1798				rockchip,pins =
1799					<3 RK_PD1 2 &pcfg_pull_none>;
1800			};
1801
1802			pdm_sdi3: pdm-sdi3 {
1803				rockchip,pins =
1804					<3 RK_PD2 2 &pcfg_pull_none>;
1805			};
1806
1807			pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1808				rockchip,pins =
1809					<3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1810			};
1811
1812			pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1813				rockchip,pins =
1814					<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1815			};
1816
1817			pdm_clk1_sleep: pdm-clk1-sleep {
1818				rockchip,pins =
1819					<3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1820			};
1821
1822			pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1823				rockchip,pins =
1824					<3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1825			};
1826
1827			pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1828				rockchip,pins =
1829					<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1830			};
1831
1832			pdm_sdi1_sleep: pdm-sdi1-sleep {
1833				rockchip,pins =
1834					<3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1835			};
1836
1837			pdm_sdi2_sleep: pdm-sdi2-sleep {
1838				rockchip,pins =
1839					<3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1840			};
1841
1842			pdm_sdi3_sleep: pdm-sdi3-sleep {
1843				rockchip,pins =
1844					<3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1845			};
1846		};
1847
1848		i2s0 {
1849			i2s0_8ch_mclk: i2s0-8ch-mclk {
1850				rockchip,pins =
1851					<3 RK_PC1 2 &pcfg_pull_none>;
1852			};
1853
1854			i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1855				rockchip,pins =
1856					<3 RK_PC3 2 &pcfg_pull_none>;
1857			};
1858
1859			i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1860				rockchip,pins =
1861					<3 RK_PB4 2 &pcfg_pull_none>;
1862			};
1863
1864			i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1865				rockchip,pins =
1866					<3 RK_PC2 2 &pcfg_pull_none>;
1867			};
1868
1869			i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1870				rockchip,pins =
1871					<3 RK_PB5 2 &pcfg_pull_none>;
1872			};
1873
1874			i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1875				rockchip,pins =
1876					<3 RK_PC4 2 &pcfg_pull_none>;
1877			};
1878
1879			i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1880				rockchip,pins =
1881					<3 RK_PC0 2 &pcfg_pull_none>;
1882			};
1883
1884			i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1885				rockchip,pins =
1886					<3 RK_PB7 2 &pcfg_pull_none>;
1887			};
1888
1889			i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1890				rockchip,pins =
1891					<3 RK_PB6 2 &pcfg_pull_none>;
1892			};
1893
1894			i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1895				rockchip,pins =
1896					<3 RK_PC5 2 &pcfg_pull_none>;
1897			};
1898
1899			i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1900				rockchip,pins =
1901					<3 RK_PB3 2 &pcfg_pull_none>;
1902			};
1903
1904			i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1905				rockchip,pins =
1906					<3 RK_PB1 2 &pcfg_pull_none>;
1907			};
1908
1909			i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1910				rockchip,pins =
1911					<3 RK_PB0 2 &pcfg_pull_none>;
1912			};
1913		};
1914
1915		i2s1 {
1916			i2s1_2ch_mclk: i2s1-2ch-mclk {
1917				rockchip,pins =
1918					<2 RK_PC3 1 &pcfg_pull_none>;
1919			};
1920
1921			i2s1_2ch_sclk: i2s1-2ch-sclk {
1922				rockchip,pins =
1923					<2 RK_PC2 1 &pcfg_pull_none>;
1924			};
1925
1926			i2s1_2ch_lrck: i2s1-2ch-lrck {
1927				rockchip,pins =
1928					<2 RK_PC1 1 &pcfg_pull_none>;
1929			};
1930
1931			i2s1_2ch_sdi: i2s1-2ch-sdi {
1932				rockchip,pins =
1933					<2 RK_PC5 1 &pcfg_pull_none>;
1934			};
1935
1936			i2s1_2ch_sdo: i2s1-2ch-sdo {
1937				rockchip,pins =
1938					<2 RK_PC4 1 &pcfg_pull_none>;
1939			};
1940		};
1941
1942		i2s2 {
1943			i2s2_2ch_mclk: i2s2-2ch-mclk {
1944				rockchip,pins =
1945					<3 RK_PA1 2 &pcfg_pull_none>;
1946			};
1947
1948			i2s2_2ch_sclk: i2s2-2ch-sclk {
1949				rockchip,pins =
1950					<3 RK_PA2 2 &pcfg_pull_none>;
1951			};
1952
1953			i2s2_2ch_lrck: i2s2-2ch-lrck {
1954				rockchip,pins =
1955					<3 RK_PA3 2 &pcfg_pull_none>;
1956			};
1957
1958			i2s2_2ch_sdi: i2s2-2ch-sdi {
1959				rockchip,pins =
1960					<3 RK_PA5 2 &pcfg_pull_none>;
1961			};
1962
1963			i2s2_2ch_sdo: i2s2-2ch-sdo {
1964				rockchip,pins =
1965					<3 RK_PA7 2 &pcfg_pull_none>;
1966			};
1967		};
1968
1969		sdmmc {
1970			sdmmc_clk: sdmmc-clk {
1971				rockchip,pins =
1972					<1 RK_PD6 1 &pcfg_pull_none_8ma>;
1973			};
1974
1975			sdmmc_cmd: sdmmc-cmd {
1976				rockchip,pins =
1977					<1 RK_PD7 1 &pcfg_pull_up_8ma>;
1978			};
1979
1980			sdmmc_det: sdmmc-det {
1981				rockchip,pins =
1982					<0 RK_PA3 1 &pcfg_pull_up_8ma>;
1983			};
1984
1985			sdmmc_bus1: sdmmc-bus1 {
1986				rockchip,pins =
1987					<1 RK_PD2 1 &pcfg_pull_up_8ma>;
1988			};
1989
1990			sdmmc_bus4: sdmmc-bus4 {
1991				rockchip,pins =
1992					<1 RK_PD2 1 &pcfg_pull_up_8ma>,
1993					<1 RK_PD3 1 &pcfg_pull_up_8ma>,
1994					<1 RK_PD4 1 &pcfg_pull_up_8ma>,
1995					<1 RK_PD5 1 &pcfg_pull_up_8ma>;
1996			};
1997		};
1998
1999		sdio {
2000			sdio_clk: sdio-clk {
2001				rockchip,pins =
2002					<1 RK_PC5 1 &pcfg_pull_none>;
2003			};
2004
2005			sdio_cmd: sdio-cmd {
2006				rockchip,pins =
2007					<1 RK_PC4 1 &pcfg_pull_up>;
2008			};
2009
2010			sdio_bus4: sdio-bus4 {
2011				rockchip,pins =
2012					<1 RK_PC6 1 &pcfg_pull_up>,
2013					<1 RK_PC7 1 &pcfg_pull_up>,
2014					<1 RK_PD0 1 &pcfg_pull_up>,
2015					<1 RK_PD1 1 &pcfg_pull_up>;
2016			};
2017		};
2018
2019		emmc {
2020			emmc_clk: emmc-clk {
2021				rockchip,pins =
2022					<1 RK_PB1 2 &pcfg_pull_none_8ma>;
2023			};
2024
2025			emmc_cmd: emmc-cmd {
2026				rockchip,pins =
2027					<1 RK_PB2 2 &pcfg_pull_up_8ma>;
2028			};
2029
2030			emmc_rstnout: emmc-rstnout {
2031				rockchip,pins =
2032					<1 RK_PB3 2 &pcfg_pull_none>;
2033			};
2034
2035			emmc_bus1: emmc-bus1 {
2036				rockchip,pins =
2037					<1 RK_PA0 2 &pcfg_pull_up_8ma>;
2038			};
2039
2040			emmc_bus4: emmc-bus4 {
2041				rockchip,pins =
2042					<1 RK_PA0 2 &pcfg_pull_up_8ma>,
2043					<1 RK_PA1 2 &pcfg_pull_up_8ma>,
2044					<1 RK_PA2 2 &pcfg_pull_up_8ma>,
2045					<1 RK_PA3 2 &pcfg_pull_up_8ma>;
2046			};
2047
2048			emmc_bus8: emmc-bus8 {
2049				rockchip,pins =
2050					<1 RK_PA0 2 &pcfg_pull_up_8ma>,
2051					<1 RK_PA1 2 &pcfg_pull_up_8ma>,
2052					<1 RK_PA2 2 &pcfg_pull_up_8ma>,
2053					<1 RK_PA3 2 &pcfg_pull_up_8ma>,
2054					<1 RK_PA4 2 &pcfg_pull_up_8ma>,
2055					<1 RK_PA5 2 &pcfg_pull_up_8ma>,
2056					<1 RK_PA6 2 &pcfg_pull_up_8ma>,
2057					<1 RK_PA7 2 &pcfg_pull_up_8ma>;
2058			};
2059		};
2060
2061		flash {
2062			flash_cs0: flash-cs0 {
2063				rockchip,pins =
2064					<1 RK_PB0 1 &pcfg_pull_none>;
2065			};
2066
2067			flash_rdy: flash-rdy {
2068				rockchip,pins =
2069					<1 RK_PB1 1 &pcfg_pull_none>;
2070			};
2071
2072			flash_dqs: flash-dqs {
2073				rockchip,pins =
2074					<1 RK_PB2 1 &pcfg_pull_none>;
2075			};
2076
2077			flash_ale: flash-ale {
2078				rockchip,pins =
2079					<1 RK_PB3 1 &pcfg_pull_none>;
2080			};
2081
2082			flash_cle: flash-cle {
2083				rockchip,pins =
2084					<1 RK_PB4 1 &pcfg_pull_none>;
2085			};
2086
2087			flash_wrn: flash-wrn {
2088				rockchip,pins =
2089					<1 RK_PB5 1 &pcfg_pull_none>;
2090			};
2091
2092			flash_csl: flash-csl {
2093				rockchip,pins =
2094					<1 RK_PB6 1 &pcfg_pull_none>;
2095			};
2096
2097			flash_rdn: flash-rdn {
2098				rockchip,pins =
2099					<1 RK_PB7 1 &pcfg_pull_none>;
2100			};
2101
2102			flash_bus8: flash-bus8 {
2103				rockchip,pins =
2104					<1 RK_PA0 1 &pcfg_pull_up_12ma>,
2105					<1 RK_PA1 1 &pcfg_pull_up_12ma>,
2106					<1 RK_PA2 1 &pcfg_pull_up_12ma>,
2107					<1 RK_PA3 1 &pcfg_pull_up_12ma>,
2108					<1 RK_PA4 1 &pcfg_pull_up_12ma>,
2109					<1 RK_PA5 1 &pcfg_pull_up_12ma>,
2110					<1 RK_PA6 1 &pcfg_pull_up_12ma>,
2111					<1 RK_PA7 1 &pcfg_pull_up_12ma>;
2112			};
2113		};
2114
2115		sfc {
2116			sfc_bus4: sfc-bus4 {
2117				rockchip,pins =
2118					<1 RK_PA0 3 &pcfg_pull_none>,
2119					<1 RK_PA1 3 &pcfg_pull_none>,
2120					<1 RK_PA2 3 &pcfg_pull_none>,
2121					<1 RK_PA3 3 &pcfg_pull_none>;
2122			};
2123
2124			sfc_bus2: sfc-bus2 {
2125				rockchip,pins =
2126					<1 RK_PA0 3 &pcfg_pull_none>,
2127					<1 RK_PA1 3 &pcfg_pull_none>;
2128			};
2129
2130			sfc_cs0: sfc-cs0 {
2131				rockchip,pins =
2132					<1 RK_PA4 3 &pcfg_pull_none>;
2133			};
2134
2135			sfc_clk: sfc-clk {
2136				rockchip,pins =
2137					<1 RK_PB1 3 &pcfg_pull_none>;
2138			};
2139		};
2140
2141		lcdc {
2142			lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2143				rockchip,pins =
2144					<3 RK_PA0 1 &pcfg_pull_none_12ma>;
2145			};
2146
2147			lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2148				rockchip,pins =
2149					<3 RK_PA1 1 &pcfg_pull_none_12ma>;
2150			};
2151
2152			lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2153				rockchip,pins =
2154					<3 RK_PA2 1 &pcfg_pull_none_12ma>;
2155			};
2156
2157			lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2158				rockchip,pins =
2159					<3 RK_PA3 1 &pcfg_pull_none_12ma>;
2160			};
2161
2162			lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2163				rockchip,pins =
2164					<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2165					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2166					<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2167					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2168					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2169					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2170					<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2171					<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2172					<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2173					<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2174					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2175					<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2176					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2177					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2178					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2179					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2180					<3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2181					<3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2182					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2183					<3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2184					<3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2185					<3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2186					<3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2187					<3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2188			};
2189
2190			lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2191				rockchip,pins =
2192					<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2193					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2194					<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2195					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2196					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2197					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2198					<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2199					<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2200					<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2201					<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2202					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2203					<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2204					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2205					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2206					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2207					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2208					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2209					<3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2210			};
2211
2212			lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2213				rockchip,pins =
2214					<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2215					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2216					<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2217					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2218					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2219					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2220					<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2221					<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2222					<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2223					<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2224					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2225					<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2226					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2227					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2228					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2229					<3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2230			};
2231
2232			lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2233				rockchip,pins =
2234					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2235					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2236					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2237					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2238					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2239					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2240					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2241					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2242					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2243					<3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2244					<3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2245					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2246					<3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2247					<3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2248					<3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2249					<3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2250					<3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2251			};
2252
2253			lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2254				rockchip,pins =
2255					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2256					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2257					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2258					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2259					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2260					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2261					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2262					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2263					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2264					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2265					<3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2266			};
2267
2268			lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2269				rockchip,pins =
2270					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2271					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2272					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2273					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2274					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2275					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2276					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2277					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2278					<3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2279			};
2280		};
2281
2282		pwm0 {
2283			pwm0_pin: pwm0-pin {
2284				rockchip,pins =
2285					<0 RK_PB7 1 &pcfg_pull_none>;
2286			};
2287		};
2288
2289		pwm1 {
2290			pwm1_pin: pwm1-pin {
2291				rockchip,pins =
2292					<0 RK_PC0 1 &pcfg_pull_none>;
2293			};
2294		};
2295
2296		pwm2 {
2297			pwm2_pin: pwm2-pin {
2298				rockchip,pins =
2299					<2 RK_PB5 1 &pcfg_pull_none>;
2300			};
2301		};
2302
2303		pwm3 {
2304			pwm3_pin: pwm3-pin {
2305				rockchip,pins =
2306					<0 RK_PC1 1 &pcfg_pull_none>;
2307			};
2308		};
2309
2310		pwm4 {
2311			pwm4_pin: pwm4-pin {
2312				rockchip,pins =
2313					<3 RK_PC2 3 &pcfg_pull_none>;
2314			};
2315		};
2316
2317		pwm5 {
2318			pwm5_pin: pwm5-pin {
2319				rockchip,pins =
2320					<3 RK_PC3 3 &pcfg_pull_none>;
2321			};
2322		};
2323
2324		pwm6 {
2325			pwm6_pin: pwm6-pin {
2326				rockchip,pins =
2327					<3 RK_PC4 3 &pcfg_pull_none>;
2328			};
2329		};
2330
2331		pwm7 {
2332			pwm7_pin: pwm7-pin {
2333				rockchip,pins =
2334					<3 RK_PC5 3 &pcfg_pull_none>;
2335			};
2336		};
2337
2338		gmac {
2339			rmii_pins: rmii-pins {
2340				rockchip,pins =
2341					<2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2342					<2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2343					<2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2344					<2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2345					<2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2346					<2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2347					<2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2348					<2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2349					<2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2350			};
2351
2352			mac_refclk_12ma: mac-refclk-12ma {
2353				rockchip,pins =
2354					<2 RK_PB2 2 &pcfg_pull_none_12ma>;
2355			};
2356
2357			mac_refclk: mac-refclk {
2358				rockchip,pins =
2359					<2 RK_PB2 2 &pcfg_pull_none>;
2360			};
2361		};
2362
2363		cif-m0 {
2364			cif_clkout_m0: cif-clkout-m0 {
2365				rockchip,pins =
2366					<2 RK_PB3 1 &pcfg_pull_none>;
2367			};
2368
2369			dvp_d2d9_m0: dvp-d2d9-m0 {
2370				rockchip,pins =
2371					<2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2372					<2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2373					<2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2374					<2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2375					<2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2376					<2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2377					<2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2378					<2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2379					<2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2380					<2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2381					<2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2382					<2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2383			};
2384
2385			dvp_d0d1_m0: dvp-d0d1-m0 {
2386				rockchip,pins =
2387					<2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2388					<2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2389			};
2390
2391			dvp_d10d11_m0:d10-d11-m0 {
2392				rockchip,pins =
2393					<2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2394					<2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2395			};
2396		};
2397
2398		cif-m1 {
2399			cif_clkout_m1: cif-clkout-m1 {
2400				rockchip,pins =
2401					<3 RK_PD0 3 &pcfg_pull_none>;
2402			};
2403
2404			dvp_d2d9_m1: dvp-d2d9-m1 {
2405				rockchip,pins =
2406					<3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2407					<3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2408					<3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2409					<3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2410					<3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2411					<3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2412					<3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2413					<3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2414					<3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2415					<3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2416					<3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2417					<3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2418			};
2419
2420			dvp_d0d1_m1: dvp-d0d1-m1 {
2421				rockchip,pins =
2422					<3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2423					<3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2424			};
2425
2426			dvp_d10d11_m1:d10-d11-m1 {
2427				rockchip,pins =
2428					<3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2429					<3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2430			};
2431		};
2432
2433		isp {
2434			isp_prelight: isp-prelight {
2435				rockchip,pins =
2436					<3 RK_PD1 4 &pcfg_pull_none>;
2437			};
2438		};
2439	};
2440};
2441