1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 mmc0 = &sdmmc; 29 mmc1 = &sdio; 30 mmc2 = &emmc; 31 serial0 = &uart0; 32 serial1 = &uart1; 33 serial2 = &uart2; 34 serial3 = &uart3; 35 serial4 = &uart4; 36 serial5 = &uart5; 37 spi0 = &spi0; 38 spi1 = &spi1; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 cpu0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a35"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 clocks = <&cru ARMCLK>; 51 #cooling-cells = <2>; 52 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 53 dynamic-power-coefficient = <90>; 54 operating-points-v2 = <&cpu0_opp_table>; 55 }; 56 57 cpu1: cpu@1 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a35"; 60 reg = <0x0 0x1>; 61 enable-method = "psci"; 62 clocks = <&cru ARMCLK>; 63 #cooling-cells = <2>; 64 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 65 dynamic-power-coefficient = <90>; 66 operating-points-v2 = <&cpu0_opp_table>; 67 }; 68 69 cpu2: cpu@2 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a35"; 72 reg = <0x0 0x2>; 73 enable-method = "psci"; 74 clocks = <&cru ARMCLK>; 75 #cooling-cells = <2>; 76 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 77 dynamic-power-coefficient = <90>; 78 operating-points-v2 = <&cpu0_opp_table>; 79 }; 80 81 cpu3: cpu@3 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a35"; 84 reg = <0x0 0x3>; 85 enable-method = "psci"; 86 clocks = <&cru ARMCLK>; 87 #cooling-cells = <2>; 88 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 89 dynamic-power-coefficient = <90>; 90 operating-points-v2 = <&cpu0_opp_table>; 91 }; 92 93 idle-states { 94 entry-method = "psci"; 95 96 CPU_SLEEP: cpu-sleep { 97 compatible = "arm,idle-state"; 98 local-timer-stop; 99 arm,psci-suspend-param = <0x0010000>; 100 entry-latency-us = <120>; 101 exit-latency-us = <250>; 102 min-residency-us = <900>; 103 }; 104 105 CLUSTER_SLEEP: cluster-sleep { 106 compatible = "arm,idle-state"; 107 local-timer-stop; 108 arm,psci-suspend-param = <0x1010000>; 109 entry-latency-us = <400>; 110 exit-latency-us = <500>; 111 min-residency-us = <2000>; 112 }; 113 }; 114 }; 115 116 cpu0_opp_table: cpu0-opp-table { 117 compatible = "operating-points-v2"; 118 opp-shared; 119 120 opp-600000000 { 121 opp-hz = /bits/ 64 <600000000>; 122 opp-microvolt = <950000 950000 1350000>; 123 clock-latency-ns = <40000>; 124 opp-suspend; 125 }; 126 opp-816000000 { 127 opp-hz = /bits/ 64 <816000000>; 128 opp-microvolt = <1050000 1050000 1350000>; 129 clock-latency-ns = <40000>; 130 }; 131 opp-1008000000 { 132 opp-hz = /bits/ 64 <1008000000>; 133 opp-microvolt = <1175000 1175000 1350000>; 134 clock-latency-ns = <40000>; 135 }; 136 opp-1200000000 { 137 opp-hz = /bits/ 64 <1200000000>; 138 opp-microvolt = <1300000 1300000 1350000>; 139 clock-latency-ns = <40000>; 140 }; 141 opp-1296000000 { 142 opp-hz = /bits/ 64 <1296000000>; 143 opp-microvolt = <1350000 1350000 1350000>; 144 clock-latency-ns = <40000>; 145 }; 146 }; 147 148 arm-pmu { 149 compatible = "arm,cortex-a35-pmu"; 150 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 154 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 155 }; 156 157 display_subsystem: display-subsystem { 158 compatible = "rockchip,display-subsystem"; 159 ports = <&vopb_out>, <&vopl_out>; 160 status = "disabled"; 161 }; 162 163 gmac_clkin: external-gmac-clock { 164 compatible = "fixed-clock"; 165 clock-frequency = <50000000>; 166 clock-output-names = "gmac_clkin"; 167 #clock-cells = <0>; 168 }; 169 170 psci { 171 compatible = "arm,psci-1.0"; 172 method = "smc"; 173 }; 174 175 timer { 176 compatible = "arm,armv8-timer"; 177 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 178 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 179 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 180 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 181 }; 182 183 thermal_zones: thermal-zones { 184 soc_thermal: soc-thermal { 185 polling-delay-passive = <20>; 186 polling-delay = <1000>; 187 sustainable-power = <750>; 188 thermal-sensors = <&tsadc 0>; 189 190 trips { 191 threshold: trip-point-0 { 192 temperature = <70000>; 193 hysteresis = <2000>; 194 type = "passive"; 195 }; 196 197 target: trip-point-1 { 198 temperature = <85000>; 199 hysteresis = <2000>; 200 type = "passive"; 201 }; 202 203 soc_crit: soc-crit { 204 temperature = <115000>; 205 hysteresis = <2000>; 206 type = "critical"; 207 }; 208 }; 209 210 cooling-maps { 211 map0 { 212 trip = <&target>; 213 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 214 contribution = <4096>; 215 }; 216 217 map1 { 218 trip = <&target>; 219 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 220 contribution = <4096>; 221 }; 222 }; 223 }; 224 225 gpu_thermal: gpu-thermal { 226 polling-delay-passive = <100>; /* milliseconds */ 227 polling-delay = <1000>; /* milliseconds */ 228 thermal-sensors = <&tsadc 1>; 229 }; 230 }; 231 232 xin24m: xin24m { 233 compatible = "fixed-clock"; 234 #clock-cells = <0>; 235 clock-frequency = <24000000>; 236 clock-output-names = "xin24m"; 237 }; 238 239 pmu: power-management@ff000000 { 240 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 241 reg = <0x0 0xff000000 0x0 0x1000>; 242 243 power: power-controller { 244 compatible = "rockchip,px30-power-controller"; 245 #power-domain-cells = <1>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 249 /* These power domains are grouped by VD_LOGIC */ 250 pd_usb@PX30_PD_USB { 251 reg = <PX30_PD_USB>; 252 clocks = <&cru HCLK_HOST>, 253 <&cru HCLK_OTG>, 254 <&cru SCLK_OTG_ADP>; 255 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 256 }; 257 pd_sdcard@PX30_PD_SDCARD { 258 reg = <PX30_PD_SDCARD>; 259 clocks = <&cru HCLK_SDMMC>, 260 <&cru SCLK_SDMMC>; 261 pm_qos = <&qos_sdmmc>; 262 }; 263 pd_gmac@PX30_PD_GMAC { 264 reg = <PX30_PD_GMAC>; 265 clocks = <&cru ACLK_GMAC>, 266 <&cru PCLK_GMAC>, 267 <&cru SCLK_MAC_REF>, 268 <&cru SCLK_GMAC_RX_TX>; 269 pm_qos = <&qos_gmac>; 270 }; 271 pd_mmc_nand@PX30_PD_MMC_NAND { 272 reg = <PX30_PD_MMC_NAND>; 273 clocks = <&cru HCLK_NANDC>, 274 <&cru HCLK_EMMC>, 275 <&cru HCLK_SDIO>, 276 <&cru HCLK_SFC>, 277 <&cru SCLK_EMMC>, 278 <&cru SCLK_NANDC>, 279 <&cru SCLK_SDIO>, 280 <&cru SCLK_SFC>; 281 pm_qos = <&qos_emmc>, <&qos_nand>, 282 <&qos_sdio>, <&qos_sfc>; 283 }; 284 pd_vpu@PX30_PD_VPU { 285 reg = <PX30_PD_VPU>; 286 clocks = <&cru ACLK_VPU>, 287 <&cru HCLK_VPU>, 288 <&cru SCLK_CORE_VPU>; 289 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 290 }; 291 pd_vo@PX30_PD_VO { 292 reg = <PX30_PD_VO>; 293 clocks = <&cru ACLK_RGA>, 294 <&cru ACLK_VOPB>, 295 <&cru ACLK_VOPL>, 296 <&cru DCLK_VOPB>, 297 <&cru DCLK_VOPL>, 298 <&cru HCLK_RGA>, 299 <&cru HCLK_VOPB>, 300 <&cru HCLK_VOPL>, 301 <&cru PCLK_MIPI_DSI>, 302 <&cru SCLK_RGA_CORE>, 303 <&cru SCLK_VOPB_PWM>; 304 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 305 <&qos_vop_m0>, <&qos_vop_m1>; 306 }; 307 pd_vi@PX30_PD_VI { 308 reg = <PX30_PD_VI>; 309 clocks = <&cru ACLK_CIF>, 310 <&cru ACLK_ISP>, 311 <&cru HCLK_CIF>, 312 <&cru HCLK_ISP>, 313 <&cru SCLK_ISP>; 314 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 315 <&qos_isp_wr>, <&qos_isp_m1>, 316 <&qos_vip>; 317 }; 318 pd_gpu@PX30_PD_GPU { 319 reg = <PX30_PD_GPU>; 320 clocks = <&cru SCLK_GPU>; 321 pm_qos = <&qos_gpu>; 322 }; 323 }; 324 }; 325 326 pmugrf: syscon@ff010000 { 327 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 328 reg = <0x0 0xff010000 0x0 0x1000>; 329 #address-cells = <1>; 330 #size-cells = <1>; 331 332 pmu_io_domains: io-domains { 333 compatible = "rockchip,px30-pmu-io-voltage-domain"; 334 status = "disabled"; 335 }; 336 337 reboot-mode { 338 compatible = "syscon-reboot-mode"; 339 offset = <0x200>; 340 mode-bootloader = <BOOT_BL_DOWNLOAD>; 341 mode-fastboot = <BOOT_FASTBOOT>; 342 mode-loader = <BOOT_BL_DOWNLOAD>; 343 mode-normal = <BOOT_NORMAL>; 344 mode-recovery = <BOOT_RECOVERY>; 345 }; 346 }; 347 348 uart0: serial@ff030000 { 349 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 350 reg = <0x0 0xff030000 0x0 0x100>; 351 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 353 clock-names = "baudclk", "apb_pclk"; 354 dmas = <&dmac 0>, <&dmac 1>; 355 dma-names = "tx", "rx"; 356 reg-shift = <2>; 357 reg-io-width = <4>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 360 status = "disabled"; 361 }; 362 363 i2s1_2ch: i2s@ff070000 { 364 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 365 reg = <0x0 0xff070000 0x0 0x1000>; 366 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 368 clock-names = "i2s_clk", "i2s_hclk"; 369 dmas = <&dmac 18>, <&dmac 19>; 370 dma-names = "tx", "rx"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 373 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 374 #sound-dai-cells = <0>; 375 status = "disabled"; 376 }; 377 378 i2s2_2ch: i2s@ff080000 { 379 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 380 reg = <0x0 0xff080000 0x0 0x1000>; 381 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 383 clock-names = "i2s_clk", "i2s_hclk"; 384 dmas = <&dmac 20>, <&dmac 21>; 385 dma-names = "tx", "rx"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 388 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 389 #sound-dai-cells = <0>; 390 status = "disabled"; 391 }; 392 393 gic: interrupt-controller@ff131000 { 394 compatible = "arm,gic-400"; 395 #interrupt-cells = <3>; 396 #address-cells = <0>; 397 interrupt-controller; 398 reg = <0x0 0xff131000 0 0x1000>, 399 <0x0 0xff132000 0 0x2000>, 400 <0x0 0xff134000 0 0x2000>, 401 <0x0 0xff136000 0 0x2000>; 402 interrupts = <GIC_PPI 9 403 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 404 }; 405 406 grf: syscon@ff140000 { 407 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 408 reg = <0x0 0xff140000 0x0 0x1000>; 409 #address-cells = <1>; 410 #size-cells = <1>; 411 412 io_domains: io-domains { 413 compatible = "rockchip,px30-io-voltage-domain"; 414 status = "disabled"; 415 }; 416 417 lvds: lvds { 418 compatible = "rockchip,px30-lvds"; 419 phys = <&dsi_dphy>; 420 phy-names = "dphy"; 421 rockchip,grf = <&grf>; 422 rockchip,output = "lvds"; 423 status = "disabled"; 424 425 ports { 426 #address-cells = <1>; 427 #size-cells = <0>; 428 429 port@0 { 430 reg = <0>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 434 lvds_vopb_in: endpoint@0 { 435 reg = <0>; 436 remote-endpoint = <&vopb_out_lvds>; 437 }; 438 439 lvds_vopl_in: endpoint@1 { 440 reg = <1>; 441 remote-endpoint = <&vopl_out_lvds>; 442 }; 443 }; 444 }; 445 }; 446 }; 447 448 uart1: serial@ff158000 { 449 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 450 reg = <0x0 0xff158000 0x0 0x100>; 451 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 453 clock-names = "baudclk", "apb_pclk"; 454 dmas = <&dmac 2>, <&dmac 3>; 455 dma-names = "tx", "rx"; 456 reg-shift = <2>; 457 reg-io-width = <4>; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 460 status = "disabled"; 461 }; 462 463 uart2: serial@ff160000 { 464 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 465 reg = <0x0 0xff160000 0x0 0x100>; 466 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 468 clock-names = "baudclk", "apb_pclk"; 469 dmas = <&dmac 4>, <&dmac 5>; 470 dma-names = "tx", "rx"; 471 reg-shift = <2>; 472 reg-io-width = <4>; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&uart2m0_xfer>; 475 status = "disabled"; 476 }; 477 478 uart3: serial@ff168000 { 479 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 480 reg = <0x0 0xff168000 0x0 0x100>; 481 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 483 clock-names = "baudclk", "apb_pclk"; 484 dmas = <&dmac 6>, <&dmac 7>; 485 dma-names = "tx", "rx"; 486 reg-shift = <2>; 487 reg-io-width = <4>; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 490 status = "disabled"; 491 }; 492 493 uart4: serial@ff170000 { 494 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 495 reg = <0x0 0xff170000 0x0 0x100>; 496 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 498 clock-names = "baudclk", "apb_pclk"; 499 dmas = <&dmac 8>, <&dmac 9>; 500 dma-names = "tx", "rx"; 501 reg-shift = <2>; 502 reg-io-width = <4>; 503 pinctrl-names = "default"; 504 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 505 status = "disabled"; 506 }; 507 508 uart5: serial@ff178000 { 509 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 510 reg = <0x0 0xff178000 0x0 0x100>; 511 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 513 clock-names = "baudclk", "apb_pclk"; 514 dmas = <&dmac 10>, <&dmac 11>; 515 dma-names = "tx", "rx"; 516 reg-shift = <2>; 517 reg-io-width = <4>; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 520 status = "disabled"; 521 }; 522 523 i2c0: i2c@ff180000 { 524 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 525 reg = <0x0 0xff180000 0x0 0x1000>; 526 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 527 clock-names = "i2c", "pclk"; 528 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 529 pinctrl-names = "default"; 530 pinctrl-0 = <&i2c0_xfer>; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 status = "disabled"; 534 }; 535 536 i2c1: i2c@ff190000 { 537 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 538 reg = <0x0 0xff190000 0x0 0x1000>; 539 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 540 clock-names = "i2c", "pclk"; 541 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 542 pinctrl-names = "default"; 543 pinctrl-0 = <&i2c1_xfer>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 status = "disabled"; 547 }; 548 549 i2c2: i2c@ff1a0000 { 550 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 551 reg = <0x0 0xff1a0000 0x0 0x1000>; 552 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 553 clock-names = "i2c", "pclk"; 554 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&i2c2_xfer>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 status = "disabled"; 560 }; 561 562 i2c3: i2c@ff1b0000 { 563 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 564 reg = <0x0 0xff1b0000 0x0 0x1000>; 565 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 566 clock-names = "i2c", "pclk"; 567 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&i2c3_xfer>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 status = "disabled"; 573 }; 574 575 spi0: spi@ff1d0000 { 576 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 577 reg = <0x0 0xff1d0000 0x0 0x1000>; 578 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 580 clock-names = "spiclk", "apb_pclk"; 581 dmas = <&dmac 12>, <&dmac 13>; 582 dma-names = "tx", "rx"; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 status = "disabled"; 588 }; 589 590 spi1: spi@ff1d8000 { 591 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 592 reg = <0x0 0xff1d8000 0x0 0x1000>; 593 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 595 clock-names = "spiclk", "apb_pclk"; 596 dmas = <&dmac 14>, <&dmac 15>; 597 dma-names = "tx", "rx"; 598 pinctrl-names = "default"; 599 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 status = "disabled"; 603 }; 604 605 wdt: watchdog@ff1e0000 { 606 compatible = "snps,dw-wdt"; 607 reg = <0x0 0xff1e0000 0x0 0x100>; 608 clocks = <&cru PCLK_WDT_NS>; 609 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 610 status = "disabled"; 611 }; 612 613 pwm0: pwm@ff200000 { 614 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 615 reg = <0x0 0xff200000 0x0 0x10>; 616 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 617 clock-names = "pwm", "pclk"; 618 pinctrl-names = "default"; 619 pinctrl-0 = <&pwm0_pin>; 620 #pwm-cells = <3>; 621 status = "disabled"; 622 }; 623 624 pwm1: pwm@ff200010 { 625 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 626 reg = <0x0 0xff200010 0x0 0x10>; 627 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 628 clock-names = "pwm", "pclk"; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&pwm1_pin>; 631 #pwm-cells = <3>; 632 status = "disabled"; 633 }; 634 635 pwm2: pwm@ff200020 { 636 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 637 reg = <0x0 0xff200020 0x0 0x10>; 638 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 639 clock-names = "pwm", "pclk"; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&pwm2_pin>; 642 #pwm-cells = <3>; 643 status = "disabled"; 644 }; 645 646 pwm3: pwm@ff200030 { 647 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 648 reg = <0x0 0xff200030 0x0 0x10>; 649 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 650 clock-names = "pwm", "pclk"; 651 pinctrl-names = "default"; 652 pinctrl-0 = <&pwm3_pin>; 653 #pwm-cells = <3>; 654 status = "disabled"; 655 }; 656 657 pwm4: pwm@ff208000 { 658 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 659 reg = <0x0 0xff208000 0x0 0x10>; 660 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 661 clock-names = "pwm", "pclk"; 662 pinctrl-names = "default"; 663 pinctrl-0 = <&pwm4_pin>; 664 #pwm-cells = <3>; 665 status = "disabled"; 666 }; 667 668 pwm5: pwm@ff208010 { 669 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 670 reg = <0x0 0xff208010 0x0 0x10>; 671 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 672 clock-names = "pwm", "pclk"; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&pwm5_pin>; 675 #pwm-cells = <3>; 676 status = "disabled"; 677 }; 678 679 pwm6: pwm@ff208020 { 680 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 681 reg = <0x0 0xff208020 0x0 0x10>; 682 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 683 clock-names = "pwm", "pclk"; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&pwm6_pin>; 686 #pwm-cells = <3>; 687 status = "disabled"; 688 }; 689 690 pwm7: pwm@ff208030 { 691 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 692 reg = <0x0 0xff208030 0x0 0x10>; 693 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 694 clock-names = "pwm", "pclk"; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&pwm7_pin>; 697 #pwm-cells = <3>; 698 status = "disabled"; 699 }; 700 701 rktimer: timer@ff210000 { 702 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 703 reg = <0x0 0xff210000 0x0 0x1000>; 704 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 706 clock-names = "pclk", "timer"; 707 }; 708 709 dmac: dmac@ff240000 { 710 compatible = "arm,pl330", "arm,primecell"; 711 reg = <0x0 0xff240000 0x0 0x4000>; 712 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 714 arm,pl330-periph-burst; 715 clocks = <&cru ACLK_DMAC>; 716 clock-names = "apb_pclk"; 717 #dma-cells = <1>; 718 }; 719 720 tsadc: tsadc@ff280000 { 721 compatible = "rockchip,px30-tsadc"; 722 reg = <0x0 0xff280000 0x0 0x100>; 723 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 724 assigned-clocks = <&cru SCLK_TSADC>; 725 assigned-clock-rates = <50000>; 726 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 727 clock-names = "tsadc", "apb_pclk"; 728 resets = <&cru SRST_TSADC>; 729 reset-names = "tsadc-apb"; 730 rockchip,grf = <&grf>; 731 rockchip,hw-tshut-temp = <120000>; 732 pinctrl-names = "init", "default", "sleep"; 733 pinctrl-0 = <&tsadc_otp_pin>; 734 pinctrl-1 = <&tsadc_otp_out>; 735 pinctrl-2 = <&tsadc_otp_pin>; 736 #thermal-sensor-cells = <1>; 737 status = "disabled"; 738 }; 739 740 saradc: saradc@ff288000 { 741 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 742 reg = <0x0 0xff288000 0x0 0x100>; 743 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 744 #io-channel-cells = <1>; 745 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 746 clock-names = "saradc", "apb_pclk"; 747 resets = <&cru SRST_SARADC_P>; 748 reset-names = "saradc-apb"; 749 status = "disabled"; 750 }; 751 752 otp: nvmem@ff290000 { 753 compatible = "rockchip,px30-otp"; 754 reg = <0x0 0xff290000 0x0 0x4000>; 755 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 756 <&cru PCLK_OTP_PHY>; 757 clock-names = "otp", "apb_pclk", "phy"; 758 resets = <&cru SRST_OTP_PHY>; 759 reset-names = "phy"; 760 #address-cells = <1>; 761 #size-cells = <1>; 762 763 /* Data cells */ 764 cpu_id: id@7 { 765 reg = <0x07 0x10>; 766 }; 767 cpu_leakage: cpu-leakage@17 { 768 reg = <0x17 0x1>; 769 }; 770 performance: performance@1e { 771 reg = <0x1e 0x1>; 772 bits = <4 3>; 773 }; 774 }; 775 776 cru: clock-controller@ff2b0000 { 777 compatible = "rockchip,px30-cru"; 778 reg = <0x0 0xff2b0000 0x0 0x1000>; 779 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 780 clock-names = "xin24m", "gpll"; 781 rockchip,grf = <&grf>; 782 #clock-cells = <1>; 783 #reset-cells = <1>; 784 785 assigned-clocks = <&cru PLL_NPLL>, 786 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 787 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 788 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 789 790 assigned-clock-rates = <1188000000>, 791 <200000000>, <200000000>, 792 <150000000>, <150000000>, 793 <100000000>, <200000000>; 794 }; 795 796 pmucru: clock-controller@ff2bc000 { 797 compatible = "rockchip,px30-pmucru"; 798 reg = <0x0 0xff2bc000 0x0 0x1000>; 799 clocks = <&xin24m>; 800 clock-names = "xin24m"; 801 rockchip,grf = <&grf>; 802 #clock-cells = <1>; 803 #reset-cells = <1>; 804 805 assigned-clocks = 806 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 807 <&pmucru SCLK_WIFI_PMU>; 808 assigned-clock-rates = 809 <1200000000>, <100000000>, 810 <26000000>; 811 }; 812 813 usb2phy_grf: syscon@ff2c0000 { 814 compatible = "rockchip,px30-usb2phy-grf", "syscon", 815 "simple-mfd"; 816 reg = <0x0 0xff2c0000 0x0 0x10000>; 817 #address-cells = <1>; 818 #size-cells = <1>; 819 820 u2phy: usb2-phy@100 { 821 compatible = "rockchip,px30-usb2phy"; 822 reg = <0x100 0x20>; 823 clocks = <&pmucru SCLK_USBPHY_REF>; 824 clock-names = "phyclk"; 825 #clock-cells = <0>; 826 assigned-clocks = <&cru USB480M>; 827 assigned-clock-parents = <&u2phy>; 828 clock-output-names = "usb480m_phy"; 829 status = "disabled"; 830 831 u2phy_host: host-port { 832 #phy-cells = <0>; 833 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 834 interrupt-names = "linestate"; 835 status = "disabled"; 836 }; 837 838 u2phy_otg: otg-port { 839 #phy-cells = <0>; 840 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 843 interrupt-names = "otg-bvalid", "otg-id", 844 "linestate"; 845 status = "disabled"; 846 }; 847 }; 848 }; 849 850 dsi_dphy: phy@ff2e0000 { 851 compatible = "rockchip,px30-dsi-dphy"; 852 reg = <0x0 0xff2e0000 0x0 0x10000>; 853 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 854 clock-names = "ref", "pclk"; 855 resets = <&cru SRST_MIPIDSIPHY_P>; 856 reset-names = "apb"; 857 #phy-cells = <0>; 858 power-domains = <&power PX30_PD_VO>; 859 status = "disabled"; 860 }; 861 862 usb20_otg: usb@ff300000 { 863 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 864 "snps,dwc2"; 865 reg = <0x0 0xff300000 0x0 0x40000>; 866 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&cru HCLK_OTG>; 868 clock-names = "otg"; 869 dr_mode = "otg"; 870 g-np-tx-fifo-size = <16>; 871 g-rx-fifo-size = <280>; 872 g-tx-fifo-size = <256 128 128 64 32 16>; 873 phys = <&u2phy_otg>; 874 phy-names = "usb2-phy"; 875 power-domains = <&power PX30_PD_USB>; 876 status = "disabled"; 877 }; 878 879 usb_host0_ehci: usb@ff340000 { 880 compatible = "generic-ehci"; 881 reg = <0x0 0xff340000 0x0 0x10000>; 882 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&cru HCLK_HOST>; 884 phys = <&u2phy_host>; 885 phy-names = "usb"; 886 power-domains = <&power PX30_PD_USB>; 887 status = "disabled"; 888 }; 889 890 usb_host0_ohci: usb@ff350000 { 891 compatible = "generic-ohci"; 892 reg = <0x0 0xff350000 0x0 0x10000>; 893 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&cru HCLK_HOST>; 895 phys = <&u2phy_host>; 896 phy-names = "usb"; 897 power-domains = <&power PX30_PD_USB>; 898 status = "disabled"; 899 }; 900 901 gmac: ethernet@ff360000 { 902 compatible = "rockchip,px30-gmac"; 903 reg = <0x0 0xff360000 0x0 0x10000>; 904 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 905 interrupt-names = "macirq"; 906 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 907 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 908 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 909 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 910 clock-names = "stmmaceth", "mac_clk_rx", 911 "mac_clk_tx", "clk_mac_ref", 912 "clk_mac_refout", "aclk_mac", 913 "pclk_mac", "clk_mac_speed"; 914 rockchip,grf = <&grf>; 915 phy-mode = "rmii"; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 918 power-domains = <&power PX30_PD_GMAC>; 919 resets = <&cru SRST_GMAC_A>; 920 reset-names = "stmmaceth"; 921 status = "disabled"; 922 }; 923 924 sdmmc: mmc@ff370000 { 925 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 926 reg = <0x0 0xff370000 0x0 0x4000>; 927 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 929 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 930 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 931 bus-width = <4>; 932 fifo-depth = <0x100>; 933 max-frequency = <150000000>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 936 power-domains = <&power PX30_PD_SDCARD>; 937 status = "disabled"; 938 }; 939 940 sdio: mmc@ff380000 { 941 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 942 reg = <0x0 0xff380000 0x0 0x4000>; 943 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 945 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 946 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 947 bus-width = <4>; 948 fifo-depth = <0x100>; 949 max-frequency = <150000000>; 950 pinctrl-names = "default"; 951 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 952 power-domains = <&power PX30_PD_MMC_NAND>; 953 status = "disabled"; 954 }; 955 956 emmc: mmc@ff390000 { 957 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 958 reg = <0x0 0xff390000 0x0 0x4000>; 959 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 961 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 962 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 963 bus-width = <8>; 964 fifo-depth = <0x100>; 965 max-frequency = <150000000>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 968 power-domains = <&power PX30_PD_MMC_NAND>; 969 status = "disabled"; 970 }; 971 972 nfc: nand-controller@ff3b0000 { 973 compatible = "rockchip,px30-nfc"; 974 reg = <0x0 0xff3b0000 0x0 0x4000>; 975 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 977 clock-names = "ahb", "nfc"; 978 assigned-clocks = <&cru SCLK_NANDC>; 979 assigned-clock-rates = <150000000>; 980 pinctrl-names = "default"; 981 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 982 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; 983 power-domains = <&power PX30_PD_MMC_NAND>; 984 status = "disabled"; 985 }; 986 987 gpu: gpu@ff400000 { 988 compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 989 reg = <0x0 0xff400000 0x0 0x4000>; 990 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 993 interrupt-names = "job", "mmu", "gpu"; 994 clocks = <&cru SCLK_GPU>; 995 #cooling-cells = <2>; 996 power-domains = <&power PX30_PD_GPU>; 997 status = "disabled"; 998 }; 999 1000 dsi: dsi@ff450000 { 1001 compatible = "rockchip,px30-mipi-dsi"; 1002 reg = <0x0 0xff450000 0x0 0x10000>; 1003 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&cru PCLK_MIPI_DSI>; 1005 clock-names = "pclk"; 1006 phys = <&dsi_dphy>; 1007 phy-names = "dphy"; 1008 power-domains = <&power PX30_PD_VO>; 1009 resets = <&cru SRST_MIPIDSI_HOST_P>; 1010 reset-names = "apb"; 1011 rockchip,grf = <&grf>; 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 status = "disabled"; 1015 1016 ports { 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 1020 port@0 { 1021 reg = <0>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 1025 dsi_in_vopb: endpoint@0 { 1026 reg = <0>; 1027 remote-endpoint = <&vopb_out_dsi>; 1028 }; 1029 1030 dsi_in_vopl: endpoint@1 { 1031 reg = <1>; 1032 remote-endpoint = <&vopl_out_dsi>; 1033 }; 1034 }; 1035 }; 1036 }; 1037 1038 vopb: vop@ff460000 { 1039 compatible = "rockchip,px30-vop-big"; 1040 reg = <0x0 0xff460000 0x0 0xefc>; 1041 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1043 <&cru HCLK_VOPB>; 1044 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1045 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1046 reset-names = "axi", "ahb", "dclk"; 1047 iommus = <&vopb_mmu>; 1048 power-domains = <&power PX30_PD_VO>; 1049 status = "disabled"; 1050 1051 vopb_out: port { 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 1055 vopb_out_dsi: endpoint@0 { 1056 reg = <0>; 1057 remote-endpoint = <&dsi_in_vopb>; 1058 }; 1059 1060 vopb_out_lvds: endpoint@1 { 1061 reg = <1>; 1062 remote-endpoint = <&lvds_vopb_in>; 1063 }; 1064 }; 1065 }; 1066 1067 vopb_mmu: iommu@ff460f00 { 1068 compatible = "rockchip,iommu"; 1069 reg = <0x0 0xff460f00 0x0 0x100>; 1070 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1071 interrupt-names = "vopb_mmu"; 1072 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1073 clock-names = "aclk", "iface"; 1074 power-domains = <&power PX30_PD_VO>; 1075 #iommu-cells = <0>; 1076 status = "disabled"; 1077 }; 1078 1079 vopl: vop@ff470000 { 1080 compatible = "rockchip,px30-vop-lit"; 1081 reg = <0x0 0xff470000 0x0 0xefc>; 1082 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1084 <&cru HCLK_VOPL>; 1085 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1086 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1087 reset-names = "axi", "ahb", "dclk"; 1088 iommus = <&vopl_mmu>; 1089 power-domains = <&power PX30_PD_VO>; 1090 status = "disabled"; 1091 1092 vopl_out: port { 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 1096 vopl_out_dsi: endpoint@0 { 1097 reg = <0>; 1098 remote-endpoint = <&dsi_in_vopl>; 1099 }; 1100 1101 vopl_out_lvds: endpoint@1 { 1102 reg = <1>; 1103 remote-endpoint = <&lvds_vopl_in>; 1104 }; 1105 }; 1106 }; 1107 1108 vopl_mmu: iommu@ff470f00 { 1109 compatible = "rockchip,iommu"; 1110 reg = <0x0 0xff470f00 0x0 0x100>; 1111 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1112 interrupt-names = "vopl_mmu"; 1113 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1114 clock-names = "aclk", "iface"; 1115 power-domains = <&power PX30_PD_VO>; 1116 #iommu-cells = <0>; 1117 status = "disabled"; 1118 }; 1119 1120 qos_gmac: qos@ff518000 { 1121 compatible = "rockchip,px30-qos", "syscon"; 1122 reg = <0x0 0xff518000 0x0 0x20>; 1123 }; 1124 1125 qos_gpu: qos@ff520000 { 1126 compatible = "rockchip,px30-qos", "syscon"; 1127 reg = <0x0 0xff520000 0x0 0x20>; 1128 }; 1129 1130 qos_sdmmc: qos@ff52c000 { 1131 compatible = "rockchip,px30-qos", "syscon"; 1132 reg = <0x0 0xff52c000 0x0 0x20>; 1133 }; 1134 1135 qos_emmc: qos@ff538000 { 1136 compatible = "rockchip,px30-qos", "syscon"; 1137 reg = <0x0 0xff538000 0x0 0x20>; 1138 }; 1139 1140 qos_nand: qos@ff538080 { 1141 compatible = "rockchip,px30-qos", "syscon"; 1142 reg = <0x0 0xff538080 0x0 0x20>; 1143 }; 1144 1145 qos_sdio: qos@ff538100 { 1146 compatible = "rockchip,px30-qos", "syscon"; 1147 reg = <0x0 0xff538100 0x0 0x20>; 1148 }; 1149 1150 qos_sfc: qos@ff538180 { 1151 compatible = "rockchip,px30-qos", "syscon"; 1152 reg = <0x0 0xff538180 0x0 0x20>; 1153 }; 1154 1155 qos_usb_host: qos@ff540000 { 1156 compatible = "rockchip,px30-qos", "syscon"; 1157 reg = <0x0 0xff540000 0x0 0x20>; 1158 }; 1159 1160 qos_usb_otg: qos@ff540080 { 1161 compatible = "rockchip,px30-qos", "syscon"; 1162 reg = <0x0 0xff540080 0x0 0x20>; 1163 }; 1164 1165 qos_isp_128: qos@ff548000 { 1166 compatible = "rockchip,px30-qos", "syscon"; 1167 reg = <0x0 0xff548000 0x0 0x20>; 1168 }; 1169 1170 qos_isp_rd: qos@ff548080 { 1171 compatible = "rockchip,px30-qos", "syscon"; 1172 reg = <0x0 0xff548080 0x0 0x20>; 1173 }; 1174 1175 qos_isp_wr: qos@ff548100 { 1176 compatible = "rockchip,px30-qos", "syscon"; 1177 reg = <0x0 0xff548100 0x0 0x20>; 1178 }; 1179 1180 qos_isp_m1: qos@ff548180 { 1181 compatible = "rockchip,px30-qos", "syscon"; 1182 reg = <0x0 0xff548180 0x0 0x20>; 1183 }; 1184 1185 qos_vip: qos@ff548200 { 1186 compatible = "rockchip,px30-qos", "syscon"; 1187 reg = <0x0 0xff548200 0x0 0x20>; 1188 }; 1189 1190 qos_rga_rd: qos@ff550000 { 1191 compatible = "rockchip,px30-qos", "syscon"; 1192 reg = <0x0 0xff550000 0x0 0x20>; 1193 }; 1194 1195 qos_rga_wr: qos@ff550080 { 1196 compatible = "rockchip,px30-qos", "syscon"; 1197 reg = <0x0 0xff550080 0x0 0x20>; 1198 }; 1199 1200 qos_vop_m0: qos@ff550100 { 1201 compatible = "rockchip,px30-qos", "syscon"; 1202 reg = <0x0 0xff550100 0x0 0x20>; 1203 }; 1204 1205 qos_vop_m1: qos@ff550180 { 1206 compatible = "rockchip,px30-qos", "syscon"; 1207 reg = <0x0 0xff550180 0x0 0x20>; 1208 }; 1209 1210 qos_vpu: qos@ff558000 { 1211 compatible = "rockchip,px30-qos", "syscon"; 1212 reg = <0x0 0xff558000 0x0 0x20>; 1213 }; 1214 1215 qos_vpu_r128: qos@ff558080 { 1216 compatible = "rockchip,px30-qos", "syscon"; 1217 reg = <0x0 0xff558080 0x0 0x20>; 1218 }; 1219 1220 pinctrl: pinctrl { 1221 compatible = "rockchip,px30-pinctrl"; 1222 rockchip,grf = <&grf>; 1223 rockchip,pmu = <&pmugrf>; 1224 #address-cells = <2>; 1225 #size-cells = <2>; 1226 ranges; 1227 1228 gpio0: gpio0@ff040000 { 1229 compatible = "rockchip,gpio-bank"; 1230 reg = <0x0 0xff040000 0x0 0x100>; 1231 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&pmucru PCLK_GPIO0_PMU>; 1233 gpio-controller; 1234 #gpio-cells = <2>; 1235 1236 interrupt-controller; 1237 #interrupt-cells = <2>; 1238 }; 1239 1240 gpio1: gpio1@ff250000 { 1241 compatible = "rockchip,gpio-bank"; 1242 reg = <0x0 0xff250000 0x0 0x100>; 1243 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1244 clocks = <&cru PCLK_GPIO1>; 1245 gpio-controller; 1246 #gpio-cells = <2>; 1247 1248 interrupt-controller; 1249 #interrupt-cells = <2>; 1250 }; 1251 1252 gpio2: gpio2@ff260000 { 1253 compatible = "rockchip,gpio-bank"; 1254 reg = <0x0 0xff260000 0x0 0x100>; 1255 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1256 clocks = <&cru PCLK_GPIO2>; 1257 gpio-controller; 1258 #gpio-cells = <2>; 1259 1260 interrupt-controller; 1261 #interrupt-cells = <2>; 1262 }; 1263 1264 gpio3: gpio3@ff270000 { 1265 compatible = "rockchip,gpio-bank"; 1266 reg = <0x0 0xff270000 0x0 0x100>; 1267 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&cru PCLK_GPIO3>; 1269 gpio-controller; 1270 #gpio-cells = <2>; 1271 1272 interrupt-controller; 1273 #interrupt-cells = <2>; 1274 }; 1275 1276 pcfg_pull_up: pcfg-pull-up { 1277 bias-pull-up; 1278 }; 1279 1280 pcfg_pull_down: pcfg-pull-down { 1281 bias-pull-down; 1282 }; 1283 1284 pcfg_pull_none: pcfg-pull-none { 1285 bias-disable; 1286 }; 1287 1288 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1289 bias-disable; 1290 drive-strength = <2>; 1291 }; 1292 1293 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1294 bias-pull-up; 1295 drive-strength = <2>; 1296 }; 1297 1298 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1299 bias-pull-up; 1300 drive-strength = <4>; 1301 }; 1302 1303 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1304 bias-disable; 1305 drive-strength = <4>; 1306 }; 1307 1308 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1309 bias-pull-down; 1310 drive-strength = <4>; 1311 }; 1312 1313 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1314 bias-disable; 1315 drive-strength = <8>; 1316 }; 1317 1318 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1319 bias-pull-up; 1320 drive-strength = <8>; 1321 }; 1322 1323 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1324 bias-disable; 1325 drive-strength = <12>; 1326 }; 1327 1328 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1329 bias-pull-up; 1330 drive-strength = <12>; 1331 }; 1332 1333 pcfg_pull_none_smt: pcfg-pull-none-smt { 1334 bias-disable; 1335 input-schmitt-enable; 1336 }; 1337 1338 pcfg_output_high: pcfg-output-high { 1339 output-high; 1340 }; 1341 1342 pcfg_output_low: pcfg-output-low { 1343 output-low; 1344 }; 1345 1346 pcfg_input_high: pcfg-input-high { 1347 bias-pull-up; 1348 input-enable; 1349 }; 1350 1351 pcfg_input: pcfg-input { 1352 input-enable; 1353 }; 1354 1355 i2c0 { 1356 i2c0_xfer: i2c0-xfer { 1357 rockchip,pins = 1358 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1359 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1360 }; 1361 }; 1362 1363 i2c1 { 1364 i2c1_xfer: i2c1-xfer { 1365 rockchip,pins = 1366 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1367 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1368 }; 1369 }; 1370 1371 i2c2 { 1372 i2c2_xfer: i2c2-xfer { 1373 rockchip,pins = 1374 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1375 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1376 }; 1377 }; 1378 1379 i2c3 { 1380 i2c3_xfer: i2c3-xfer { 1381 rockchip,pins = 1382 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1383 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1384 }; 1385 }; 1386 1387 tsadc { 1388 tsadc_otp_pin: tsadc-otp-pin { 1389 rockchip,pins = 1390 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1391 }; 1392 1393 tsadc_otp_out: tsadc-otp-out { 1394 rockchip,pins = 1395 <0 RK_PA6 1 &pcfg_pull_none>; 1396 }; 1397 }; 1398 1399 uart0 { 1400 uart0_xfer: uart0-xfer { 1401 rockchip,pins = 1402 <0 RK_PB2 1 &pcfg_pull_up>, 1403 <0 RK_PB3 1 &pcfg_pull_up>; 1404 }; 1405 1406 uart0_cts: uart0-cts { 1407 rockchip,pins = 1408 <0 RK_PB4 1 &pcfg_pull_none>; 1409 }; 1410 1411 uart0_rts: uart0-rts { 1412 rockchip,pins = 1413 <0 RK_PB5 1 &pcfg_pull_none>; 1414 }; 1415 }; 1416 1417 uart1 { 1418 uart1_xfer: uart1-xfer { 1419 rockchip,pins = 1420 <1 RK_PC1 1 &pcfg_pull_up>, 1421 <1 RK_PC0 1 &pcfg_pull_up>; 1422 }; 1423 1424 uart1_cts: uart1-cts { 1425 rockchip,pins = 1426 <1 RK_PC2 1 &pcfg_pull_none>; 1427 }; 1428 1429 uart1_rts: uart1-rts { 1430 rockchip,pins = 1431 <1 RK_PC3 1 &pcfg_pull_none>; 1432 }; 1433 }; 1434 1435 uart2-m0 { 1436 uart2m0_xfer: uart2m0-xfer { 1437 rockchip,pins = 1438 <1 RK_PD2 2 &pcfg_pull_up>, 1439 <1 RK_PD3 2 &pcfg_pull_up>; 1440 }; 1441 }; 1442 1443 uart2-m1 { 1444 uart2m1_xfer: uart2m1-xfer { 1445 rockchip,pins = 1446 <2 RK_PB4 2 &pcfg_pull_up>, 1447 <2 RK_PB6 2 &pcfg_pull_up>; 1448 }; 1449 }; 1450 1451 uart3-m0 { 1452 uart3m0_xfer: uart3m0-xfer { 1453 rockchip,pins = 1454 <0 RK_PC0 2 &pcfg_pull_up>, 1455 <0 RK_PC1 2 &pcfg_pull_up>; 1456 }; 1457 1458 uart3m0_cts: uart3m0-cts { 1459 rockchip,pins = 1460 <0 RK_PC2 2 &pcfg_pull_none>; 1461 }; 1462 1463 uart3m0_rts: uart3m0-rts { 1464 rockchip,pins = 1465 <0 RK_PC3 2 &pcfg_pull_none>; 1466 }; 1467 }; 1468 1469 uart3-m1 { 1470 uart3m1_xfer: uart3m1-xfer { 1471 rockchip,pins = 1472 <1 RK_PB6 2 &pcfg_pull_up>, 1473 <1 RK_PB7 2 &pcfg_pull_up>; 1474 }; 1475 1476 uart3m1_cts: uart3m1-cts { 1477 rockchip,pins = 1478 <1 RK_PB4 2 &pcfg_pull_none>; 1479 }; 1480 1481 uart3m1_rts: uart3m1-rts { 1482 rockchip,pins = 1483 <1 RK_PB5 2 &pcfg_pull_none>; 1484 }; 1485 }; 1486 1487 uart4 { 1488 uart4_xfer: uart4-xfer { 1489 rockchip,pins = 1490 <1 RK_PD4 2 &pcfg_pull_up>, 1491 <1 RK_PD5 2 &pcfg_pull_up>; 1492 }; 1493 1494 uart4_cts: uart4-cts { 1495 rockchip,pins = 1496 <1 RK_PD6 2 &pcfg_pull_none>; 1497 }; 1498 1499 uart4_rts: uart4-rts { 1500 rockchip,pins = 1501 <1 RK_PD7 2 &pcfg_pull_none>; 1502 }; 1503 }; 1504 1505 uart5 { 1506 uart5_xfer: uart5-xfer { 1507 rockchip,pins = 1508 <3 RK_PA2 4 &pcfg_pull_up>, 1509 <3 RK_PA1 4 &pcfg_pull_up>; 1510 }; 1511 1512 uart5_cts: uart5-cts { 1513 rockchip,pins = 1514 <3 RK_PA3 4 &pcfg_pull_none>; 1515 }; 1516 1517 uart5_rts: uart5-rts { 1518 rockchip,pins = 1519 <3 RK_PA5 4 &pcfg_pull_none>; 1520 }; 1521 }; 1522 1523 spi0 { 1524 spi0_clk: spi0-clk { 1525 rockchip,pins = 1526 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1527 }; 1528 1529 spi0_csn: spi0-csn { 1530 rockchip,pins = 1531 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1532 }; 1533 1534 spi0_miso: spi0-miso { 1535 rockchip,pins = 1536 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1537 }; 1538 1539 spi0_mosi: spi0-mosi { 1540 rockchip,pins = 1541 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1542 }; 1543 1544 spi0_clk_hs: spi0-clk-hs { 1545 rockchip,pins = 1546 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1547 }; 1548 1549 spi0_miso_hs: spi0-miso-hs { 1550 rockchip,pins = 1551 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1552 }; 1553 1554 spi0_mosi_hs: spi0-mosi-hs { 1555 rockchip,pins = 1556 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1557 }; 1558 }; 1559 1560 spi1 { 1561 spi1_clk: spi1-clk { 1562 rockchip,pins = 1563 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1564 }; 1565 1566 spi1_csn0: spi1-csn0 { 1567 rockchip,pins = 1568 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1569 }; 1570 1571 spi1_csn1: spi1-csn1 { 1572 rockchip,pins = 1573 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1574 }; 1575 1576 spi1_miso: spi1-miso { 1577 rockchip,pins = 1578 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1579 }; 1580 1581 spi1_mosi: spi1-mosi { 1582 rockchip,pins = 1583 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1584 }; 1585 1586 spi1_clk_hs: spi1-clk-hs { 1587 rockchip,pins = 1588 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1589 }; 1590 1591 spi1_miso_hs: spi1-miso-hs { 1592 rockchip,pins = 1593 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1594 }; 1595 1596 spi1_mosi_hs: spi1-mosi-hs { 1597 rockchip,pins = 1598 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1599 }; 1600 }; 1601 1602 pdm { 1603 pdm_clk0m0: pdm-clk0m0 { 1604 rockchip,pins = 1605 <3 RK_PC6 2 &pcfg_pull_none>; 1606 }; 1607 1608 pdm_clk0m1: pdm-clk0m1 { 1609 rockchip,pins = 1610 <2 RK_PC6 1 &pcfg_pull_none>; 1611 }; 1612 1613 pdm_clk1: pdm-clk1 { 1614 rockchip,pins = 1615 <3 RK_PC7 2 &pcfg_pull_none>; 1616 }; 1617 1618 pdm_sdi0m0: pdm-sdi0m0 { 1619 rockchip,pins = 1620 <3 RK_PD3 2 &pcfg_pull_none>; 1621 }; 1622 1623 pdm_sdi0m1: pdm-sdi0m1 { 1624 rockchip,pins = 1625 <2 RK_PC5 2 &pcfg_pull_none>; 1626 }; 1627 1628 pdm_sdi1: pdm-sdi1 { 1629 rockchip,pins = 1630 <3 RK_PD0 2 &pcfg_pull_none>; 1631 }; 1632 1633 pdm_sdi2: pdm-sdi2 { 1634 rockchip,pins = 1635 <3 RK_PD1 2 &pcfg_pull_none>; 1636 }; 1637 1638 pdm_sdi3: pdm-sdi3 { 1639 rockchip,pins = 1640 <3 RK_PD2 2 &pcfg_pull_none>; 1641 }; 1642 1643 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1644 rockchip,pins = 1645 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1646 }; 1647 1648 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1649 rockchip,pins = 1650 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1651 }; 1652 1653 pdm_clk1_sleep: pdm-clk1-sleep { 1654 rockchip,pins = 1655 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1656 }; 1657 1658 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1659 rockchip,pins = 1660 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1661 }; 1662 1663 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1664 rockchip,pins = 1665 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1666 }; 1667 1668 pdm_sdi1_sleep: pdm-sdi1-sleep { 1669 rockchip,pins = 1670 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1671 }; 1672 1673 pdm_sdi2_sleep: pdm-sdi2-sleep { 1674 rockchip,pins = 1675 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1676 }; 1677 1678 pdm_sdi3_sleep: pdm-sdi3-sleep { 1679 rockchip,pins = 1680 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1681 }; 1682 }; 1683 1684 i2s0 { 1685 i2s0_8ch_mclk: i2s0-8ch-mclk { 1686 rockchip,pins = 1687 <3 RK_PC1 2 &pcfg_pull_none>; 1688 }; 1689 1690 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1691 rockchip,pins = 1692 <3 RK_PC3 2 &pcfg_pull_none>; 1693 }; 1694 1695 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1696 rockchip,pins = 1697 <3 RK_PB4 2 &pcfg_pull_none>; 1698 }; 1699 1700 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1701 rockchip,pins = 1702 <3 RK_PC2 2 &pcfg_pull_none>; 1703 }; 1704 1705 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1706 rockchip,pins = 1707 <3 RK_PB5 2 &pcfg_pull_none>; 1708 }; 1709 1710 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1711 rockchip,pins = 1712 <3 RK_PC4 2 &pcfg_pull_none>; 1713 }; 1714 1715 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1716 rockchip,pins = 1717 <3 RK_PC0 2 &pcfg_pull_none>; 1718 }; 1719 1720 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1721 rockchip,pins = 1722 <3 RK_PB7 2 &pcfg_pull_none>; 1723 }; 1724 1725 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1726 rockchip,pins = 1727 <3 RK_PB6 2 &pcfg_pull_none>; 1728 }; 1729 1730 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1731 rockchip,pins = 1732 <3 RK_PC5 2 &pcfg_pull_none>; 1733 }; 1734 1735 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1736 rockchip,pins = 1737 <3 RK_PB3 2 &pcfg_pull_none>; 1738 }; 1739 1740 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1741 rockchip,pins = 1742 <3 RK_PB1 2 &pcfg_pull_none>; 1743 }; 1744 1745 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1746 rockchip,pins = 1747 <3 RK_PB0 2 &pcfg_pull_none>; 1748 }; 1749 }; 1750 1751 i2s1 { 1752 i2s1_2ch_mclk: i2s1-2ch-mclk { 1753 rockchip,pins = 1754 <2 RK_PC3 1 &pcfg_pull_none>; 1755 }; 1756 1757 i2s1_2ch_sclk: i2s1-2ch-sclk { 1758 rockchip,pins = 1759 <2 RK_PC2 1 &pcfg_pull_none>; 1760 }; 1761 1762 i2s1_2ch_lrck: i2s1-2ch-lrck { 1763 rockchip,pins = 1764 <2 RK_PC1 1 &pcfg_pull_none>; 1765 }; 1766 1767 i2s1_2ch_sdi: i2s1-2ch-sdi { 1768 rockchip,pins = 1769 <2 RK_PC5 1 &pcfg_pull_none>; 1770 }; 1771 1772 i2s1_2ch_sdo: i2s1-2ch-sdo { 1773 rockchip,pins = 1774 <2 RK_PC4 1 &pcfg_pull_none>; 1775 }; 1776 }; 1777 1778 i2s2 { 1779 i2s2_2ch_mclk: i2s2-2ch-mclk { 1780 rockchip,pins = 1781 <3 RK_PA1 2 &pcfg_pull_none>; 1782 }; 1783 1784 i2s2_2ch_sclk: i2s2-2ch-sclk { 1785 rockchip,pins = 1786 <3 RK_PA2 2 &pcfg_pull_none>; 1787 }; 1788 1789 i2s2_2ch_lrck: i2s2-2ch-lrck { 1790 rockchip,pins = 1791 <3 RK_PA3 2 &pcfg_pull_none>; 1792 }; 1793 1794 i2s2_2ch_sdi: i2s2-2ch-sdi { 1795 rockchip,pins = 1796 <3 RK_PA5 2 &pcfg_pull_none>; 1797 }; 1798 1799 i2s2_2ch_sdo: i2s2-2ch-sdo { 1800 rockchip,pins = 1801 <3 RK_PA7 2 &pcfg_pull_none>; 1802 }; 1803 }; 1804 1805 sdmmc { 1806 sdmmc_clk: sdmmc-clk { 1807 rockchip,pins = 1808 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1809 }; 1810 1811 sdmmc_cmd: sdmmc-cmd { 1812 rockchip,pins = 1813 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1814 }; 1815 1816 sdmmc_det: sdmmc-det { 1817 rockchip,pins = 1818 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1819 }; 1820 1821 sdmmc_bus1: sdmmc-bus1 { 1822 rockchip,pins = 1823 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1824 }; 1825 1826 sdmmc_bus4: sdmmc-bus4 { 1827 rockchip,pins = 1828 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1829 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1830 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1831 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1832 }; 1833 }; 1834 1835 sdio { 1836 sdio_clk: sdio-clk { 1837 rockchip,pins = 1838 <1 RK_PC5 1 &pcfg_pull_none>; 1839 }; 1840 1841 sdio_cmd: sdio-cmd { 1842 rockchip,pins = 1843 <1 RK_PC4 1 &pcfg_pull_up>; 1844 }; 1845 1846 sdio_bus4: sdio-bus4 { 1847 rockchip,pins = 1848 <1 RK_PC6 1 &pcfg_pull_up>, 1849 <1 RK_PC7 1 &pcfg_pull_up>, 1850 <1 RK_PD0 1 &pcfg_pull_up>, 1851 <1 RK_PD1 1 &pcfg_pull_up>; 1852 }; 1853 }; 1854 1855 emmc { 1856 emmc_clk: emmc-clk { 1857 rockchip,pins = 1858 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 1859 }; 1860 1861 emmc_cmd: emmc-cmd { 1862 rockchip,pins = 1863 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 1864 }; 1865 1866 emmc_rstnout: emmc-rstnout { 1867 rockchip,pins = 1868 <1 RK_PB3 2 &pcfg_pull_none>; 1869 }; 1870 1871 emmc_bus1: emmc-bus1 { 1872 rockchip,pins = 1873 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 1874 }; 1875 1876 emmc_bus4: emmc-bus4 { 1877 rockchip,pins = 1878 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1879 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1880 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1881 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 1882 }; 1883 1884 emmc_bus8: emmc-bus8 { 1885 rockchip,pins = 1886 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1887 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1888 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1889 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 1890 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 1891 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 1892 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 1893 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 1894 }; 1895 }; 1896 1897 flash { 1898 flash_cs0: flash-cs0 { 1899 rockchip,pins = 1900 <1 RK_PB0 1 &pcfg_pull_none>; 1901 }; 1902 1903 flash_rdy: flash-rdy { 1904 rockchip,pins = 1905 <1 RK_PB1 1 &pcfg_pull_none>; 1906 }; 1907 1908 flash_dqs: flash-dqs { 1909 rockchip,pins = 1910 <1 RK_PB2 1 &pcfg_pull_none>; 1911 }; 1912 1913 flash_ale: flash-ale { 1914 rockchip,pins = 1915 <1 RK_PB3 1 &pcfg_pull_none>; 1916 }; 1917 1918 flash_cle: flash-cle { 1919 rockchip,pins = 1920 <1 RK_PB4 1 &pcfg_pull_none>; 1921 }; 1922 1923 flash_wrn: flash-wrn { 1924 rockchip,pins = 1925 <1 RK_PB5 1 &pcfg_pull_none>; 1926 }; 1927 1928 flash_csl: flash-csl { 1929 rockchip,pins = 1930 <1 RK_PB6 1 &pcfg_pull_none>; 1931 }; 1932 1933 flash_rdn: flash-rdn { 1934 rockchip,pins = 1935 <1 RK_PB7 1 &pcfg_pull_none>; 1936 }; 1937 1938 flash_bus8: flash-bus8 { 1939 rockchip,pins = 1940 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 1941 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 1942 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 1943 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 1944 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 1945 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 1946 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 1947 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 1948 }; 1949 }; 1950 1951 lcdc { 1952 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1953 rockchip,pins = 1954 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 1955 }; 1956 1957 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1958 rockchip,pins = 1959 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 1960 }; 1961 1962 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1963 rockchip,pins = 1964 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 1965 }; 1966 1967 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1968 rockchip,pins = 1969 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 1970 }; 1971 1972 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1973 rockchip,pins = 1974 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1975 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1976 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1977 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1978 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1979 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1980 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 1981 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 1982 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 1983 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 1984 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 1985 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 1986 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 1987 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 1988 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 1989 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 1990 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 1991 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 1992 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 1993 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 1994 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 1995 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 1996 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 1997 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 1998 }; 1999 2000 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 2001 rockchip,pins = 2002 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2003 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2004 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2005 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2006 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2007 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2008 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2009 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2010 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2011 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2012 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2013 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2014 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2015 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2016 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2017 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2018 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2019 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2020 }; 2021 2022 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2023 rockchip,pins = 2024 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2025 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2026 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2027 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2028 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2029 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2030 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2031 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2032 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2033 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2034 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2035 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2036 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2037 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2038 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2039 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2040 }; 2041 2042 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2043 rockchip,pins = 2044 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2045 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2046 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2047 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2048 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2049 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2050 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2051 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2052 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2053 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2054 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2055 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2056 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2057 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2058 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2059 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2060 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2061 }; 2062 2063 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2064 rockchip,pins = 2065 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2066 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2067 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2068 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2069 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2070 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2071 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2072 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2073 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2074 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2075 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2076 }; 2077 2078 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2079 rockchip,pins = 2080 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2081 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2082 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2083 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2084 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2085 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2086 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2087 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2088 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2089 }; 2090 }; 2091 2092 pwm0 { 2093 pwm0_pin: pwm0-pin { 2094 rockchip,pins = 2095 <0 RK_PB7 1 &pcfg_pull_none>; 2096 }; 2097 }; 2098 2099 pwm1 { 2100 pwm1_pin: pwm1-pin { 2101 rockchip,pins = 2102 <0 RK_PC0 1 &pcfg_pull_none>; 2103 }; 2104 }; 2105 2106 pwm2 { 2107 pwm2_pin: pwm2-pin { 2108 rockchip,pins = 2109 <2 RK_PB5 1 &pcfg_pull_none>; 2110 }; 2111 }; 2112 2113 pwm3 { 2114 pwm3_pin: pwm3-pin { 2115 rockchip,pins = 2116 <0 RK_PC1 1 &pcfg_pull_none>; 2117 }; 2118 }; 2119 2120 pwm4 { 2121 pwm4_pin: pwm4-pin { 2122 rockchip,pins = 2123 <3 RK_PC2 3 &pcfg_pull_none>; 2124 }; 2125 }; 2126 2127 pwm5 { 2128 pwm5_pin: pwm5-pin { 2129 rockchip,pins = 2130 <3 RK_PC3 3 &pcfg_pull_none>; 2131 }; 2132 }; 2133 2134 pwm6 { 2135 pwm6_pin: pwm6-pin { 2136 rockchip,pins = 2137 <3 RK_PC4 3 &pcfg_pull_none>; 2138 }; 2139 }; 2140 2141 pwm7 { 2142 pwm7_pin: pwm7-pin { 2143 rockchip,pins = 2144 <3 RK_PC5 3 &pcfg_pull_none>; 2145 }; 2146 }; 2147 2148 gmac { 2149 rmii_pins: rmii-pins { 2150 rockchip,pins = 2151 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 2152 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 2153 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 2154 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 2155 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 2156 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 2157 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 2158 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 2159 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 2160 }; 2161 2162 mac_refclk_12ma: mac-refclk-12ma { 2163 rockchip,pins = 2164 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 2165 }; 2166 2167 mac_refclk: mac-refclk { 2168 rockchip,pins = 2169 <2 RK_PB2 2 &pcfg_pull_none>; 2170 }; 2171 }; 2172 2173 cif-m0 { 2174 cif_clkout_m0: cif-clkout-m0 { 2175 rockchip,pins = 2176 <2 RK_PB3 1 &pcfg_pull_none>; 2177 }; 2178 2179 dvp_d2d9_m0: dvp-d2d9-m0 { 2180 rockchip,pins = 2181 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 2182 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 2183 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 2184 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 2185 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 2186 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 2187 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 2188 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 2189 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 2190 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 2191 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 2192 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 2193 }; 2194 2195 dvp_d0d1_m0: dvp-d0d1-m0 { 2196 rockchip,pins = 2197 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 2198 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 2199 }; 2200 2201 dvp_d10d11_m0:d10-d11-m0 { 2202 rockchip,pins = 2203 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 2204 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 2205 }; 2206 }; 2207 2208 cif-m1 { 2209 cif_clkout_m1: cif-clkout-m1 { 2210 rockchip,pins = 2211 <3 RK_PD0 3 &pcfg_pull_none>; 2212 }; 2213 2214 dvp_d2d9_m1: dvp-d2d9-m1 { 2215 rockchip,pins = 2216 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 2217 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 2218 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 2219 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 2220 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 2221 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 2222 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 2223 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 2224 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 2225 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 2226 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 2227 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 2228 }; 2229 2230 dvp_d0d1_m1: dvp-d0d1-m1 { 2231 rockchip,pins = 2232 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 2233 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 2234 }; 2235 2236 dvp_d10d11_m1:d10-d11-m1 { 2237 rockchip,pins = 2238 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 2239 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 2240 }; 2241 }; 2242 2243 isp { 2244 isp_prelight: isp-prelight { 2245 rockchip,pins = 2246 <3 RK_PD1 4 &pcfg_pull_none>; 2247 }; 2248 }; 2249 }; 2250}; 2251