1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/px30-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/power/px30-power.h>
12#include <dt-bindings/soc/rockchip,boot-mode.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	compatible = "rockchip,px30";
17
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		ethernet0 = &gmac;
24		i2c0 = &i2c0;
25		i2c1 = &i2c1;
26		i2c2 = &i2c2;
27		i2c3 = &i2c3;
28		serial0 = &uart0;
29		serial1 = &uart1;
30		serial2 = &uart2;
31		serial3 = &uart3;
32		serial4 = &uart4;
33		serial5 = &uart5;
34		spi0 = &spi0;
35		spi1 = &spi1;
36	};
37
38	cpus {
39		#address-cells = <2>;
40		#size-cells = <0>;
41
42		cpu0: cpu@0 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a35";
45			reg = <0x0 0x0>;
46			enable-method = "psci";
47			clocks = <&cru ARMCLK>;
48			#cooling-cells = <2>;
49			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
50			dynamic-power-coefficient = <90>;
51			operating-points-v2 = <&cpu0_opp_table>;
52		};
53
54		cpu1: cpu@1 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a35";
57			reg = <0x0 0x1>;
58			enable-method = "psci";
59			clocks = <&cru ARMCLK>;
60			#cooling-cells = <2>;
61			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
62			dynamic-power-coefficient = <90>;
63			operating-points-v2 = <&cpu0_opp_table>;
64		};
65
66		cpu2: cpu@2 {
67			device_type = "cpu";
68			compatible = "arm,cortex-a35";
69			reg = <0x0 0x2>;
70			enable-method = "psci";
71			clocks = <&cru ARMCLK>;
72			#cooling-cells = <2>;
73			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
74			dynamic-power-coefficient = <90>;
75			operating-points-v2 = <&cpu0_opp_table>;
76		};
77
78		cpu3: cpu@3 {
79			device_type = "cpu";
80			compatible = "arm,cortex-a35";
81			reg = <0x0 0x3>;
82			enable-method = "psci";
83			clocks = <&cru ARMCLK>;
84			#cooling-cells = <2>;
85			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86			dynamic-power-coefficient = <90>;
87			operating-points-v2 = <&cpu0_opp_table>;
88		};
89
90		idle-states {
91			entry-method = "psci";
92
93			CPU_SLEEP: cpu-sleep {
94				compatible = "arm,idle-state";
95				local-timer-stop;
96				arm,psci-suspend-param = <0x0010000>;
97				entry-latency-us = <120>;
98				exit-latency-us = <250>;
99				min-residency-us = <900>;
100			};
101
102			CLUSTER_SLEEP: cluster-sleep {
103				compatible = "arm,idle-state";
104				local-timer-stop;
105				arm,psci-suspend-param = <0x1010000>;
106				entry-latency-us = <400>;
107				exit-latency-us = <500>;
108				min-residency-us = <2000>;
109			};
110		};
111	};
112
113	cpu0_opp_table: cpu0-opp-table {
114		compatible = "operating-points-v2";
115		opp-shared;
116
117		opp-600000000 {
118			opp-hz = /bits/ 64 <600000000>;
119			opp-microvolt = <950000 950000 1350000>;
120			clock-latency-ns = <40000>;
121			opp-suspend;
122		};
123		opp-816000000 {
124			opp-hz = /bits/ 64 <816000000>;
125			opp-microvolt = <1050000 1050000 1350000>;
126			clock-latency-ns = <40000>;
127		};
128		opp-1008000000 {
129			opp-hz = /bits/ 64 <1008000000>;
130			opp-microvolt = <1175000 1175000 1350000>;
131			clock-latency-ns = <40000>;
132		};
133		opp-1200000000 {
134			opp-hz = /bits/ 64 <1200000000>;
135			opp-microvolt = <1300000 1300000 1350000>;
136			clock-latency-ns = <40000>;
137		};
138		opp-1296000000 {
139			opp-hz = /bits/ 64 <1296000000>;
140			opp-microvolt = <1350000 1350000 1350000>;
141			clock-latency-ns = <40000>;
142		};
143	};
144
145	arm-pmu {
146		compatible = "arm,cortex-a35-pmu";
147		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
148			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
149			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
150			     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
151		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
152	};
153
154	display_subsystem: display-subsystem {
155		compatible = "rockchip,display-subsystem";
156		ports = <&vopb_out>, <&vopl_out>;
157		status = "disabled";
158	};
159
160	gmac_clkin: external-gmac-clock {
161		compatible = "fixed-clock";
162		clock-frequency = <50000000>;
163		clock-output-names = "gmac_clkin";
164		#clock-cells = <0>;
165	};
166
167	psci {
168		compatible = "arm,psci-1.0";
169		method = "smc";
170	};
171
172	timer {
173		compatible = "arm,armv8-timer";
174		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
177			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
178	};
179
180	thermal_zones: thermal-zones {
181		soc_thermal: soc-thermal {
182			polling-delay-passive = <20>;
183			polling-delay = <1000>;
184			sustainable-power = <750>;
185			thermal-sensors = <&tsadc 0>;
186
187			trips {
188				threshold: trip-point-0 {
189					temperature = <70000>;
190					hysteresis = <2000>;
191					type = "passive";
192				};
193
194				target: trip-point-1 {
195					temperature = <85000>;
196					hysteresis = <2000>;
197					type = "passive";
198				};
199
200				soc_crit: soc-crit {
201					temperature = <115000>;
202					hysteresis = <2000>;
203					type = "critical";
204				};
205			};
206
207			cooling-maps {
208				map0 {
209					trip = <&target>;
210					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211					contribution = <4096>;
212				};
213
214				map1 {
215					trip = <&target>;
216					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
217					contribution = <4096>;
218				};
219			};
220		};
221
222		gpu_thermal: gpu-thermal {
223			polling-delay-passive = <100>; /* milliseconds */
224			polling-delay = <1000>; /* milliseconds */
225			thermal-sensors = <&tsadc 1>;
226		};
227	};
228
229	xin24m: xin24m {
230		compatible = "fixed-clock";
231		#clock-cells = <0>;
232		clock-frequency = <24000000>;
233		clock-output-names = "xin24m";
234	};
235
236	pmu: power-management@ff000000 {
237		compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
238		reg = <0x0 0xff000000 0x0 0x1000>;
239
240		power: power-controller {
241			compatible = "rockchip,px30-power-controller";
242			#power-domain-cells = <1>;
243			#address-cells = <1>;
244			#size-cells = <0>;
245
246			/* These power domains are grouped by VD_LOGIC */
247			pd_usb@PX30_PD_USB {
248				reg = <PX30_PD_USB>;
249				clocks = <&cru HCLK_HOST>,
250					 <&cru HCLK_OTG>,
251					 <&cru SCLK_OTG_ADP>;
252				pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
253			};
254			pd_sdcard@PX30_PD_SDCARD {
255				reg = <PX30_PD_SDCARD>;
256				clocks = <&cru HCLK_SDMMC>,
257					 <&cru SCLK_SDMMC>;
258				pm_qos = <&qos_sdmmc>;
259			};
260			pd_gmac@PX30_PD_GMAC {
261				reg = <PX30_PD_GMAC>;
262				clocks = <&cru ACLK_GMAC>,
263					 <&cru PCLK_GMAC>,
264					 <&cru SCLK_MAC_REF>,
265					 <&cru SCLK_GMAC_RX_TX>;
266				pm_qos = <&qos_gmac>;
267			};
268			pd_mmc_nand@PX30_PD_MMC_NAND {
269				reg = <PX30_PD_MMC_NAND>;
270				clocks =  <&cru HCLK_NANDC>,
271					  <&cru HCLK_EMMC>,
272					  <&cru HCLK_SDIO>,
273					  <&cru HCLK_SFC>,
274					  <&cru SCLK_EMMC>,
275					  <&cru SCLK_NANDC>,
276					  <&cru SCLK_SDIO>,
277					  <&cru SCLK_SFC>;
278				pm_qos = <&qos_emmc>, <&qos_nand>,
279					 <&qos_sdio>, <&qos_sfc>;
280			};
281			pd_vpu@PX30_PD_VPU {
282				reg = <PX30_PD_VPU>;
283				clocks = <&cru ACLK_VPU>,
284					 <&cru HCLK_VPU>,
285					 <&cru SCLK_CORE_VPU>;
286				pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
287			};
288			pd_vo@PX30_PD_VO {
289				reg = <PX30_PD_VO>;
290				clocks = <&cru ACLK_RGA>,
291					 <&cru ACLK_VOPB>,
292					 <&cru ACLK_VOPL>,
293					 <&cru DCLK_VOPB>,
294					 <&cru DCLK_VOPL>,
295					 <&cru HCLK_RGA>,
296					 <&cru HCLK_VOPB>,
297					 <&cru HCLK_VOPL>,
298					 <&cru PCLK_MIPI_DSI>,
299					 <&cru SCLK_RGA_CORE>,
300					 <&cru SCLK_VOPB_PWM>;
301				pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
302					 <&qos_vop_m0>, <&qos_vop_m1>;
303			};
304			pd_vi@PX30_PD_VI {
305				reg = <PX30_PD_VI>;
306				clocks = <&cru ACLK_CIF>,
307					 <&cru ACLK_ISP>,
308					 <&cru HCLK_CIF>,
309					 <&cru HCLK_ISP>,
310					 <&cru SCLK_ISP>;
311				pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
312					 <&qos_isp_wr>, <&qos_isp_m1>,
313					 <&qos_vip>;
314			};
315			pd_gpu@PX30_PD_GPU {
316				reg = <PX30_PD_GPU>;
317				clocks = <&cru SCLK_GPU>;
318				pm_qos = <&qos_gpu>;
319			};
320		};
321	};
322
323	pmugrf: syscon@ff010000 {
324		compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
325		reg = <0x0 0xff010000 0x0 0x1000>;
326		#address-cells = <1>;
327		#size-cells = <1>;
328
329		pmu_io_domains: io-domains {
330			compatible = "rockchip,px30-pmu-io-voltage-domain";
331			status = "disabled";
332		};
333
334		reboot-mode {
335			compatible = "syscon-reboot-mode";
336			offset = <0x200>;
337			mode-bootloader = <BOOT_BL_DOWNLOAD>;
338			mode-fastboot = <BOOT_FASTBOOT>;
339			mode-loader = <BOOT_BL_DOWNLOAD>;
340			mode-normal = <BOOT_NORMAL>;
341			mode-recovery = <BOOT_RECOVERY>;
342		};
343	};
344
345	uart0: serial@ff030000 {
346		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
347		reg = <0x0 0xff030000 0x0 0x100>;
348		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
349		clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
350		clock-names = "baudclk", "apb_pclk";
351		dmas = <&dmac 0>, <&dmac 1>;
352		dma-names = "tx", "rx";
353		reg-shift = <2>;
354		reg-io-width = <4>;
355		pinctrl-names = "default";
356		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
357		status = "disabled";
358	};
359
360	i2s1_2ch: i2s@ff070000 {
361		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
362		reg = <0x0 0xff070000 0x0 0x1000>;
363		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
364		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
365		clock-names = "i2s_clk", "i2s_hclk";
366		dmas = <&dmac 18>, <&dmac 19>;
367		dma-names = "tx", "rx";
368		pinctrl-names = "default";
369		pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
370			     &i2s1_2ch_sdi &i2s1_2ch_sdo>;
371		#sound-dai-cells = <0>;
372		status = "disabled";
373	};
374
375	i2s2_2ch: i2s@ff080000 {
376		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
377		reg = <0x0 0xff080000 0x0 0x1000>;
378		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
379		clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
380		clock-names = "i2s_clk", "i2s_hclk";
381		dmas = <&dmac 20>, <&dmac 21>;
382		dma-names = "tx", "rx";
383		pinctrl-names = "default";
384		pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
385			     &i2s2_2ch_sdi &i2s2_2ch_sdo>;
386		#sound-dai-cells = <0>;
387		status = "disabled";
388	};
389
390	gic: interrupt-controller@ff131000 {
391		compatible = "arm,gic-400";
392		#interrupt-cells = <3>;
393		#address-cells = <0>;
394		interrupt-controller;
395		reg = <0x0 0xff131000 0 0x1000>,
396		      <0x0 0xff132000 0 0x2000>,
397		      <0x0 0xff134000 0 0x2000>,
398		      <0x0 0xff136000 0 0x2000>;
399		interrupts = <GIC_PPI 9
400		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
401	};
402
403	grf: syscon@ff140000 {
404		compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
405		reg = <0x0 0xff140000 0x0 0x1000>;
406		#address-cells = <1>;
407		#size-cells = <1>;
408
409		io_domains: io-domains {
410			compatible = "rockchip,px30-io-voltage-domain";
411			status = "disabled";
412		};
413
414		lvds: lvds {
415			compatible = "rockchip,px30-lvds";
416			phys = <&dsi_dphy>;
417			phy-names = "dphy";
418			rockchip,grf = <&grf>;
419			rockchip,output = "lvds";
420			status = "disabled";
421
422			ports {
423				#address-cells = <1>;
424				#size-cells = <0>;
425
426				port@0 {
427					reg = <0>;
428					#address-cells = <1>;
429					#size-cells = <0>;
430
431					lvds_vopb_in: endpoint@0 {
432						reg = <0>;
433						remote-endpoint = <&vopb_out_lvds>;
434					};
435
436					lvds_vopl_in: endpoint@1 {
437						reg = <1>;
438						remote-endpoint = <&vopl_out_lvds>;
439					};
440				};
441			};
442		};
443	};
444
445	uart1: serial@ff158000 {
446		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
447		reg = <0x0 0xff158000 0x0 0x100>;
448		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
449		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
450		clock-names = "baudclk", "apb_pclk";
451		dmas = <&dmac 2>, <&dmac 3>;
452		dma-names = "tx", "rx";
453		reg-shift = <2>;
454		reg-io-width = <4>;
455		pinctrl-names = "default";
456		pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
457		status = "disabled";
458	};
459
460	uart2: serial@ff160000 {
461		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
462		reg = <0x0 0xff160000 0x0 0x100>;
463		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
464		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
465		clock-names = "baudclk", "apb_pclk";
466		dmas = <&dmac 4>, <&dmac 5>;
467		dma-names = "tx", "rx";
468		reg-shift = <2>;
469		reg-io-width = <4>;
470		pinctrl-names = "default";
471		pinctrl-0 = <&uart2m0_xfer>;
472		status = "disabled";
473	};
474
475	uart3: serial@ff168000 {
476		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
477		reg = <0x0 0xff168000 0x0 0x100>;
478		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
479		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
480		clock-names = "baudclk", "apb_pclk";
481		dmas = <&dmac 6>, <&dmac 7>;
482		dma-names = "tx", "rx";
483		reg-shift = <2>;
484		reg-io-width = <4>;
485		pinctrl-names = "default";
486		pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
487		status = "disabled";
488	};
489
490	uart4: serial@ff170000 {
491		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
492		reg = <0x0 0xff170000 0x0 0x100>;
493		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
494		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
495		clock-names = "baudclk", "apb_pclk";
496		dmas = <&dmac 8>, <&dmac 9>;
497		dma-names = "tx", "rx";
498		reg-shift = <2>;
499		reg-io-width = <4>;
500		pinctrl-names = "default";
501		pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
502		status = "disabled";
503	};
504
505	uart5: serial@ff178000 {
506		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
507		reg = <0x0 0xff178000 0x0 0x100>;
508		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
509		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
510		clock-names = "baudclk", "apb_pclk";
511		dmas = <&dmac 10>, <&dmac 11>;
512		dma-names = "tx", "rx";
513		reg-shift = <2>;
514		reg-io-width = <4>;
515		pinctrl-names = "default";
516		pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
517		status = "disabled";
518	};
519
520	i2c0: i2c@ff180000 {
521		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
522		reg = <0x0 0xff180000 0x0 0x1000>;
523		clocks =  <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
524		clock-names = "i2c", "pclk";
525		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
526		pinctrl-names = "default";
527		pinctrl-0 = <&i2c0_xfer>;
528		#address-cells = <1>;
529		#size-cells = <0>;
530		status = "disabled";
531	};
532
533	i2c1: i2c@ff190000 {
534		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
535		reg = <0x0 0xff190000 0x0 0x1000>;
536		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
537		clock-names = "i2c", "pclk";
538		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
539		pinctrl-names = "default";
540		pinctrl-0 = <&i2c1_xfer>;
541		#address-cells = <1>;
542		#size-cells = <0>;
543		status = "disabled";
544	};
545
546	i2c2: i2c@ff1a0000 {
547		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
548		reg = <0x0 0xff1a0000 0x0 0x1000>;
549		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
550		clock-names = "i2c", "pclk";
551		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
552		pinctrl-names = "default";
553		pinctrl-0 = <&i2c2_xfer>;
554		#address-cells = <1>;
555		#size-cells = <0>;
556		status = "disabled";
557	};
558
559	i2c3: i2c@ff1b0000 {
560		compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
561		reg = <0x0 0xff1b0000 0x0 0x1000>;
562		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
563		clock-names = "i2c", "pclk";
564		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
565		pinctrl-names = "default";
566		pinctrl-0 = <&i2c3_xfer>;
567		#address-cells = <1>;
568		#size-cells = <0>;
569		status = "disabled";
570	};
571
572	spi0: spi@ff1d0000 {
573		compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
574		reg = <0x0 0xff1d0000 0x0 0x1000>;
575		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
576		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
577		clock-names = "spiclk", "apb_pclk";
578		dmas = <&dmac 12>, <&dmac 13>;
579		dma-names = "tx", "rx";
580		pinctrl-names = "default";
581		pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
582		#address-cells = <1>;
583		#size-cells = <0>;
584		status = "disabled";
585	};
586
587	spi1: spi@ff1d8000 {
588		compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
589		reg = <0x0 0xff1d8000 0x0 0x1000>;
590		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
591		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
592		clock-names = "spiclk", "apb_pclk";
593		dmas = <&dmac 14>, <&dmac 15>;
594		dma-names = "tx", "rx";
595		pinctrl-names = "default";
596		pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
597		#address-cells = <1>;
598		#size-cells = <0>;
599		status = "disabled";
600	};
601
602	wdt: watchdog@ff1e0000 {
603		compatible = "snps,dw-wdt";
604		reg = <0x0 0xff1e0000 0x0 0x100>;
605		clocks = <&cru PCLK_WDT_NS>;
606		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
607		status = "disabled";
608	};
609
610	pwm0: pwm@ff200000 {
611		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
612		reg = <0x0 0xff200000 0x0 0x10>;
613		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
614		clock-names = "pwm", "pclk";
615		pinctrl-names = "default";
616		pinctrl-0 = <&pwm0_pin>;
617		#pwm-cells = <3>;
618		status = "disabled";
619	};
620
621	pwm1: pwm@ff200010 {
622		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
623		reg = <0x0 0xff200010 0x0 0x10>;
624		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
625		clock-names = "pwm", "pclk";
626		pinctrl-names = "default";
627		pinctrl-0 = <&pwm1_pin>;
628		#pwm-cells = <3>;
629		status = "disabled";
630	};
631
632	pwm2: pwm@ff200020 {
633		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
634		reg = <0x0 0xff200020 0x0 0x10>;
635		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
636		clock-names = "pwm", "pclk";
637		pinctrl-names = "default";
638		pinctrl-0 = <&pwm2_pin>;
639		#pwm-cells = <3>;
640		status = "disabled";
641	};
642
643	pwm3: pwm@ff200030 {
644		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
645		reg = <0x0 0xff200030 0x0 0x10>;
646		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
647		clock-names = "pwm", "pclk";
648		pinctrl-names = "default";
649		pinctrl-0 = <&pwm3_pin>;
650		#pwm-cells = <3>;
651		status = "disabled";
652	};
653
654	pwm4: pwm@ff208000 {
655		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
656		reg = <0x0 0xff208000 0x0 0x10>;
657		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
658		clock-names = "pwm", "pclk";
659		pinctrl-names = "default";
660		pinctrl-0 = <&pwm4_pin>;
661		#pwm-cells = <3>;
662		status = "disabled";
663	};
664
665	pwm5: pwm@ff208010 {
666		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
667		reg = <0x0 0xff208010 0x0 0x10>;
668		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
669		clock-names = "pwm", "pclk";
670		pinctrl-names = "default";
671		pinctrl-0 = <&pwm5_pin>;
672		#pwm-cells = <3>;
673		status = "disabled";
674	};
675
676	pwm6: pwm@ff208020 {
677		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
678		reg = <0x0 0xff208020 0x0 0x10>;
679		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
680		clock-names = "pwm", "pclk";
681		pinctrl-names = "default";
682		pinctrl-0 = <&pwm6_pin>;
683		#pwm-cells = <3>;
684		status = "disabled";
685	};
686
687	pwm7: pwm@ff208030 {
688		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
689		reg = <0x0 0xff208030 0x0 0x10>;
690		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
691		clock-names = "pwm", "pclk";
692		pinctrl-names = "default";
693		pinctrl-0 = <&pwm7_pin>;
694		#pwm-cells = <3>;
695		status = "disabled";
696	};
697
698	rktimer: timer@ff210000 {
699		compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
700		reg = <0x0 0xff210000 0x0 0x1000>;
701		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
702		clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
703		clock-names = "pclk", "timer";
704	};
705
706	amba: bus {
707		compatible = "simple-bus";
708		#address-cells = <2>;
709		#size-cells = <2>;
710		ranges;
711
712		dmac: dmac@ff240000 {
713			compatible = "arm,pl330", "arm,primecell";
714			reg = <0x0 0xff240000 0x0 0x4000>;
715			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
716				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
717			clocks = <&cru ACLK_DMAC>;
718			clock-names = "apb_pclk";
719			#dma-cells = <1>;
720		};
721	};
722
723	tsadc: tsadc@ff280000 {
724		compatible = "rockchip,px30-tsadc";
725		reg = <0x0 0xff280000 0x0 0x100>;
726		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
727		assigned-clocks = <&cru SCLK_TSADC>;
728		assigned-clock-rates = <50000>;
729		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
730		clock-names = "tsadc", "apb_pclk";
731		resets = <&cru SRST_TSADC>;
732		reset-names = "tsadc-apb";
733		rockchip,grf = <&grf>;
734		rockchip,hw-tshut-temp = <120000>;
735		pinctrl-names = "init", "default", "sleep";
736		pinctrl-0 = <&tsadc_otp_gpio>;
737		pinctrl-1 = <&tsadc_otp_out>;
738		pinctrl-2 = <&tsadc_otp_gpio>;
739		#thermal-sensor-cells = <1>;
740		status = "disabled";
741	};
742
743	saradc: saradc@ff288000 {
744		compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
745		reg = <0x0 0xff288000 0x0 0x100>;
746		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
747		#io-channel-cells = <1>;
748		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
749		clock-names = "saradc", "apb_pclk";
750		resets = <&cru SRST_SARADC_P>;
751		reset-names = "saradc-apb";
752		status = "disabled";
753	};
754
755	otp: nvmem@ff290000 {
756		compatible = "rockchip,px30-otp";
757		reg = <0x0 0xff290000 0x0 0x4000>;
758		clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
759			 <&cru PCLK_OTP_PHY>;
760		clock-names = "otp", "apb_pclk", "phy";
761		resets = <&cru SRST_OTP_PHY>;
762		reset-names = "phy";
763		#address-cells = <1>;
764		#size-cells = <1>;
765
766		/* Data cells */
767		cpu_id: id@7 {
768			reg = <0x07 0x10>;
769		};
770		cpu_leakage: cpu-leakage@17 {
771			reg = <0x17 0x1>;
772		};
773		performance: performance@1e {
774			reg = <0x1e 0x1>;
775			bits = <4 3>;
776		};
777	};
778
779	cru: clock-controller@ff2b0000 {
780		compatible = "rockchip,px30-cru";
781		reg = <0x0 0xff2b0000 0x0 0x1000>;
782		clocks = <&xin24m>, <&pmucru PLL_GPLL>;
783		clock-names = "xin24m", "gpll";
784		rockchip,grf = <&grf>;
785		#clock-cells = <1>;
786		#reset-cells = <1>;
787
788		assigned-clocks = <&cru PLL_NPLL>,
789			<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
790			<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
791			<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
792
793		assigned-clock-rates = <1188000000>,
794			<200000000>, <200000000>,
795			<150000000>, <150000000>,
796			<100000000>, <200000000>;
797	};
798
799	pmucru: clock-controller@ff2bc000 {
800		compatible = "rockchip,px30-pmucru";
801		reg = <0x0 0xff2bc000 0x0 0x1000>;
802		clocks = <&xin24m>;
803		clock-names = "xin24m";
804		rockchip,grf = <&grf>;
805		#clock-cells = <1>;
806		#reset-cells = <1>;
807
808		assigned-clocks =
809			<&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
810			<&pmucru SCLK_WIFI_PMU>;
811		assigned-clock-rates =
812			<1200000000>, <100000000>,
813			<26000000>;
814	};
815
816	usb2phy_grf: syscon@ff2c0000 {
817		compatible = "rockchip,px30-usb2phy-grf", "syscon",
818			     "simple-mfd";
819		reg = <0x0 0xff2c0000 0x0 0x10000>;
820		#address-cells = <1>;
821		#size-cells = <1>;
822
823		u2phy: usb2-phy@100 {
824			compatible = "rockchip,px30-usb2phy";
825			reg = <0x100 0x20>;
826			clocks = <&pmucru SCLK_USBPHY_REF>;
827			clock-names = "phyclk";
828			#clock-cells = <0>;
829			assigned-clocks = <&cru USB480M>;
830			assigned-clock-parents = <&u2phy>;
831			clock-output-names = "usb480m_phy";
832			status = "disabled";
833
834			u2phy_host: host-port {
835				#phy-cells = <0>;
836				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
837				interrupt-names = "linestate";
838				status = "disabled";
839			};
840
841			u2phy_otg: otg-port {
842				#phy-cells = <0>;
843				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
844					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
845					     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
846				interrupt-names = "otg-bvalid", "otg-id",
847						  "linestate";
848				status = "disabled";
849			};
850		};
851	};
852
853	dsi_dphy: phy@ff2e0000 {
854		compatible = "rockchip,px30-dsi-dphy";
855		reg = <0x0 0xff2e0000 0x0 0x10000>;
856		clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
857		clock-names = "ref", "pclk";
858		resets = <&cru SRST_MIPIDSIPHY_P>;
859		reset-names = "apb";
860		#phy-cells = <0>;
861		power-domains = <&power PX30_PD_VO>;
862		status = "disabled";
863	};
864
865	usb20_otg: usb@ff300000 {
866		compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
867			     "snps,dwc2";
868		reg = <0x0 0xff300000 0x0 0x40000>;
869		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
870		clocks = <&cru HCLK_OTG>;
871		clock-names = "otg";
872		dr_mode = "otg";
873		g-np-tx-fifo-size = <16>;
874		g-rx-fifo-size = <280>;
875		g-tx-fifo-size = <256 128 128 64 32 16>;
876		phys = <&u2phy_otg>;
877		phy-names = "usb2-phy";
878		power-domains = <&power PX30_PD_USB>;
879		status = "disabled";
880	};
881
882	usb_host0_ehci: usb@ff340000 {
883		compatible = "generic-ehci";
884		reg = <0x0 0xff340000 0x0 0x10000>;
885		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
886		clocks = <&cru HCLK_HOST>;
887		phys = <&u2phy_host>;
888		phy-names = "usb";
889		power-domains = <&power PX30_PD_USB>;
890		status = "disabled";
891	};
892
893	usb_host0_ohci: usb@ff350000 {
894		compatible = "generic-ohci";
895		reg = <0x0 0xff350000 0x0 0x10000>;
896		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
897		clocks = <&cru HCLK_HOST>;
898		phys = <&u2phy_host>;
899		phy-names = "usb";
900		power-domains = <&power PX30_PD_USB>;
901		status = "disabled";
902	};
903
904	gmac: ethernet@ff360000 {
905		compatible = "rockchip,px30-gmac";
906		reg = <0x0 0xff360000 0x0 0x10000>;
907		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
908		interrupt-names = "macirq";
909		clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
910			 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
911			 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
912			 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
913		clock-names = "stmmaceth", "mac_clk_rx",
914			      "mac_clk_tx", "clk_mac_ref",
915			      "clk_mac_refout", "aclk_mac",
916			      "pclk_mac", "clk_mac_speed";
917		rockchip,grf = <&grf>;
918		phy-mode = "rmii";
919		pinctrl-names = "default";
920		pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
921		power-domains = <&power PX30_PD_GMAC>;
922		resets = <&cru SRST_GMAC_A>;
923		reset-names = "stmmaceth";
924		status = "disabled";
925	};
926
927	sdmmc: mmc@ff370000 {
928		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
929		reg = <0x0 0xff370000 0x0 0x4000>;
930		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
931		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
932			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
933		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
934		bus-width = <4>;
935		fifo-depth = <0x100>;
936		max-frequency = <150000000>;
937		pinctrl-names = "default";
938		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
939		power-domains = <&power PX30_PD_SDCARD>;
940		status = "disabled";
941	};
942
943	sdio: mmc@ff380000 {
944		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
945		reg = <0x0 0xff380000 0x0 0x4000>;
946		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
947		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
948			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
949		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
950		bus-width = <4>;
951		fifo-depth = <0x100>;
952		max-frequency = <150000000>;
953		pinctrl-names = "default";
954		pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
955		power-domains = <&power PX30_PD_MMC_NAND>;
956		status = "disabled";
957	};
958
959	emmc: mmc@ff390000 {
960		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
961		reg = <0x0 0xff390000 0x0 0x4000>;
962		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
963		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
964			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
965		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
966		bus-width = <8>;
967		fifo-depth = <0x100>;
968		max-frequency = <150000000>;
969		pinctrl-names = "default";
970		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
971		power-domains = <&power PX30_PD_MMC_NAND>;
972		status = "disabled";
973	};
974
975	gpu: gpu@ff400000 {
976		compatible = "rockchip,px30-mali", "arm,mali-bifrost";
977		reg = <0x0 0xff400000 0x0 0x4000>;
978		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
979			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
980			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
981		interrupt-names = "job", "mmu", "gpu";
982		clocks = <&cru SCLK_GPU>;
983		#cooling-cells = <2>;
984		power-domains = <&power PX30_PD_GPU>;
985		status = "disabled";
986	};
987
988	dsi: dsi@ff450000 {
989		compatible = "rockchip,px30-mipi-dsi";
990		reg = <0x0 0xff450000 0x0 0x10000>;
991		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
992		clocks = <&cru PCLK_MIPI_DSI>;
993		clock-names = "pclk";
994		phys = <&dsi_dphy>;
995		phy-names = "dphy";
996		power-domains = <&power PX30_PD_VO>;
997		resets = <&cru SRST_MIPIDSI_HOST_P>;
998		reset-names = "apb";
999		rockchip,grf = <&grf>;
1000		#address-cells = <1>;
1001		#size-cells = <0>;
1002		status = "disabled";
1003
1004		ports {
1005			#address-cells = <1>;
1006			#size-cells = <0>;
1007
1008			port@0 {
1009				reg = <0>;
1010				#address-cells = <1>;
1011				#size-cells = <0>;
1012
1013				dsi_in_vopb: endpoint@0 {
1014					reg = <0>;
1015					remote-endpoint = <&vopb_out_dsi>;
1016				};
1017
1018				dsi_in_vopl: endpoint@1 {
1019					reg = <1>;
1020					remote-endpoint = <&vopl_out_dsi>;
1021				};
1022			};
1023		};
1024	};
1025
1026	vopb: vop@ff460000 {
1027		compatible = "rockchip,px30-vop-big";
1028		reg = <0x0 0xff460000 0x0 0xefc>;
1029		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1030		clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1031			 <&cru HCLK_VOPB>;
1032		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1033		resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1034		reset-names = "axi", "ahb", "dclk";
1035		iommus = <&vopb_mmu>;
1036		power-domains = <&power PX30_PD_VO>;
1037		status = "disabled";
1038
1039		vopb_out: port {
1040			#address-cells = <1>;
1041			#size-cells = <0>;
1042
1043			vopb_out_dsi: endpoint@0 {
1044				reg = <0>;
1045				remote-endpoint = <&dsi_in_vopb>;
1046			};
1047
1048			vopb_out_lvds: endpoint@1 {
1049				reg = <1>;
1050				remote-endpoint = <&lvds_vopb_in>;
1051			};
1052		};
1053	};
1054
1055	vopb_mmu: iommu@ff460f00 {
1056		compatible = "rockchip,iommu";
1057		reg = <0x0 0xff460f00 0x0 0x100>;
1058		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1059		interrupt-names = "vopb_mmu";
1060		clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1061		clock-names = "aclk", "iface";
1062		power-domains = <&power PX30_PD_VO>;
1063		#iommu-cells = <0>;
1064		status = "disabled";
1065	};
1066
1067	vopl: vop@ff470000 {
1068		compatible = "rockchip,px30-vop-lit";
1069		reg = <0x0 0xff470000 0x0 0xefc>;
1070		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1071		clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1072			 <&cru HCLK_VOPL>;
1073		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1074		resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1075		reset-names = "axi", "ahb", "dclk";
1076		iommus = <&vopl_mmu>;
1077		power-domains = <&power PX30_PD_VO>;
1078		status = "disabled";
1079
1080		vopl_out: port {
1081			#address-cells = <1>;
1082			#size-cells = <0>;
1083
1084			vopl_out_dsi: endpoint@0 {
1085				reg = <0>;
1086				remote-endpoint = <&dsi_in_vopl>;
1087			};
1088
1089			vopl_out_lvds: endpoint@1 {
1090				reg = <1>;
1091				remote-endpoint = <&lvds_vopl_in>;
1092			};
1093		};
1094	};
1095
1096	vopl_mmu: iommu@ff470f00 {
1097		compatible = "rockchip,iommu";
1098		reg = <0x0 0xff470f00 0x0 0x100>;
1099		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1100		interrupt-names = "vopl_mmu";
1101		clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1102		clock-names = "aclk", "iface";
1103		power-domains = <&power PX30_PD_VO>;
1104		#iommu-cells = <0>;
1105		status = "disabled";
1106	};
1107
1108	qos_gmac: qos@ff518000 {
1109		compatible = "syscon";
1110		reg = <0x0 0xff518000 0x0 0x20>;
1111	};
1112
1113	qos_gpu: qos@ff520000 {
1114		compatible = "syscon";
1115		reg = <0x0 0xff520000 0x0 0x20>;
1116	};
1117
1118	qos_sdmmc: qos@ff52c000 {
1119		compatible = "syscon";
1120		reg = <0x0 0xff52c000 0x0 0x20>;
1121	};
1122
1123	qos_emmc: qos@ff538000 {
1124		compatible = "syscon";
1125		reg = <0x0 0xff538000 0x0 0x20>;
1126	};
1127
1128	qos_nand: qos@ff538080 {
1129		compatible = "syscon";
1130		reg = <0x0 0xff538080 0x0 0x20>;
1131	};
1132
1133	qos_sdio: qos@ff538100 {
1134		compatible = "syscon";
1135		reg = <0x0 0xff538100 0x0 0x20>;
1136	};
1137
1138	qos_sfc: qos@ff538180 {
1139		compatible = "syscon";
1140		reg = <0x0 0xff538180 0x0 0x20>;
1141	};
1142
1143	qos_usb_host: qos@ff540000 {
1144		compatible = "syscon";
1145		reg = <0x0 0xff540000 0x0 0x20>;
1146	};
1147
1148	qos_usb_otg: qos@ff540080 {
1149		compatible = "syscon";
1150		reg = <0x0 0xff540080 0x0 0x20>;
1151	};
1152
1153	qos_isp_128: qos@ff548000 {
1154		compatible = "syscon";
1155		reg = <0x0 0xff548000 0x0 0x20>;
1156	};
1157
1158	qos_isp_rd: qos@ff548080 {
1159		compatible = "syscon";
1160		reg = <0x0 0xff548080 0x0 0x20>;
1161	};
1162
1163	qos_isp_wr: qos@ff548100 {
1164		compatible = "syscon";
1165		reg = <0x0 0xff548100 0x0 0x20>;
1166	};
1167
1168	qos_isp_m1: qos@ff548180 {
1169		compatible = "syscon";
1170		reg = <0x0 0xff548180 0x0 0x20>;
1171	};
1172
1173	qos_vip: qos@ff548200 {
1174		compatible = "syscon";
1175		reg = <0x0 0xff548200 0x0 0x20>;
1176	};
1177
1178	qos_rga_rd: qos@ff550000 {
1179		compatible = "syscon";
1180		reg = <0x0 0xff550000 0x0 0x20>;
1181	};
1182
1183	qos_rga_wr: qos@ff550080 {
1184		compatible = "syscon";
1185		reg = <0x0 0xff550080 0x0 0x20>;
1186	};
1187
1188	qos_vop_m0: qos@ff550100 {
1189		compatible = "syscon";
1190		reg = <0x0 0xff550100 0x0 0x20>;
1191	};
1192
1193	qos_vop_m1: qos@ff550180 {
1194		compatible = "syscon";
1195		reg = <0x0 0xff550180 0x0 0x20>;
1196	};
1197
1198	qos_vpu: qos@ff558000 {
1199		compatible = "syscon";
1200		reg = <0x0 0xff558000 0x0 0x20>;
1201	};
1202
1203	qos_vpu_r128: qos@ff558080 {
1204		compatible = "syscon";
1205		reg = <0x0 0xff558080 0x0 0x20>;
1206	};
1207
1208	pinctrl: pinctrl {
1209		compatible = "rockchip,px30-pinctrl";
1210		rockchip,grf = <&grf>;
1211		rockchip,pmu = <&pmugrf>;
1212		#address-cells = <2>;
1213		#size-cells = <2>;
1214		ranges;
1215
1216		gpio0: gpio0@ff040000 {
1217			compatible = "rockchip,gpio-bank";
1218			reg = <0x0 0xff040000 0x0 0x100>;
1219			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1220			clocks = <&pmucru PCLK_GPIO0_PMU>;
1221			gpio-controller;
1222			#gpio-cells = <2>;
1223
1224			interrupt-controller;
1225			#interrupt-cells = <2>;
1226		};
1227
1228		gpio1: gpio1@ff250000 {
1229			compatible = "rockchip,gpio-bank";
1230			reg = <0x0 0xff250000 0x0 0x100>;
1231			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1232			clocks = <&cru PCLK_GPIO1>;
1233			gpio-controller;
1234			#gpio-cells = <2>;
1235
1236			interrupt-controller;
1237			#interrupt-cells = <2>;
1238		};
1239
1240		gpio2: gpio2@ff260000 {
1241			compatible = "rockchip,gpio-bank";
1242			reg = <0x0 0xff260000 0x0 0x100>;
1243			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1244			clocks = <&cru PCLK_GPIO2>;
1245			gpio-controller;
1246			#gpio-cells = <2>;
1247
1248			interrupt-controller;
1249			#interrupt-cells = <2>;
1250		};
1251
1252		gpio3: gpio3@ff270000 {
1253			compatible = "rockchip,gpio-bank";
1254			reg = <0x0 0xff270000 0x0 0x100>;
1255			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1256			clocks = <&cru PCLK_GPIO3>;
1257			gpio-controller;
1258			#gpio-cells = <2>;
1259
1260			interrupt-controller;
1261			#interrupt-cells = <2>;
1262		};
1263
1264		pcfg_pull_up: pcfg-pull-up {
1265			bias-pull-up;
1266		};
1267
1268		pcfg_pull_down: pcfg-pull-down {
1269			bias-pull-down;
1270		};
1271
1272		pcfg_pull_none: pcfg-pull-none {
1273			bias-disable;
1274		};
1275
1276		pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1277			bias-disable;
1278			drive-strength = <2>;
1279		};
1280
1281		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1282			bias-pull-up;
1283			drive-strength = <2>;
1284		};
1285
1286		pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1287			bias-pull-up;
1288			drive-strength = <4>;
1289		};
1290
1291		pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1292			bias-disable;
1293			drive-strength = <4>;
1294		};
1295
1296		pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1297			bias-pull-down;
1298			drive-strength = <4>;
1299		};
1300
1301		pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1302			bias-disable;
1303			drive-strength = <8>;
1304		};
1305
1306		pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1307			bias-pull-up;
1308			drive-strength = <8>;
1309		};
1310
1311		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1312			bias-disable;
1313			drive-strength = <12>;
1314		};
1315
1316		pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1317			bias-pull-up;
1318			drive-strength = <12>;
1319		};
1320
1321		pcfg_pull_none_smt: pcfg-pull-none-smt {
1322			bias-disable;
1323			input-schmitt-enable;
1324		};
1325
1326		pcfg_output_high: pcfg-output-high {
1327			output-high;
1328		};
1329
1330		pcfg_output_low: pcfg-output-low {
1331			output-low;
1332		};
1333
1334		pcfg_input_high: pcfg-input-high {
1335			bias-pull-up;
1336			input-enable;
1337		};
1338
1339		pcfg_input: pcfg-input {
1340			input-enable;
1341		};
1342
1343		i2c0 {
1344			i2c0_xfer: i2c0-xfer {
1345				rockchip,pins =
1346					<0 RK_PB0 1 &pcfg_pull_none_smt>,
1347					<0 RK_PB1 1 &pcfg_pull_none_smt>;
1348			};
1349		};
1350
1351		i2c1 {
1352			i2c1_xfer: i2c1-xfer {
1353				rockchip,pins =
1354					<0 RK_PC2 1 &pcfg_pull_none_smt>,
1355					<0 RK_PC3 1 &pcfg_pull_none_smt>;
1356			};
1357		};
1358
1359		i2c2 {
1360			i2c2_xfer: i2c2-xfer {
1361				rockchip,pins =
1362					<2 RK_PB7 2 &pcfg_pull_none_smt>,
1363					<2 RK_PC0 2 &pcfg_pull_none_smt>;
1364			};
1365		};
1366
1367		i2c3 {
1368			i2c3_xfer: i2c3-xfer {
1369				rockchip,pins =
1370					<1 RK_PB4 4 &pcfg_pull_none_smt>,
1371					<1 RK_PB5 4 &pcfg_pull_none_smt>;
1372			};
1373		};
1374
1375		tsadc {
1376			tsadc_otp_gpio: tsadc-otp-gpio {
1377				rockchip,pins =
1378					<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1379			};
1380
1381			tsadc_otp_out: tsadc-otp-out {
1382				rockchip,pins =
1383					<0 RK_PA6 1 &pcfg_pull_none>;
1384			};
1385		};
1386
1387		uart0 {
1388			uart0_xfer: uart0-xfer {
1389				rockchip,pins =
1390					<0 RK_PB2 1 &pcfg_pull_up>,
1391					<0 RK_PB3 1 &pcfg_pull_up>;
1392			};
1393
1394			uart0_cts: uart0-cts {
1395				rockchip,pins =
1396					<0 RK_PB4 1 &pcfg_pull_none>;
1397			};
1398
1399			uart0_rts: uart0-rts {
1400				rockchip,pins =
1401					<0 RK_PB5 1 &pcfg_pull_none>;
1402			};
1403		};
1404
1405		uart1 {
1406			uart1_xfer: uart1-xfer {
1407				rockchip,pins =
1408					<1 RK_PC1 1 &pcfg_pull_up>,
1409					<1 RK_PC0 1 &pcfg_pull_up>;
1410			};
1411
1412			uart1_cts: uart1-cts {
1413				rockchip,pins =
1414					<1 RK_PC2 1 &pcfg_pull_none>;
1415			};
1416
1417			uart1_rts: uart1-rts {
1418				rockchip,pins =
1419					<1 RK_PC3 1 &pcfg_pull_none>;
1420			};
1421		};
1422
1423		uart2-m0 {
1424			uart2m0_xfer: uart2m0-xfer {
1425				rockchip,pins =
1426					<1 RK_PD2 2 &pcfg_pull_up>,
1427					<1 RK_PD3 2 &pcfg_pull_up>;
1428			};
1429		};
1430
1431		uart2-m1 {
1432			uart2m1_xfer: uart2m1-xfer {
1433				rockchip,pins =
1434					<2 RK_PB4 2 &pcfg_pull_up>,
1435					<2 RK_PB6 2 &pcfg_pull_up>;
1436			};
1437		};
1438
1439		uart3-m0 {
1440			uart3m0_xfer: uart3m0-xfer {
1441				rockchip,pins =
1442					<0 RK_PC0 2 &pcfg_pull_up>,
1443					<0 RK_PC1 2 &pcfg_pull_up>;
1444			};
1445
1446			uart3m0_cts: uart3m0-cts {
1447				rockchip,pins =
1448					<0 RK_PC2 2 &pcfg_pull_none>;
1449			};
1450
1451			uart3m0_rts: uart3m0-rts {
1452				rockchip,pins =
1453					<0 RK_PC3 2 &pcfg_pull_none>;
1454			};
1455		};
1456
1457		uart3-m1 {
1458			uart3m1_xfer: uart3m1-xfer {
1459				rockchip,pins =
1460					<1 RK_PB6 2 &pcfg_pull_up>,
1461					<1 RK_PB7 2 &pcfg_pull_up>;
1462			};
1463
1464			uart3m1_cts: uart3m1-cts {
1465				rockchip,pins =
1466					<1 RK_PB4 2 &pcfg_pull_none>;
1467			};
1468
1469			uart3m1_rts: uart3m1-rts {
1470				rockchip,pins =
1471					<1 RK_PB5 2 &pcfg_pull_none>;
1472			};
1473		};
1474
1475		uart4 {
1476			uart4_xfer: uart4-xfer {
1477				rockchip,pins =
1478					<1 RK_PD4 2 &pcfg_pull_up>,
1479					<1 RK_PD5 2 &pcfg_pull_up>;
1480			};
1481
1482			uart4_cts: uart4-cts {
1483				rockchip,pins =
1484					<1 RK_PD6 2 &pcfg_pull_none>;
1485			};
1486
1487			uart4_rts: uart4-rts {
1488				rockchip,pins =
1489					<1 RK_PD7 2 &pcfg_pull_none>;
1490			};
1491		};
1492
1493		uart5 {
1494			uart5_xfer: uart5-xfer {
1495				rockchip,pins =
1496					<3 RK_PA2 4 &pcfg_pull_up>,
1497					<3 RK_PA1 4 &pcfg_pull_up>;
1498			};
1499
1500			uart5_cts: uart5-cts {
1501				rockchip,pins =
1502					<3 RK_PA3 4 &pcfg_pull_none>;
1503			};
1504
1505			uart5_rts: uart5-rts {
1506				rockchip,pins =
1507					<3 RK_PA5 4 &pcfg_pull_none>;
1508			};
1509		};
1510
1511		spi0 {
1512			spi0_clk: spi0-clk {
1513				rockchip,pins =
1514					<1 RK_PB7 3 &pcfg_pull_up_4ma>;
1515			};
1516
1517			spi0_csn: spi0-csn {
1518				rockchip,pins =
1519					<1 RK_PB6 3 &pcfg_pull_up_4ma>;
1520			};
1521
1522			spi0_miso: spi0-miso {
1523				rockchip,pins =
1524					<1 RK_PB5 3 &pcfg_pull_up_4ma>;
1525			};
1526
1527			spi0_mosi: spi0-mosi {
1528				rockchip,pins =
1529					<1 RK_PB4 3 &pcfg_pull_up_4ma>;
1530			};
1531
1532			spi0_clk_hs: spi0-clk-hs {
1533				rockchip,pins =
1534					<1 RK_PB7 3 &pcfg_pull_up_8ma>;
1535			};
1536
1537			spi0_miso_hs: spi0-miso-hs {
1538				rockchip,pins =
1539					<1 RK_PB5 3 &pcfg_pull_up_8ma>;
1540			};
1541
1542			spi0_mosi_hs: spi0-mosi-hs {
1543				rockchip,pins =
1544					<1 RK_PB4 3 &pcfg_pull_up_8ma>;
1545			};
1546		};
1547
1548		spi1 {
1549			spi1_clk: spi1-clk {
1550				rockchip,pins =
1551					<3 RK_PB7 4 &pcfg_pull_up_4ma>;
1552			};
1553
1554			spi1_csn0: spi1-csn0 {
1555				rockchip,pins =
1556					<3 RK_PB1 4 &pcfg_pull_up_4ma>;
1557			};
1558
1559			spi1_csn1: spi1-csn1 {
1560				rockchip,pins =
1561					<3 RK_PB2 2 &pcfg_pull_up_4ma>;
1562			};
1563
1564			spi1_miso: spi1-miso {
1565				rockchip,pins =
1566					<3 RK_PB6 4 &pcfg_pull_up_4ma>;
1567			};
1568
1569			spi1_mosi: spi1-mosi {
1570				rockchip,pins =
1571					<3 RK_PB4 4 &pcfg_pull_up_4ma>;
1572			};
1573
1574			spi1_clk_hs: spi1-clk-hs {
1575				rockchip,pins =
1576					<3 RK_PB7 4 &pcfg_pull_up_8ma>;
1577			};
1578
1579			spi1_miso_hs: spi1-miso-hs {
1580				rockchip,pins =
1581					<3 RK_PB6 4 &pcfg_pull_up_8ma>;
1582			};
1583
1584			spi1_mosi_hs: spi1-mosi-hs {
1585				rockchip,pins =
1586					<3 RK_PB4 4 &pcfg_pull_up_8ma>;
1587			};
1588		};
1589
1590		pdm {
1591			pdm_clk0m0: pdm-clk0m0 {
1592				rockchip,pins =
1593					<3 RK_PC6 2 &pcfg_pull_none>;
1594			};
1595
1596			pdm_clk0m1: pdm-clk0m1 {
1597				rockchip,pins =
1598					<2 RK_PC6 1 &pcfg_pull_none>;
1599			};
1600
1601			pdm_clk1: pdm-clk1 {
1602				rockchip,pins =
1603					<3 RK_PC7 2 &pcfg_pull_none>;
1604			};
1605
1606			pdm_sdi0m0: pdm-sdi0m0 {
1607				rockchip,pins =
1608					<3 RK_PD3 2 &pcfg_pull_none>;
1609			};
1610
1611			pdm_sdi0m1: pdm-sdi0m1 {
1612				rockchip,pins =
1613					<2 RK_PC5 2 &pcfg_pull_none>;
1614			};
1615
1616			pdm_sdi1: pdm-sdi1 {
1617				rockchip,pins =
1618					<3 RK_PD0 2 &pcfg_pull_none>;
1619			};
1620
1621			pdm_sdi2: pdm-sdi2 {
1622				rockchip,pins =
1623					<3 RK_PD1 2 &pcfg_pull_none>;
1624			};
1625
1626			pdm_sdi3: pdm-sdi3 {
1627				rockchip,pins =
1628					<3 RK_PD2 2 &pcfg_pull_none>;
1629			};
1630
1631			pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1632				rockchip,pins =
1633					<3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1634			};
1635
1636			pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1637				rockchip,pins =
1638					<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1639			};
1640
1641			pdm_clk1_sleep: pdm-clk1-sleep {
1642				rockchip,pins =
1643					<3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1644			};
1645
1646			pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1647				rockchip,pins =
1648					<3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1649			};
1650
1651			pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1652				rockchip,pins =
1653					<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1654			};
1655
1656			pdm_sdi1_sleep: pdm-sdi1-sleep {
1657				rockchip,pins =
1658					<3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1659			};
1660
1661			pdm_sdi2_sleep: pdm-sdi2-sleep {
1662				rockchip,pins =
1663					<3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1664			};
1665
1666			pdm_sdi3_sleep: pdm-sdi3-sleep {
1667				rockchip,pins =
1668					<3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1669			};
1670		};
1671
1672		i2s0 {
1673			i2s0_8ch_mclk: i2s0-8ch-mclk {
1674				rockchip,pins =
1675					<3 RK_PC1 2 &pcfg_pull_none>;
1676			};
1677
1678			i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1679				rockchip,pins =
1680					<3 RK_PC3 2 &pcfg_pull_none>;
1681			};
1682
1683			i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1684				rockchip,pins =
1685					<3 RK_PB4 2 &pcfg_pull_none>;
1686			};
1687
1688			i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1689				rockchip,pins =
1690					<3 RK_PC2 2 &pcfg_pull_none>;
1691			};
1692
1693			i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1694				rockchip,pins =
1695					<3 RK_PB5 2 &pcfg_pull_none>;
1696			};
1697
1698			i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1699				rockchip,pins =
1700					<3 RK_PC4 2 &pcfg_pull_none>;
1701			};
1702
1703			i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1704				rockchip,pins =
1705					<3 RK_PC0 2 &pcfg_pull_none>;
1706			};
1707
1708			i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1709				rockchip,pins =
1710					<3 RK_PB7 2 &pcfg_pull_none>;
1711			};
1712
1713			i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1714				rockchip,pins =
1715					<3 RK_PB6 2 &pcfg_pull_none>;
1716			};
1717
1718			i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1719				rockchip,pins =
1720					<3 RK_PC5 2 &pcfg_pull_none>;
1721			};
1722
1723			i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1724				rockchip,pins =
1725					<3 RK_PB3 2 &pcfg_pull_none>;
1726			};
1727
1728			i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1729				rockchip,pins =
1730					<3 RK_PB1 2 &pcfg_pull_none>;
1731			};
1732
1733			i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1734				rockchip,pins =
1735					<3 RK_PB0 2 &pcfg_pull_none>;
1736			};
1737		};
1738
1739		i2s1 {
1740			i2s1_2ch_mclk: i2s1-2ch-mclk {
1741				rockchip,pins =
1742					<2 RK_PC3 1 &pcfg_pull_none>;
1743			};
1744
1745			i2s1_2ch_sclk: i2s1-2ch-sclk {
1746				rockchip,pins =
1747					<2 RK_PC2 1 &pcfg_pull_none>;
1748			};
1749
1750			i2s1_2ch_lrck: i2s1-2ch-lrck {
1751				rockchip,pins =
1752					<2 RK_PC1 1 &pcfg_pull_none>;
1753			};
1754
1755			i2s1_2ch_sdi: i2s1-2ch-sdi {
1756				rockchip,pins =
1757					<2 RK_PC5 1 &pcfg_pull_none>;
1758			};
1759
1760			i2s1_2ch_sdo: i2s1-2ch-sdo {
1761				rockchip,pins =
1762					<2 RK_PC4 1 &pcfg_pull_none>;
1763			};
1764		};
1765
1766		i2s2 {
1767			i2s2_2ch_mclk: i2s2-2ch-mclk {
1768				rockchip,pins =
1769					<3 RK_PA1 2 &pcfg_pull_none>;
1770			};
1771
1772			i2s2_2ch_sclk: i2s2-2ch-sclk {
1773				rockchip,pins =
1774					<3 RK_PA2 2 &pcfg_pull_none>;
1775			};
1776
1777			i2s2_2ch_lrck: i2s2-2ch-lrck {
1778				rockchip,pins =
1779					<3 RK_PA3 2 &pcfg_pull_none>;
1780			};
1781
1782			i2s2_2ch_sdi: i2s2-2ch-sdi {
1783				rockchip,pins =
1784					<3 RK_PA5 2 &pcfg_pull_none>;
1785			};
1786
1787			i2s2_2ch_sdo: i2s2-2ch-sdo {
1788				rockchip,pins =
1789					<3 RK_PA7 2 &pcfg_pull_none>;
1790			};
1791		};
1792
1793		sdmmc {
1794			sdmmc_clk: sdmmc-clk {
1795				rockchip,pins =
1796					<1 RK_PD6 1 &pcfg_pull_none_8ma>;
1797			};
1798
1799			sdmmc_cmd: sdmmc-cmd {
1800				rockchip,pins =
1801					<1 RK_PD7 1 &pcfg_pull_up_8ma>;
1802			};
1803
1804			sdmmc_det: sdmmc-det {
1805				rockchip,pins =
1806					<0 RK_PA3 1 &pcfg_pull_up_8ma>;
1807			};
1808
1809			sdmmc_bus1: sdmmc-bus1 {
1810				rockchip,pins =
1811					<1 RK_PD2 1 &pcfg_pull_up_8ma>;
1812			};
1813
1814			sdmmc_bus4: sdmmc-bus4 {
1815				rockchip,pins =
1816					<1 RK_PD2 1 &pcfg_pull_up_8ma>,
1817					<1 RK_PD3 1 &pcfg_pull_up_8ma>,
1818					<1 RK_PD4 1 &pcfg_pull_up_8ma>,
1819					<1 RK_PD5 1 &pcfg_pull_up_8ma>;
1820			};
1821		};
1822
1823		sdio {
1824			sdio_clk: sdio-clk {
1825				rockchip,pins =
1826					<1 RK_PC5 1 &pcfg_pull_none>;
1827			};
1828
1829			sdio_cmd: sdio-cmd {
1830				rockchip,pins =
1831					<1 RK_PC4 1 &pcfg_pull_up>;
1832			};
1833
1834			sdio_bus4: sdio-bus4 {
1835				rockchip,pins =
1836					<1 RK_PC6 1 &pcfg_pull_up>,
1837					<1 RK_PC7 1 &pcfg_pull_up>,
1838					<1 RK_PD0 1 &pcfg_pull_up>,
1839					<1 RK_PD1 1 &pcfg_pull_up>;
1840			};
1841		};
1842
1843		emmc {
1844			emmc_clk: emmc-clk {
1845				rockchip,pins =
1846					<1 RK_PB1 2 &pcfg_pull_none_8ma>;
1847			};
1848
1849			emmc_cmd: emmc-cmd {
1850				rockchip,pins =
1851					<1 RK_PB2 2 &pcfg_pull_up_8ma>;
1852			};
1853
1854			emmc_rstnout: emmc-rstnout {
1855				rockchip,pins =
1856					<1 RK_PB3 2 &pcfg_pull_none>;
1857			};
1858
1859			emmc_bus1: emmc-bus1 {
1860				rockchip,pins =
1861					<1 RK_PA0 2 &pcfg_pull_up_8ma>;
1862			};
1863
1864			emmc_bus4: emmc-bus4 {
1865				rockchip,pins =
1866					<1 RK_PA0 2 &pcfg_pull_up_8ma>,
1867					<1 RK_PA1 2 &pcfg_pull_up_8ma>,
1868					<1 RK_PA2 2 &pcfg_pull_up_8ma>,
1869					<1 RK_PA3 2 &pcfg_pull_up_8ma>;
1870			};
1871
1872			emmc_bus8: emmc-bus8 {
1873				rockchip,pins =
1874					<1 RK_PA0 2 &pcfg_pull_up_8ma>,
1875					<1 RK_PA1 2 &pcfg_pull_up_8ma>,
1876					<1 RK_PA2 2 &pcfg_pull_up_8ma>,
1877					<1 RK_PA3 2 &pcfg_pull_up_8ma>,
1878					<1 RK_PA4 2 &pcfg_pull_up_8ma>,
1879					<1 RK_PA5 2 &pcfg_pull_up_8ma>,
1880					<1 RK_PA6 2 &pcfg_pull_up_8ma>,
1881					<1 RK_PA7 2 &pcfg_pull_up_8ma>;
1882			};
1883		};
1884
1885		flash {
1886			flash_cs0: flash-cs0 {
1887				rockchip,pins =
1888					<1 RK_PB0 1 &pcfg_pull_none>;
1889			};
1890
1891			flash_rdy: flash-rdy {
1892				rockchip,pins =
1893					<1 RK_PB1 1 &pcfg_pull_none>;
1894			};
1895
1896			flash_dqs: flash-dqs {
1897				rockchip,pins =
1898					<1 RK_PB2 1 &pcfg_pull_none>;
1899			};
1900
1901			flash_ale: flash-ale {
1902				rockchip,pins =
1903					<1 RK_PB3 1 &pcfg_pull_none>;
1904			};
1905
1906			flash_cle: flash-cle {
1907				rockchip,pins =
1908					<1 RK_PB4 1 &pcfg_pull_none>;
1909			};
1910
1911			flash_wrn: flash-wrn {
1912				rockchip,pins =
1913					<1 RK_PB5 1 &pcfg_pull_none>;
1914			};
1915
1916			flash_csl: flash-csl {
1917				rockchip,pins =
1918					<1 RK_PB6 1 &pcfg_pull_none>;
1919			};
1920
1921			flash_rdn: flash-rdn {
1922				rockchip,pins =
1923					<1 RK_PB7 1 &pcfg_pull_none>;
1924			};
1925
1926			flash_bus8: flash-bus8 {
1927				rockchip,pins =
1928					<1 RK_PA0 1 &pcfg_pull_up_12ma>,
1929					<1 RK_PA1 1 &pcfg_pull_up_12ma>,
1930					<1 RK_PA2 1 &pcfg_pull_up_12ma>,
1931					<1 RK_PA3 1 &pcfg_pull_up_12ma>,
1932					<1 RK_PA4 1 &pcfg_pull_up_12ma>,
1933					<1 RK_PA5 1 &pcfg_pull_up_12ma>,
1934					<1 RK_PA6 1 &pcfg_pull_up_12ma>,
1935					<1 RK_PA7 1 &pcfg_pull_up_12ma>;
1936			};
1937		};
1938
1939		lcdc {
1940			lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1941				rockchip,pins =
1942					<3 RK_PA0 1 &pcfg_pull_none_12ma>;
1943			};
1944
1945			lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1946				rockchip,pins =
1947					<3 RK_PA1 1 &pcfg_pull_none_12ma>;
1948			};
1949
1950			lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1951				rockchip,pins =
1952					<3 RK_PA2 1 &pcfg_pull_none_12ma>;
1953			};
1954
1955			lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
1956				rockchip,pins =
1957					<3 RK_PA3 1 &pcfg_pull_none_12ma>;
1958			};
1959
1960			lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
1961				rockchip,pins =
1962					<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1963					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1964					<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1965					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1966					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1967					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1968					<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1969					<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1970					<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1971					<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1972					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1973					<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1974					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1975					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1976					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1977					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1978					<3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1979					<3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1980					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1981					<3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1982					<3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1983					<3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1984					<3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1985					<3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1986			};
1987
1988			lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
1989				rockchip,pins =
1990					<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1991					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1992					<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1993					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1994					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1995					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1996					<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1997					<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1998					<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1999					<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2000					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2001					<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2002					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2003					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2004					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2005					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2006					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2007					<3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2008			};
2009
2010			lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2011				rockchip,pins =
2012					<3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2013					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2014					<3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2015					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2016					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2017					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2018					<3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2019					<3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2020					<3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2021					<3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2022					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2023					<3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2024					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2025					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2026					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2027					<3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2028			};
2029
2030			lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2031				rockchip,pins =
2032					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2033					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2034					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2035					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2036					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2037					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2038					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2039					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2040					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2041					<3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2042					<3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2043					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2044					<3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2045					<3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2046					<3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2047					<3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2048					<3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2049			};
2050
2051			lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2052				rockchip,pins =
2053					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2054					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2055					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2056					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2057					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2058					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2059					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2060					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2061					<3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2062					<3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2063					<3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2064			};
2065
2066			lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2067				rockchip,pins =
2068					<3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2069					<3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2070					<3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2071					<3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2072					<3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2073					<3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2074					<3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2075					<3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2076					<3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2077			};
2078		};
2079
2080		pwm0 {
2081			pwm0_pin: pwm0-pin {
2082				rockchip,pins =
2083					<0 RK_PB7 1 &pcfg_pull_none>;
2084			};
2085		};
2086
2087		pwm1 {
2088			pwm1_pin: pwm1-pin {
2089				rockchip,pins =
2090					<0 RK_PC0 1 &pcfg_pull_none>;
2091			};
2092		};
2093
2094		pwm2 {
2095			pwm2_pin: pwm2-pin {
2096				rockchip,pins =
2097					<2 RK_PB5 1 &pcfg_pull_none>;
2098			};
2099		};
2100
2101		pwm3 {
2102			pwm3_pin: pwm3-pin {
2103				rockchip,pins =
2104					<0 RK_PC1 1 &pcfg_pull_none>;
2105			};
2106		};
2107
2108		pwm4 {
2109			pwm4_pin: pwm4-pin {
2110				rockchip,pins =
2111					<3 RK_PC2 3 &pcfg_pull_none>;
2112			};
2113		};
2114
2115		pwm5 {
2116			pwm5_pin: pwm5-pin {
2117				rockchip,pins =
2118					<3 RK_PC3 3 &pcfg_pull_none>;
2119			};
2120		};
2121
2122		pwm6 {
2123			pwm6_pin: pwm6-pin {
2124				rockchip,pins =
2125					<3 RK_PC4 3 &pcfg_pull_none>;
2126			};
2127		};
2128
2129		pwm7 {
2130			pwm7_pin: pwm7-pin {
2131				rockchip,pins =
2132					<3 RK_PC5 3 &pcfg_pull_none>;
2133			};
2134		};
2135
2136		gmac {
2137			rmii_pins: rmii-pins {
2138				rockchip,pins =
2139					<2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2140					<2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2141					<2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2142					<2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2143					<2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2144					<2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2145					<2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2146					<2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2147					<2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2148			};
2149
2150			mac_refclk_12ma: mac-refclk-12ma {
2151				rockchip,pins =
2152					<2 RK_PB2 2 &pcfg_pull_none_12ma>;
2153			};
2154
2155			mac_refclk: mac-refclk {
2156				rockchip,pins =
2157					<2 RK_PB2 2 &pcfg_pull_none>;
2158			};
2159		};
2160
2161		cif-m0 {
2162			cif_clkout_m0: cif-clkout-m0 {
2163				rockchip,pins =
2164					<2 RK_PB3 1 &pcfg_pull_none>;
2165			};
2166
2167			dvp_d2d9_m0: dvp-d2d9-m0 {
2168				rockchip,pins =
2169					<2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2170					<2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2171					<2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2172					<2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2173					<2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2174					<2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2175					<2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2176					<2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2177					<2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2178					<2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2179					<2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2180					<2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2181			};
2182
2183			dvp_d0d1_m0: dvp-d0d1-m0 {
2184				rockchip,pins =
2185					<2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2186					<2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2187			};
2188
2189			dvp_d10d11_m0:d10-d11-m0 {
2190				rockchip,pins =
2191					<2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2192					<2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2193			};
2194		};
2195
2196		cif-m1 {
2197			cif_clkout_m1: cif-clkout-m1 {
2198				rockchip,pins =
2199					<3 RK_PD0 3 &pcfg_pull_none>;
2200			};
2201
2202			dvp_d2d9_m1: dvp-d2d9-m1 {
2203				rockchip,pins =
2204					<3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2205					<3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2206					<3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2207					<3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2208					<3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2209					<3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2210					<3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2211					<3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2212					<3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2213					<3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2214					<3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2215					<3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2216			};
2217
2218			dvp_d0d1_m1: dvp-d0d1-m1 {
2219				rockchip,pins =
2220					<3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2221					<3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2222			};
2223
2224			dvp_d10d11_m1:d10-d11-m1 {
2225				rockchip,pins =
2226					<3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2227					<3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2228			};
2229		};
2230
2231		isp {
2232			isp_prelight: isp-prelight {
2233				rockchip,pins =
2234					<3 RK_PD1 4 &pcfg_pull_none>;
2235			};
2236		};
2237	};
2238};
2239