1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2LC SMARC SOM common parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10 11/ { 12 aliases { 13 ethernet0 = ð0; 14 }; 15 16 chosen { 17 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 18 }; 19 20 memory@48000000 { 21 device_type = "memory"; 22 /* first 128MB is reserved for secure area. */ 23 reg = <0x0 0x48000000 0x0 0x38000000>; 24 }; 25 26 reg_1p8v: regulator0 { 27 compatible = "regulator-fixed"; 28 regulator-name = "fixed-1.8V"; 29 regulator-min-microvolt = <1800000>; 30 regulator-max-microvolt = <1800000>; 31 regulator-boot-on; 32 regulator-always-on; 33 }; 34 35 reg_3p3v: regulator1 { 36 compatible = "regulator-fixed"; 37 regulator-name = "fixed-3.3V"; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 regulator-boot-on; 41 regulator-always-on; 42 }; 43 44 vccq_sdhi0: regulator-vccq-sdhi0 { 45 compatible = "regulator-gpio"; 46 47 regulator-name = "SDHI0 VccQ"; 48 regulator-min-microvolt = <1800000>; 49 regulator-max-microvolt = <3300000>; 50 states = <3300000 1>, <1800000 0>; 51 regulator-boot-on; 52 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; 53 regulator-always-on; 54 }; 55}; 56 57ð0 { 58 pinctrl-0 = <ð0_pins>; 59 pinctrl-names = "default"; 60 phy-handle = <&phy0>; 61 phy-mode = "rgmii-id"; 62 status = "okay"; 63 64 phy0: ethernet-phy@7 { 65 compatible = "ethernet-phy-id0022.1640", 66 "ethernet-phy-ieee802.3-c22"; 67 reg = <7>; 68 rxc-skew-psec = <2400>; 69 txc-skew-psec = <2400>; 70 rxdv-skew-psec = <0>; 71 txdv-skew-psec = <0>; 72 rxd0-skew-psec = <0>; 73 rxd1-skew-psec = <0>; 74 rxd2-skew-psec = <0>; 75 rxd3-skew-psec = <0>; 76 txd0-skew-psec = <0>; 77 txd1-skew-psec = <0>; 78 txd2-skew-psec = <0>; 79 txd3-skew-psec = <0>; 80 }; 81}; 82 83&extal_clk { 84 clock-frequency = <24000000>; 85}; 86 87&pinctrl { 88 eth0_pins: eth0 { 89 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ 90 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ 91 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ 92 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */ 93 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ 94 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ 95 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ 96 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ 97 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ 98 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ 99 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ 100 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ 101 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ 102 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ 103 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ 104 }; 105 106 gpio-sd0-pwr-en-hog { 107 gpio-hog; 108 gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>; 109 output-high; 110 line-name = "gpio_sd0_pwr_en"; 111 }; 112 113 /* 114 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] 115 * The below switch logic can be used to select the device between 116 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT. 117 * SW1[2] should be at OFF position to enable 64 GB eMMC 118 * SW1[2] should be at position ON to enable uSD card CN3 119 */ 120 gpio-sd0-dev-sel-hog { 121 gpio-hog; 122 gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>; 123 output-high; 124 line-name = "gpio_sd0_dev_sel"; 125 }; 126 127 sdhi0_emmc_pins: sd0emmc { 128 sd0_emmc_data { 129 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", 130 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; 131 power-source = <1800>; 132 }; 133 134 sd0_emmc_ctrl { 135 pins = "SD0_CLK", "SD0_CMD"; 136 power-source = <1800>; 137 }; 138 139 sd0_emmc_rst { 140 pins = "SD0_RST#"; 141 power-source = <1800>; 142 }; 143 }; 144 145 sdhi0_pins: sd0 { 146 sd0_data { 147 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 148 power-source = <3300>; 149 }; 150 151 sd0_ctrl { 152 pins = "SD0_CLK", "SD0_CMD"; 153 power-source = <3300>; 154 }; 155 156 sd0_mux { 157 pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */ 158 }; 159 }; 160 161 sdhi0_pins_uhs: sd0_uhs { 162 sd0_data_uhs { 163 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 164 power-source = <1800>; 165 }; 166 167 sd0_ctrl_uhs { 168 pins = "SD0_CLK", "SD0_CMD"; 169 power-source = <1800>; 170 }; 171 172 sd0_mux_uhs { 173 pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */ 174 }; 175 }; 176}; 177 178#if (!SW_SD0_DEV_SEL) 179&sdhi0 { 180 pinctrl-0 = <&sdhi0_pins>; 181 pinctrl-1 = <&sdhi0_pins_uhs>; 182 pinctrl-names = "default", "state_uhs"; 183 184 vmmc-supply = <®_3p3v>; 185 vqmmc-supply = <&vccq_sdhi0>; 186 bus-width = <4>; 187 sd-uhs-sdr50; 188 sd-uhs-sdr104; 189 status = "okay"; 190}; 191#endif 192 193#if SW_SD0_DEV_SEL 194&sdhi0 { 195 pinctrl-0 = <&sdhi0_emmc_pins>; 196 pinctrl-1 = <&sdhi0_emmc_pins>; 197 pinctrl-names = "default", "state_uhs"; 198 199 vmmc-supply = <®_3p3v>; 200 vqmmc-supply = <®_1p8v>; 201 bus-width = <8>; 202 mmc-hs200-1_8v; 203 non-removable; 204 fixed-emmc-driver-type = <1>; 205 status = "okay"; 206}; 207#endif 208 209&wdt0 { 210 status = "okay"; 211 timeout-sec = <60>; 212}; 213 214&wdt1 { 215 status = "okay"; 216 timeout-sec = <60>; 217}; 218 219&wdt2 { 220 status = "okay"; 221 timeout-sec = <60>; 222}; 223