1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2LC SMARC SOM common parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10 11/ { 12 aliases { 13 ethernet0 = ð0; 14 }; 15 16 chosen { 17 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 18 }; 19 20 memory@48000000 { 21 device_type = "memory"; 22 /* first 128MB is reserved for secure area. */ 23 reg = <0x0 0x48000000 0x0 0x38000000>; 24 }; 25 26 reg_1p8v: regulator0 { 27 compatible = "regulator-fixed"; 28 regulator-name = "fixed-1.8V"; 29 regulator-min-microvolt = <1800000>; 30 regulator-max-microvolt = <1800000>; 31 regulator-boot-on; 32 regulator-always-on; 33 }; 34 35 reg_3p3v: regulator1 { 36 compatible = "regulator-fixed"; 37 regulator-name = "fixed-3.3V"; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 regulator-boot-on; 41 regulator-always-on; 42 }; 43 44 vccq_sdhi0: regulator-vccq-sdhi0 { 45 compatible = "regulator-gpio"; 46 47 regulator-name = "SDHI0 VccQ"; 48 regulator-min-microvolt = <1800000>; 49 regulator-max-microvolt = <3300000>; 50 states = <3300000 1>, <1800000 0>; 51 regulator-boot-on; 52 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; 53 regulator-always-on; 54 }; 55}; 56 57ð0 { 58 pinctrl-0 = <ð0_pins>; 59 pinctrl-names = "default"; 60 phy-handle = <&phy0>; 61 phy-mode = "rgmii-id"; 62 status = "okay"; 63 64 phy0: ethernet-phy@7 { 65 compatible = "ethernet-phy-id0022.1640", 66 "ethernet-phy-ieee802.3-c22"; 67 reg = <7>; 68 rxc-skew-psec = <2400>; 69 txc-skew-psec = <2400>; 70 rxdv-skew-psec = <0>; 71 txdv-skew-psec = <0>; 72 rxd0-skew-psec = <0>; 73 rxd1-skew-psec = <0>; 74 rxd2-skew-psec = <0>; 75 rxd3-skew-psec = <0>; 76 txd0-skew-psec = <0>; 77 txd1-skew-psec = <0>; 78 txd2-skew-psec = <0>; 79 txd3-skew-psec = <0>; 80 }; 81}; 82 83&extal_clk { 84 clock-frequency = <24000000>; 85}; 86 87&pinctrl { 88 eth0_pins: eth0 { 89 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */ 90 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */ 91 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */ 92 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */ 93 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */ 94 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */ 95 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */ 96 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */ 97 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */ 98 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */ 99 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */ 100 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ 101 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ 102 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ 103 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ 104 }; 105 106 gpio-sd0-pwr-en-hog { 107 gpio-hog; 108 gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>; 109 output-high; 110 line-name = "gpio_sd0_pwr_en"; 111 }; 112 113 qspi0_pins: qspi0 { 114 qspi0-data { 115 pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; 116 power-source = <1800>; 117 }; 118 119 qspi0-ctrl { 120 pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; 121 power-source = <1800>; 122 }; 123 }; 124 125 /* 126 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] 127 * The below switch logic can be used to select the device between 128 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT. 129 * SW1[2] should be at OFF position to enable 64 GB eMMC 130 * SW1[2] should be at position ON to enable uSD card CN3 131 */ 132 gpio-sd0-dev-sel-hog { 133 gpio-hog; 134 gpios = <RZG2L_GPIO(40, 2) GPIO_ACTIVE_HIGH>; 135 output-high; 136 line-name = "gpio_sd0_dev_sel"; 137 }; 138 139 sdhi0_emmc_pins: sd0emmc { 140 sd0_emmc_data { 141 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", 142 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; 143 power-source = <1800>; 144 }; 145 146 sd0_emmc_ctrl { 147 pins = "SD0_CLK", "SD0_CMD"; 148 power-source = <1800>; 149 }; 150 151 sd0_emmc_rst { 152 pins = "SD0_RST#"; 153 power-source = <1800>; 154 }; 155 }; 156 157 sdhi0_pins: sd0 { 158 sd0_data { 159 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 160 power-source = <3300>; 161 }; 162 163 sd0_ctrl { 164 pins = "SD0_CLK", "SD0_CMD"; 165 power-source = <3300>; 166 }; 167 168 sd0_mux { 169 pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */ 170 }; 171 }; 172 173 sdhi0_pins_uhs: sd0_uhs { 174 sd0_data_uhs { 175 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; 176 power-source = <1800>; 177 }; 178 179 sd0_ctrl_uhs { 180 pins = "SD0_CLK", "SD0_CMD"; 181 power-source = <1800>; 182 }; 183 184 sd0_mux_uhs { 185 pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */ 186 }; 187 }; 188}; 189 190&sbc { 191 pinctrl-0 = <&qspi0_pins>; 192 pinctrl-names = "default"; 193 status = "okay"; 194 195 flash@0 { 196 compatible = "micron,mt25qu512a", "jedec,spi-nor"; 197 reg = <0>; 198 m25p,fast-read; 199 spi-max-frequency = <50000000>; 200 spi-rx-bus-width = <4>; 201 202 partitions { 203 compatible = "fixed-partitions"; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 207 boot@0 { 208 reg = <0x00000000 0x2000000>; 209 read-only; 210 }; 211 user@2000000 { 212 reg = <0x2000000 0x2000000>; 213 }; 214 }; 215 }; 216}; 217 218#if (!SW_SD0_DEV_SEL) 219&sdhi0 { 220 pinctrl-0 = <&sdhi0_pins>; 221 pinctrl-1 = <&sdhi0_pins_uhs>; 222 pinctrl-names = "default", "state_uhs"; 223 224 vmmc-supply = <®_3p3v>; 225 vqmmc-supply = <&vccq_sdhi0>; 226 bus-width = <4>; 227 sd-uhs-sdr50; 228 sd-uhs-sdr104; 229 status = "okay"; 230}; 231#endif 232 233#if SW_SD0_DEV_SEL 234&sdhi0 { 235 pinctrl-0 = <&sdhi0_emmc_pins>; 236 pinctrl-1 = <&sdhi0_emmc_pins>; 237 pinctrl-names = "default", "state_uhs"; 238 239 vmmc-supply = <®_3p3v>; 240 vqmmc-supply = <®_1p8v>; 241 bus-width = <8>; 242 mmc-hs200-1_8v; 243 non-removable; 244 fixed-emmc-driver-type = <1>; 245 status = "okay"; 246}; 247#endif 248 249&wdt0 { 250 status = "okay"; 251 timeout-sec = <60>; 252}; 253 254&wdt1 { 255 status = "okay"; 256 timeout-sec = <60>; 257}; 258 259&wdt2 { 260 status = "okay"; 261 timeout-sec = <60>; 262}; 263