1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2L SMARC EVK common parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11/*
12 * SSI-WM8978
13 *
14 * This command is required when Playback/Capture
15 *
16 *	amixer cset name='Left Input Mixer L2 Switch' on
17 *	amixer cset name='Right Input Mixer R2 Switch' on
18 *	amixer cset name='Headphone Playback Volume' 100
19 *	amixer cset name='PCM Volume' 100%
20 *	amixer cset name='Input PGA Volume' 25
21 *
22 */
23
24/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
25#define PMOD1_SER0	1
26
27/ {
28	aliases {
29		serial0 = &scif0;
30		serial1 = &scif2;
31		i2c0 = &i2c0;
32		i2c1 = &i2c1;
33		i2c3 = &i2c3;
34	};
35
36	chosen {
37		stdout-path = "serial0:115200n8";
38	};
39
40	audio_mclock: audio_mclock {
41		compatible = "fixed-clock";
42		#clock-cells = <0>;
43		clock-frequency = <11289600>;
44	};
45
46	snd_rzg2l: sound {
47		compatible = "simple-audio-card";
48		simple-audio-card,format = "i2s";
49		simple-audio-card,bitclock-master = <&cpu_dai>;
50		simple-audio-card,frame-master = <&cpu_dai>;
51		simple-audio-card,mclk-fs = <256>;
52
53		simple-audio-card,widgets = "Microphone", "Microphone Jack";
54		simple-audio-card,routing =
55			    "L2", "Mic Bias",
56			    "R2", "Mic Bias",
57			    "Mic Bias", "Microphone Jack";
58
59		cpu_dai: simple-audio-card,cpu {
60			sound-dai = <&ssi0>;
61		};
62
63		codec_dai: simple-audio-card,codec {
64			clocks = <&audio_mclock>;
65			sound-dai = <&wm8978>;
66		};
67	};
68
69	usb0_vbus_otg: regulator-usb0-vbus-otg {
70		compatible = "regulator-fixed";
71
72		regulator-name = "USB0_VBUS_OTG";
73		regulator-min-microvolt = <5000000>;
74		regulator-max-microvolt = <5000000>;
75	};
76
77	vccq_sdhi1: regulator-vccq-sdhi1 {
78		compatible = "regulator-gpio";
79		regulator-name = "SDHI1 VccQ";
80		regulator-min-microvolt = <1800000>;
81		regulator-max-microvolt = <3300000>;
82		gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
83		gpios-states = <1>;
84		states = <3300000 1>, <1800000 0>;
85	};
86};
87
88&audio_clk1{
89	clock-frequency = <11289600>;
90};
91
92&audio_clk2{
93	clock-frequency = <12288000>;
94};
95
96&canfd {
97	pinctrl-0 = <&can0_pins &can1_pins>;
98	pinctrl-names = "default";
99	status = "okay";
100
101	channel0 {
102		status = "okay";
103	};
104
105	channel1 {
106		status = "okay";
107	};
108};
109
110&ehci0 {
111	dr_mode = "otg";
112	status = "okay";
113};
114
115&ehci1 {
116	status = "okay";
117};
118
119&hsusb {
120	dr_mode = "otg";
121	status = "okay";
122};
123
124&i2c0 {
125	pinctrl-0 = <&i2c0_pins>;
126	pinctrl-names = "default";
127
128	status = "okay";
129};
130
131&i2c1 {
132	pinctrl-0 = <&i2c1_pins>;
133	pinctrl-names = "default";
134
135	status = "okay";
136};
137
138&i2c3 {
139	pinctrl-0 = <&i2c3_pins>;
140	pinctrl-names = "default";
141	clock-frequency = <400000>;
142
143	status = "okay";
144
145	wm8978: codec@1a {
146		compatible = "wlf,wm8978";
147		#sound-dai-cells = <0>;
148		reg = <0x1a>;
149	};
150};
151
152&ohci0 {
153	dr_mode = "otg";
154	status = "okay";
155};
156
157&ohci1 {
158	status = "okay";
159};
160
161&phyrst {
162	status = "okay";
163};
164
165&pinctrl {
166	pinctrl-0 = <&sound_clk_pins>;
167	pinctrl-names = "default";
168
169	can0_pins: can0 {
170		pinmux = <RZG2L_PORT_PINMUX(10, 1, 2)>, /* TX */
171			 <RZG2L_PORT_PINMUX(11, 0, 2)>; /* RX */
172	};
173
174	/* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
175	can0-stb {
176		gpio-hog;
177		gpios = <RZG2L_GPIO(42, 2) GPIO_ACTIVE_HIGH>;
178		output-low;
179		line-name = "can0_stb";
180	};
181
182	can1_pins: can1 {
183		pinmux = <RZG2L_PORT_PINMUX(12, 1, 2)>, /* TX */
184			 <RZG2L_PORT_PINMUX(13, 0, 2)>; /* RX */
185	};
186
187	/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
188	can1-stb {
189		gpio-hog;
190		gpios = <RZG2L_GPIO(42, 3) GPIO_ACTIVE_HIGH>;
191		output-low;
192		line-name = "can1_stb";
193	};
194
195	i2c0_pins: i2c0 {
196		pins = "RIIC0_SDA", "RIIC0_SCL";
197		input-enable;
198	};
199
200	i2c1_pins: i2c1 {
201		pins = "RIIC1_SDA", "RIIC1_SCL";
202		input-enable;
203	};
204
205	i2c3_pins: i2c3 {
206		pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
207			 <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
208	};
209
210	scif0_pins: scif0 {
211		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
212			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
213	};
214
215	scif2_pins: scif2 {
216		pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
217			 <RZG2L_PORT_PINMUX(48, 1, 1)>, /* RxD */
218			 <RZG2L_PORT_PINMUX(48, 3, 1)>, /* CTS# */
219			 <RZG2L_PORT_PINMUX(48, 4, 1)>; /* RTS# */
220	};
221
222	sd1-pwr-en-hog {
223		gpio-hog;
224		gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
225		output-high;
226		line-name = "sd1_pwr_en";
227	};
228
229	sdhi1_pins: sd1 {
230		sd1_data {
231			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
232			power-source = <3300>;
233		};
234
235		sd1_ctrl {
236			pins = "SD1_CLK", "SD1_CMD";
237			power-source = <3300>;
238		};
239
240		sd1_mux {
241			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
242		};
243	};
244
245	sdhi1_pins_uhs: sd1_uhs {
246		sd1_data_uhs {
247			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
248			power-source = <1800>;
249		};
250
251		sd1_ctrl_uhs {
252			pins = "SD1_CLK", "SD1_CMD";
253			power-source = <1800>;
254		};
255
256		sd1_mux_uhs {
257			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
258		};
259	};
260
261	sound_clk_pins: sound_clk {
262		pins = "AUDIO_CLK1", "AUDIO_CLK2";
263		input-enable;
264	};
265
266	spi1_pins: spi1 {
267		pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
268			 <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
269			 <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
270			 <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
271	};
272
273	ssi0_pins: ssi0 {
274		pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
275			 <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
276			 <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
277			 <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
278	};
279
280	usb0_pins: usb0 {
281		pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
282			 <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
283			 <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
284	};
285
286	usb1_pins: usb1 {
287		pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
288			 <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
289	};
290};
291
292&scif0 {
293	pinctrl-0 = <&scif0_pins>;
294	pinctrl-names = "default";
295	status = "okay";
296};
297
298/*
299 * To enable SCIF2 (SER0) on PMOD1 (CN7)
300 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
301 * SW2 should be at position 2->3 so that SER0_TX line is activated
302 * SW3 should be at position 2->3 so that SER0_RX line is activated
303 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
304 */
305#if PMOD1_SER0
306&scif2 {
307	pinctrl-0 = <&scif2_pins>;
308	pinctrl-names = "default";
309
310	uart-has-rtscts;
311	status = "okay";
312};
313#endif
314
315&sdhi1 {
316	pinctrl-0 = <&sdhi1_pins>;
317	pinctrl-1 = <&sdhi1_pins_uhs>;
318	pinctrl-names = "default", "state_uhs";
319
320	vmmc-supply = <&reg_3p3v>;
321	vqmmc-supply = <&vccq_sdhi1>;
322	bus-width = <4>;
323	sd-uhs-sdr50;
324	sd-uhs-sdr104;
325	status = "okay";
326};
327
328&spi1 {
329	pinctrl-0 = <&spi1_pins>;
330	pinctrl-names = "default";
331
332	status = "okay";
333};
334
335&ssi0 {
336	pinctrl-0 = <&ssi0_pins>;
337	pinctrl-names = "default";
338
339	status = "okay";
340};
341
342&usb2_phy0 {
343	pinctrl-0 = <&usb0_pins>;
344	pinctrl-names = "default";
345
346	vbus-supply = <&usb0_vbus_otg>;
347	status = "okay";
348};
349
350&usb2_phy1 {
351	pinctrl-0 = <&usb1_pins>;
352	pinctrl-names = "default";
353
354	status = "okay";
355};
356