1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2M SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a09g011-cpg.h> 10 11/ { 12 compatible = "renesas,r9a09g011"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 17 extal_clk: extal { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by the board */ 21 clock-frequency = <0>; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu-map { 29 cluster0 { 30 core0 { 31 cpu = <&cpu0>; 32 }; 33 }; 34 }; 35 36 cpu0: cpu@0 { 37 compatible = "arm,cortex-a53"; 38 reg = <0>; 39 device_type = "cpu"; 40 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>; 41 }; 42 }; 43 44 soc: soc { 45 compatible = "simple-bus"; 46 interrupt-parent = <&gic>; 47 #address-cells = <2>; 48 #size-cells = <2>; 49 ranges; 50 51 gic: interrupt-controller@82000000 { 52 compatible = "arm,gic-400"; 53 #interrupt-cells = <3>; 54 #address-cells = <0>; 55 interrupt-controller; 56 reg = <0x0 0x82010000 0 0x1000>, 57 <0x0 0x82020000 0 0x20000>, 58 <0x0 0x82040000 0 0x20000>, 59 <0x0 0x82060000 0 0x20000>; 60 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 61 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>; 62 clock-names = "clk"; 63 }; 64 65 avb: ethernet@a3300000 { 66 compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m"; 67 reg = <0 0xa3300000 0 0x800>; 68 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */ 69 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */ 70 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */ 87 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */ 88 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */ 91 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */ 92 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */ 93 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */ 94 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */ 95 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */ 96 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */ 97 interrupt-names = "ch0", "ch1", "ch2", "ch3", 98 "ch4", "ch5", "ch6", "ch7", 99 "ch8", "ch9", "ch10", "ch11", 100 "ch12", "ch13", "ch14", "ch15", 101 "ch16", "ch17", "ch18", "ch19", 102 "ch20", "ch21", "dia", "dib", 103 "err_a", "err_b", "mgmt_a", "mgmt_b", 104 "line3"; 105 clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>, 106 <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>, 107 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>; 108 clock-names = "axi", "chi", "gptp"; 109 resets = <&cpg R9A09G011_ETH0_RST_HW_N>; 110 power-domains = <&cpg>; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 status = "disable"; 114 }; 115 116 cpg: clock-controller@a3500000 { 117 compatible = "renesas,r9a09g011-cpg"; 118 reg = <0 0xa3500000 0 0x1000>; 119 clocks = <&extal_clk>; 120 clock-names = "extal"; 121 #clock-cells = <2>; 122 #reset-cells = <1>; 123 #power-domain-cells = <0>; 124 }; 125 126 i2c0: i2c@a4030000 { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c"; 130 reg = <0 0xa4030000 0 0x80>; 131 interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, 132 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; 133 interrupt-names = "tia", "tis"; 134 clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>; 135 resets = <&cpg R9A09G011_IIC_GPA_PRESETN>; 136 power-domains = <&cpg>; 137 status = "disabled"; 138 }; 139 140 i2c2: i2c@a4030100 { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c"; 144 reg = <0 0xa4030100 0 0x80>; 145 interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>, 146 <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>; 147 interrupt-names = "tia", "tis"; 148 clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>; 149 resets = <&cpg R9A09G011_IIC_GPB_PRESETN>; 150 power-domains = <&cpg>; 151 status = "disabled"; 152 }; 153 154 uart0: serial@a4040000 { 155 compatible = "renesas,r9a09g011-uart", "renesas,em-uart"; 156 reg = <0 0xa4040000 0 0x80>; 157 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>, 159 <&cpg CPG_MOD R9A09G011_URT_PCLK>; 160 clock-names = "sclk", "pclk"; 161 status = "disabled"; 162 }; 163 164 pinctrl: pinctrl@b6250000 { 165 compatible = "renesas,r9a09g011-pinctrl"; 166 reg = <0 0xb6250000 0 0x800>; 167 gpio-controller; 168 #gpio-cells = <2>; 169 gpio-ranges = <&pinctrl 0 0 352>; 170 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>; 210 power-domains = <&cpg>; 211 resets = <&cpg R9A09G011_PFC_PRESETN>; 212 }; 213 }; 214 215 timer { 216 compatible = "arm,armv8-timer"; 217 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 218 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 219 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 220 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 221 }; 222}; 223