1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/V2L SoC
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/r9a07g054-cpg.h>
10
11/ {
12	compatible = "renesas,r9a07g054";
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	audio_clk1: audio1-clk {
17		compatible = "fixed-clock";
18		#clock-cells = <0>;
19		/* This value must be overridden by boards that provide it */
20		clock-frequency = <0>;
21	};
22
23	audio_clk2: audio2-clk {
24		compatible = "fixed-clock";
25		#clock-cells = <0>;
26		/* This value must be overridden by boards that provide it */
27		clock-frequency = <0>;
28	};
29
30	/* External CAN clock - to be overridden by boards that provide it */
31	can_clk: can-clk {
32		compatible = "fixed-clock";
33		#clock-cells = <0>;
34		clock-frequency = <0>;
35	};
36
37	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
38	extal_clk: extal-clk {
39		compatible = "fixed-clock";
40		#clock-cells = <0>;
41		/* This value must be overridden by the board */
42		clock-frequency = <0>;
43	};
44
45	cluster0_opp: opp-table-0 {
46		compatible = "operating-points-v2";
47		opp-shared;
48
49		opp-150000000 {
50			opp-hz = /bits/ 64 <150000000>;
51			opp-microvolt = <1100000>;
52			clock-latency-ns = <300000>;
53		};
54		opp-300000000 {
55			opp-hz = /bits/ 64 <300000000>;
56			opp-microvolt = <1100000>;
57			clock-latency-ns = <300000>;
58		};
59		opp-600000000 {
60			opp-hz = /bits/ 64 <600000000>;
61			opp-microvolt = <1100000>;
62			clock-latency-ns = <300000>;
63		};
64		opp-1200000000 {
65			opp-hz = /bits/ 64 <1200000000>;
66			opp-microvolt = <1100000>;
67			clock-latency-ns = <300000>;
68			opp-suspend;
69		};
70	};
71
72	cpus {
73		#address-cells = <1>;
74		#size-cells = <0>;
75
76		cpu-map {
77			cluster0 {
78				core0 {
79					cpu = <&cpu0>;
80				};
81				core1 {
82					cpu = <&cpu1>;
83				};
84			};
85		};
86
87		cpu0: cpu@0 {
88			compatible = "arm,cortex-a55";
89			reg = <0>;
90			device_type = "cpu";
91			#cooling-cells = <2>;
92			next-level-cache = <&L3_CA55>;
93			enable-method = "psci";
94			clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
95			operating-points-v2 = <&cluster0_opp>;
96		};
97
98		cpu1: cpu@100 {
99			compatible = "arm,cortex-a55";
100			reg = <0x100>;
101			device_type = "cpu";
102			next-level-cache = <&L3_CA55>;
103			enable-method = "psci";
104			clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
105			operating-points-v2 = <&cluster0_opp>;
106		};
107
108		L3_CA55: cache-controller-0 {
109			compatible = "cache";
110			cache-unified;
111			cache-size = <0x40000>;
112			cache-level = <3>;
113		};
114	};
115
116	gpu_opp_table: opp-table-1 {
117		compatible = "operating-points-v2";
118
119		opp-500000000 {
120			opp-hz = /bits/ 64 <500000000>;
121			opp-microvolt = <1100000>;
122		};
123
124		opp-400000000 {
125			opp-hz = /bits/ 64 <400000000>;
126			opp-microvolt = <1100000>;
127		};
128
129		opp-250000000 {
130			opp-hz = /bits/ 64 <250000000>;
131			opp-microvolt = <1100000>;
132		};
133
134		opp-200000000 {
135			opp-hz = /bits/ 64 <200000000>;
136			opp-microvolt = <1100000>;
137		};
138
139		opp-125000000 {
140			opp-hz = /bits/ 64 <125000000>;
141			opp-microvolt = <1100000>;
142		};
143
144		opp-100000000 {
145			opp-hz = /bits/ 64 <100000000>;
146			opp-microvolt = <1100000>;
147		};
148
149		opp-62500000 {
150			opp-hz = /bits/ 64 <62500000>;
151			opp-microvolt = <1100000>;
152		};
153
154		opp-50000000 {
155			opp-hz = /bits/ 64 <50000000>;
156			opp-microvolt = <1100000>;
157		};
158	};
159
160	psci {
161		compatible = "arm,psci-1.0", "arm,psci-0.2";
162		method = "smc";
163	};
164
165	soc: soc {
166		compatible = "simple-bus";
167		interrupt-parent = <&gic>;
168		#address-cells = <2>;
169		#size-cells = <2>;
170		ranges;
171
172		ssi0: ssi@10049c00 {
173			compatible = "renesas,r9a07g054-ssi",
174				     "renesas,rz-ssi";
175			reg = <0 0x10049c00 0 0x400>;
176			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
177				     <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
178				     <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
179				     <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
180			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
181			clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
182				 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
183				 <&audio_clk1>, <&audio_clk2>;
184			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
185			resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
186			dmas = <&dmac 0x2655>, <&dmac 0x2656>;
187			dma-names = "tx", "rx";
188			power-domains = <&cpg>;
189			#sound-dai-cells = <0>;
190			status = "disabled";
191		};
192
193		ssi1: ssi@1004a000 {
194			compatible = "renesas,r9a07g054-ssi",
195				     "renesas,rz-ssi";
196			reg = <0 0x1004a000 0 0x400>;
197			interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
198				     <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
199				     <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
200				     <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
201			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
202			clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
203				 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
204				 <&audio_clk1>, <&audio_clk2>;
205			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
206			resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
207			dmas = <&dmac 0x2659>, <&dmac 0x265a>;
208			dma-names = "tx", "rx";
209			power-domains = <&cpg>;
210			#sound-dai-cells = <0>;
211			status = "disabled";
212		};
213
214		ssi2: ssi@1004a400 {
215			compatible = "renesas,r9a07g054-ssi",
216				     "renesas,rz-ssi";
217			reg = <0 0x1004a400 0 0x400>;
218			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
219				     <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
220				     <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
221				     <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
222			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
223			clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
224				 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
225				 <&audio_clk1>, <&audio_clk2>;
226			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
227			resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
228			dmas = <&dmac 0x265f>;
229			dma-names = "rt";
230			power-domains = <&cpg>;
231			#sound-dai-cells = <0>;
232			status = "disabled";
233		};
234
235		ssi3: ssi@1004a800 {
236			compatible = "renesas,r9a07g054-ssi",
237				     "renesas,rz-ssi";
238			reg = <0 0x1004a800 0 0x400>;
239			interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
240				     <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
241				     <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
242				     <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
243			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
244			clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
245				 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
246				 <&audio_clk1>, <&audio_clk2>;
247			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
248			resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
249			dmas = <&dmac 0x2661>, <&dmac 0x2662>;
250			dma-names = "tx", "rx";
251			power-domains = <&cpg>;
252			#sound-dai-cells = <0>;
253			status = "disabled";
254		};
255
256		spi0: spi@1004ac00 {
257			compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
258			reg = <0 0x1004ac00 0 0x400>;
259			interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
260				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
261				     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
262			interrupt-names = "error", "rx", "tx";
263			clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
264			resets = <&cpg R9A07G054_RSPI0_RST>;
265			dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
266			dma-names = "tx", "rx";
267			power-domains = <&cpg>;
268			num-cs = <1>;
269			#address-cells = <1>;
270			#size-cells = <0>;
271			status = "disabled";
272		};
273
274		spi1: spi@1004b000 {
275			compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
276			reg = <0 0x1004b000 0 0x400>;
277			interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
278				     <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
279				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
280			interrupt-names = "error", "rx", "tx";
281			clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
282			resets = <&cpg R9A07G054_RSPI1_RST>;
283			dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
284			dma-names = "tx", "rx";
285			power-domains = <&cpg>;
286			num-cs = <1>;
287			#address-cells = <1>;
288			#size-cells = <0>;
289			status = "disabled";
290		};
291
292		spi2: spi@1004b400 {
293			compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
294			reg = <0 0x1004b400 0 0x400>;
295			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
296				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
297				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
298			interrupt-names = "error", "rx", "tx";
299			clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
300			resets = <&cpg R9A07G054_RSPI2_RST>;
301			dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
302			dma-names = "tx", "rx";
303			power-domains = <&cpg>;
304			num-cs = <1>;
305			#address-cells = <1>;
306			#size-cells = <0>;
307			status = "disabled";
308		};
309
310		scif0: serial@1004b800 {
311			compatible = "renesas,scif-r9a07g054",
312				     "renesas,scif-r9a07g044";
313			reg = <0 0x1004b800 0 0x400>;
314			interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
315				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
316				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
317				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
318				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
319				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
320			interrupt-names = "eri", "rxi", "txi",
321					  "bri", "dri", "tei";
322			clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
323			clock-names = "fck";
324			power-domains = <&cpg>;
325			resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
326			status = "disabled";
327		};
328
329		scif1: serial@1004bc00 {
330			compatible = "renesas,scif-r9a07g054",
331				     "renesas,scif-r9a07g044";
332			reg = <0 0x1004bc00 0 0x400>;
333			interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
334				     <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
335				     <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
336				     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
337				     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
338				     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
339			interrupt-names = "eri", "rxi", "txi",
340					  "bri", "dri", "tei";
341			clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
342			clock-names = "fck";
343			power-domains = <&cpg>;
344			resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
345			status = "disabled";
346		};
347
348		scif2: serial@1004c000 {
349			compatible = "renesas,scif-r9a07g054",
350				     "renesas,scif-r9a07g044";
351			reg = <0 0x1004c000 0 0x400>;
352			interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
353				     <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
354				     <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
355				     <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
356				     <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
357				     <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
358			interrupt-names = "eri", "rxi", "txi",
359					  "bri", "dri", "tei";
360			clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
361			clock-names = "fck";
362			power-domains = <&cpg>;
363			resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
364			status = "disabled";
365		};
366
367		scif3: serial@1004c400 {
368			compatible = "renesas,scif-r9a07g054",
369				     "renesas,scif-r9a07g044";
370			reg = <0 0x1004c400 0 0x400>;
371			interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
372				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
373				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
374				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
375				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
376				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
377			interrupt-names = "eri", "rxi", "txi",
378					  "bri", "dri", "tei";
379			clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
380			clock-names = "fck";
381			power-domains = <&cpg>;
382			resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
383			status = "disabled";
384		};
385
386		scif4: serial@1004c800 {
387			compatible = "renesas,scif-r9a07g054",
388				     "renesas,scif-r9a07g044";
389			reg = <0 0x1004c800 0 0x400>;
390			interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
391				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
392				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
393				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
394				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
395				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
396			interrupt-names = "eri", "rxi", "txi",
397					  "bri", "dri", "tei";
398			clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
399			clock-names = "fck";
400			power-domains = <&cpg>;
401			resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
402			status = "disabled";
403		};
404
405		sci0: serial@1004d000 {
406			compatible = "renesas,r9a07g054-sci", "renesas,sci";
407			reg = <0 0x1004d000 0 0x400>;
408			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
409				     <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
410				     <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
411				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
412			interrupt-names = "eri", "rxi", "txi", "tei";
413			clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
414			clock-names = "fck";
415			power-domains = <&cpg>;
416			resets = <&cpg R9A07G054_SCI0_RST>;
417			status = "disabled";
418		};
419
420		sci1: serial@1004d400 {
421			compatible = "renesas,r9a07g054-sci", "renesas,sci";
422			reg = <0 0x1004d400 0 0x400>;
423			interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
424				     <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
425				     <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
426				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
427			interrupt-names = "eri", "rxi", "txi", "tei";
428			clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
429			clock-names = "fck";
430			power-domains = <&cpg>;
431			resets = <&cpg R9A07G054_SCI1_RST>;
432			status = "disabled";
433		};
434
435		canfd: can@10050000 {
436			compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd";
437			reg = <0 0x10050000 0 0x8000>;
438			interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
439				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
440				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
441				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
442				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
443				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
444				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
445				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
446			interrupt-names = "g_err", "g_recc",
447					  "ch0_err", "ch0_rec", "ch0_trx",
448					  "ch1_err", "ch1_rec", "ch1_trx";
449			clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
450				 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
451				 <&can_clk>;
452			clock-names = "fck", "canfd", "can_clk";
453			assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
454			assigned-clock-rates = <50000000>;
455			resets = <&cpg R9A07G054_CANFD_RSTP_N>,
456				 <&cpg R9A07G054_CANFD_RSTC_N>;
457			reset-names = "rstp_n", "rstc_n";
458			power-domains = <&cpg>;
459			status = "disabled";
460
461			channel0 {
462				status = "disabled";
463			};
464			channel1 {
465				status = "disabled";
466			};
467		};
468
469		i2c0: i2c@10058000 {
470			#address-cells = <1>;
471			#size-cells = <0>;
472			compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
473			reg = <0 0x10058000 0 0x400>;
474			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
475				     <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
476				     <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
477				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
478				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
479				     <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
480				     <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
481				     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
482			interrupt-names = "tei", "ri", "ti", "spi", "sti",
483					  "naki", "ali", "tmoi";
484			clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
485			clock-frequency = <100000>;
486			resets = <&cpg R9A07G054_I2C0_MRST>;
487			power-domains = <&cpg>;
488			status = "disabled";
489		};
490
491		i2c1: i2c@10058400 {
492			#address-cells = <1>;
493			#size-cells = <0>;
494			compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
495			reg = <0 0x10058400 0 0x400>;
496			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
497				     <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
498				     <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
499				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
500				     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
501				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
502				     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
503				     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
504			interrupt-names = "tei", "ri", "ti", "spi", "sti",
505					  "naki", "ali", "tmoi";
506			clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
507			clock-frequency = <100000>;
508			resets = <&cpg R9A07G054_I2C1_MRST>;
509			power-domains = <&cpg>;
510			status = "disabled";
511		};
512
513		i2c2: i2c@10058800 {
514			#address-cells = <1>;
515			#size-cells = <0>;
516			compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
517			reg = <0 0x10058800 0 0x400>;
518			interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
519				     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
520				     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
521				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
522				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
523				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
524				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
525				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
526			interrupt-names = "tei", "ri", "ti", "spi", "sti",
527					  "naki", "ali", "tmoi";
528			clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
529			clock-frequency = <100000>;
530			resets = <&cpg R9A07G054_I2C2_MRST>;
531			power-domains = <&cpg>;
532			status = "disabled";
533		};
534
535		i2c3: i2c@10058c00 {
536			#address-cells = <1>;
537			#size-cells = <0>;
538			compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
539			reg = <0 0x10058c00 0 0x400>;
540			interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
541				     <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
542				     <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
543				     <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
544				     <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
545				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
546				     <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
547				     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
548			interrupt-names = "tei", "ri", "ti", "spi", "sti",
549					  "naki", "ali", "tmoi";
550			clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
551			clock-frequency = <100000>;
552			resets = <&cpg R9A07G054_I2C3_MRST>;
553			power-domains = <&cpg>;
554			status = "disabled";
555		};
556
557		adc: adc@10059000 {
558			compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc";
559			reg = <0 0x10059000 0 0x400>;
560			interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
561			clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
562				 <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
563			clock-names = "adclk", "pclk";
564			resets = <&cpg R9A07G054_ADC_PRESETN>,
565				 <&cpg R9A07G054_ADC_ADRST_N>;
566			reset-names = "presetn", "adrst-n";
567			power-domains = <&cpg>;
568			status = "disabled";
569
570			#address-cells = <1>;
571			#size-cells = <0>;
572
573			channel@0 {
574				reg = <0>;
575			};
576			channel@1 {
577				reg = <1>;
578			};
579			channel@2 {
580				reg = <2>;
581			};
582			channel@3 {
583				reg = <3>;
584			};
585			channel@4 {
586				reg = <4>;
587			};
588			channel@5 {
589				reg = <5>;
590			};
591			channel@6 {
592				reg = <6>;
593			};
594			channel@7 {
595				reg = <7>;
596			};
597		};
598
599		tsu: thermal@10059400 {
600			compatible = "renesas,r9a07g054-tsu",
601				     "renesas,rzg2l-tsu";
602			reg = <0 0x10059400 0 0x400>;
603			clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
604			resets = <&cpg R9A07G054_TSU_PRESETN>;
605			power-domains = <&cpg>;
606			#thermal-sensor-cells = <1>;
607		};
608
609		sbc: spi@10060000 {
610			compatible = "renesas,r9a07g054-rpc-if",
611				     "renesas,rzg2l-rpc-if";
612			reg = <0 0x10060000 0 0x10000>,
613			      <0 0x20000000 0 0x10000000>,
614			      <0 0x10070000 0 0x10000>;
615			reg-names = "regs", "dirmap", "wbuf";
616			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
617			clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
618				 <&cpg CPG_MOD R9A07G054_SPI_CLK>;
619			resets = <&cpg R9A07G054_SPI_RST>;
620			power-domains = <&cpg>;
621			#address-cells = <1>;
622			#size-cells = <0>;
623			status = "disabled";
624		};
625
626		cpg: clock-controller@11010000 {
627			compatible = "renesas,r9a07g054-cpg";
628			reg = <0 0x11010000 0 0x10000>;
629			clocks = <&extal_clk>;
630			clock-names = "extal";
631			#clock-cells = <2>;
632			#reset-cells = <1>;
633			#power-domain-cells = <0>;
634		};
635
636		sysc: system-controller@11020000 {
637			compatible = "renesas,r9a07g054-sysc";
638			reg = <0 0x11020000 0 0x10000>;
639			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
640				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
641				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
642				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
643			interrupt-names = "lpm_int", "ca55stbydone_int",
644					  "cm33stbyr_int", "ca55_deny";
645			status = "disabled";
646		};
647
648		pinctrl: pinctrl@11030000 {
649			compatible = "renesas,r9a07g054-pinctrl",
650				     "renesas,r9a07g044-pinctrl";
651			reg = <0 0x11030000 0 0x10000>;
652			gpio-controller;
653			#gpio-cells = <2>;
654			#interrupt-cells = <2>;
655			interrupt-parent = <&irqc>;
656			interrupt-controller;
657			gpio-ranges = <&pinctrl 0 0 392>;
658			clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
659			power-domains = <&cpg>;
660			resets = <&cpg R9A07G054_GPIO_RSTN>,
661				 <&cpg R9A07G054_GPIO_PORT_RESETN>,
662				 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
663		};
664
665		irqc: interrupt-controller@110a0000 {
666			compatible = "renesas,r9a07g054-irqc",
667				     "renesas,rzg2l-irqc";
668			#interrupt-cells = <2>;
669			#address-cells = <0>;
670			interrupt-controller;
671			reg = <0 0x110a0000 0 0x10000>;
672			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
673				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
674				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
675				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
676				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
677				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
678				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
679				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
680				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
681				     <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
682				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
683				     <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
684				     <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
685				     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
686				     <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
687				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
688				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
689				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
690				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
691				     <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
692				     <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
693				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
694				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
695				     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
696				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
697				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
698				     <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
699				     <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
700				     <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
701				     <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
702				     <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
703				     <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
704				     <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
705				     <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
706				     <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
707				     <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
708				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
709				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
710				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
711				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
712				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
713			clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
714				 <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
715			clock-names = "clk", "pclk";
716			power-domains = <&cpg>;
717			resets = <&cpg R9A07G054_IA55_RESETN>;
718		};
719
720		dmac: dma-controller@11820000 {
721			compatible = "renesas,r9a07g054-dmac",
722				     "renesas,rz-dmac";
723			reg = <0 0x11820000 0 0x10000>,
724			      <0 0x11830000 0 0x10000>;
725			interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
726				     <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
727				     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
728				     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
729				     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
730				     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
731				     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
732				     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
733				     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
734				     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
735				     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
736				     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
737				     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
738				     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
739				     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
740				     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
741				     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
742			interrupt-names = "error",
743					  "ch0", "ch1", "ch2", "ch3",
744					  "ch4", "ch5", "ch6", "ch7",
745					  "ch8", "ch9", "ch10", "ch11",
746					  "ch12", "ch13", "ch14", "ch15";
747			clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
748				 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
749			power-domains = <&cpg>;
750			resets = <&cpg R9A07G054_DMAC_ARESETN>,
751				 <&cpg R9A07G054_DMAC_RST_ASYNC>;
752			#dma-cells = <1>;
753			dma-channels = <16>;
754		};
755
756		gpu: gpu@11840000 {
757			compatible = "renesas,r9a07g054-mali",
758				     "arm,mali-bifrost";
759			reg = <0x0 0x11840000 0x0 0x10000>;
760			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
761				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
762				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
763				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
764			interrupt-names = "job", "mmu", "gpu", "event";
765			clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
766				 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
767				 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
768			clock-names = "gpu", "bus", "bus_ace";
769			power-domains = <&cpg>;
770			resets = <&cpg R9A07G054_GPU_RESETN>,
771				 <&cpg R9A07G054_GPU_AXI_RESETN>,
772				 <&cpg R9A07G054_GPU_ACE_RESETN>;
773			reset-names = "rst", "axi_rst", "ace_rst";
774			operating-points-v2 = <&gpu_opp_table>;
775		};
776
777		gic: interrupt-controller@11900000 {
778			compatible = "arm,gic-v3";
779			#interrupt-cells = <3>;
780			#address-cells = <0>;
781			interrupt-controller;
782			reg = <0x0 0x11900000 0 0x40000>,
783			      <0x0 0x11940000 0 0x60000>;
784			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
785		};
786
787		sdhi0: mmc@11c00000 {
788			compatible = "renesas,sdhi-r9a07g054",
789				     "renesas,rcar-gen3-sdhi";
790			reg = <0x0 0x11c00000 0 0x10000>;
791			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
792				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
793			clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
794				 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
795				 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
796				 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
797			clock-names = "core", "clkh", "cd", "aclk";
798			resets = <&cpg R9A07G054_SDHI0_IXRST>;
799			power-domains = <&cpg>;
800			status = "disabled";
801		};
802
803		sdhi1: mmc@11c10000 {
804			compatible = "renesas,sdhi-r9a07g054",
805				     "renesas,rcar-gen3-sdhi";
806			reg = <0x0 0x11c10000 0 0x10000>;
807			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
808				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
809			clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
810				 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
811				 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
812				 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
813			clock-names = "core", "clkh", "cd", "aclk";
814			resets = <&cpg R9A07G054_SDHI1_IXRST>;
815			power-domains = <&cpg>;
816			status = "disabled";
817		};
818
819		eth0: ethernet@11c20000 {
820			compatible = "renesas,r9a07g054-gbeth",
821				     "renesas,rzg2l-gbeth";
822			reg = <0 0x11c20000 0 0x10000>;
823			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
824				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
825				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
826			interrupt-names = "mux", "fil", "arp_ns";
827			phy-mode = "rgmii";
828			clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
829				 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
830				 <&cpg CPG_CORE R9A07G054_CLK_HP>;
831			clock-names = "axi", "chi", "refclk";
832			resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
833			power-domains = <&cpg>;
834			#address-cells = <1>;
835			#size-cells = <0>;
836			status = "disabled";
837		};
838
839		eth1: ethernet@11c30000 {
840			compatible = "renesas,r9a07g054-gbeth",
841				     "renesas,rzg2l-gbeth";
842			reg = <0 0x11c30000 0 0x10000>;
843			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
844				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
845				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
846			interrupt-names = "mux", "fil", "arp_ns";
847			phy-mode = "rgmii";
848			clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
849				 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
850				 <&cpg CPG_CORE R9A07G054_CLK_HP>;
851			clock-names = "axi", "chi", "refclk";
852			resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
853			power-domains = <&cpg>;
854			#address-cells = <1>;
855			#size-cells = <0>;
856			status = "disabled";
857		};
858
859		phyrst: usbphy-ctrl@11c40000 {
860			compatible = "renesas,r9a07g054-usbphy-ctrl",
861				     "renesas,rzg2l-usbphy-ctrl";
862			reg = <0 0x11c40000 0 0x10000>;
863			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
864			resets = <&cpg R9A07G054_USB_PRESETN>;
865			power-domains = <&cpg>;
866			#reset-cells = <1>;
867			status = "disabled";
868		};
869
870		ohci0: usb@11c50000 {
871			compatible = "generic-ohci";
872			reg = <0 0x11c50000 0 0x100>;
873			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
874			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
875				 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
876			resets = <&phyrst 0>,
877				 <&cpg R9A07G054_USB_U2H0_HRESETN>;
878			phys = <&usb2_phy0 1>;
879			phy-names = "usb";
880			power-domains = <&cpg>;
881			status = "disabled";
882		};
883
884		ohci1: usb@11c70000 {
885			compatible = "generic-ohci";
886			reg = <0 0x11c70000 0 0x100>;
887			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
888			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
889				 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
890			resets = <&phyrst 1>,
891				 <&cpg R9A07G054_USB_U2H1_HRESETN>;
892			phys = <&usb2_phy1 1>;
893			phy-names = "usb";
894			power-domains = <&cpg>;
895			status = "disabled";
896		};
897
898		ehci0: usb@11c50100 {
899			compatible = "generic-ehci";
900			reg = <0 0x11c50100 0 0x100>;
901			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
902			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
903				 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
904			resets = <&phyrst 0>,
905				 <&cpg R9A07G054_USB_U2H0_HRESETN>;
906			phys = <&usb2_phy0 2>;
907			phy-names = "usb";
908			companion = <&ohci0>;
909			power-domains = <&cpg>;
910			status = "disabled";
911		};
912
913		ehci1: usb@11c70100 {
914			compatible = "generic-ehci";
915			reg = <0 0x11c70100 0 0x100>;
916			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
917			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
918				 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
919			resets = <&phyrst 1>,
920				 <&cpg R9A07G054_USB_U2H1_HRESETN>;
921			phys = <&usb2_phy1 2>;
922			phy-names = "usb";
923			companion = <&ohci1>;
924			power-domains = <&cpg>;
925			status = "disabled";
926		};
927
928		usb2_phy0: usb-phy@11c50200 {
929			compatible = "renesas,usb2-phy-r9a07g054",
930				     "renesas,rzg2l-usb2-phy";
931			reg = <0 0x11c50200 0 0x700>;
932			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
933			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
934				 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
935			resets = <&phyrst 0>;
936			#phy-cells = <1>;
937			power-domains = <&cpg>;
938			status = "disabled";
939		};
940
941		usb2_phy1: usb-phy@11c70200 {
942			compatible = "renesas,usb2-phy-r9a07g054",
943				     "renesas,rzg2l-usb2-phy";
944			reg = <0 0x11c70200 0 0x700>;
945			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
946			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
947				 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
948			resets = <&phyrst 1>;
949			#phy-cells = <1>;
950			power-domains = <&cpg>;
951			status = "disabled";
952		};
953
954		hsusb: usb@11c60000 {
955			compatible = "renesas,usbhs-r9a07g054",
956				     "renesas,rza2-usbhs";
957			reg = <0 0x11c60000 0 0x10000>;
958			interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
959				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
960				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
961				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
962			clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
963				 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
964			resets = <&phyrst 0>,
965				 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
966			renesas,buswait = <7>;
967			phys = <&usb2_phy0 3>;
968			phy-names = "usb";
969			power-domains = <&cpg>;
970			status = "disabled";
971		};
972
973		wdt0: watchdog@12800800 {
974			compatible = "renesas,r9a07g054-wdt",
975				     "renesas,rzg2l-wdt";
976			reg = <0 0x12800800 0 0x400>;
977			clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
978				 <&cpg CPG_MOD R9A07G054_WDT0_CLK>;
979			clock-names = "pclk", "oscclk";
980			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
981				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
982			interrupt-names = "wdt", "perrout";
983			resets = <&cpg R9A07G054_WDT0_PRESETN>;
984			power-domains = <&cpg>;
985			status = "disabled";
986		};
987
988		wdt1: watchdog@12800c00 {
989			compatible = "renesas,r9a07g054-wdt",
990				     "renesas,rzg2l-wdt";
991			reg = <0 0x12800C00 0 0x400>;
992			clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
993				 <&cpg CPG_MOD R9A07G054_WDT1_CLK>;
994			clock-names = "pclk", "oscclk";
995			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
996				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
997			interrupt-names = "wdt", "perrout";
998			resets = <&cpg R9A07G054_WDT1_PRESETN>;
999			power-domains = <&cpg>;
1000			status = "disabled";
1001		};
1002
1003		ostm0: timer@12801000 {
1004			compatible = "renesas,r9a07g054-ostm",
1005				     "renesas,ostm";
1006			reg = <0x0 0x12801000 0x0 0x400>;
1007			interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
1008			clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
1009			resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
1010			power-domains = <&cpg>;
1011			status = "disabled";
1012		};
1013
1014		ostm1: timer@12801400 {
1015			compatible = "renesas,r9a07g054-ostm",
1016				     "renesas,ostm";
1017			reg = <0x0 0x12801400 0x0 0x400>;
1018			interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
1019			clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
1020			resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
1021			power-domains = <&cpg>;
1022			status = "disabled";
1023		};
1024
1025		ostm2: timer@12801800 {
1026			compatible = "renesas,r9a07g054-ostm",
1027				     "renesas,ostm";
1028			reg = <0x0 0x12801800 0x0 0x400>;
1029			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
1030			clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
1031			resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
1032			power-domains = <&cpg>;
1033			status = "disabled";
1034		};
1035	};
1036
1037	thermal-zones {
1038		cpu-thermal {
1039			polling-delay-passive = <250>;
1040			polling-delay = <1000>;
1041			thermal-sensors = <&tsu 0>;
1042			sustainable-power = <717>;
1043
1044			cooling-maps {
1045				map0 {
1046					trip = <&target>;
1047					cooling-device = <&cpu0 0 2>;
1048					contribution = <1024>;
1049				};
1050			};
1051
1052			trips {
1053				sensor_crit: sensor-crit {
1054					temperature = <125000>;
1055					hysteresis = <1000>;
1056					type = "critical";
1057				};
1058
1059				target: trip-point {
1060					temperature = <100000>;
1061					hysteresis = <1000>;
1062					type = "passive";
1063				};
1064			};
1065		};
1066	};
1067
1068	timer {
1069		compatible = "arm,armv8-timer";
1070		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1071				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1072				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1073				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1074	};
1075};
1076