1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2L SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g054-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g054"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio_clk1 { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio_clk2 { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu-map { 50 cluster0 { 51 core0 { 52 cpu = <&cpu0>; 53 }; 54 core1 { 55 cpu = <&cpu1>; 56 }; 57 }; 58 }; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a55"; 62 reg = <0>; 63 device_type = "cpu"; 64 #cooling-cells = <2>; 65 next-level-cache = <&L3_CA55>; 66 enable-method = "psci"; 67 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; 68 }; 69 70 cpu1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 next-level-cache = <&L3_CA55>; 75 enable-method = "psci"; 76 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; 77 }; 78 79 L3_CA55: cache-controller-0 { 80 compatible = "cache"; 81 cache-unified; 82 cache-size = <0x40000>; 83 }; 84 }; 85 86 psci { 87 compatible = "arm,psci-1.0", "arm,psci-0.2"; 88 method = "smc"; 89 }; 90 91 soc: soc { 92 compatible = "simple-bus"; 93 interrupt-parent = <&gic>; 94 #address-cells = <2>; 95 #size-cells = <2>; 96 ranges; 97 98 ssi0: ssi@10049c00 { 99 reg = <0 0x10049c00 0 0x400>; 100 #sound-dai-cells = <0>; 101 /* place holder */ 102 }; 103 104 spi1: spi@1004b000 { 105 reg = <0 0x1004b000 0 0x400>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 /* place holder */ 109 }; 110 111 scif0: serial@1004b800 { 112 compatible = "renesas,scif-r9a07g054", 113 "renesas,scif-r9a07g044"; 114 reg = <0 0x1004b800 0 0x400>; 115 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 121 interrupt-names = "eri", "rxi", "txi", 122 "bri", "dri", "tei"; 123 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>; 124 clock-names = "fck"; 125 power-domains = <&cpg>; 126 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>; 127 status = "disabled"; 128 }; 129 130 scif1: serial@1004bc00 { 131 compatible = "renesas,scif-r9a07g054", 132 "renesas,scif-r9a07g044"; 133 reg = <0 0x1004bc00 0 0x400>; 134 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 140 interrupt-names = "eri", "rxi", "txi", 141 "bri", "dri", "tei"; 142 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>; 143 clock-names = "fck"; 144 power-domains = <&cpg>; 145 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>; 146 status = "disabled"; 147 }; 148 149 scif2: serial@1004c000 { 150 compatible = "renesas,scif-r9a07g054", 151 "renesas,scif-r9a07g044"; 152 reg = <0 0x1004c000 0 0x400>; 153 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 159 interrupt-names = "eri", "rxi", "txi", 160 "bri", "dri", "tei"; 161 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>; 162 clock-names = "fck"; 163 power-domains = <&cpg>; 164 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>; 165 status = "disabled"; 166 }; 167 168 scif3: serial@1004c400 { 169 compatible = "renesas,scif-r9a07g054", 170 "renesas,scif-r9a07g044"; 171 reg = <0 0x1004c400 0 0x400>; 172 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 178 interrupt-names = "eri", "rxi", "txi", 179 "bri", "dri", "tei"; 180 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>; 181 clock-names = "fck"; 182 power-domains = <&cpg>; 183 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>; 184 status = "disabled"; 185 }; 186 187 scif4: serial@1004c800 { 188 compatible = "renesas,scif-r9a07g054", 189 "renesas,scif-r9a07g044"; 190 reg = <0 0x1004c800 0 0x400>; 191 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 197 interrupt-names = "eri", "rxi", "txi", 198 "bri", "dri", "tei"; 199 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>; 200 clock-names = "fck"; 201 power-domains = <&cpg>; 202 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>; 203 status = "disabled"; 204 }; 205 206 sci0: serial@1004d000 { 207 compatible = "renesas,r9a07g054-sci", "renesas,sci"; 208 reg = <0 0x1004d000 0 0x400>; 209 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 213 interrupt-names = "eri", "rxi", "txi", "tei"; 214 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>; 215 clock-names = "fck"; 216 power-domains = <&cpg>; 217 resets = <&cpg R9A07G054_SCI0_RST>; 218 status = "disabled"; 219 }; 220 221 sci1: serial@1004d400 { 222 compatible = "renesas,r9a07g054-sci", "renesas,sci"; 223 reg = <0 0x1004d400 0 0x400>; 224 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 228 interrupt-names = "eri", "rxi", "txi", "tei"; 229 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>; 230 clock-names = "fck"; 231 power-domains = <&cpg>; 232 resets = <&cpg R9A07G054_SCI1_RST>; 233 status = "disabled"; 234 }; 235 236 canfd: can@10050000 { 237 reg = <0 0x10050000 0 0x8000>; 238 /* place holder */ 239 }; 240 241 i2c0: i2c@10058000 { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 reg = <0 0x10058000 0 0x400>; 245 /* place holder */ 246 }; 247 248 i2c1: i2c@10058400 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 reg = <0 0x10058400 0 0x400>; 252 /* place holder */ 253 }; 254 255 i2c3: i2c@10058c00 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 reg = <0 0x10058c00 0 0x400>; 259 /* place holder */ 260 }; 261 262 adc: adc@10059000 { 263 reg = <0 0x10059000 0 0x400>; 264 /* place holder */ 265 }; 266 267 sbc: spi@10060000 { 268 reg = <0 0x10060000 0 0x10000>, 269 <0 0x20000000 0 0x10000000>, 270 <0 0x10070000 0 0x10000>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 /* place holder */ 274 }; 275 276 cpg: clock-controller@11010000 { 277 compatible = "renesas,r9a07g054-cpg"; 278 reg = <0 0x11010000 0 0x10000>; 279 clocks = <&extal_clk>; 280 clock-names = "extal"; 281 #clock-cells = <2>; 282 #reset-cells = <1>; 283 #power-domain-cells = <0>; 284 }; 285 286 sysc: system-controller@11020000 { 287 compatible = "renesas,r9a07g054-sysc"; 288 reg = <0 0x11020000 0 0x10000>; 289 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-names = "lpm_int", "ca55stbydone_int", 294 "cm33stbyr_int", "ca55_deny"; 295 status = "disabled"; 296 }; 297 298 pinctrl: pinctrl@11030000 { 299 compatible = "renesas,r9a07g054-pinctrl", 300 "renesas,r9a07g044-pinctrl"; 301 reg = <0 0x11030000 0 0x10000>; 302 gpio-controller; 303 #gpio-cells = <2>; 304 gpio-ranges = <&pinctrl 0 0 392>; 305 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>; 306 power-domains = <&cpg>; 307 resets = <&cpg R9A07G054_GPIO_RSTN>, 308 <&cpg R9A07G054_GPIO_PORT_RESETN>, 309 <&cpg R9A07G054_GPIO_SPARE_RESETN>; 310 }; 311 312 dmac: dma-controller@11820000 { 313 compatible = "renesas,r9a07g054-dmac", 314 "renesas,rz-dmac"; 315 reg = <0 0x11820000 0 0x10000>, 316 <0 0x11830000 0 0x10000>; 317 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 318 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 321 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 322 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 323 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 325 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 326 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 327 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 328 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 329 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 330 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 331 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 332 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 333 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 334 interrupt-names = "error", 335 "ch0", "ch1", "ch2", "ch3", 336 "ch4", "ch5", "ch6", "ch7", 337 "ch8", "ch9", "ch10", "ch11", 338 "ch12", "ch13", "ch14", "ch15"; 339 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>, 340 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>; 341 power-domains = <&cpg>; 342 resets = <&cpg R9A07G054_DMAC_ARESETN>, 343 <&cpg R9A07G054_DMAC_RST_ASYNC>; 344 #dma-cells = <1>; 345 dma-channels = <16>; 346 }; 347 348 gpu: gpu@11840000 { 349 reg = <0x0 0x11840000 0x0 0x10000>; 350 /* place holder */ 351 }; 352 353 gic: interrupt-controller@11900000 { 354 compatible = "arm,gic-v3"; 355 #interrupt-cells = <3>; 356 #address-cells = <0>; 357 interrupt-controller; 358 reg = <0x0 0x11900000 0 0x40000>, 359 <0x0 0x11940000 0 0x60000>; 360 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 361 }; 362 363 sdhi0: mmc@11c00000 { 364 reg = <0x0 0x11c00000 0 0x10000>; 365 /* place holder */ 366 }; 367 368 sdhi1: mmc@11c10000 { 369 reg = <0x0 0x11c10000 0 0x10000>; 370 /* place holder */ 371 }; 372 373 eth0: ethernet@11c20000 { 374 compatible = "renesas,r9a07g054-gbeth", 375 "renesas,rzg2l-gbeth"; 376 reg = <0 0x11c20000 0 0x10000>; 377 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 380 interrupt-names = "mux", "fil", "arp_ns"; 381 phy-mode = "rgmii"; 382 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>, 383 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>, 384 <&cpg CPG_CORE R9A07G054_CLK_HP>; 385 clock-names = "axi", "chi", "refclk"; 386 resets = <&cpg R9A07G054_ETH0_RST_HW_N>; 387 power-domains = <&cpg>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 status = "disabled"; 391 }; 392 393 eth1: ethernet@11c30000 { 394 compatible = "renesas,r9a07g054-gbeth", 395 "renesas,rzg2l-gbeth"; 396 reg = <0 0x11c30000 0 0x10000>; 397 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 400 interrupt-names = "mux", "fil", "arp_ns"; 401 phy-mode = "rgmii"; 402 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>, 403 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>, 404 <&cpg CPG_CORE R9A07G054_CLK_HP>; 405 clock-names = "axi", "chi", "refclk"; 406 resets = <&cpg R9A07G054_ETH1_RST_HW_N>; 407 power-domains = <&cpg>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "disabled"; 411 }; 412 413 phyrst: usbphy-ctrl@11c40000 { 414 reg = <0 0x11c40000 0 0x10000>; 415 /* place holder */ 416 }; 417 418 ohci0: usb@11c50000 { 419 reg = <0 0x11c50000 0 0x100>; 420 /* place holder */ 421 }; 422 423 ohci1: usb@11c70000 { 424 reg = <0 0x11c70000 0 0x100>; 425 /* place holder */ 426 }; 427 428 ehci0: usb@11c50100 { 429 reg = <0 0x11c50100 0 0x100>; 430 /* place holder */ 431 }; 432 433 ehci1: usb@11c70100 { 434 reg = <0 0x11c70100 0 0x100>; 435 /* place holder */ 436 }; 437 438 usb2_phy0: usb-phy@11c50200 { 439 reg = <0 0x11c50200 0 0x700>; 440 /* place holder */ 441 }; 442 443 usb2_phy1: usb-phy@11c70200 { 444 reg = <0 0x11c70200 0 0x700>; 445 /* place holder */ 446 }; 447 448 hsusb: usb@11c60000 { 449 reg = <0 0x11c60000 0 0x10000>; 450 /* place holder */ 451 }; 452 453 wdt0: watchdog@12800800 { 454 reg = <0 0x12800800 0 0x400>; 455 /* place holder */ 456 }; 457 458 wdt1: watchdog@12800c00 { 459 reg = <0 0x12800C00 0 0x400>; 460 /* place holder */ 461 }; 462 463 wdt2: watchdog@12800400 { 464 reg = <0 0x12800400 0 0x400>; 465 /* place holder */ 466 }; 467 468 ostm0: timer@12801000 { 469 reg = <0x0 0x12801000 0x0 0x400>; 470 /* place holder */ 471 }; 472 473 ostm1: timer@12801400 { 474 reg = <0x0 0x12801400 0x0 0x400>; 475 /* place holder */ 476 }; 477 478 ostm2: timer@12801800 { 479 reg = <0x0 0x12801800 0x0 0x400>; 480 /* place holder */ 481 }; 482 }; 483 484 timer { 485 compatible = "arm,armv8-timer"; 486 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 487 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 488 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 489 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 490 }; 491}; 492