1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g044-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g044"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio_clk1 { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio_clk2 { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 psci { 46 compatible = "arm,psci-1.0", "arm,psci-0.2"; 47 method = "smc"; 48 }; 49 50 cpus { 51 #address-cells = <1>; 52 #size-cells = <0>; 53 54 cpu-map { 55 cluster0 { 56 core0 { 57 cpu = <&cpu0>; 58 }; 59 core1 { 60 cpu = <&cpu1>; 61 }; 62 }; 63 }; 64 65 cpu0: cpu@0 { 66 compatible = "arm,cortex-a55"; 67 reg = <0>; 68 device_type = "cpu"; 69 next-level-cache = <&L3_CA55>; 70 enable-method = "psci"; 71 }; 72 73 cpu1: cpu@100 { 74 compatible = "arm,cortex-a55"; 75 reg = <0x100>; 76 device_type = "cpu"; 77 next-level-cache = <&L3_CA55>; 78 enable-method = "psci"; 79 }; 80 81 L3_CA55: cache-controller-0 { 82 compatible = "cache"; 83 cache-unified; 84 cache-size = <0x40000>; 85 }; 86 }; 87 88 soc: soc { 89 compatible = "simple-bus"; 90 interrupt-parent = <&gic>; 91 #address-cells = <2>; 92 #size-cells = <2>; 93 ranges; 94 95 ssi0: ssi@10049c00 { 96 compatible = "renesas,r9a07g044-ssi", 97 "renesas,rz-ssi"; 98 reg = <0 0x10049c00 0 0x400>; 99 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 101 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 102 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; 103 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 104 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, 105 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, 106 <&audio_clk1>, <&audio_clk2>; 107 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 108 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>; 109 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 110 dma-names = "tx", "rx"; 111 power-domains = <&cpg>; 112 #sound-dai-cells = <0>; 113 status = "disabled"; 114 }; 115 116 ssi1: ssi@1004a000 { 117 compatible = "renesas,r9a07g044-ssi", 118 "renesas,rz-ssi"; 119 reg = <0 0x1004a000 0 0x400>; 120 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 122 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, 123 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; 124 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 125 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>, 126 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>, 127 <&audio_clk1>, <&audio_clk2>; 128 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 129 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>; 130 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 131 dma-names = "tx", "rx"; 132 power-domains = <&cpg>; 133 #sound-dai-cells = <0>; 134 status = "disabled"; 135 }; 136 137 ssi2: ssi@1004a400 { 138 compatible = "renesas,r9a07g044-ssi", 139 "renesas,rz-ssi"; 140 reg = <0 0x1004a400 0 0x400>; 141 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, 143 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, 144 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 145 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 146 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>, 147 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>, 148 <&audio_clk1>, <&audio_clk2>; 149 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 150 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>; 151 dmas = <&dmac 0x265f>; 152 dma-names = "rt"; 153 power-domains = <&cpg>; 154 #sound-dai-cells = <0>; 155 status = "disabled"; 156 }; 157 158 ssi3: ssi@1004a800 { 159 compatible = "renesas,r9a07g044-ssi", 160 "renesas,rz-ssi"; 161 reg = <0 0x1004a800 0 0x400>; 162 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 164 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, 165 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; 166 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 167 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>, 168 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>, 169 <&audio_clk1>, <&audio_clk2>; 170 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 171 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>; 172 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 173 dma-names = "tx", "rx"; 174 power-domains = <&cpg>; 175 #sound-dai-cells = <0>; 176 status = "disabled"; 177 }; 178 179 scif0: serial@1004b800 { 180 compatible = "renesas,scif-r9a07g044"; 181 reg = <0 0x1004b800 0 0x400>; 182 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 188 interrupt-names = "eri", "rxi", "txi", 189 "bri", "dri", "tei"; 190 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; 191 clock-names = "fck"; 192 power-domains = <&cpg>; 193 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; 194 status = "disabled"; 195 }; 196 197 canfd: can@10050000 { 198 compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; 199 reg = <0 0x10050000 0 0x8000>; 200 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 208 interrupt-names = "g_err", "g_recc", 209 "ch0_err", "ch0_rec", "ch0_trx", 210 "ch1_err", "ch1_rec", "ch1_trx"; 211 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>, 212 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>, 213 <&can_clk>; 214 clock-names = "fck", "canfd", "can_clk"; 215 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>; 216 assigned-clock-rates = <50000000>; 217 resets = <&cpg R9A07G044_CANFD_RSTP_N>, 218 <&cpg R9A07G044_CANFD_RSTC_N>; 219 reset-names = "rstp_n", "rstc_n"; 220 power-domains = <&cpg>; 221 status = "disabled"; 222 223 channel0 { 224 status = "disabled"; 225 }; 226 channel1 { 227 status = "disabled"; 228 }; 229 }; 230 231 i2c0: i2c@10058000 { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 235 reg = <0 0x10058000 0 0x400>; 236 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 238 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 239 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 244 interrupt-names = "tei", "ri", "ti", "spi", "sti", 245 "naki", "ali", "tmoi"; 246 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>; 247 clock-frequency = <100000>; 248 resets = <&cpg R9A07G044_I2C0_MRST>; 249 power-domains = <&cpg>; 250 status = "disabled"; 251 }; 252 253 i2c1: i2c@10058400 { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 257 reg = <0 0x10058400 0 0x400>; 258 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 260 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 261 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 266 interrupt-names = "tei", "ri", "ti", "spi", "sti", 267 "naki", "ali", "tmoi"; 268 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>; 269 clock-frequency = <100000>; 270 resets = <&cpg R9A07G044_I2C1_MRST>; 271 power-domains = <&cpg>; 272 status = "disabled"; 273 }; 274 275 i2c2: i2c@10058800 { 276 #address-cells = <1>; 277 #size-cells = <0>; 278 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 279 reg = <0 0x10058800 0 0x400>; 280 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 282 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 283 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 288 interrupt-names = "tei", "ri", "ti", "spi", "sti", 289 "naki", "ali", "tmoi"; 290 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>; 291 clock-frequency = <100000>; 292 resets = <&cpg R9A07G044_I2C2_MRST>; 293 power-domains = <&cpg>; 294 status = "disabled"; 295 }; 296 297 i2c3: i2c@10058c00 { 298 #address-cells = <1>; 299 #size-cells = <0>; 300 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 301 reg = <0 0x10058c00 0 0x400>; 302 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 304 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 305 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 310 interrupt-names = "tei", "ri", "ti", "spi", "sti", 311 "naki", "ali", "tmoi"; 312 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>; 313 clock-frequency = <100000>; 314 resets = <&cpg R9A07G044_I2C3_MRST>; 315 power-domains = <&cpg>; 316 status = "disabled"; 317 }; 318 319 adc: adc@10059000 { 320 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc"; 321 reg = <0 0x10059000 0 0x400>; 322 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; 323 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>, 324 <&cpg CPG_MOD R9A07G044_ADC_PCLK>; 325 clock-names = "adclk", "pclk"; 326 resets = <&cpg R9A07G044_ADC_PRESETN>, 327 <&cpg R9A07G044_ADC_ADRST_N>; 328 reset-names = "presetn", "adrst-n"; 329 power-domains = <&cpg>; 330 status = "disabled"; 331 332 #address-cells = <1>; 333 #size-cells = <0>; 334 335 channel@0 { 336 reg = <0>; 337 }; 338 channel@1 { 339 reg = <1>; 340 }; 341 channel@2 { 342 reg = <2>; 343 }; 344 channel@3 { 345 reg = <3>; 346 }; 347 channel@4 { 348 reg = <4>; 349 }; 350 channel@5 { 351 reg = <5>; 352 }; 353 channel@6 { 354 reg = <6>; 355 }; 356 channel@7 { 357 reg = <7>; 358 }; 359 }; 360 361 sbc: spi@10060000 { 362 compatible = "renesas,r9a07g044-rpc-if", 363 "renesas,rzg2l-rpc-if"; 364 reg = <0 0x10060000 0 0x10000>, 365 <0 0x20000000 0 0x10000000>, 366 <0 0x10070000 0 0x10000>; 367 reg-names = "regs", "dirmap", "wbuf"; 368 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>, 370 <&cpg CPG_MOD R9A07G044_SPI_CLK>; 371 resets = <&cpg R9A07G044_SPI_RST>; 372 power-domains = <&cpg>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 status = "disabled"; 376 }; 377 378 cpg: clock-controller@11010000 { 379 compatible = "renesas,r9a07g044-cpg"; 380 reg = <0 0x11010000 0 0x10000>; 381 clocks = <&extal_clk>; 382 clock-names = "extal"; 383 #clock-cells = <2>; 384 #reset-cells = <1>; 385 #power-domain-cells = <0>; 386 }; 387 388 sysc: system-controller@11020000 { 389 compatible = "renesas,r9a07g044-sysc"; 390 reg = <0 0x11020000 0 0x10000>; 391 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 395 interrupt-names = "lpm_int", "ca55stbydone_int", 396 "cm33stbyr_int", "ca55_deny"; 397 status = "disabled"; 398 }; 399 400 pinctrl: pin-controller@11030000 { 401 compatible = "renesas,r9a07g044-pinctrl"; 402 reg = <0 0x11030000 0 0x10000>; 403 gpio-controller; 404 #gpio-cells = <2>; 405 gpio-ranges = <&pinctrl 0 0 392>; 406 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; 407 power-domains = <&cpg>; 408 resets = <&cpg R9A07G044_GPIO_RSTN>, 409 <&cpg R9A07G044_GPIO_PORT_RESETN>, 410 <&cpg R9A07G044_GPIO_SPARE_RESETN>; 411 }; 412 413 dmac: dma-controller@11820000 { 414 compatible = "renesas,r9a07g044-dmac", 415 "renesas,rz-dmac"; 416 reg = <0 0x11820000 0 0x10000>, 417 <0 0x11830000 0 0x10000>; 418 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 422 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 423 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 424 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 425 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 426 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 427 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 428 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 429 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 430 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 431 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 432 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 433 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 434 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 435 interrupt-names = "error", 436 "ch0", "ch1", "ch2", "ch3", 437 "ch4", "ch5", "ch6", "ch7", 438 "ch8", "ch9", "ch10", "ch11", 439 "ch12", "ch13", "ch14", "ch15"; 440 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, 441 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; 442 power-domains = <&cpg>; 443 resets = <&cpg R9A07G044_DMAC_ARESETN>, 444 <&cpg R9A07G044_DMAC_RST_ASYNC>; 445 #dma-cells = <1>; 446 dma-channels = <16>; 447 }; 448 449 gic: interrupt-controller@11900000 { 450 compatible = "arm,gic-v3"; 451 #interrupt-cells = <3>; 452 #address-cells = <0>; 453 interrupt-controller; 454 reg = <0x0 0x11900000 0 0x40000>, 455 <0x0 0x11940000 0 0x60000>; 456 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 457 }; 458 459 sdhi0: mmc@11c00000 { 460 compatible = "renesas,sdhi-r9a07g044", 461 "renesas,rcar-gen3-sdhi"; 462 reg = <0x0 0x11c00000 0 0x10000>; 463 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>, 466 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, 467 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>, 468 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; 469 clock-names = "imclk", "imclk2", "clk_hs", "aclk"; 470 resets = <&cpg R9A07G044_SDHI0_IXRST>; 471 power-domains = <&cpg>; 472 status = "disabled"; 473 }; 474 475 sdhi1: mmc@11c10000 { 476 compatible = "renesas,sdhi-r9a07g044", 477 "renesas,rcar-gen3-sdhi"; 478 reg = <0x0 0x11c10000 0 0x10000>; 479 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>, 482 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, 483 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>, 484 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; 485 clock-names = "imclk", "imclk2", "clk_hs", "aclk"; 486 resets = <&cpg R9A07G044_SDHI1_IXRST>; 487 power-domains = <&cpg>; 488 status = "disabled"; 489 }; 490 491 eth0: ethernet@11c20000 { 492 compatible = "renesas,r9a07g044-gbeth", 493 "renesas,rzg2l-gbeth"; 494 reg = <0 0x11c20000 0 0x10000>; 495 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 498 interrupt-names = "mux", "fil", "arp_ns"; 499 phy-mode = "rgmii"; 500 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>, 501 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>, 502 <&cpg CPG_CORE R9A07G044_CLK_HP>; 503 clock-names = "axi", "chi", "refclk"; 504 resets = <&cpg R9A07G044_ETH0_RST_HW_N>; 505 power-domains = <&cpg>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 status = "disabled"; 509 }; 510 511 eth1: ethernet@11c30000 { 512 compatible = "renesas,r9a07g044-gbeth", 513 "renesas,rzg2l-gbeth"; 514 reg = <0 0x11c30000 0 0x10000>; 515 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 518 interrupt-names = "mux", "fil", "arp_ns"; 519 phy-mode = "rgmii"; 520 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>, 521 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>, 522 <&cpg CPG_CORE R9A07G044_CLK_HP>; 523 clock-names = "axi", "chi", "refclk"; 524 resets = <&cpg R9A07G044_ETH1_RST_HW_N>; 525 power-domains = <&cpg>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 status = "disabled"; 529 }; 530 531 phyrst: usbphy-ctrl@11c40000 { 532 compatible = "renesas,r9a07g044-usbphy-ctrl", 533 "renesas,rzg2l-usbphy-ctrl"; 534 reg = <0 0x11c40000 0 0x10000>; 535 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; 536 resets = <&cpg R9A07G044_USB_PRESETN>; 537 power-domains = <&cpg>; 538 #reset-cells = <1>; 539 status = "disabled"; 540 }; 541 542 ohci0: usb@11c50000 { 543 compatible = "generic-ohci"; 544 reg = <0 0x11c50000 0 0x100>; 545 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 547 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 548 resets = <&phyrst 0>, 549 <&cpg R9A07G044_USB_U2H0_HRESETN>; 550 phys = <&usb2_phy0 1>; 551 phy-names = "usb"; 552 power-domains = <&cpg>; 553 status = "disabled"; 554 }; 555 556 ohci1: usb@11c70000 { 557 compatible = "generic-ohci"; 558 reg = <0 0x11c70000 0 0x100>; 559 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 561 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 562 resets = <&phyrst 1>, 563 <&cpg R9A07G044_USB_U2H1_HRESETN>; 564 phys = <&usb2_phy1 1>; 565 phy-names = "usb"; 566 power-domains = <&cpg>; 567 status = "disabled"; 568 }; 569 570 ehci0: usb@11c50100 { 571 compatible = "generic-ehci"; 572 reg = <0 0x11c50100 0 0x100>; 573 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 575 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 576 resets = <&phyrst 0>, 577 <&cpg R9A07G044_USB_U2H0_HRESETN>; 578 phys = <&usb2_phy0 2>; 579 phy-names = "usb"; 580 companion = <&ohci0>; 581 power-domains = <&cpg>; 582 status = "disabled"; 583 }; 584 585 ehci1: usb@11c70100 { 586 compatible = "generic-ehci"; 587 reg = <0 0x11c70100 0 0x100>; 588 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 590 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 591 resets = <&phyrst 1>, 592 <&cpg R9A07G044_USB_U2H1_HRESETN>; 593 phys = <&usb2_phy1 2>; 594 phy-names = "usb"; 595 companion = <&ohci1>; 596 power-domains = <&cpg>; 597 status = "disabled"; 598 }; 599 600 usb2_phy0: usb-phy@11c50200 { 601 compatible = "renesas,usb2-phy-r9a07g044", 602 "renesas,rzg2l-usb2-phy"; 603 reg = <0 0x11c50200 0 0x700>; 604 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 606 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 607 resets = <&phyrst 0>; 608 #phy-cells = <1>; 609 power-domains = <&cpg>; 610 status = "disabled"; 611 }; 612 613 usb2_phy1: usb-phy@11c70200 { 614 compatible = "renesas,usb2-phy-r9a07g044", 615 "renesas,rzg2l-usb2-phy"; 616 reg = <0 0x11c70200 0 0x700>; 617 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 619 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 620 resets = <&phyrst 1>; 621 #phy-cells = <1>; 622 power-domains = <&cpg>; 623 status = "disabled"; 624 }; 625 626 hsusb: usb@11c60000 { 627 compatible = "renesas,usbhs-r9a07g044", 628 "renesas,rza2-usbhs"; 629 reg = <0 0x11c60000 0 0x10000>; 630 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 631 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 635 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>; 636 resets = <&phyrst 0>, 637 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>; 638 renesas,buswait = <7>; 639 phys = <&usb2_phy0 3>; 640 phy-names = "usb"; 641 power-domains = <&cpg>; 642 status = "disabled"; 643 }; 644 }; 645 646 timer { 647 compatible = "arm,armv8-timer"; 648 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 649 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 650 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 651 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 652 }; 653}; 654