1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/r9a07g044-cpg.h>
10
11/ {
12	compatible = "renesas,r9a07g044";
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
17	extal_clk: extal {
18		compatible = "fixed-clock";
19		#clock-cells = <0>;
20		/* This value must be overridden by the board */
21		clock-frequency = <0>;
22	};
23
24	psci {
25		compatible = "arm,psci-1.0", "arm,psci-0.2";
26		method = "smc";
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		cpu-map {
34			cluster0 {
35				core0 {
36					cpu = <&cpu0>;
37				};
38				core1 {
39					cpu = <&cpu1>;
40				};
41			};
42		};
43
44		cpu0: cpu@0 {
45			compatible = "arm,cortex-a55";
46			reg = <0>;
47			device_type = "cpu";
48			next-level-cache = <&L3_CA55>;
49			enable-method = "psci";
50		};
51
52		cpu1: cpu@100 {
53			compatible = "arm,cortex-a55";
54			reg = <0x100>;
55			device_type = "cpu";
56			next-level-cache = <&L3_CA55>;
57			enable-method = "psci";
58		};
59
60		L3_CA55: cache-controller-0 {
61			compatible = "cache";
62			cache-unified;
63			cache-size = <0x40000>;
64		};
65	};
66
67	soc: soc {
68		compatible = "simple-bus";
69		interrupt-parent = <&gic>;
70		#address-cells = <2>;
71		#size-cells = <2>;
72		ranges;
73
74		scif0: serial@1004b800 {
75			compatible = "renesas,scif-r9a07g044";
76			reg = <0 0x1004b800 0 0x400>;
77			interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
78				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
79				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
80				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
81				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
82				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
83			interrupt-names = "eri", "rxi", "txi",
84					  "bri", "dri", "tei";
85			clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
86			clock-names = "fck";
87			power-domains = <&cpg>;
88			resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
89			status = "disabled";
90		};
91
92		cpg: clock-controller@11010000 {
93			compatible = "renesas,r9a07g044-cpg";
94			reg = <0 0x11010000 0 0x10000>;
95			clocks = <&extal_clk>;
96			clock-names = "extal";
97			#clock-cells = <2>;
98			#reset-cells = <1>;
99			#power-domain-cells = <0>;
100		};
101
102		sysc: system-controller@11020000 {
103			compatible = "renesas,r9a07g044-sysc";
104			reg = <0 0x11020000 0 0x10000>;
105			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
106				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
107				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
108				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
109			interrupt-names = "lpm_int", "ca55stbydone_int",
110					  "cm33stbyr_int", "ca55_deny";
111			status = "disabled";
112		};
113
114		gic: interrupt-controller@11900000 {
115			compatible = "arm,gic-v3";
116			#interrupt-cells = <3>;
117			#address-cells = <0>;
118			interrupt-controller;
119			reg = <0x0 0x11900000 0 0x40000>,
120			      <0x0 0x11940000 0 0x60000>;
121			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
122		};
123	};
124
125	timer {
126		compatible = "arm,armv8-timer";
127		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
128				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
129				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
130				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
131	};
132};
133