1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/r9a07g044-cpg.h>
10
11/ {
12	compatible = "renesas,r9a07g044";
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	/* External CAN clock - to be overridden by boards that provide it */
17	can_clk: can {
18		compatible = "fixed-clock";
19		#clock-cells = <0>;
20		clock-frequency = <0>;
21	};
22
23	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
24	extal_clk: extal {
25		compatible = "fixed-clock";
26		#clock-cells = <0>;
27		/* This value must be overridden by the board */
28		clock-frequency = <0>;
29	};
30
31	psci {
32		compatible = "arm,psci-1.0", "arm,psci-0.2";
33		method = "smc";
34	};
35
36	cpus {
37		#address-cells = <1>;
38		#size-cells = <0>;
39
40		cpu-map {
41			cluster0 {
42				core0 {
43					cpu = <&cpu0>;
44				};
45				core1 {
46					cpu = <&cpu1>;
47				};
48			};
49		};
50
51		cpu0: cpu@0 {
52			compatible = "arm,cortex-a55";
53			reg = <0>;
54			device_type = "cpu";
55			next-level-cache = <&L3_CA55>;
56			enable-method = "psci";
57		};
58
59		cpu1: cpu@100 {
60			compatible = "arm,cortex-a55";
61			reg = <0x100>;
62			device_type = "cpu";
63			next-level-cache = <&L3_CA55>;
64			enable-method = "psci";
65		};
66
67		L3_CA55: cache-controller-0 {
68			compatible = "cache";
69			cache-unified;
70			cache-size = <0x40000>;
71		};
72	};
73
74	soc: soc {
75		compatible = "simple-bus";
76		interrupt-parent = <&gic>;
77		#address-cells = <2>;
78		#size-cells = <2>;
79		ranges;
80
81		scif0: serial@1004b800 {
82			compatible = "renesas,scif-r9a07g044";
83			reg = <0 0x1004b800 0 0x400>;
84			interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
85				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
86				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
87				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
88				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
89				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
90			interrupt-names = "eri", "rxi", "txi",
91					  "bri", "dri", "tei";
92			clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
93			clock-names = "fck";
94			power-domains = <&cpg>;
95			resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
96			status = "disabled";
97		};
98
99		canfd: can@10050000 {
100			compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
101			reg = <0 0x10050000 0 0x8000>;
102			interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
103				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
104				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
105				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
106				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
107				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
108				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
109				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
110			interrupt-names = "g_err", "g_recc",
111					  "ch0_err", "ch0_rec", "ch0_trx",
112					  "ch1_err", "ch1_rec", "ch1_trx";
113			clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
114				 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
115				 <&can_clk>;
116			clock-names = "fck", "canfd", "can_clk";
117			assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
118			assigned-clock-rates = <50000000>;
119			resets = <&cpg R9A07G044_CANFD_RSTP_N>,
120				 <&cpg R9A07G044_CANFD_RSTC_N>;
121			reset-names = "rstp_n", "rstc_n";
122			power-domains = <&cpg>;
123			status = "disabled";
124
125			channel0 {
126				status = "disabled";
127			};
128			channel1 {
129				status = "disabled";
130			};
131		};
132
133		i2c0: i2c@10058000 {
134			#address-cells = <1>;
135			#size-cells = <0>;
136			compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
137			reg = <0 0x10058000 0 0x400>;
138			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
139				     <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
140				     <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
141				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
142				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
143				     <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
144				     <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
145				     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
146			interrupt-names = "tei", "ri", "ti", "spi", "sti",
147					  "naki", "ali", "tmoi";
148			clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
149			clock-frequency = <100000>;
150			resets = <&cpg R9A07G044_I2C0_MRST>;
151			power-domains = <&cpg>;
152			status = "disabled";
153		};
154
155		i2c1: i2c@10058400 {
156			#address-cells = <1>;
157			#size-cells = <0>;
158			compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
159			reg = <0 0x10058400 0 0x400>;
160			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
161				     <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
162				     <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
163				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
164				     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
165				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
166				     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
167				     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
168			interrupt-names = "tei", "ri", "ti", "spi", "sti",
169					  "naki", "ali", "tmoi";
170			clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
171			clock-frequency = <100000>;
172			resets = <&cpg R9A07G044_I2C1_MRST>;
173			power-domains = <&cpg>;
174			status = "disabled";
175		};
176
177		i2c2: i2c@10058800 {
178			#address-cells = <1>;
179			#size-cells = <0>;
180			compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
181			reg = <0 0x10058800 0 0x400>;
182			interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
183				     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
184				     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
185				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
186				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
187				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
188				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
189				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
190			interrupt-names = "tei", "ri", "ti", "spi", "sti",
191					  "naki", "ali", "tmoi";
192			clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
193			clock-frequency = <100000>;
194			resets = <&cpg R9A07G044_I2C2_MRST>;
195			power-domains = <&cpg>;
196			status = "disabled";
197		};
198
199		i2c3: i2c@10058c00 {
200			#address-cells = <1>;
201			#size-cells = <0>;
202			compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
203			reg = <0 0x10058c00 0 0x400>;
204			interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
205				     <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
206				     <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
207				     <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
208				     <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
209				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
210				     <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
211				     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
212			interrupt-names = "tei", "ri", "ti", "spi", "sti",
213					  "naki", "ali", "tmoi";
214			clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
215			clock-frequency = <100000>;
216			resets = <&cpg R9A07G044_I2C3_MRST>;
217			power-domains = <&cpg>;
218			status = "disabled";
219		};
220
221		adc: adc@10059000 {
222			compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
223			reg = <0 0x10059000 0 0x400>;
224			interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
225			clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
226				 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
227			clock-names = "adclk", "pclk";
228			resets = <&cpg R9A07G044_ADC_PRESETN>,
229				 <&cpg R9A07G044_ADC_ADRST_N>;
230			reset-names = "presetn", "adrst-n";
231			power-domains = <&cpg>;
232			status = "disabled";
233
234			#address-cells = <1>;
235			#size-cells = <0>;
236
237			channel@0 {
238				reg = <0>;
239			};
240			channel@1 {
241				reg = <1>;
242			};
243			channel@2 {
244				reg = <2>;
245			};
246			channel@3 {
247				reg = <3>;
248			};
249			channel@4 {
250				reg = <4>;
251			};
252			channel@5 {
253				reg = <5>;
254			};
255			channel@6 {
256				reg = <6>;
257			};
258			channel@7 {
259				reg = <7>;
260			};
261		};
262
263		cpg: clock-controller@11010000 {
264			compatible = "renesas,r9a07g044-cpg";
265			reg = <0 0x11010000 0 0x10000>;
266			clocks = <&extal_clk>;
267			clock-names = "extal";
268			#clock-cells = <2>;
269			#reset-cells = <1>;
270			#power-domain-cells = <0>;
271		};
272
273		sysc: system-controller@11020000 {
274			compatible = "renesas,r9a07g044-sysc";
275			reg = <0 0x11020000 0 0x10000>;
276			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
277				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
278				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
279				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
280			interrupt-names = "lpm_int", "ca55stbydone_int",
281					  "cm33stbyr_int", "ca55_deny";
282			status = "disabled";
283		};
284
285		pinctrl: pin-controller@11030000 {
286			compatible = "renesas,r9a07g044-pinctrl";
287			reg = <0 0x11030000 0 0x10000>;
288			gpio-controller;
289			#gpio-cells = <2>;
290			gpio-ranges = <&pinctrl 0 0 392>;
291			clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
292			power-domains = <&cpg>;
293			resets = <&cpg R9A07G044_GPIO_RSTN>,
294				 <&cpg R9A07G044_GPIO_PORT_RESETN>,
295				 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
296		};
297
298		gic: interrupt-controller@11900000 {
299			compatible = "arm,gic-v3";
300			#interrupt-cells = <3>;
301			#address-cells = <0>;
302			interrupt-controller;
303			reg = <0x0 0x11900000 0 0x40000>,
304			      <0x0 0x11940000 0 0x60000>;
305			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
306		};
307	};
308
309	timer {
310		compatible = "arm,armv8-timer";
311		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
312				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
313				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
314				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
315	};
316};
317