1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2UL SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr 11 12#include "r9a07g043.dtsi" 13 14/ { 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a55"; 21 reg = <0>; 22 device_type = "cpu"; 23 #cooling-cells = <2>; 24 next-level-cache = <&L3_CA55>; 25 enable-method = "psci"; 26 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 27 operating-points-v2 = <&cluster0_opp>; 28 }; 29 30 L3_CA55: cache-controller-0 { 31 compatible = "cache"; 32 cache-unified; 33 cache-size = <0x40000>; 34 cache-level = <3>; 35 }; 36 }; 37 38 pmu { 39 compatible = "arm,cortex-a55-pmu"; 40 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 41 }; 42 43 psci { 44 compatible = "arm,psci-1.0", "arm,psci-0.2"; 45 method = "smc"; 46 }; 47 48 timer { 49 compatible = "arm,armv8-timer"; 50 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 51 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 52 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 53 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 54 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 55 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 56 "hyp-virt"; 57 }; 58}; 59 60&pinctrl { 61 interrupt-parent = <&irqc>; 62}; 63 64&soc { 65 interrupt-parent = <&gic>; 66 67 irqc: interrupt-controller@110a0000 { 68 compatible = "renesas,r9a07g043u-irqc", 69 "renesas,rzg2l-irqc"; 70 reg = <0 0x110a0000 0 0x10000>; 71 #interrupt-cells = <2>; 72 #address-cells = <0>; 73 interrupt-controller; 74 interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>, 75 <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>, 76 <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>, 77 <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>, 78 <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>, 79 <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>, 80 <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>, 81 <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>, 82 <SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>, 83 <SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>, 84 <SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>, 85 <SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>, 86 <SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>, 87 <SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>, 88 <SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>, 89 <SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>, 90 <SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>, 91 <SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>, 92 <SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>, 93 <SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>, 94 <SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>, 95 <SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>, 96 <SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>, 97 <SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>, 98 <SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>, 99 <SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>, 100 <SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>, 101 <SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>, 102 <SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>, 103 <SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>, 104 <SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>, 105 <SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>, 106 <SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>, 107 <SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>, 108 <SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>, 109 <SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>, 110 <SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>, 111 <SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>, 112 <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>, 113 <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>, 114 <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>, 115 <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>, 116 <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>, 117 <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>, 118 <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>, 119 <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>, 120 <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>, 121 <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>; 122 interrupt-names = "nmi", 123 "irq0", "irq1", "irq2", "irq3", 124 "irq4", "irq5", "irq6", "irq7", 125 "tint0", "tint1", "tint2", "tint3", 126 "tint4", "tint5", "tint6", "tint7", 127 "tint8", "tint9", "tint10", "tint11", 128 "tint12", "tint13", "tint14", "tint15", 129 "tint16", "tint17", "tint18", "tint19", 130 "tint20", "tint21", "tint22", "tint23", 131 "tint24", "tint25", "tint26", "tint27", 132 "tint28", "tint29", "tint30", "tint31", 133 "bus-err", "ec7tie1-0", "ec7tie2-0", 134 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", 135 "ec7tiovf-1"; 136 clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>, 137 <&cpg CPG_MOD R9A07G043_IA55_PCLK>; 138 clock-names = "clk", "pclk"; 139 power-domains = <&cpg>; 140 resets = <&cpg R9A07G043_IA55_RESETN>; 141 }; 142 143 gic: interrupt-controller@11900000 { 144 compatible = "arm,gic-v3"; 145 #interrupt-cells = <3>; 146 #address-cells = <0>; 147 interrupt-controller; 148 reg = <0x0 0x11900000 0 0x20000>, 149 <0x0 0x11940000 0 0x40000>; 150 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 151 }; 152}; 153 154&sysc { 155 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>, 156 <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>, 157 <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>, 158 <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>; 159 interrupt-names = "lpm_int", "ca55stbydone_int", 160 "cm33stbyr_int", "ca55_deny"; 161}; 162