1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the R-Car V4H (R8A779G0) SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779g0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779g0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779g0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cluster0_opp: opp-table-0 { 18 compatible = "operating-points-v2"; 19 opp-shared; 20 21 opp-500000000 { 22 opp-hz = /bits/ 64 <500000000>; 23 opp-microvolt = <825000>; 24 clock-latency-ns = <500000>; 25 }; 26 opp-1000000000 { 27 opp-hz = /bits/ 64 <1000000000>; 28 opp-microvolt = <825000>; 29 clock-latency-ns = <500000>; 30 }; 31 opp-1500000000 { 32 opp-hz = /bits/ 64 <1500000000>; 33 opp-microvolt = <825000>; 34 clock-latency-ns = <500000>; 35 }; 36 opp-1700000000 { 37 opp-hz = /bits/ 64 <1700000000>; 38 opp-microvolt = <825000>; 39 clock-latency-ns = <500000>; 40 opp-suspend; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu-map { 49 cluster0 { 50 core0 { 51 cpu = <&a76_0>; 52 }; 53 core1 { 54 cpu = <&a76_1>; 55 }; 56 }; 57 58 cluster1 { 59 core0 { 60 cpu = <&a76_2>; 61 }; 62 core1 { 63 cpu = <&a76_3>; 64 }; 65 }; 66 }; 67 68 a76_0: cpu@0 { 69 compatible = "arm,cortex-a76"; 70 reg = <0>; 71 device_type = "cpu"; 72 power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; 73 next-level-cache = <&L3_CA76_0>; 74 enable-method = "psci"; 75 cpu-idle-states = <&CPU_SLEEP_0>; 76 clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; 77 operating-points-v2 = <&cluster0_opp>; 78 }; 79 80 a76_1: cpu@100 { 81 compatible = "arm,cortex-a76"; 82 reg = <0x100>; 83 device_type = "cpu"; 84 power-domains = <&sysc R8A779G0_PD_A1E0D0C1>; 85 next-level-cache = <&L3_CA76_0>; 86 enable-method = "psci"; 87 cpu-idle-states = <&CPU_SLEEP_0>; 88 clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; 89 operating-points-v2 = <&cluster0_opp>; 90 }; 91 92 a76_2: cpu@10000 { 93 compatible = "arm,cortex-a76"; 94 reg = <0x10000>; 95 device_type = "cpu"; 96 power-domains = <&sysc R8A779G0_PD_A1E0D1C0>; 97 next-level-cache = <&L3_CA76_1>; 98 enable-method = "psci"; 99 cpu-idle-states = <&CPU_SLEEP_0>; 100 clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; 101 operating-points-v2 = <&cluster0_opp>; 102 }; 103 104 a76_3: cpu@10100 { 105 compatible = "arm,cortex-a76"; 106 reg = <0x10100>; 107 device_type = "cpu"; 108 power-domains = <&sysc R8A779G0_PD_A1E0D1C1>; 109 next-level-cache = <&L3_CA76_1>; 110 enable-method = "psci"; 111 cpu-idle-states = <&CPU_SLEEP_0>; 112 clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; 113 operating-points-v2 = <&cluster0_opp>; 114 }; 115 116 idle-states { 117 entry-method = "psci"; 118 119 CPU_SLEEP_0: cpu-sleep-0 { 120 compatible = "arm,idle-state"; 121 arm,psci-suspend-param = <0x0010000>; 122 local-timer-stop; 123 entry-latency-us = <400>; 124 exit-latency-us = <500>; 125 min-residency-us = <4000>; 126 }; 127 }; 128 129 L3_CA76_0: cache-controller-0 { 130 compatible = "cache"; 131 power-domains = <&sysc R8A779G0_PD_A2E0D0>; 132 cache-unified; 133 cache-level = <3>; 134 }; 135 136 L3_CA76_1: cache-controller-1 { 137 compatible = "cache"; 138 power-domains = <&sysc R8A779G0_PD_A2E0D1>; 139 cache-unified; 140 cache-level = <3>; 141 }; 142 }; 143 144 psci { 145 compatible = "arm,psci-1.0", "arm,psci-0.2"; 146 method = "smc"; 147 }; 148 149 extal_clk: extal { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 /* This value must be overridden by the board */ 153 clock-frequency = <0>; 154 }; 155 156 extalr_clk: extalr { 157 compatible = "fixed-clock"; 158 #clock-cells = <0>; 159 /* This value must be overridden by the board */ 160 clock-frequency = <0>; 161 }; 162 163 pmu_a76 { 164 compatible = "arm,cortex-a76-pmu"; 165 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 166 }; 167 168 /* External SCIF clock - to be overridden by boards that provide it */ 169 scif_clk: scif { 170 compatible = "fixed-clock"; 171 #clock-cells = <0>; 172 clock-frequency = <0>; 173 }; 174 175 soc: soc { 176 compatible = "simple-bus"; 177 interrupt-parent = <&gic>; 178 #address-cells = <2>; 179 #size-cells = <2>; 180 ranges; 181 182 rwdt: watchdog@e6020000 { 183 compatible = "renesas,r8a779g0-wdt", 184 "renesas,rcar-gen4-wdt"; 185 reg = <0 0xe6020000 0 0x0c>; 186 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&cpg CPG_MOD 907>; 188 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 189 resets = <&cpg 907>; 190 status = "disabled"; 191 }; 192 193 pfc: pinctrl@e6050000 { 194 compatible = "renesas,pfc-r8a779g0"; 195 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 196 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, 197 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, 198 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, 199 <0 0xe6068000 0 0x16c>; 200 }; 201 202 gpio0: gpio@e6050180 { 203 compatible = "renesas,gpio-r8a779g0", 204 "renesas,rcar-gen4-gpio"; 205 reg = <0 0xe6050180 0 0x54>; 206 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&cpg CPG_MOD 915>; 208 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 209 resets = <&cpg 915>; 210 gpio-controller; 211 #gpio-cells = <2>; 212 gpio-ranges = <&pfc 0 0 19>; 213 interrupt-controller; 214 #interrupt-cells = <2>; 215 }; 216 217 gpio1: gpio@e6050980 { 218 compatible = "renesas,gpio-r8a779g0", 219 "renesas,rcar-gen4-gpio"; 220 reg = <0 0xe6050980 0 0x54>; 221 interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&cpg CPG_MOD 915>; 223 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 224 resets = <&cpg 915>; 225 gpio-controller; 226 #gpio-cells = <2>; 227 gpio-ranges = <&pfc 0 32 29>; 228 interrupt-controller; 229 #interrupt-cells = <2>; 230 }; 231 232 gpio2: gpio@e6058180 { 233 compatible = "renesas,gpio-r8a779g0", 234 "renesas,rcar-gen4-gpio"; 235 reg = <0 0xe6058180 0 0x54>; 236 interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&cpg CPG_MOD 916>; 238 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 239 resets = <&cpg 916>; 240 gpio-controller; 241 #gpio-cells = <2>; 242 gpio-ranges = <&pfc 0 64 20>; 243 interrupt-controller; 244 #interrupt-cells = <2>; 245 }; 246 247 gpio3: gpio@e6058980 { 248 compatible = "renesas,gpio-r8a779g0", 249 "renesas,rcar-gen4-gpio"; 250 reg = <0 0xe6058980 0 0x54>; 251 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&cpg CPG_MOD 916>; 253 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 254 resets = <&cpg 916>; 255 gpio-controller; 256 #gpio-cells = <2>; 257 gpio-ranges = <&pfc 0 96 30>; 258 interrupt-controller; 259 #interrupt-cells = <2>; 260 }; 261 262 gpio4: gpio@e6060180 { 263 compatible = "renesas,gpio-r8a779g0", 264 "renesas,rcar-gen4-gpio"; 265 reg = <0 0xe6060180 0 0x54>; 266 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cpg CPG_MOD 917>; 268 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 269 resets = <&cpg 917>; 270 gpio-controller; 271 #gpio-cells = <2>; 272 gpio-ranges = <&pfc 0 128 25>; 273 interrupt-controller; 274 #interrupt-cells = <2>; 275 }; 276 277 gpio5: gpio@e6060980 { 278 compatible = "renesas,gpio-r8a779g0", 279 "renesas,rcar-gen4-gpio"; 280 reg = <0 0xe6060980 0 0x54>; 281 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&cpg CPG_MOD 917>; 283 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 284 resets = <&cpg 917>; 285 gpio-controller; 286 #gpio-cells = <2>; 287 gpio-ranges = <&pfc 0 160 21>; 288 interrupt-controller; 289 #interrupt-cells = <2>; 290 }; 291 292 gpio6: gpio@e6061180 { 293 compatible = "renesas,gpio-r8a779g0", 294 "renesas,rcar-gen4-gpio"; 295 reg = <0 0xe6061180 0 0x54>; 296 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cpg CPG_MOD 917>; 298 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 299 resets = <&cpg 917>; 300 gpio-controller; 301 #gpio-cells = <2>; 302 gpio-ranges = <&pfc 0 192 21>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 }; 306 307 gpio7: gpio@e6061980 { 308 compatible = "renesas,gpio-r8a779g0", 309 "renesas,rcar-gen4-gpio"; 310 reg = <0 0xe6061980 0 0x54>; 311 interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&cpg CPG_MOD 917>; 313 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 314 resets = <&cpg 917>; 315 gpio-controller; 316 #gpio-cells = <2>; 317 gpio-ranges = <&pfc 0 224 21>; 318 interrupt-controller; 319 #interrupt-cells = <2>; 320 }; 321 322 gpio8: gpio@e6068180 { 323 compatible = "renesas,gpio-r8a779g0", 324 "renesas,rcar-gen4-gpio"; 325 reg = <0 0xe6068180 0 0x54>; 326 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cpg CPG_MOD 918>; 328 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 329 resets = <&cpg 918>; 330 gpio-controller; 331 #gpio-cells = <2>; 332 gpio-ranges = <&pfc 0 256 14>; 333 interrupt-controller; 334 #interrupt-cells = <2>; 335 }; 336 337 cmt0: timer@e60f0000 { 338 compatible = "renesas,r8a779g0-cmt0", 339 "renesas,rcar-gen4-cmt0"; 340 reg = <0 0xe60f0000 0 0x1004>; 341 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cpg CPG_MOD 910>; 344 clock-names = "fck"; 345 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 346 resets = <&cpg 910>; 347 status = "disabled"; 348 }; 349 350 cmt1: timer@e6130000 { 351 compatible = "renesas,r8a779g0-cmt1", 352 "renesas,rcar-gen4-cmt1"; 353 reg = <0 0xe6130000 0 0x1004>; 354 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&cpg CPG_MOD 911>; 363 clock-names = "fck"; 364 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 365 resets = <&cpg 911>; 366 status = "disabled"; 367 }; 368 369 cmt2: timer@e6140000 { 370 compatible = "renesas,r8a779g0-cmt1", 371 "renesas,rcar-gen4-cmt1"; 372 reg = <0 0xe6140000 0 0x1004>; 373 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&cpg CPG_MOD 912>; 382 clock-names = "fck"; 383 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 384 resets = <&cpg 912>; 385 status = "disabled"; 386 }; 387 388 cmt3: timer@e6148000 { 389 compatible = "renesas,r8a779g0-cmt1", 390 "renesas,rcar-gen4-cmt1"; 391 reg = <0 0xe6148000 0 0x1004>; 392 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&cpg CPG_MOD 913>; 401 clock-names = "fck"; 402 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 403 resets = <&cpg 913>; 404 status = "disabled"; 405 }; 406 407 cpg: clock-controller@e6150000 { 408 compatible = "renesas,r8a779g0-cpg-mssr"; 409 reg = <0 0xe6150000 0 0x4000>; 410 clocks = <&extal_clk>, <&extalr_clk>; 411 clock-names = "extal", "extalr"; 412 #clock-cells = <2>; 413 #power-domain-cells = <0>; 414 #reset-cells = <1>; 415 }; 416 417 rst: reset-controller@e6160000 { 418 compatible = "renesas,r8a779g0-rst"; 419 reg = <0 0xe6160000 0 0x4000>; 420 }; 421 422 sysc: system-controller@e6180000 { 423 compatible = "renesas,r8a779g0-sysc"; 424 reg = <0 0xe6180000 0 0x4000>; 425 #power-domain-cells = <1>; 426 }; 427 428 intc_ex: interrupt-controller@e61c0000 { 429 compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc"; 430 #interrupt-cells = <2>; 431 interrupt-controller; 432 reg = <0 0xe61c0000 0 0x200>; 433 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&cpg CPG_MOD 611>; 440 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 441 resets = <&cpg 611>; 442 }; 443 444 tmu0: timer@e61e0000 { 445 compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 446 reg = <0 0xe61e0000 0 0x30>; 447 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&cpg CPG_MOD 713>; 451 clock-names = "fck"; 452 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 453 resets = <&cpg 713>; 454 status = "disabled"; 455 }; 456 457 tmu1: timer@e6fc0000 { 458 compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 459 reg = <0 0xe6fc0000 0 0x30>; 460 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&cpg CPG_MOD 714>; 464 clock-names = "fck"; 465 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 466 resets = <&cpg 714>; 467 status = "disabled"; 468 }; 469 470 tmu2: timer@e6fd0000 { 471 compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 472 reg = <0 0xe6fd0000 0 0x30>; 473 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&cpg CPG_MOD 715>; 477 clock-names = "fck"; 478 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 479 resets = <&cpg 715>; 480 status = "disabled"; 481 }; 482 483 tmu3: timer@e6fe0000 { 484 compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 485 reg = <0 0xe6fe0000 0 0x30>; 486 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&cpg CPG_MOD 716>; 490 clock-names = "fck"; 491 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 492 resets = <&cpg 716>; 493 status = "disabled"; 494 }; 495 496 tmu4: timer@ffc00000 { 497 compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 498 reg = <0 0xffc00000 0 0x30>; 499 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&cpg CPG_MOD 717>; 503 clock-names = "fck"; 504 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 505 resets = <&cpg 717>; 506 status = "disabled"; 507 }; 508 509 i2c0: i2c@e6500000 { 510 compatible = "renesas,i2c-r8a779g0", 511 "renesas,rcar-gen4-i2c"; 512 reg = <0 0xe6500000 0 0x40>; 513 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&cpg CPG_MOD 518>; 515 dmas = <&dmac0 0x91>, <&dmac0 0x90>, 516 <&dmac1 0x91>, <&dmac1 0x90>; 517 dma-names = "tx", "rx", "tx", "rx"; 518 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 519 resets = <&cpg 518>; 520 i2c-scl-internal-delay-ns = <110>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 status = "disabled"; 524 }; 525 526 i2c1: i2c@e6508000 { 527 compatible = "renesas,i2c-r8a779g0", 528 "renesas,rcar-gen4-i2c"; 529 reg = <0 0xe6508000 0 0x40>; 530 interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&cpg CPG_MOD 519>; 532 dmas = <&dmac0 0x93>, <&dmac0 0x92>, 533 <&dmac1 0x93>, <&dmac1 0x92>; 534 dma-names = "tx", "rx", "tx", "rx"; 535 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 536 resets = <&cpg 519>; 537 i2c-scl-internal-delay-ns = <110>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 status = "disabled"; 541 }; 542 543 i2c2: i2c@e6510000 { 544 compatible = "renesas,i2c-r8a779g0", 545 "renesas,rcar-gen4-i2c"; 546 reg = <0 0xe6510000 0 0x40>; 547 interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&cpg CPG_MOD 520>; 549 dmas = <&dmac0 0x95>, <&dmac0 0x94>, 550 <&dmac1 0x95>, <&dmac1 0x94>; 551 dma-names = "tx", "rx", "tx", "rx"; 552 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 553 resets = <&cpg 520>; 554 i2c-scl-internal-delay-ns = <110>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 status = "disabled"; 558 }; 559 560 i2c3: i2c@e66d0000 { 561 compatible = "renesas,i2c-r8a779g0", 562 "renesas,rcar-gen4-i2c"; 563 reg = <0 0xe66d0000 0 0x40>; 564 interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cpg CPG_MOD 521>; 566 dmas = <&dmac0 0x97>, <&dmac0 0x96>, 567 <&dmac1 0x97>, <&dmac1 0x96>; 568 dma-names = "tx", "rx", "tx", "rx"; 569 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 570 resets = <&cpg 521>; 571 i2c-scl-internal-delay-ns = <110>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 status = "disabled"; 575 }; 576 577 i2c4: i2c@e66d8000 { 578 compatible = "renesas,i2c-r8a779g0", 579 "renesas,rcar-gen4-i2c"; 580 reg = <0 0xe66d8000 0 0x40>; 581 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&cpg CPG_MOD 522>; 583 dma-names = "tx", "rx", "tx", "rx"; 584 dmas = <&dmac0 0x99>, <&dmac0 0x98>, 585 <&dmac1 0x99>, <&dmac1 0x98>; 586 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 587 resets = <&cpg 522>; 588 i2c-scl-internal-delay-ns = <110>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 status = "disabled"; 592 }; 593 594 i2c5: i2c@e66e0000 { 595 compatible = "renesas,i2c-r8a779g0", 596 "renesas,rcar-gen4-i2c"; 597 reg = <0 0xe66e0000 0 0x40>; 598 interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&cpg CPG_MOD 523>; 600 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 601 <&dmac1 0x9b>, <&dmac1 0x9a>; 602 dma-names = "tx", "rx", "tx", "rx"; 603 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 604 resets = <&cpg 523>; 605 i2c-scl-internal-delay-ns = <110>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 status = "disabled"; 609 }; 610 611 hscif0: serial@e6540000 { 612 compatible = "renesas,hscif-r8a779g0", 613 "renesas,rcar-gen4-hscif", "renesas,hscif"; 614 reg = <0 0xe6540000 0 0x60>; 615 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&cpg CPG_MOD 514>, 617 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 618 <&scif_clk>; 619 clock-names = "fck", "brg_int", "scif_clk"; 620 dmas = <&dmac0 0x31>, <&dmac0 0x30>, 621 <&dmac1 0x31>, <&dmac1 0x30>; 622 dma-names = "tx", "rx", "tx", "rx"; 623 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 624 resets = <&cpg 514>; 625 status = "disabled"; 626 }; 627 628 hscif1: serial@e6550000 { 629 compatible = "renesas,hscif-r8a779g0", 630 "renesas,rcar-gen4-hscif", "renesas,hscif"; 631 reg = <0 0xe6550000 0 0x60>; 632 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&cpg CPG_MOD 515>, 634 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 635 <&scif_clk>; 636 clock-names = "fck", "brg_int", "scif_clk"; 637 dmas = <&dmac0 0x33>, <&dmac0 0x32>, 638 <&dmac1 0x33>, <&dmac1 0x32>; 639 dma-names = "tx", "rx", "tx", "rx"; 640 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 641 resets = <&cpg 515>; 642 status = "disabled"; 643 }; 644 645 hscif2: serial@e6560000 { 646 compatible = "renesas,hscif-r8a779g0", 647 "renesas,rcar-gen4-hscif", "renesas,hscif"; 648 reg = <0 0xe6560000 0 0x60>; 649 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&cpg CPG_MOD 516>, 651 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 652 <&scif_clk>; 653 clock-names = "fck", "brg_int", "scif_clk"; 654 dmas = <&dmac0 0x35>, <&dmac0 0x34>, 655 <&dmac1 0x35>, <&dmac1 0x34>; 656 dma-names = "tx", "rx", "tx", "rx"; 657 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 658 resets = <&cpg 516>; 659 status = "disabled"; 660 }; 661 662 hscif3: serial@e66a0000 { 663 compatible = "renesas,hscif-r8a779g0", 664 "renesas,rcar-gen4-hscif", "renesas,hscif"; 665 reg = <0 0xe66a0000 0 0x60>; 666 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&cpg CPG_MOD 517>, 668 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 669 <&scif_clk>; 670 clock-names = "fck", "brg_int", "scif_clk"; 671 dmas = <&dmac0 0x37>, <&dmac0 0x36>, 672 <&dmac1 0x37>, <&dmac1 0x36>; 673 dma-names = "tx", "rx", "tx", "rx"; 674 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 675 resets = <&cpg 517>; 676 status = "disabled"; 677 }; 678 679 avb0: ethernet@e6800000 { 680 compatible = "renesas,etheravb-r8a779g0", 681 "renesas,etheravb-rcar-gen4"; 682 reg = <0 0xe6800000 0 0x800>; 683 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 708 interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", 709 "ch5", "ch6", "ch7", "ch8", "ch9", 710 "ch10", "ch11", "ch12", "ch13", 711 "ch14", "ch15", "ch16", "ch17", 712 "ch18", "ch19", "ch20", "ch21", 713 "ch22", "ch23", "ch24"; 714 clocks = <&cpg CPG_MOD 211>; 715 clock-names = "fck"; 716 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 717 resets = <&cpg 211>; 718 phy-mode = "rgmii"; 719 rx-internal-delay-ps = <0>; 720 tx-internal-delay-ps = <0>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 status = "disabled"; 724 }; 725 726 avb1: ethernet@e6810000 { 727 compatible = "renesas,etheravb-r8a779g0", 728 "renesas,etheravb-rcar-gen4"; 729 reg = <0 0xe6810000 0 0x800>; 730 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 755 interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", 756 "ch5", "ch6", "ch7", "ch8", "ch9", 757 "ch10", "ch11", "ch12", "ch13", 758 "ch14", "ch15", "ch16", "ch17", 759 "ch18", "ch19", "ch20", "ch21", 760 "ch22", "ch23", "ch24"; 761 clocks = <&cpg CPG_MOD 212>; 762 clock-names = "fck"; 763 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 764 resets = <&cpg 212>; 765 phy-mode = "rgmii"; 766 rx-internal-delay-ps = <0>; 767 tx-internal-delay-ps = <0>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 status = "disabled"; 771 }; 772 773 avb2: ethernet@e6820000 { 774 compatible = "renesas,etheravb-r8a779g0", 775 "renesas,etheravb-rcar-gen4"; 776 reg = <0 0xe6820000 0 0x1000>; 777 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 802 interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", 803 "ch5", "ch6", "ch7", "ch8", "ch9", 804 "ch10", "ch11", "ch12", "ch13", 805 "ch14", "ch15", "ch16", "ch17", 806 "ch18", "ch19", "ch20", "ch21", 807 "ch22", "ch23", "ch24"; 808 clocks = <&cpg CPG_MOD 213>; 809 clock-names = "fck"; 810 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 811 resets = <&cpg 213>; 812 phy-mode = "rgmii"; 813 rx-internal-delay-ps = <0>; 814 tx-internal-delay-ps = <0>; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 status = "disabled"; 818 }; 819 820 pwm0: pwm@e6e30000 { 821 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 822 reg = <0 0xe6e30000 0 0x10>; 823 #pwm-cells = <2>; 824 clocks = <&cpg CPG_MOD 628>; 825 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 826 resets = <&cpg 628>; 827 status = "disabled"; 828 }; 829 830 pwm1: pwm@e6e31000 { 831 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 832 reg = <0 0xe6e31000 0 0x10>; 833 #pwm-cells = <2>; 834 clocks = <&cpg CPG_MOD 628>; 835 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 836 resets = <&cpg 628>; 837 status = "disabled"; 838 }; 839 840 pwm2: pwm@e6e32000 { 841 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 842 reg = <0 0xe6e32000 0 0x10>; 843 #pwm-cells = <2>; 844 clocks = <&cpg CPG_MOD 628>; 845 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 846 resets = <&cpg 628>; 847 status = "disabled"; 848 }; 849 850 pwm3: pwm@e6e33000 { 851 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 852 reg = <0 0xe6e33000 0 0x10>; 853 #pwm-cells = <2>; 854 clocks = <&cpg CPG_MOD 628>; 855 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 856 resets = <&cpg 628>; 857 status = "disabled"; 858 }; 859 860 pwm4: pwm@e6e34000 { 861 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 862 reg = <0 0xe6e34000 0 0x10>; 863 #pwm-cells = <2>; 864 clocks = <&cpg CPG_MOD 628>; 865 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 866 resets = <&cpg 628>; 867 status = "disabled"; 868 }; 869 870 pwm5: pwm@e6e35000 { 871 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 872 reg = <0 0xe6e35000 0 0x10>; 873 #pwm-cells = <2>; 874 clocks = <&cpg CPG_MOD 628>; 875 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 876 resets = <&cpg 628>; 877 status = "disabled"; 878 }; 879 880 pwm6: pwm@e6e36000 { 881 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 882 reg = <0 0xe6e36000 0 0x10>; 883 #pwm-cells = <2>; 884 clocks = <&cpg CPG_MOD 628>; 885 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 886 resets = <&cpg 628>; 887 status = "disabled"; 888 }; 889 890 pwm7: pwm@e6e37000 { 891 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 892 reg = <0 0xe6e37000 0 0x10>; 893 #pwm-cells = <2>; 894 clocks = <&cpg CPG_MOD 628>; 895 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 896 resets = <&cpg 628>; 897 status = "disabled"; 898 }; 899 900 pwm8: pwm@e6e38000 { 901 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 902 reg = <0 0xe6e38000 0 0x10>; 903 #pwm-cells = <2>; 904 clocks = <&cpg CPG_MOD 628>; 905 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 906 resets = <&cpg 628>; 907 status = "disabled"; 908 }; 909 910 pwm9: pwm@e6e39000 { 911 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 912 reg = <0 0xe6e39000 0 0x10>; 913 #pwm-cells = <2>; 914 clocks = <&cpg CPG_MOD 628>; 915 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 916 resets = <&cpg 628>; 917 status = "disabled"; 918 }; 919 920 scif0: serial@e6e60000 { 921 compatible = "renesas,scif-r8a779g0", 922 "renesas,rcar-gen4-scif", "renesas,scif"; 923 reg = <0 0xe6e60000 0 64>; 924 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&cpg CPG_MOD 702>, 926 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 927 <&scif_clk>; 928 clock-names = "fck", "brg_int", "scif_clk"; 929 dmas = <&dmac0 0x51>, <&dmac0 0x50>, 930 <&dmac1 0x51>, <&dmac1 0x50>; 931 dma-names = "tx", "rx", "tx", "rx"; 932 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 933 resets = <&cpg 702>; 934 status = "disabled"; 935 }; 936 937 scif1: serial@e6e68000 { 938 compatible = "renesas,scif-r8a779g0", 939 "renesas,rcar-gen4-scif", "renesas,scif"; 940 reg = <0 0xe6e68000 0 64>; 941 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&cpg CPG_MOD 703>, 943 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 944 <&scif_clk>; 945 clock-names = "fck", "brg_int", "scif_clk"; 946 dmas = <&dmac0 0x53>, <&dmac0 0x52>, 947 <&dmac1 0x53>, <&dmac1 0x52>; 948 dma-names = "tx", "rx", "tx", "rx"; 949 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 950 resets = <&cpg 703>; 951 status = "disabled"; 952 }; 953 954 scif3: serial@e6c50000 { 955 compatible = "renesas,scif-r8a779g0", 956 "renesas,rcar-gen4-scif", "renesas,scif"; 957 reg = <0 0xe6c50000 0 64>; 958 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&cpg CPG_MOD 704>, 960 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 961 <&scif_clk>; 962 clock-names = "fck", "brg_int", "scif_clk"; 963 dmas = <&dmac0 0x57>, <&dmac0 0x56>, 964 <&dmac1 0x57>, <&dmac1 0x56>; 965 dma-names = "tx", "rx", "tx", "rx"; 966 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 967 resets = <&cpg 704>; 968 status = "disabled"; 969 }; 970 971 scif4: serial@e6c40000 { 972 compatible = "renesas,scif-r8a779g0", 973 "renesas,rcar-gen4-scif", "renesas,scif"; 974 reg = <0 0xe6c40000 0 64>; 975 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&cpg CPG_MOD 705>, 977 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 978 <&scif_clk>; 979 clock-names = "fck", "brg_int", "scif_clk"; 980 dmas = <&dmac0 0x59>, <&dmac0 0x58>, 981 <&dmac1 0x59>, <&dmac1 0x58>; 982 dma-names = "tx", "rx", "tx", "rx"; 983 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 984 resets = <&cpg 705>; 985 status = "disabled"; 986 }; 987 988 tpu: pwm@e6e80000 { 989 compatible = "renesas,tpu-r8a779g0", "renesas,tpu"; 990 reg = <0 0xe6e80000 0 0x148>; 991 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&cpg CPG_MOD 718>; 993 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 994 resets = <&cpg 718>; 995 #pwm-cells = <3>; 996 status = "disabled"; 997 }; 998 999 msiof0: spi@e6e90000 { 1000 compatible = "renesas,msiof-r8a779g0", 1001 "renesas,rcar-gen4-msiof"; 1002 reg = <0 0xe6e90000 0 0x0064>; 1003 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&cpg CPG_MOD 618>; 1005 dmas = <&dmac0 0x41>, <&dmac0 0x40>, 1006 <&dmac1 0x41>, <&dmac1 0x40>; 1007 dma-names = "tx", "rx", "tx", "rx"; 1008 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1009 resets = <&cpg 618>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 msiof1: spi@e6ea0000 { 1016 compatible = "renesas,msiof-r8a779g0", 1017 "renesas,rcar-gen4-msiof"; 1018 reg = <0 0xe6ea0000 0 0x0064>; 1019 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&cpg CPG_MOD 619>; 1021 dmas = <&dmac0 0x43>, <&dmac0 0x42>, 1022 <&dmac1 0x43>, <&dmac1 0x42>; 1023 dma-names = "tx", "rx", "tx", "rx"; 1024 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1025 resets = <&cpg 619>; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 msiof2: spi@e6c00000 { 1032 compatible = "renesas,msiof-r8a779g0", 1033 "renesas,rcar-gen4-msiof"; 1034 reg = <0 0xe6c00000 0 0x0064>; 1035 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&cpg CPG_MOD 620>; 1037 dmas = <&dmac0 0x45>, <&dmac0 0x44>, 1038 <&dmac1 0x45>, <&dmac1 0x44>; 1039 dma-names = "tx", "rx", "tx", "rx"; 1040 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1041 resets = <&cpg 620>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 msiof3: spi@e6c10000 { 1048 compatible = "renesas,msiof-r8a779g0", 1049 "renesas,rcar-gen4-msiof"; 1050 reg = <0 0xe6c10000 0 0x0064>; 1051 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&cpg CPG_MOD 621>; 1053 dmas = <&dmac0 0x47>, <&dmac0 0x46>, 1054 <&dmac1 0x47>, <&dmac1 0x46>; 1055 dma-names = "tx", "rx", "tx", "rx"; 1056 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1057 resets = <&cpg 621>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 status = "disabled"; 1061 }; 1062 1063 msiof4: spi@e6c20000 { 1064 compatible = "renesas,msiof-r8a779g0", 1065 "renesas,rcar-gen4-msiof"; 1066 reg = <0 0xe6c20000 0 0x0064>; 1067 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&cpg CPG_MOD 622>; 1069 dmas = <&dmac0 0x49>, <&dmac0 0x48>, 1070 <&dmac1 0x49>, <&dmac1 0x48>; 1071 dma-names = "tx", "rx", "tx", "rx"; 1072 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1073 resets = <&cpg 622>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 status = "disabled"; 1077 }; 1078 1079 msiof5: spi@e6c28000 { 1080 compatible = "renesas,msiof-r8a779g0", 1081 "renesas,rcar-gen4-msiof"; 1082 reg = <0 0xe6c28000 0 0x0064>; 1083 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&cpg CPG_MOD 623>; 1085 dmas = <&dmac0 0x4b>, <&dmac0 0x4a>, 1086 <&dmac1 0x4b>, <&dmac1 0x4a>; 1087 dma-names = "tx", "rx", "tx", "rx"; 1088 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1089 resets = <&cpg 623>; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 dmac0: dma-controller@e7350000 { 1096 compatible = "renesas,dmac-r8a779g0", 1097 "renesas,rcar-gen4-dmac"; 1098 reg = <0 0xe7350000 0 0x1000>, 1099 <0 0xe7300000 0 0x10000>; 1100 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1117 interrupt-names = "error", 1118 "ch0", "ch1", "ch2", "ch3", "ch4", 1119 "ch5", "ch6", "ch7", "ch8", "ch9", 1120 "ch10", "ch11", "ch12", "ch13", 1121 "ch14", "ch15"; 1122 clocks = <&cpg CPG_MOD 709>; 1123 clock-names = "fck"; 1124 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1125 resets = <&cpg 709>; 1126 #dma-cells = <1>; 1127 dma-channels = <16>; 1128 }; 1129 1130 dmac1: dma-controller@e7351000 { 1131 compatible = "renesas,dmac-r8a779g0", 1132 "renesas,rcar-gen4-dmac"; 1133 reg = <0 0xe7351000 0 0x1000>, 1134 <0 0xe7310000 0 0x10000>; 1135 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1152 interrupt-names = "error", 1153 "ch0", "ch1", "ch2", "ch3", "ch4", 1154 "ch5", "ch6", "ch7", "ch8", "ch9", 1155 "ch10", "ch11", "ch12", "ch13", 1156 "ch14", "ch15"; 1157 clocks = <&cpg CPG_MOD 710>; 1158 clock-names = "fck"; 1159 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1160 resets = <&cpg 710>; 1161 #dma-cells = <1>; 1162 dma-channels = <16>; 1163 }; 1164 1165 mmc0: mmc@ee140000 { 1166 compatible = "renesas,sdhi-r8a779g0", 1167 "renesas,rcar-gen4-sdhi"; 1168 reg = <0 0xee140000 0 0x2000>; 1169 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 1170 clocks = <&cpg CPG_MOD 706>, 1171 <&cpg CPG_CORE R8A779G0_CLK_SD0H>; 1172 clock-names = "core", "clkh"; 1173 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1174 resets = <&cpg 706>; 1175 max-frequency = <200000000>; 1176 status = "disabled"; 1177 }; 1178 1179 rpc: spi@ee200000 { 1180 compatible = "renesas,r8a779g0-rpc-if", 1181 "renesas,rcar-gen4-rpc-if"; 1182 reg = <0 0xee200000 0 0x200>, 1183 <0 0x08000000 0 0x04000000>, 1184 <0 0xee208000 0 0x100>; 1185 reg-names = "regs", "dirmap", "wbuf"; 1186 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&cpg CPG_MOD 629>; 1188 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1189 resets = <&cpg 629>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 status = "disabled"; 1193 }; 1194 1195 gic: interrupt-controller@f1000000 { 1196 compatible = "arm,gic-v3"; 1197 #interrupt-cells = <3>; 1198 #address-cells = <0>; 1199 interrupt-controller; 1200 reg = <0x0 0xf1000000 0 0x20000>, 1201 <0x0 0xf1060000 0 0x110000>; 1202 interrupts = <GIC_PPI 9 1203 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1204 }; 1205 1206 prr: chipid@fff00044 { 1207 compatible = "renesas,prr"; 1208 reg = <0 0xfff00044 0 4>; 1209 }; 1210 }; 1211 1212 timer { 1213 compatible = "arm,armv8-timer"; 1214 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1215 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1216 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1217 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1218 }; 1219}; 1220