1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the R-Car V4H (R8A779G0) SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a779g0-sysc.h>
11
12/ {
13	compatible = "renesas,r8a779g0";
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		a76_0: cpu@0 {
22			compatible = "arm,cortex-a76";
23			reg = <0>;
24			device_type = "cpu";
25			power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
26		};
27	};
28
29	extal_clk: extal {
30		compatible = "fixed-clock";
31		#clock-cells = <0>;
32		/* This value must be overridden by the board */
33		clock-frequency = <0>;
34	};
35
36	extalr_clk: extalr {
37		compatible = "fixed-clock";
38		#clock-cells = <0>;
39		/* This value must be overridden by the board */
40		clock-frequency = <0>;
41	};
42
43	pmu_a76 {
44		compatible = "arm,cortex-a76-pmu";
45		interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
46	};
47
48	/* External SCIF clock - to be overridden by boards that provide it */
49	scif_clk: scif {
50		compatible = "fixed-clock";
51		#clock-cells = <0>;
52		clock-frequency = <0>;
53	};
54
55	soc: soc {
56		compatible = "simple-bus";
57		interrupt-parent = <&gic>;
58		#address-cells = <2>;
59		#size-cells = <2>;
60		ranges;
61
62		cpg: clock-controller@e6150000 {
63			compatible = "renesas,r8a779g0-cpg-mssr";
64			reg = <0 0xe6150000 0 0x4000>;
65			clocks = <&extal_clk>, <&extalr_clk>;
66			clock-names = "extal", "extalr";
67			#clock-cells = <2>;
68			#power-domain-cells = <0>;
69			#reset-cells = <1>;
70		};
71
72		rst: reset-controller@e6160000 {
73			compatible = "renesas,r8a779g0-rst";
74			reg = <0 0xe6160000 0 0x4000>;
75		};
76
77		sysc: system-controller@e6180000 {
78			compatible = "renesas,r8a779g0-sysc";
79			reg = <0 0xe6180000 0 0x4000>;
80			#power-domain-cells = <1>;
81		};
82
83		hscif0: serial@e6540000 {
84			compatible = "renesas,hscif-r8a779g0",
85				     "renesas,rcar-gen4-hscif",
86				     "renesas,hscif";
87			reg = <0 0xe6540000 0 96>;
88			interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
89			clocks = <&cpg CPG_MOD 514>,
90				 <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>,
91				 <&scif_clk>;
92			clock-names = "fck", "brg_int", "scif_clk";
93			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
94			resets = <&cpg 514>;
95			status = "disabled";
96		};
97
98		gic: interrupt-controller@f1000000 {
99			compatible = "arm,gic-v3";
100			#interrupt-cells = <3>;
101			#address-cells = <0>;
102			interrupt-controller;
103			reg = <0x0 0xf1000000 0 0x20000>,
104			      <0x0 0xf1060000 0 0x110000>;
105			interrupts = <GIC_PPI 9
106				      (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
107		};
108
109		prr: chipid@fff00044 {
110			compatible = "renesas,prr";
111			reg = <0 0xfff00044 0 4>;
112		};
113	};
114
115	timer {
116		compatible = "arm,armv8-timer";
117		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
118				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
119				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
120				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
121	};
122};
123