1987da486SYoshihiro Shimoda// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2987da486SYoshihiro Shimoda/* 3987da486SYoshihiro Shimoda * Device Tree Source for the R-Car V4H (R8A779G0) SoC 4987da486SYoshihiro Shimoda * 5987da486SYoshihiro Shimoda * Copyright (C) 2022 Renesas Electronics Corp. 6987da486SYoshihiro Shimoda */ 7987da486SYoshihiro Shimoda 8987da486SYoshihiro Shimoda#include <dt-bindings/clock/r8a779g0-cpg-mssr.h> 9987da486SYoshihiro Shimoda#include <dt-bindings/interrupt-controller/arm-gic.h> 10987da486SYoshihiro Shimoda#include <dt-bindings/power/r8a779g0-sysc.h> 11987da486SYoshihiro Shimoda 12987da486SYoshihiro Shimoda/ { 13987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0"; 14987da486SYoshihiro Shimoda #address-cells = <2>; 15987da486SYoshihiro Shimoda #size-cells = <2>; 16987da486SYoshihiro Shimoda 17987da486SYoshihiro Shimoda cpus { 18987da486SYoshihiro Shimoda #address-cells = <1>; 19987da486SYoshihiro Shimoda #size-cells = <0>; 20987da486SYoshihiro Shimoda 21987da486SYoshihiro Shimoda a76_0: cpu@0 { 22987da486SYoshihiro Shimoda compatible = "arm,cortex-a76"; 23987da486SYoshihiro Shimoda reg = <0>; 24987da486SYoshihiro Shimoda device_type = "cpu"; 25987da486SYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; 26987da486SYoshihiro Shimoda }; 27987da486SYoshihiro Shimoda }; 28987da486SYoshihiro Shimoda 29987da486SYoshihiro Shimoda extal_clk: extal { 30987da486SYoshihiro Shimoda compatible = "fixed-clock"; 31987da486SYoshihiro Shimoda #clock-cells = <0>; 32987da486SYoshihiro Shimoda /* This value must be overridden by the board */ 33987da486SYoshihiro Shimoda clock-frequency = <0>; 34987da486SYoshihiro Shimoda }; 35987da486SYoshihiro Shimoda 36987da486SYoshihiro Shimoda extalr_clk: extalr { 37987da486SYoshihiro Shimoda compatible = "fixed-clock"; 38987da486SYoshihiro Shimoda #clock-cells = <0>; 39987da486SYoshihiro Shimoda /* This value must be overridden by the board */ 40987da486SYoshihiro Shimoda clock-frequency = <0>; 41987da486SYoshihiro Shimoda }; 42987da486SYoshihiro Shimoda 43987da486SYoshihiro Shimoda pmu_a76 { 44987da486SYoshihiro Shimoda compatible = "arm,cortex-a76-pmu"; 45987da486SYoshihiro Shimoda interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 46987da486SYoshihiro Shimoda }; 47987da486SYoshihiro Shimoda 48987da486SYoshihiro Shimoda /* External SCIF clock - to be overridden by boards that provide it */ 49987da486SYoshihiro Shimoda scif_clk: scif { 50987da486SYoshihiro Shimoda compatible = "fixed-clock"; 51987da486SYoshihiro Shimoda #clock-cells = <0>; 52987da486SYoshihiro Shimoda clock-frequency = <0>; 53987da486SYoshihiro Shimoda }; 54987da486SYoshihiro Shimoda 55987da486SYoshihiro Shimoda soc: soc { 56987da486SYoshihiro Shimoda compatible = "simple-bus"; 57987da486SYoshihiro Shimoda interrupt-parent = <&gic>; 58987da486SYoshihiro Shimoda #address-cells = <2>; 59987da486SYoshihiro Shimoda #size-cells = <2>; 60987da486SYoshihiro Shimoda ranges; 61987da486SYoshihiro Shimoda 62a43306faSGeert Uytterhoeven rwdt: watchdog@e6020000 { 63a43306faSGeert Uytterhoeven compatible = "renesas,r8a779g0-wdt", 64a43306faSGeert Uytterhoeven "renesas,rcar-gen4-wdt"; 65a43306faSGeert Uytterhoeven reg = <0 0xe6020000 0 0x0c>; 66a43306faSGeert Uytterhoeven interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 67a43306faSGeert Uytterhoeven clocks = <&cpg CPG_MOD 907>; 68a43306faSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 69a43306faSGeert Uytterhoeven resets = <&cpg 907>; 70a43306faSGeert Uytterhoeven status = "disabled"; 71a43306faSGeert Uytterhoeven }; 72a43306faSGeert Uytterhoeven 734cebce25SGeert Uytterhoeven pfc: pinctrl@e6050000 { 744cebce25SGeert Uytterhoeven compatible = "renesas,pfc-r8a779g0"; 754cebce25SGeert Uytterhoeven reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 764cebce25SGeert Uytterhoeven <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, 774cebce25SGeert Uytterhoeven <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, 784cebce25SGeert Uytterhoeven <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, 794cebce25SGeert Uytterhoeven <0 0xe6068000 0 0x16c>; 804cebce25SGeert Uytterhoeven }; 814cebce25SGeert Uytterhoeven 82987da486SYoshihiro Shimoda cpg: clock-controller@e6150000 { 83987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0-cpg-mssr"; 84987da486SYoshihiro Shimoda reg = <0 0xe6150000 0 0x4000>; 85987da486SYoshihiro Shimoda clocks = <&extal_clk>, <&extalr_clk>; 86987da486SYoshihiro Shimoda clock-names = "extal", "extalr"; 87987da486SYoshihiro Shimoda #clock-cells = <2>; 88987da486SYoshihiro Shimoda #power-domain-cells = <0>; 89987da486SYoshihiro Shimoda #reset-cells = <1>; 90987da486SYoshihiro Shimoda }; 91987da486SYoshihiro Shimoda 92987da486SYoshihiro Shimoda rst: reset-controller@e6160000 { 93987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0-rst"; 94987da486SYoshihiro Shimoda reg = <0 0xe6160000 0 0x4000>; 95987da486SYoshihiro Shimoda }; 96987da486SYoshihiro Shimoda 97987da486SYoshihiro Shimoda sysc: system-controller@e6180000 { 98987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0-sysc"; 99987da486SYoshihiro Shimoda reg = <0 0xe6180000 0 0x4000>; 100987da486SYoshihiro Shimoda #power-domain-cells = <1>; 101987da486SYoshihiro Shimoda }; 102987da486SYoshihiro Shimoda 103*ff77ba05SGeert Uytterhoeven i2c0: i2c@e6500000 { 104*ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 105*ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 106*ff77ba05SGeert Uytterhoeven reg = <0 0xe6500000 0 0x40>; 107*ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 108*ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 518>; 109*ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 110*ff77ba05SGeert Uytterhoeven resets = <&cpg 518>; 111*ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 112*ff77ba05SGeert Uytterhoeven #address-cells = <1>; 113*ff77ba05SGeert Uytterhoeven #size-cells = <0>; 114*ff77ba05SGeert Uytterhoeven status = "disabled"; 115*ff77ba05SGeert Uytterhoeven }; 116*ff77ba05SGeert Uytterhoeven 117*ff77ba05SGeert Uytterhoeven i2c1: i2c@e6508000 { 118*ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 119*ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 120*ff77ba05SGeert Uytterhoeven reg = <0 0xe6508000 0 0x40>; 121*ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; 122*ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 519>; 123*ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 124*ff77ba05SGeert Uytterhoeven resets = <&cpg 519>; 125*ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 126*ff77ba05SGeert Uytterhoeven #address-cells = <1>; 127*ff77ba05SGeert Uytterhoeven #size-cells = <0>; 128*ff77ba05SGeert Uytterhoeven status = "disabled"; 129*ff77ba05SGeert Uytterhoeven }; 130*ff77ba05SGeert Uytterhoeven 131*ff77ba05SGeert Uytterhoeven i2c2: i2c@e6510000 { 132*ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 133*ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 134*ff77ba05SGeert Uytterhoeven reg = <0 0xe6510000 0 0x40>; 135*ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; 136*ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 520>; 137*ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 138*ff77ba05SGeert Uytterhoeven resets = <&cpg 520>; 139*ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 140*ff77ba05SGeert Uytterhoeven #address-cells = <1>; 141*ff77ba05SGeert Uytterhoeven #size-cells = <0>; 142*ff77ba05SGeert Uytterhoeven status = "disabled"; 143*ff77ba05SGeert Uytterhoeven }; 144*ff77ba05SGeert Uytterhoeven 145*ff77ba05SGeert Uytterhoeven i2c3: i2c@e66d0000 { 146*ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 147*ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 148*ff77ba05SGeert Uytterhoeven reg = <0 0xe66d0000 0 0x40>; 149*ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 150*ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 521>; 151*ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 152*ff77ba05SGeert Uytterhoeven resets = <&cpg 521>; 153*ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 154*ff77ba05SGeert Uytterhoeven #address-cells = <1>; 155*ff77ba05SGeert Uytterhoeven #size-cells = <0>; 156*ff77ba05SGeert Uytterhoeven status = "disabled"; 157*ff77ba05SGeert Uytterhoeven }; 158*ff77ba05SGeert Uytterhoeven 159*ff77ba05SGeert Uytterhoeven i2c4: i2c@e66d8000 { 160*ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 161*ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 162*ff77ba05SGeert Uytterhoeven reg = <0 0xe66d8000 0 0x40>; 163*ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 164*ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 522>; 165*ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 166*ff77ba05SGeert Uytterhoeven resets = <&cpg 522>; 167*ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 168*ff77ba05SGeert Uytterhoeven #address-cells = <1>; 169*ff77ba05SGeert Uytterhoeven #size-cells = <0>; 170*ff77ba05SGeert Uytterhoeven status = "disabled"; 171*ff77ba05SGeert Uytterhoeven }; 172*ff77ba05SGeert Uytterhoeven 173*ff77ba05SGeert Uytterhoeven i2c5: i2c@e66e0000 { 174*ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 175*ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 176*ff77ba05SGeert Uytterhoeven reg = <0 0xe66e0000 0 0x40>; 177*ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>; 178*ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 523>; 179*ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 180*ff77ba05SGeert Uytterhoeven resets = <&cpg 523>; 181*ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 182*ff77ba05SGeert Uytterhoeven #address-cells = <1>; 183*ff77ba05SGeert Uytterhoeven #size-cells = <0>; 184*ff77ba05SGeert Uytterhoeven status = "disabled"; 185*ff77ba05SGeert Uytterhoeven }; 186*ff77ba05SGeert Uytterhoeven 187987da486SYoshihiro Shimoda hscif0: serial@e6540000 { 188987da486SYoshihiro Shimoda compatible = "renesas,hscif-r8a779g0", 189987da486SYoshihiro Shimoda "renesas,rcar-gen4-hscif", 190987da486SYoshihiro Shimoda "renesas,hscif"; 191987da486SYoshihiro Shimoda reg = <0 0xe6540000 0 96>; 192ab2866f1SGeert Uytterhoeven interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 193987da486SYoshihiro Shimoda clocks = <&cpg CPG_MOD 514>, 194987da486SYoshihiro Shimoda <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>, 195987da486SYoshihiro Shimoda <&scif_clk>; 196987da486SYoshihiro Shimoda clock-names = "fck", "brg_int", "scif_clk"; 197987da486SYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 198987da486SYoshihiro Shimoda resets = <&cpg 514>; 199987da486SYoshihiro Shimoda status = "disabled"; 200987da486SYoshihiro Shimoda }; 201987da486SYoshihiro Shimoda 202987da486SYoshihiro Shimoda gic: interrupt-controller@f1000000 { 203987da486SYoshihiro Shimoda compatible = "arm,gic-v3"; 204987da486SYoshihiro Shimoda #interrupt-cells = <3>; 205987da486SYoshihiro Shimoda #address-cells = <0>; 206987da486SYoshihiro Shimoda interrupt-controller; 207987da486SYoshihiro Shimoda reg = <0x0 0xf1000000 0 0x20000>, 208987da486SYoshihiro Shimoda <0x0 0xf1060000 0 0x110000>; 209987da486SYoshihiro Shimoda interrupts = <GIC_PPI 9 210987da486SYoshihiro Shimoda (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 211987da486SYoshihiro Shimoda }; 212987da486SYoshihiro Shimoda 213987da486SYoshihiro Shimoda prr: chipid@fff00044 { 214987da486SYoshihiro Shimoda compatible = "renesas,prr"; 215987da486SYoshihiro Shimoda reg = <0 0xfff00044 0 4>; 216987da486SYoshihiro Shimoda }; 217987da486SYoshihiro Shimoda }; 218987da486SYoshihiro Shimoda 219987da486SYoshihiro Shimoda timer { 220987da486SYoshihiro Shimoda compatible = "arm,armv8-timer"; 221987da486SYoshihiro Shimoda interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 222987da486SYoshihiro Shimoda <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 223987da486SYoshihiro Shimoda <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 224987da486SYoshihiro Shimoda <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 225987da486SYoshihiro Shimoda }; 226987da486SYoshihiro Shimoda}; 227