1987da486SYoshihiro Shimoda// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2987da486SYoshihiro Shimoda/* 3987da486SYoshihiro Shimoda * Device Tree Source for the R-Car V4H (R8A779G0) SoC 4987da486SYoshihiro Shimoda * 5987da486SYoshihiro Shimoda * Copyright (C) 2022 Renesas Electronics Corp. 6987da486SYoshihiro Shimoda */ 7987da486SYoshihiro Shimoda 8987da486SYoshihiro Shimoda#include <dt-bindings/clock/r8a779g0-cpg-mssr.h> 9987da486SYoshihiro Shimoda#include <dt-bindings/interrupt-controller/arm-gic.h> 10987da486SYoshihiro Shimoda#include <dt-bindings/power/r8a779g0-sysc.h> 11987da486SYoshihiro Shimoda 12987da486SYoshihiro Shimoda/ { 13987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0"; 14987da486SYoshihiro Shimoda #address-cells = <2>; 15987da486SYoshihiro Shimoda #size-cells = <2>; 16987da486SYoshihiro Shimoda 175056a0c7SGeert Uytterhoeven /* External CAN clock - to be overridden by boards that provide it */ 185056a0c7SGeert Uytterhoeven can_clk: can { 195056a0c7SGeert Uytterhoeven compatible = "fixed-clock"; 205056a0c7SGeert Uytterhoeven #clock-cells = <0>; 215056a0c7SGeert Uytterhoeven clock-frequency = <0>; 225056a0c7SGeert Uytterhoeven }; 235056a0c7SGeert Uytterhoeven 249a0e6306SGeert Uytterhoeven cluster0_opp: opp-table-0 { 259a0e6306SGeert Uytterhoeven compatible = "operating-points-v2"; 269a0e6306SGeert Uytterhoeven opp-shared; 279a0e6306SGeert Uytterhoeven 289a0e6306SGeert Uytterhoeven opp-500000000 { 299a0e6306SGeert Uytterhoeven opp-hz = /bits/ 64 <500000000>; 309a0e6306SGeert Uytterhoeven opp-microvolt = <825000>; 319a0e6306SGeert Uytterhoeven clock-latency-ns = <500000>; 329a0e6306SGeert Uytterhoeven }; 339a0e6306SGeert Uytterhoeven opp-1000000000 { 349a0e6306SGeert Uytterhoeven opp-hz = /bits/ 64 <1000000000>; 359a0e6306SGeert Uytterhoeven opp-microvolt = <825000>; 369a0e6306SGeert Uytterhoeven clock-latency-ns = <500000>; 379a0e6306SGeert Uytterhoeven }; 389a0e6306SGeert Uytterhoeven opp-1500000000 { 399a0e6306SGeert Uytterhoeven opp-hz = /bits/ 64 <1500000000>; 409a0e6306SGeert Uytterhoeven opp-microvolt = <825000>; 419a0e6306SGeert Uytterhoeven clock-latency-ns = <500000>; 429a0e6306SGeert Uytterhoeven }; 439a0e6306SGeert Uytterhoeven opp-1700000000 { 449a0e6306SGeert Uytterhoeven opp-hz = /bits/ 64 <1700000000>; 459a0e6306SGeert Uytterhoeven opp-microvolt = <825000>; 469a0e6306SGeert Uytterhoeven clock-latency-ns = <500000>; 479a0e6306SGeert Uytterhoeven opp-suspend; 489a0e6306SGeert Uytterhoeven }; 4987d85b48SGeert Uytterhoeven opp-1800000000 { 5087d85b48SGeert Uytterhoeven opp-hz = /bits/ 64 <1800000000>; 5187d85b48SGeert Uytterhoeven opp-microvolt = <880000>; 5287d85b48SGeert Uytterhoeven clock-latency-ns = <500000>; 5387d85b48SGeert Uytterhoeven turbo-mode; 5487d85b48SGeert Uytterhoeven }; 559a0e6306SGeert Uytterhoeven }; 569a0e6306SGeert Uytterhoeven 57987da486SYoshihiro Shimoda cpus { 58987da486SYoshihiro Shimoda #address-cells = <1>; 59987da486SYoshihiro Shimoda #size-cells = <0>; 60987da486SYoshihiro Shimoda 6168c9c53dSGeert Uytterhoeven cpu-map { 6268c9c53dSGeert Uytterhoeven cluster0 { 6368c9c53dSGeert Uytterhoeven core0 { 6468c9c53dSGeert Uytterhoeven cpu = <&a76_0>; 6568c9c53dSGeert Uytterhoeven }; 6668c9c53dSGeert Uytterhoeven core1 { 6768c9c53dSGeert Uytterhoeven cpu = <&a76_1>; 6868c9c53dSGeert Uytterhoeven }; 6968c9c53dSGeert Uytterhoeven }; 7068c9c53dSGeert Uytterhoeven 7168c9c53dSGeert Uytterhoeven cluster1 { 7268c9c53dSGeert Uytterhoeven core0 { 7368c9c53dSGeert Uytterhoeven cpu = <&a76_2>; 7468c9c53dSGeert Uytterhoeven }; 7568c9c53dSGeert Uytterhoeven core1 { 7668c9c53dSGeert Uytterhoeven cpu = <&a76_3>; 7768c9c53dSGeert Uytterhoeven }; 7868c9c53dSGeert Uytterhoeven }; 7968c9c53dSGeert Uytterhoeven }; 8068c9c53dSGeert Uytterhoeven 81987da486SYoshihiro Shimoda a76_0: cpu@0 { 82987da486SYoshihiro Shimoda compatible = "arm,cortex-a76"; 83987da486SYoshihiro Shimoda reg = <0>; 84987da486SYoshihiro Shimoda device_type = "cpu"; 85987da486SYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; 86f0840721SGeert Uytterhoeven next-level-cache = <&L3_CA76_0>; 8768c9c53dSGeert Uytterhoeven enable-method = "psci"; 885bb355a8SGeert Uytterhoeven cpu-idle-states = <&CPU_SLEEP_0>; 89ee8ce199SGeert Uytterhoeven clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; 909a0e6306SGeert Uytterhoeven operating-points-v2 = <&cluster0_opp>; 9168c9c53dSGeert Uytterhoeven }; 9268c9c53dSGeert Uytterhoeven 9368c9c53dSGeert Uytterhoeven a76_1: cpu@100 { 9468c9c53dSGeert Uytterhoeven compatible = "arm,cortex-a76"; 9568c9c53dSGeert Uytterhoeven reg = <0x100>; 9668c9c53dSGeert Uytterhoeven device_type = "cpu"; 9768c9c53dSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_A1E0D0C1>; 9868c9c53dSGeert Uytterhoeven next-level-cache = <&L3_CA76_0>; 9968c9c53dSGeert Uytterhoeven enable-method = "psci"; 1005bb355a8SGeert Uytterhoeven cpu-idle-states = <&CPU_SLEEP_0>; 101ee8ce199SGeert Uytterhoeven clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; 1029a0e6306SGeert Uytterhoeven operating-points-v2 = <&cluster0_opp>; 10368c9c53dSGeert Uytterhoeven }; 10468c9c53dSGeert Uytterhoeven 10568c9c53dSGeert Uytterhoeven a76_2: cpu@10000 { 10668c9c53dSGeert Uytterhoeven compatible = "arm,cortex-a76"; 10768c9c53dSGeert Uytterhoeven reg = <0x10000>; 10868c9c53dSGeert Uytterhoeven device_type = "cpu"; 10968c9c53dSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_A1E0D1C0>; 11068c9c53dSGeert Uytterhoeven next-level-cache = <&L3_CA76_1>; 11168c9c53dSGeert Uytterhoeven enable-method = "psci"; 1125bb355a8SGeert Uytterhoeven cpu-idle-states = <&CPU_SLEEP_0>; 113ee8ce199SGeert Uytterhoeven clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; 1149a0e6306SGeert Uytterhoeven operating-points-v2 = <&cluster0_opp>; 11568c9c53dSGeert Uytterhoeven }; 11668c9c53dSGeert Uytterhoeven 11768c9c53dSGeert Uytterhoeven a76_3: cpu@10100 { 11868c9c53dSGeert Uytterhoeven compatible = "arm,cortex-a76"; 11968c9c53dSGeert Uytterhoeven reg = <0x10100>; 12068c9c53dSGeert Uytterhoeven device_type = "cpu"; 12168c9c53dSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_A1E0D1C1>; 12268c9c53dSGeert Uytterhoeven next-level-cache = <&L3_CA76_1>; 12368c9c53dSGeert Uytterhoeven enable-method = "psci"; 1245bb355a8SGeert Uytterhoeven cpu-idle-states = <&CPU_SLEEP_0>; 125ee8ce199SGeert Uytterhoeven clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; 1269a0e6306SGeert Uytterhoeven operating-points-v2 = <&cluster0_opp>; 1275bb355a8SGeert Uytterhoeven }; 1285bb355a8SGeert Uytterhoeven 1295bb355a8SGeert Uytterhoeven idle-states { 1305bb355a8SGeert Uytterhoeven entry-method = "psci"; 1315bb355a8SGeert Uytterhoeven 1325bb355a8SGeert Uytterhoeven CPU_SLEEP_0: cpu-sleep-0 { 1335bb355a8SGeert Uytterhoeven compatible = "arm,idle-state"; 1345bb355a8SGeert Uytterhoeven arm,psci-suspend-param = <0x0010000>; 1355bb355a8SGeert Uytterhoeven local-timer-stop; 1365bb355a8SGeert Uytterhoeven entry-latency-us = <400>; 1375bb355a8SGeert Uytterhoeven exit-latency-us = <500>; 1385bb355a8SGeert Uytterhoeven min-residency-us = <4000>; 1395bb355a8SGeert Uytterhoeven }; 140f0840721SGeert Uytterhoeven }; 141f0840721SGeert Uytterhoeven 142f0840721SGeert Uytterhoeven L3_CA76_0: cache-controller-0 { 143f0840721SGeert Uytterhoeven compatible = "cache"; 144f0840721SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_A2E0D0>; 145f0840721SGeert Uytterhoeven cache-unified; 146f0840721SGeert Uytterhoeven cache-level = <3>; 147987da486SYoshihiro Shimoda }; 14868c9c53dSGeert Uytterhoeven 14968c9c53dSGeert Uytterhoeven L3_CA76_1: cache-controller-1 { 15068c9c53dSGeert Uytterhoeven compatible = "cache"; 15168c9c53dSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_A2E0D1>; 15268c9c53dSGeert Uytterhoeven cache-unified; 15368c9c53dSGeert Uytterhoeven cache-level = <3>; 15468c9c53dSGeert Uytterhoeven }; 15568c9c53dSGeert Uytterhoeven }; 15668c9c53dSGeert Uytterhoeven 15768c9c53dSGeert Uytterhoeven psci { 15868c9c53dSGeert Uytterhoeven compatible = "arm,psci-1.0", "arm,psci-0.2"; 15968c9c53dSGeert Uytterhoeven method = "smc"; 160987da486SYoshihiro Shimoda }; 161987da486SYoshihiro Shimoda 162987da486SYoshihiro Shimoda extal_clk: extal { 163987da486SYoshihiro Shimoda compatible = "fixed-clock"; 164987da486SYoshihiro Shimoda #clock-cells = <0>; 165987da486SYoshihiro Shimoda /* This value must be overridden by the board */ 166987da486SYoshihiro Shimoda clock-frequency = <0>; 167987da486SYoshihiro Shimoda }; 168987da486SYoshihiro Shimoda 169987da486SYoshihiro Shimoda extalr_clk: extalr { 170987da486SYoshihiro Shimoda compatible = "fixed-clock"; 171987da486SYoshihiro Shimoda #clock-cells = <0>; 172987da486SYoshihiro Shimoda /* This value must be overridden by the board */ 173987da486SYoshihiro Shimoda clock-frequency = <0>; 174987da486SYoshihiro Shimoda }; 175987da486SYoshihiro Shimoda 176987da486SYoshihiro Shimoda pmu_a76 { 177987da486SYoshihiro Shimoda compatible = "arm,cortex-a76-pmu"; 178987da486SYoshihiro Shimoda interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 179987da486SYoshihiro Shimoda }; 180987da486SYoshihiro Shimoda 181987da486SYoshihiro Shimoda /* External SCIF clock - to be overridden by boards that provide it */ 182987da486SYoshihiro Shimoda scif_clk: scif { 183987da486SYoshihiro Shimoda compatible = "fixed-clock"; 184987da486SYoshihiro Shimoda #clock-cells = <0>; 185987da486SYoshihiro Shimoda clock-frequency = <0>; 186987da486SYoshihiro Shimoda }; 187987da486SYoshihiro Shimoda 188987da486SYoshihiro Shimoda soc: soc { 189987da486SYoshihiro Shimoda compatible = "simple-bus"; 190987da486SYoshihiro Shimoda interrupt-parent = <&gic>; 191987da486SYoshihiro Shimoda #address-cells = <2>; 192987da486SYoshihiro Shimoda #size-cells = <2>; 193987da486SYoshihiro Shimoda ranges; 194987da486SYoshihiro Shimoda 195a43306faSGeert Uytterhoeven rwdt: watchdog@e6020000 { 196a43306faSGeert Uytterhoeven compatible = "renesas,r8a779g0-wdt", 197a43306faSGeert Uytterhoeven "renesas,rcar-gen4-wdt"; 198a43306faSGeert Uytterhoeven reg = <0 0xe6020000 0 0x0c>; 199a43306faSGeert Uytterhoeven interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 200a43306faSGeert Uytterhoeven clocks = <&cpg CPG_MOD 907>; 201a43306faSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 202a43306faSGeert Uytterhoeven resets = <&cpg 907>; 203a43306faSGeert Uytterhoeven status = "disabled"; 204a43306faSGeert Uytterhoeven }; 205a43306faSGeert Uytterhoeven 2064cebce25SGeert Uytterhoeven pfc: pinctrl@e6050000 { 2074cebce25SGeert Uytterhoeven compatible = "renesas,pfc-r8a779g0"; 2084cebce25SGeert Uytterhoeven reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 2094cebce25SGeert Uytterhoeven <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, 2104cebce25SGeert Uytterhoeven <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, 2114cebce25SGeert Uytterhoeven <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, 2124cebce25SGeert Uytterhoeven <0 0xe6068000 0 0x16c>; 2134cebce25SGeert Uytterhoeven }; 2144cebce25SGeert Uytterhoeven 215120c7a58SGeert Uytterhoeven gpio0: gpio@e6050180 { 216120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 217120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 218120c7a58SGeert Uytterhoeven reg = <0 0xe6050180 0 0x54>; 219120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>; 220120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 915>; 221120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 222120c7a58SGeert Uytterhoeven resets = <&cpg 915>; 223120c7a58SGeert Uytterhoeven gpio-controller; 224120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 225120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 0 19>; 226120c7a58SGeert Uytterhoeven interrupt-controller; 227120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 228120c7a58SGeert Uytterhoeven }; 229120c7a58SGeert Uytterhoeven 230120c7a58SGeert Uytterhoeven gpio1: gpio@e6050980 { 231120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 232120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 233120c7a58SGeert Uytterhoeven reg = <0 0xe6050980 0 0x54>; 234120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>; 235120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 915>; 236120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 237120c7a58SGeert Uytterhoeven resets = <&cpg 915>; 238120c7a58SGeert Uytterhoeven gpio-controller; 239120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 240120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 32 29>; 241120c7a58SGeert Uytterhoeven interrupt-controller; 242120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 243120c7a58SGeert Uytterhoeven }; 244120c7a58SGeert Uytterhoeven 245120c7a58SGeert Uytterhoeven gpio2: gpio@e6058180 { 246120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 247120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 248120c7a58SGeert Uytterhoeven reg = <0 0xe6058180 0 0x54>; 249120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>; 250120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 916>; 251120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 252120c7a58SGeert Uytterhoeven resets = <&cpg 916>; 253120c7a58SGeert Uytterhoeven gpio-controller; 254120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 255120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 64 20>; 256120c7a58SGeert Uytterhoeven interrupt-controller; 257120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 258120c7a58SGeert Uytterhoeven }; 259120c7a58SGeert Uytterhoeven 260120c7a58SGeert Uytterhoeven gpio3: gpio@e6058980 { 261120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 262120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 263120c7a58SGeert Uytterhoeven reg = <0 0xe6058980 0 0x54>; 264120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>; 265120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 916>; 266120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 267120c7a58SGeert Uytterhoeven resets = <&cpg 916>; 268120c7a58SGeert Uytterhoeven gpio-controller; 269120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 270120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 96 30>; 271120c7a58SGeert Uytterhoeven interrupt-controller; 272120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 273120c7a58SGeert Uytterhoeven }; 274120c7a58SGeert Uytterhoeven 275120c7a58SGeert Uytterhoeven gpio4: gpio@e6060180 { 276120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 277120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 278120c7a58SGeert Uytterhoeven reg = <0 0xe6060180 0 0x54>; 279120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>; 280120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 917>; 281120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 282120c7a58SGeert Uytterhoeven resets = <&cpg 917>; 283120c7a58SGeert Uytterhoeven gpio-controller; 284120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 285120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 128 25>; 286120c7a58SGeert Uytterhoeven interrupt-controller; 287120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 288120c7a58SGeert Uytterhoeven }; 289120c7a58SGeert Uytterhoeven 290120c7a58SGeert Uytterhoeven gpio5: gpio@e6060980 { 291120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 292120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 293120c7a58SGeert Uytterhoeven reg = <0 0xe6060980 0 0x54>; 294120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; 295120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 917>; 296120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 297120c7a58SGeert Uytterhoeven resets = <&cpg 917>; 298120c7a58SGeert Uytterhoeven gpio-controller; 299120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 300120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 160 21>; 301120c7a58SGeert Uytterhoeven interrupt-controller; 302120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 303120c7a58SGeert Uytterhoeven }; 304120c7a58SGeert Uytterhoeven 305120c7a58SGeert Uytterhoeven gpio6: gpio@e6061180 { 306120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 307120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 308120c7a58SGeert Uytterhoeven reg = <0 0xe6061180 0 0x54>; 309120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 310120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 917>; 311120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 312120c7a58SGeert Uytterhoeven resets = <&cpg 917>; 313120c7a58SGeert Uytterhoeven gpio-controller; 314120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 315120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 192 21>; 316120c7a58SGeert Uytterhoeven interrupt-controller; 317120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 318120c7a58SGeert Uytterhoeven }; 319120c7a58SGeert Uytterhoeven 320120c7a58SGeert Uytterhoeven gpio7: gpio@e6061980 { 321120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 322120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 323120c7a58SGeert Uytterhoeven reg = <0 0xe6061980 0 0x54>; 324120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>; 325120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 917>; 326120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 327120c7a58SGeert Uytterhoeven resets = <&cpg 917>; 328120c7a58SGeert Uytterhoeven gpio-controller; 329120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 330120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 224 21>; 331120c7a58SGeert Uytterhoeven interrupt-controller; 332120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 333120c7a58SGeert Uytterhoeven }; 334120c7a58SGeert Uytterhoeven 335120c7a58SGeert Uytterhoeven gpio8: gpio@e6068180 { 336120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 337120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 338120c7a58SGeert Uytterhoeven reg = <0 0xe6068180 0 0x54>; 339120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>; 340120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 918>; 341120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 342120c7a58SGeert Uytterhoeven resets = <&cpg 918>; 343120c7a58SGeert Uytterhoeven gpio-controller; 344120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 345120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 256 14>; 346120c7a58SGeert Uytterhoeven interrupt-controller; 347120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 348120c7a58SGeert Uytterhoeven }; 349120c7a58SGeert Uytterhoeven 35040a6dd7bSThanh Quan cmt0: timer@e60f0000 { 35140a6dd7bSThanh Quan compatible = "renesas,r8a779g0-cmt0", 35240a6dd7bSThanh Quan "renesas,rcar-gen4-cmt0"; 35340a6dd7bSThanh Quan reg = <0 0xe60f0000 0 0x1004>; 35440a6dd7bSThanh Quan interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 35540a6dd7bSThanh Quan <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 35640a6dd7bSThanh Quan clocks = <&cpg CPG_MOD 910>; 35740a6dd7bSThanh Quan clock-names = "fck"; 35840a6dd7bSThanh Quan power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 35940a6dd7bSThanh Quan resets = <&cpg 910>; 36040a6dd7bSThanh Quan status = "disabled"; 36140a6dd7bSThanh Quan }; 36240a6dd7bSThanh Quan 36340a6dd7bSThanh Quan cmt1: timer@e6130000 { 36440a6dd7bSThanh Quan compatible = "renesas,r8a779g0-cmt1", 36540a6dd7bSThanh Quan "renesas,rcar-gen4-cmt1"; 36640a6dd7bSThanh Quan reg = <0 0xe6130000 0 0x1004>; 36740a6dd7bSThanh Quan interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 36840a6dd7bSThanh Quan <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 36940a6dd7bSThanh Quan <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 37040a6dd7bSThanh Quan <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 37140a6dd7bSThanh Quan <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 37240a6dd7bSThanh Quan <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 37340a6dd7bSThanh Quan <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 37440a6dd7bSThanh Quan <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 37540a6dd7bSThanh Quan clocks = <&cpg CPG_MOD 911>; 37640a6dd7bSThanh Quan clock-names = "fck"; 37740a6dd7bSThanh Quan power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 37840a6dd7bSThanh Quan resets = <&cpg 911>; 37940a6dd7bSThanh Quan status = "disabled"; 38040a6dd7bSThanh Quan }; 38140a6dd7bSThanh Quan 38240a6dd7bSThanh Quan cmt2: timer@e6140000 { 38340a6dd7bSThanh Quan compatible = "renesas,r8a779g0-cmt1", 38440a6dd7bSThanh Quan "renesas,rcar-gen4-cmt1"; 38540a6dd7bSThanh Quan reg = <0 0xe6140000 0 0x1004>; 38640a6dd7bSThanh Quan interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 38740a6dd7bSThanh Quan <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 38840a6dd7bSThanh Quan <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 38940a6dd7bSThanh Quan <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 39040a6dd7bSThanh Quan <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 39140a6dd7bSThanh Quan <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 39240a6dd7bSThanh Quan <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 39340a6dd7bSThanh Quan <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 39440a6dd7bSThanh Quan clocks = <&cpg CPG_MOD 912>; 39540a6dd7bSThanh Quan clock-names = "fck"; 39640a6dd7bSThanh Quan power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 39740a6dd7bSThanh Quan resets = <&cpg 912>; 39840a6dd7bSThanh Quan status = "disabled"; 39940a6dd7bSThanh Quan }; 40040a6dd7bSThanh Quan 40140a6dd7bSThanh Quan cmt3: timer@e6148000 { 40240a6dd7bSThanh Quan compatible = "renesas,r8a779g0-cmt1", 40340a6dd7bSThanh Quan "renesas,rcar-gen4-cmt1"; 40440a6dd7bSThanh Quan reg = <0 0xe6148000 0 0x1004>; 40540a6dd7bSThanh Quan interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 40640a6dd7bSThanh Quan <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 40740a6dd7bSThanh Quan <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 40840a6dd7bSThanh Quan <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 40940a6dd7bSThanh Quan <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 41040a6dd7bSThanh Quan <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 41140a6dd7bSThanh Quan <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 41240a6dd7bSThanh Quan <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 41340a6dd7bSThanh Quan clocks = <&cpg CPG_MOD 913>; 41440a6dd7bSThanh Quan clock-names = "fck"; 41540a6dd7bSThanh Quan power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 41640a6dd7bSThanh Quan resets = <&cpg 913>; 41740a6dd7bSThanh Quan status = "disabled"; 41840a6dd7bSThanh Quan }; 41940a6dd7bSThanh Quan 420987da486SYoshihiro Shimoda cpg: clock-controller@e6150000 { 421987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0-cpg-mssr"; 422987da486SYoshihiro Shimoda reg = <0 0xe6150000 0 0x4000>; 423987da486SYoshihiro Shimoda clocks = <&extal_clk>, <&extalr_clk>; 424987da486SYoshihiro Shimoda clock-names = "extal", "extalr"; 425987da486SYoshihiro Shimoda #clock-cells = <2>; 426987da486SYoshihiro Shimoda #power-domain-cells = <0>; 427987da486SYoshihiro Shimoda #reset-cells = <1>; 428987da486SYoshihiro Shimoda }; 429987da486SYoshihiro Shimoda 430987da486SYoshihiro Shimoda rst: reset-controller@e6160000 { 431987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0-rst"; 432987da486SYoshihiro Shimoda reg = <0 0xe6160000 0 0x4000>; 433987da486SYoshihiro Shimoda }; 434987da486SYoshihiro Shimoda 435987da486SYoshihiro Shimoda sysc: system-controller@e6180000 { 436987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0-sysc"; 437987da486SYoshihiro Shimoda reg = <0 0xe6180000 0 0x4000>; 438987da486SYoshihiro Shimoda #power-domain-cells = <1>; 439987da486SYoshihiro Shimoda }; 440987da486SYoshihiro Shimoda 441d8ac71d2SGeert Uytterhoeven tsc: thermal@e6198000 { 442d8ac71d2SGeert Uytterhoeven compatible = "renesas,r8a779g0-thermal"; 443d8ac71d2SGeert Uytterhoeven reg = <0 0xe6198000 0 0x200>, 444d8ac71d2SGeert Uytterhoeven <0 0xe61a0000 0 0x200>, 445d8ac71d2SGeert Uytterhoeven <0 0xe61a8000 0 0x200>, 446d8ac71d2SGeert Uytterhoeven <0 0xe61b0000 0 0x200>; 447d8ac71d2SGeert Uytterhoeven clocks = <&cpg CPG_MOD 919>; 448d8ac71d2SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 449d8ac71d2SGeert Uytterhoeven resets = <&cpg 919>; 450d8ac71d2SGeert Uytterhoeven #thermal-sensor-cells = <1>; 451d8ac71d2SGeert Uytterhoeven }; 452d8ac71d2SGeert Uytterhoeven 453b6ce840bSGeert Uytterhoeven intc_ex: interrupt-controller@e61c0000 { 454b6ce840bSGeert Uytterhoeven compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc"; 455b6ce840bSGeert Uytterhoeven #interrupt-cells = <2>; 456b6ce840bSGeert Uytterhoeven interrupt-controller; 457b6ce840bSGeert Uytterhoeven reg = <0 0xe61c0000 0 0x200>; 458b6ce840bSGeert Uytterhoeven interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 459b6ce840bSGeert Uytterhoeven <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 460b6ce840bSGeert Uytterhoeven <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 461b6ce840bSGeert Uytterhoeven <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 462b6ce840bSGeert Uytterhoeven <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 463b6ce840bSGeert Uytterhoeven <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 464b6ce840bSGeert Uytterhoeven clocks = <&cpg CPG_MOD 611>; 465b6ce840bSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 466b6ce840bSGeert Uytterhoeven resets = <&cpg 611>; 467b6ce840bSGeert Uytterhoeven }; 468b6ce840bSGeert Uytterhoeven 46952478925SWolfram Sang tmu0: timer@e61e0000 { 47052478925SWolfram Sang compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 47152478925SWolfram Sang reg = <0 0xe61e0000 0 0x30>; 47252478925SWolfram Sang interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 47352478925SWolfram Sang <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 47452478925SWolfram Sang <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; 47552478925SWolfram Sang clocks = <&cpg CPG_MOD 713>; 47652478925SWolfram Sang clock-names = "fck"; 47752478925SWolfram Sang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 47852478925SWolfram Sang resets = <&cpg 713>; 47952478925SWolfram Sang status = "disabled"; 48052478925SWolfram Sang }; 48152478925SWolfram Sang 48252478925SWolfram Sang tmu1: timer@e6fc0000 { 48352478925SWolfram Sang compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 48452478925SWolfram Sang reg = <0 0xe6fc0000 0 0x30>; 48552478925SWolfram Sang interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 48652478925SWolfram Sang <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 48752478925SWolfram Sang <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 48852478925SWolfram Sang clocks = <&cpg CPG_MOD 714>; 48952478925SWolfram Sang clock-names = "fck"; 49052478925SWolfram Sang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 49152478925SWolfram Sang resets = <&cpg 714>; 49252478925SWolfram Sang status = "disabled"; 49352478925SWolfram Sang }; 49452478925SWolfram Sang 49552478925SWolfram Sang tmu2: timer@e6fd0000 { 49652478925SWolfram Sang compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 49752478925SWolfram Sang reg = <0 0xe6fd0000 0 0x30>; 49852478925SWolfram Sang interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 49952478925SWolfram Sang <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 50052478925SWolfram Sang <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 50152478925SWolfram Sang clocks = <&cpg CPG_MOD 715>; 50252478925SWolfram Sang clock-names = "fck"; 50352478925SWolfram Sang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 50452478925SWolfram Sang resets = <&cpg 715>; 50552478925SWolfram Sang status = "disabled"; 50652478925SWolfram Sang }; 50752478925SWolfram Sang 50852478925SWolfram Sang tmu3: timer@e6fe0000 { 50952478925SWolfram Sang compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 51052478925SWolfram Sang reg = <0 0xe6fe0000 0 0x30>; 51152478925SWolfram Sang interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 51252478925SWolfram Sang <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51352478925SWolfram Sang <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 51452478925SWolfram Sang clocks = <&cpg CPG_MOD 716>; 51552478925SWolfram Sang clock-names = "fck"; 51652478925SWolfram Sang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 51752478925SWolfram Sang resets = <&cpg 716>; 51852478925SWolfram Sang status = "disabled"; 51952478925SWolfram Sang }; 52052478925SWolfram Sang 52152478925SWolfram Sang tmu4: timer@ffc00000 { 52252478925SWolfram Sang compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 52352478925SWolfram Sang reg = <0 0xffc00000 0 0x30>; 52452478925SWolfram Sang interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 52552478925SWolfram Sang <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 52652478925SWolfram Sang <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 52752478925SWolfram Sang clocks = <&cpg CPG_MOD 717>; 52852478925SWolfram Sang clock-names = "fck"; 52952478925SWolfram Sang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 53052478925SWolfram Sang resets = <&cpg 717>; 53152478925SWolfram Sang status = "disabled"; 53252478925SWolfram Sang }; 53352478925SWolfram Sang 534ff77ba05SGeert Uytterhoeven i2c0: i2c@e6500000 { 535ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 536ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 537ff77ba05SGeert Uytterhoeven reg = <0 0xe6500000 0 0x40>; 538ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 539ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 518>; 54008f28288SGeert Uytterhoeven dmas = <&dmac0 0x91>, <&dmac0 0x90>, 54108f28288SGeert Uytterhoeven <&dmac1 0x91>, <&dmac1 0x90>; 54208f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 543ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 544ff77ba05SGeert Uytterhoeven resets = <&cpg 518>; 545ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 546ff77ba05SGeert Uytterhoeven #address-cells = <1>; 547ff77ba05SGeert Uytterhoeven #size-cells = <0>; 548ff77ba05SGeert Uytterhoeven status = "disabled"; 549ff77ba05SGeert Uytterhoeven }; 550ff77ba05SGeert Uytterhoeven 551ff77ba05SGeert Uytterhoeven i2c1: i2c@e6508000 { 552ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 553ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 554ff77ba05SGeert Uytterhoeven reg = <0 0xe6508000 0 0x40>; 555ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; 556ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 519>; 55708f28288SGeert Uytterhoeven dmas = <&dmac0 0x93>, <&dmac0 0x92>, 55808f28288SGeert Uytterhoeven <&dmac1 0x93>, <&dmac1 0x92>; 55908f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 560ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 561ff77ba05SGeert Uytterhoeven resets = <&cpg 519>; 562ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 563ff77ba05SGeert Uytterhoeven #address-cells = <1>; 564ff77ba05SGeert Uytterhoeven #size-cells = <0>; 565ff77ba05SGeert Uytterhoeven status = "disabled"; 566ff77ba05SGeert Uytterhoeven }; 567ff77ba05SGeert Uytterhoeven 568ff77ba05SGeert Uytterhoeven i2c2: i2c@e6510000 { 569ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 570ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 571ff77ba05SGeert Uytterhoeven reg = <0 0xe6510000 0 0x40>; 572ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; 573ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 520>; 57408f28288SGeert Uytterhoeven dmas = <&dmac0 0x95>, <&dmac0 0x94>, 57508f28288SGeert Uytterhoeven <&dmac1 0x95>, <&dmac1 0x94>; 57608f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 577ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 578ff77ba05SGeert Uytterhoeven resets = <&cpg 520>; 579ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 580ff77ba05SGeert Uytterhoeven #address-cells = <1>; 581ff77ba05SGeert Uytterhoeven #size-cells = <0>; 582ff77ba05SGeert Uytterhoeven status = "disabled"; 583ff77ba05SGeert Uytterhoeven }; 584ff77ba05SGeert Uytterhoeven 585ff77ba05SGeert Uytterhoeven i2c3: i2c@e66d0000 { 586ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 587ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 588ff77ba05SGeert Uytterhoeven reg = <0 0xe66d0000 0 0x40>; 589ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 590ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 521>; 59108f28288SGeert Uytterhoeven dmas = <&dmac0 0x97>, <&dmac0 0x96>, 59208f28288SGeert Uytterhoeven <&dmac1 0x97>, <&dmac1 0x96>; 59308f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 594ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 595ff77ba05SGeert Uytterhoeven resets = <&cpg 521>; 596ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 597ff77ba05SGeert Uytterhoeven #address-cells = <1>; 598ff77ba05SGeert Uytterhoeven #size-cells = <0>; 599ff77ba05SGeert Uytterhoeven status = "disabled"; 600ff77ba05SGeert Uytterhoeven }; 601ff77ba05SGeert Uytterhoeven 602ff77ba05SGeert Uytterhoeven i2c4: i2c@e66d8000 { 603ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 604ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 605ff77ba05SGeert Uytterhoeven reg = <0 0xe66d8000 0 0x40>; 606ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 607ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 522>; 60808f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 60908f28288SGeert Uytterhoeven dmas = <&dmac0 0x99>, <&dmac0 0x98>, 61008f28288SGeert Uytterhoeven <&dmac1 0x99>, <&dmac1 0x98>; 611ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 612ff77ba05SGeert Uytterhoeven resets = <&cpg 522>; 613ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 614ff77ba05SGeert Uytterhoeven #address-cells = <1>; 615ff77ba05SGeert Uytterhoeven #size-cells = <0>; 616ff77ba05SGeert Uytterhoeven status = "disabled"; 617ff77ba05SGeert Uytterhoeven }; 618ff77ba05SGeert Uytterhoeven 619ff77ba05SGeert Uytterhoeven i2c5: i2c@e66e0000 { 620ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 621ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 622ff77ba05SGeert Uytterhoeven reg = <0 0xe66e0000 0 0x40>; 623ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>; 624ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 523>; 62508f28288SGeert Uytterhoeven dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 62608f28288SGeert Uytterhoeven <&dmac1 0x9b>, <&dmac1 0x9a>; 62708f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 628ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 629ff77ba05SGeert Uytterhoeven resets = <&cpg 523>; 630ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 631ff77ba05SGeert Uytterhoeven #address-cells = <1>; 632ff77ba05SGeert Uytterhoeven #size-cells = <0>; 633ff77ba05SGeert Uytterhoeven status = "disabled"; 634ff77ba05SGeert Uytterhoeven }; 635ff77ba05SGeert Uytterhoeven 636987da486SYoshihiro Shimoda hscif0: serial@e6540000 { 637987da486SYoshihiro Shimoda compatible = "renesas,hscif-r8a779g0", 63839d9dfc6SGeert Uytterhoeven "renesas,rcar-gen4-hscif", "renesas,hscif"; 63939d9dfc6SGeert Uytterhoeven reg = <0 0xe6540000 0 0x60>; 640ab2866f1SGeert Uytterhoeven interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 641987da486SYoshihiro Shimoda clocks = <&cpg CPG_MOD 514>, 642a4290d40SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 643987da486SYoshihiro Shimoda <&scif_clk>; 644987da486SYoshihiro Shimoda clock-names = "fck", "brg_int", "scif_clk"; 64508f28288SGeert Uytterhoeven dmas = <&dmac0 0x31>, <&dmac0 0x30>, 64608f28288SGeert Uytterhoeven <&dmac1 0x31>, <&dmac1 0x30>; 64708f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 648987da486SYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 649987da486SYoshihiro Shimoda resets = <&cpg 514>; 650987da486SYoshihiro Shimoda status = "disabled"; 651987da486SYoshihiro Shimoda }; 652987da486SYoshihiro Shimoda 65339d9dfc6SGeert Uytterhoeven hscif1: serial@e6550000 { 65439d9dfc6SGeert Uytterhoeven compatible = "renesas,hscif-r8a779g0", 65539d9dfc6SGeert Uytterhoeven "renesas,rcar-gen4-hscif", "renesas,hscif"; 65639d9dfc6SGeert Uytterhoeven reg = <0 0xe6550000 0 0x60>; 65739d9dfc6SGeert Uytterhoeven interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 65839d9dfc6SGeert Uytterhoeven clocks = <&cpg CPG_MOD 515>, 65939d9dfc6SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 66039d9dfc6SGeert Uytterhoeven <&scif_clk>; 66139d9dfc6SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 66239d9dfc6SGeert Uytterhoeven dmas = <&dmac0 0x33>, <&dmac0 0x32>, 66339d9dfc6SGeert Uytterhoeven <&dmac1 0x33>, <&dmac1 0x32>; 66439d9dfc6SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 66539d9dfc6SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 66639d9dfc6SGeert Uytterhoeven resets = <&cpg 515>; 66739d9dfc6SGeert Uytterhoeven status = "disabled"; 66839d9dfc6SGeert Uytterhoeven }; 66939d9dfc6SGeert Uytterhoeven 67039d9dfc6SGeert Uytterhoeven hscif2: serial@e6560000 { 67139d9dfc6SGeert Uytterhoeven compatible = "renesas,hscif-r8a779g0", 67239d9dfc6SGeert Uytterhoeven "renesas,rcar-gen4-hscif", "renesas,hscif"; 67339d9dfc6SGeert Uytterhoeven reg = <0 0xe6560000 0 0x60>; 67439d9dfc6SGeert Uytterhoeven interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 67539d9dfc6SGeert Uytterhoeven clocks = <&cpg CPG_MOD 516>, 67639d9dfc6SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 67739d9dfc6SGeert Uytterhoeven <&scif_clk>; 67839d9dfc6SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 67939d9dfc6SGeert Uytterhoeven dmas = <&dmac0 0x35>, <&dmac0 0x34>, 68039d9dfc6SGeert Uytterhoeven <&dmac1 0x35>, <&dmac1 0x34>; 68139d9dfc6SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 68239d9dfc6SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 68339d9dfc6SGeert Uytterhoeven resets = <&cpg 516>; 68439d9dfc6SGeert Uytterhoeven status = "disabled"; 68539d9dfc6SGeert Uytterhoeven }; 68639d9dfc6SGeert Uytterhoeven 68739d9dfc6SGeert Uytterhoeven hscif3: serial@e66a0000 { 68839d9dfc6SGeert Uytterhoeven compatible = "renesas,hscif-r8a779g0", 68939d9dfc6SGeert Uytterhoeven "renesas,rcar-gen4-hscif", "renesas,hscif"; 69039d9dfc6SGeert Uytterhoeven reg = <0 0xe66a0000 0 0x60>; 69139d9dfc6SGeert Uytterhoeven interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 69239d9dfc6SGeert Uytterhoeven clocks = <&cpg CPG_MOD 517>, 69339d9dfc6SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 69439d9dfc6SGeert Uytterhoeven <&scif_clk>; 69539d9dfc6SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 69639d9dfc6SGeert Uytterhoeven dmas = <&dmac0 0x37>, <&dmac0 0x36>, 69739d9dfc6SGeert Uytterhoeven <&dmac1 0x37>, <&dmac1 0x36>; 69839d9dfc6SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 69939d9dfc6SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 70039d9dfc6SGeert Uytterhoeven resets = <&cpg 517>; 70139d9dfc6SGeert Uytterhoeven status = "disabled"; 70239d9dfc6SGeert Uytterhoeven }; 70339d9dfc6SGeert Uytterhoeven 7045056a0c7SGeert Uytterhoeven canfd: can@e6660000 { 7055056a0c7SGeert Uytterhoeven compatible = "renesas,r8a779g0-canfd", 7065056a0c7SGeert Uytterhoeven "renesas,rcar-gen4-canfd"; 7075056a0c7SGeert Uytterhoeven reg = <0 0xe6660000 0 0x8500>; 7085056a0c7SGeert Uytterhoeven interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 7095056a0c7SGeert Uytterhoeven <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 7105056a0c7SGeert Uytterhoeven interrupt-names = "ch_int", "g_int"; 7115056a0c7SGeert Uytterhoeven clocks = <&cpg CPG_MOD 328>, 7125056a0c7SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_CANFD>, 7135056a0c7SGeert Uytterhoeven <&can_clk>; 7145056a0c7SGeert Uytterhoeven clock-names = "fck", "canfd", "can_clk"; 7155056a0c7SGeert Uytterhoeven assigned-clocks = <&cpg CPG_CORE R8A779G0_CLK_CANFD>; 7165056a0c7SGeert Uytterhoeven assigned-clock-rates = <80000000>; 7175056a0c7SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 7185056a0c7SGeert Uytterhoeven resets = <&cpg 328>; 7195056a0c7SGeert Uytterhoeven status = "disabled"; 7205056a0c7SGeert Uytterhoeven 7215056a0c7SGeert Uytterhoeven channel0 { 7225056a0c7SGeert Uytterhoeven status = "disabled"; 7235056a0c7SGeert Uytterhoeven }; 7245056a0c7SGeert Uytterhoeven 7255056a0c7SGeert Uytterhoeven channel1 { 7265056a0c7SGeert Uytterhoeven status = "disabled"; 7275056a0c7SGeert Uytterhoeven }; 7285056a0c7SGeert Uytterhoeven 7295056a0c7SGeert Uytterhoeven channel2 { 7305056a0c7SGeert Uytterhoeven status = "disabled"; 7315056a0c7SGeert Uytterhoeven }; 7325056a0c7SGeert Uytterhoeven 7335056a0c7SGeert Uytterhoeven channel3 { 7345056a0c7SGeert Uytterhoeven status = "disabled"; 7355056a0c7SGeert Uytterhoeven }; 7365056a0c7SGeert Uytterhoeven 7375056a0c7SGeert Uytterhoeven channel4 { 7385056a0c7SGeert Uytterhoeven status = "disabled"; 7395056a0c7SGeert Uytterhoeven }; 7405056a0c7SGeert Uytterhoeven 7415056a0c7SGeert Uytterhoeven channel5 { 7425056a0c7SGeert Uytterhoeven status = "disabled"; 7435056a0c7SGeert Uytterhoeven }; 7445056a0c7SGeert Uytterhoeven 7455056a0c7SGeert Uytterhoeven channel6 { 7465056a0c7SGeert Uytterhoeven status = "disabled"; 7475056a0c7SGeert Uytterhoeven }; 7485056a0c7SGeert Uytterhoeven 7495056a0c7SGeert Uytterhoeven channel7 { 7505056a0c7SGeert Uytterhoeven status = "disabled"; 7515056a0c7SGeert Uytterhoeven }; 7525056a0c7SGeert Uytterhoeven }; 7535056a0c7SGeert Uytterhoeven 754848c82dbSGeert Uytterhoeven avb0: ethernet@e6800000 { 755848c82dbSGeert Uytterhoeven compatible = "renesas,etheravb-r8a779g0", 756848c82dbSGeert Uytterhoeven "renesas,etheravb-rcar-gen4"; 757848c82dbSGeert Uytterhoeven reg = <0 0xe6800000 0 0x800>; 758848c82dbSGeert Uytterhoeven interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 759848c82dbSGeert Uytterhoeven <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 760848c82dbSGeert Uytterhoeven <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 761848c82dbSGeert Uytterhoeven <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 762848c82dbSGeert Uytterhoeven <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 763848c82dbSGeert Uytterhoeven <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 764848c82dbSGeert Uytterhoeven <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 765848c82dbSGeert Uytterhoeven <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 766848c82dbSGeert Uytterhoeven <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 767848c82dbSGeert Uytterhoeven <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 768848c82dbSGeert Uytterhoeven <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 769848c82dbSGeert Uytterhoeven <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 770848c82dbSGeert Uytterhoeven <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 771848c82dbSGeert Uytterhoeven <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 772848c82dbSGeert Uytterhoeven <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 773848c82dbSGeert Uytterhoeven <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 774848c82dbSGeert Uytterhoeven <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 775848c82dbSGeert Uytterhoeven <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 776848c82dbSGeert Uytterhoeven <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 777848c82dbSGeert Uytterhoeven <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 778848c82dbSGeert Uytterhoeven <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 779848c82dbSGeert Uytterhoeven <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 780848c82dbSGeert Uytterhoeven <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 781848c82dbSGeert Uytterhoeven <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 782848c82dbSGeert Uytterhoeven <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 783848c82dbSGeert Uytterhoeven interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", 784848c82dbSGeert Uytterhoeven "ch5", "ch6", "ch7", "ch8", "ch9", 785848c82dbSGeert Uytterhoeven "ch10", "ch11", "ch12", "ch13", 786848c82dbSGeert Uytterhoeven "ch14", "ch15", "ch16", "ch17", 787848c82dbSGeert Uytterhoeven "ch18", "ch19", "ch20", "ch21", 788848c82dbSGeert Uytterhoeven "ch22", "ch23", "ch24"; 789848c82dbSGeert Uytterhoeven clocks = <&cpg CPG_MOD 211>; 790848c82dbSGeert Uytterhoeven clock-names = "fck"; 791848c82dbSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 792848c82dbSGeert Uytterhoeven resets = <&cpg 211>; 793848c82dbSGeert Uytterhoeven phy-mode = "rgmii"; 794848c82dbSGeert Uytterhoeven rx-internal-delay-ps = <0>; 795848c82dbSGeert Uytterhoeven tx-internal-delay-ps = <0>; 796848c82dbSGeert Uytterhoeven #address-cells = <1>; 797848c82dbSGeert Uytterhoeven #size-cells = <0>; 798848c82dbSGeert Uytterhoeven status = "disabled"; 799848c82dbSGeert Uytterhoeven }; 800848c82dbSGeert Uytterhoeven 801848c82dbSGeert Uytterhoeven avb1: ethernet@e6810000 { 802848c82dbSGeert Uytterhoeven compatible = "renesas,etheravb-r8a779g0", 803848c82dbSGeert Uytterhoeven "renesas,etheravb-rcar-gen4"; 804848c82dbSGeert Uytterhoeven reg = <0 0xe6810000 0 0x800>; 805848c82dbSGeert Uytterhoeven interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 806848c82dbSGeert Uytterhoeven <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 807848c82dbSGeert Uytterhoeven <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 808848c82dbSGeert Uytterhoeven <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 809848c82dbSGeert Uytterhoeven <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 810848c82dbSGeert Uytterhoeven <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 811848c82dbSGeert Uytterhoeven <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 812848c82dbSGeert Uytterhoeven <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 813848c82dbSGeert Uytterhoeven <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 814848c82dbSGeert Uytterhoeven <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 815848c82dbSGeert Uytterhoeven <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 816848c82dbSGeert Uytterhoeven <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 817848c82dbSGeert Uytterhoeven <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 818848c82dbSGeert Uytterhoeven <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 819848c82dbSGeert Uytterhoeven <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 820848c82dbSGeert Uytterhoeven <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 821848c82dbSGeert Uytterhoeven <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 822848c82dbSGeert Uytterhoeven <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 823848c82dbSGeert Uytterhoeven <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 824848c82dbSGeert Uytterhoeven <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 825848c82dbSGeert Uytterhoeven <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 826848c82dbSGeert Uytterhoeven <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 827848c82dbSGeert Uytterhoeven <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 828848c82dbSGeert Uytterhoeven <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 829848c82dbSGeert Uytterhoeven <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 830848c82dbSGeert Uytterhoeven interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", 831848c82dbSGeert Uytterhoeven "ch5", "ch6", "ch7", "ch8", "ch9", 832848c82dbSGeert Uytterhoeven "ch10", "ch11", "ch12", "ch13", 833848c82dbSGeert Uytterhoeven "ch14", "ch15", "ch16", "ch17", 834848c82dbSGeert Uytterhoeven "ch18", "ch19", "ch20", "ch21", 835848c82dbSGeert Uytterhoeven "ch22", "ch23", "ch24"; 836848c82dbSGeert Uytterhoeven clocks = <&cpg CPG_MOD 212>; 837848c82dbSGeert Uytterhoeven clock-names = "fck"; 838848c82dbSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 839848c82dbSGeert Uytterhoeven resets = <&cpg 212>; 840848c82dbSGeert Uytterhoeven phy-mode = "rgmii"; 841848c82dbSGeert Uytterhoeven rx-internal-delay-ps = <0>; 842848c82dbSGeert Uytterhoeven tx-internal-delay-ps = <0>; 843848c82dbSGeert Uytterhoeven #address-cells = <1>; 844848c82dbSGeert Uytterhoeven #size-cells = <0>; 845848c82dbSGeert Uytterhoeven status = "disabled"; 846848c82dbSGeert Uytterhoeven }; 847848c82dbSGeert Uytterhoeven 848848c82dbSGeert Uytterhoeven avb2: ethernet@e6820000 { 849848c82dbSGeert Uytterhoeven compatible = "renesas,etheravb-r8a779g0", 850848c82dbSGeert Uytterhoeven "renesas,etheravb-rcar-gen4"; 851848c82dbSGeert Uytterhoeven reg = <0 0xe6820000 0 0x1000>; 852848c82dbSGeert Uytterhoeven interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 853848c82dbSGeert Uytterhoeven <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 854848c82dbSGeert Uytterhoeven <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 855848c82dbSGeert Uytterhoeven <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 856848c82dbSGeert Uytterhoeven <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 857848c82dbSGeert Uytterhoeven <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 858848c82dbSGeert Uytterhoeven <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 859848c82dbSGeert Uytterhoeven <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 860848c82dbSGeert Uytterhoeven <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 861848c82dbSGeert Uytterhoeven <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 862848c82dbSGeert Uytterhoeven <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 863848c82dbSGeert Uytterhoeven <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 864848c82dbSGeert Uytterhoeven <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 865848c82dbSGeert Uytterhoeven <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 866848c82dbSGeert Uytterhoeven <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 867848c82dbSGeert Uytterhoeven <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 868848c82dbSGeert Uytterhoeven <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 869848c82dbSGeert Uytterhoeven <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 870848c82dbSGeert Uytterhoeven <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 871848c82dbSGeert Uytterhoeven <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 872848c82dbSGeert Uytterhoeven <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 873848c82dbSGeert Uytterhoeven <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 874848c82dbSGeert Uytterhoeven <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 875848c82dbSGeert Uytterhoeven <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 876848c82dbSGeert Uytterhoeven <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 877848c82dbSGeert Uytterhoeven interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", 878848c82dbSGeert Uytterhoeven "ch5", "ch6", "ch7", "ch8", "ch9", 879848c82dbSGeert Uytterhoeven "ch10", "ch11", "ch12", "ch13", 880848c82dbSGeert Uytterhoeven "ch14", "ch15", "ch16", "ch17", 881848c82dbSGeert Uytterhoeven "ch18", "ch19", "ch20", "ch21", 882848c82dbSGeert Uytterhoeven "ch22", "ch23", "ch24"; 883848c82dbSGeert Uytterhoeven clocks = <&cpg CPG_MOD 213>; 884848c82dbSGeert Uytterhoeven clock-names = "fck"; 885848c82dbSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 886848c82dbSGeert Uytterhoeven resets = <&cpg 213>; 887848c82dbSGeert Uytterhoeven phy-mode = "rgmii"; 888848c82dbSGeert Uytterhoeven rx-internal-delay-ps = <0>; 889848c82dbSGeert Uytterhoeven tx-internal-delay-ps = <0>; 890848c82dbSGeert Uytterhoeven #address-cells = <1>; 891848c82dbSGeert Uytterhoeven #size-cells = <0>; 892848c82dbSGeert Uytterhoeven status = "disabled"; 893848c82dbSGeert Uytterhoeven }; 894848c82dbSGeert Uytterhoeven 8955b9d1306SCongDang pwm0: pwm@e6e30000 { 8965b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 8975b9d1306SCongDang reg = <0 0xe6e30000 0 0x10>; 8985b9d1306SCongDang #pwm-cells = <2>; 8995b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9005b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9015b9d1306SCongDang resets = <&cpg 628>; 9025b9d1306SCongDang status = "disabled"; 9035b9d1306SCongDang }; 9045b9d1306SCongDang 9055b9d1306SCongDang pwm1: pwm@e6e31000 { 9065b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9075b9d1306SCongDang reg = <0 0xe6e31000 0 0x10>; 9085b9d1306SCongDang #pwm-cells = <2>; 9095b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9105b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9115b9d1306SCongDang resets = <&cpg 628>; 9125b9d1306SCongDang status = "disabled"; 9135b9d1306SCongDang }; 9145b9d1306SCongDang 9155b9d1306SCongDang pwm2: pwm@e6e32000 { 9165b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9175b9d1306SCongDang reg = <0 0xe6e32000 0 0x10>; 9185b9d1306SCongDang #pwm-cells = <2>; 9195b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9205b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9215b9d1306SCongDang resets = <&cpg 628>; 9225b9d1306SCongDang status = "disabled"; 9235b9d1306SCongDang }; 9245b9d1306SCongDang 9255b9d1306SCongDang pwm3: pwm@e6e33000 { 9265b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9275b9d1306SCongDang reg = <0 0xe6e33000 0 0x10>; 9285b9d1306SCongDang #pwm-cells = <2>; 9295b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9305b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9315b9d1306SCongDang resets = <&cpg 628>; 9325b9d1306SCongDang status = "disabled"; 9335b9d1306SCongDang }; 9345b9d1306SCongDang 9355b9d1306SCongDang pwm4: pwm@e6e34000 { 9365b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9375b9d1306SCongDang reg = <0 0xe6e34000 0 0x10>; 9385b9d1306SCongDang #pwm-cells = <2>; 9395b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9405b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9415b9d1306SCongDang resets = <&cpg 628>; 9425b9d1306SCongDang status = "disabled"; 9435b9d1306SCongDang }; 9445b9d1306SCongDang 9455b9d1306SCongDang pwm5: pwm@e6e35000 { 9465b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9475b9d1306SCongDang reg = <0 0xe6e35000 0 0x10>; 9485b9d1306SCongDang #pwm-cells = <2>; 9495b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9505b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9515b9d1306SCongDang resets = <&cpg 628>; 9525b9d1306SCongDang status = "disabled"; 9535b9d1306SCongDang }; 9545b9d1306SCongDang 9555b9d1306SCongDang pwm6: pwm@e6e36000 { 9565b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9575b9d1306SCongDang reg = <0 0xe6e36000 0 0x10>; 9585b9d1306SCongDang #pwm-cells = <2>; 9595b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9605b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9615b9d1306SCongDang resets = <&cpg 628>; 9625b9d1306SCongDang status = "disabled"; 9635b9d1306SCongDang }; 9645b9d1306SCongDang 9655b9d1306SCongDang pwm7: pwm@e6e37000 { 9665b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9675b9d1306SCongDang reg = <0 0xe6e37000 0 0x10>; 9685b9d1306SCongDang #pwm-cells = <2>; 9695b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9705b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9715b9d1306SCongDang resets = <&cpg 628>; 9725b9d1306SCongDang status = "disabled"; 9735b9d1306SCongDang }; 9745b9d1306SCongDang 9755b9d1306SCongDang pwm8: pwm@e6e38000 { 9765b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9775b9d1306SCongDang reg = <0 0xe6e38000 0 0x10>; 9785b9d1306SCongDang #pwm-cells = <2>; 9795b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9805b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9815b9d1306SCongDang resets = <&cpg 628>; 9825b9d1306SCongDang status = "disabled"; 9835b9d1306SCongDang }; 9845b9d1306SCongDang 9855b9d1306SCongDang pwm9: pwm@e6e39000 { 9865b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9875b9d1306SCongDang reg = <0 0xe6e39000 0 0x10>; 9885b9d1306SCongDang #pwm-cells = <2>; 9895b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9905b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9915b9d1306SCongDang resets = <&cpg 628>; 9925b9d1306SCongDang status = "disabled"; 9935b9d1306SCongDang }; 9945b9d1306SCongDang 995a4c31c56SGeert Uytterhoeven scif0: serial@e6e60000 { 996a4c31c56SGeert Uytterhoeven compatible = "renesas,scif-r8a779g0", 997a4c31c56SGeert Uytterhoeven "renesas,rcar-gen4-scif", "renesas,scif"; 998a4c31c56SGeert Uytterhoeven reg = <0 0xe6e60000 0 64>; 999a4c31c56SGeert Uytterhoeven interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 1000a4c31c56SGeert Uytterhoeven clocks = <&cpg CPG_MOD 702>, 1001a4c31c56SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 1002a4c31c56SGeert Uytterhoeven <&scif_clk>; 1003a4c31c56SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 1004a4c31c56SGeert Uytterhoeven dmas = <&dmac0 0x51>, <&dmac0 0x50>, 1005a4c31c56SGeert Uytterhoeven <&dmac1 0x51>, <&dmac1 0x50>; 1006a4c31c56SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1007a4c31c56SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1008a4c31c56SGeert Uytterhoeven resets = <&cpg 702>; 1009a4c31c56SGeert Uytterhoeven status = "disabled"; 1010a4c31c56SGeert Uytterhoeven }; 1011a4c31c56SGeert Uytterhoeven 1012a4c31c56SGeert Uytterhoeven scif1: serial@e6e68000 { 1013a4c31c56SGeert Uytterhoeven compatible = "renesas,scif-r8a779g0", 1014a4c31c56SGeert Uytterhoeven "renesas,rcar-gen4-scif", "renesas,scif"; 1015a4c31c56SGeert Uytterhoeven reg = <0 0xe6e68000 0 64>; 1016a4c31c56SGeert Uytterhoeven interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 1017a4c31c56SGeert Uytterhoeven clocks = <&cpg CPG_MOD 703>, 1018a4c31c56SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 1019a4c31c56SGeert Uytterhoeven <&scif_clk>; 1020a4c31c56SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 1021a4c31c56SGeert Uytterhoeven dmas = <&dmac0 0x53>, <&dmac0 0x52>, 1022a4c31c56SGeert Uytterhoeven <&dmac1 0x53>, <&dmac1 0x52>; 1023a4c31c56SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1024a4c31c56SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1025a4c31c56SGeert Uytterhoeven resets = <&cpg 703>; 1026a4c31c56SGeert Uytterhoeven status = "disabled"; 1027a4c31c56SGeert Uytterhoeven }; 1028a4c31c56SGeert Uytterhoeven 1029a4c31c56SGeert Uytterhoeven scif3: serial@e6c50000 { 1030a4c31c56SGeert Uytterhoeven compatible = "renesas,scif-r8a779g0", 1031a4c31c56SGeert Uytterhoeven "renesas,rcar-gen4-scif", "renesas,scif"; 1032a4c31c56SGeert Uytterhoeven reg = <0 0xe6c50000 0 64>; 1033a4c31c56SGeert Uytterhoeven interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 1034a4c31c56SGeert Uytterhoeven clocks = <&cpg CPG_MOD 704>, 1035a4c31c56SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 1036a4c31c56SGeert Uytterhoeven <&scif_clk>; 1037a4c31c56SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 1038a4c31c56SGeert Uytterhoeven dmas = <&dmac0 0x57>, <&dmac0 0x56>, 1039a4c31c56SGeert Uytterhoeven <&dmac1 0x57>, <&dmac1 0x56>; 1040a4c31c56SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1041a4c31c56SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1042a4c31c56SGeert Uytterhoeven resets = <&cpg 704>; 1043a4c31c56SGeert Uytterhoeven status = "disabled"; 1044a4c31c56SGeert Uytterhoeven }; 1045a4c31c56SGeert Uytterhoeven 1046a4c31c56SGeert Uytterhoeven scif4: serial@e6c40000 { 1047a4c31c56SGeert Uytterhoeven compatible = "renesas,scif-r8a779g0", 1048a4c31c56SGeert Uytterhoeven "renesas,rcar-gen4-scif", "renesas,scif"; 1049a4c31c56SGeert Uytterhoeven reg = <0 0xe6c40000 0 64>; 1050a4c31c56SGeert Uytterhoeven interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1051a4c31c56SGeert Uytterhoeven clocks = <&cpg CPG_MOD 705>, 1052a4c31c56SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 1053a4c31c56SGeert Uytterhoeven <&scif_clk>; 1054a4c31c56SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 1055a4c31c56SGeert Uytterhoeven dmas = <&dmac0 0x59>, <&dmac0 0x58>, 1056a4c31c56SGeert Uytterhoeven <&dmac1 0x59>, <&dmac1 0x58>; 1057a4c31c56SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1058a4c31c56SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1059a4c31c56SGeert Uytterhoeven resets = <&cpg 705>; 1060a4c31c56SGeert Uytterhoeven status = "disabled"; 1061a4c31c56SGeert Uytterhoeven }; 1062a4c31c56SGeert Uytterhoeven 10634a76d4abSCongDang tpu: pwm@e6e80000 { 10644a76d4abSCongDang compatible = "renesas,tpu-r8a779g0", "renesas,tpu"; 10654a76d4abSCongDang reg = <0 0xe6e80000 0 0x148>; 10664a76d4abSCongDang interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 10674a76d4abSCongDang clocks = <&cpg CPG_MOD 718>; 10684a76d4abSCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 10694a76d4abSCongDang resets = <&cpg 718>; 10704a76d4abSCongDang #pwm-cells = <3>; 10714a76d4abSCongDang status = "disabled"; 10724a76d4abSCongDang }; 10734a76d4abSCongDang 1074e0768073SGeert Uytterhoeven msiof0: spi@e6e90000 { 1075e0768073SGeert Uytterhoeven compatible = "renesas,msiof-r8a779g0", 1076e0768073SGeert Uytterhoeven "renesas,rcar-gen4-msiof"; 1077e0768073SGeert Uytterhoeven reg = <0 0xe6e90000 0 0x0064>; 1078e0768073SGeert Uytterhoeven interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1079e0768073SGeert Uytterhoeven clocks = <&cpg CPG_MOD 618>; 1080e0768073SGeert Uytterhoeven dmas = <&dmac0 0x41>, <&dmac0 0x40>, 1081e0768073SGeert Uytterhoeven <&dmac1 0x41>, <&dmac1 0x40>; 1082e0768073SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1083e0768073SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1084e0768073SGeert Uytterhoeven resets = <&cpg 618>; 1085e0768073SGeert Uytterhoeven #address-cells = <1>; 1086e0768073SGeert Uytterhoeven #size-cells = <0>; 1087e0768073SGeert Uytterhoeven status = "disabled"; 1088e0768073SGeert Uytterhoeven }; 1089e0768073SGeert Uytterhoeven 1090e0768073SGeert Uytterhoeven msiof1: spi@e6ea0000 { 1091e0768073SGeert Uytterhoeven compatible = "renesas,msiof-r8a779g0", 1092e0768073SGeert Uytterhoeven "renesas,rcar-gen4-msiof"; 1093e0768073SGeert Uytterhoeven reg = <0 0xe6ea0000 0 0x0064>; 1094e0768073SGeert Uytterhoeven interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1095e0768073SGeert Uytterhoeven clocks = <&cpg CPG_MOD 619>; 1096e0768073SGeert Uytterhoeven dmas = <&dmac0 0x43>, <&dmac0 0x42>, 1097e0768073SGeert Uytterhoeven <&dmac1 0x43>, <&dmac1 0x42>; 1098e0768073SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1099e0768073SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1100e0768073SGeert Uytterhoeven resets = <&cpg 619>; 1101e0768073SGeert Uytterhoeven #address-cells = <1>; 1102e0768073SGeert Uytterhoeven #size-cells = <0>; 1103e0768073SGeert Uytterhoeven status = "disabled"; 1104e0768073SGeert Uytterhoeven }; 1105e0768073SGeert Uytterhoeven 1106e0768073SGeert Uytterhoeven msiof2: spi@e6c00000 { 1107e0768073SGeert Uytterhoeven compatible = "renesas,msiof-r8a779g0", 1108e0768073SGeert Uytterhoeven "renesas,rcar-gen4-msiof"; 1109e0768073SGeert Uytterhoeven reg = <0 0xe6c00000 0 0x0064>; 1110e0768073SGeert Uytterhoeven interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1111e0768073SGeert Uytterhoeven clocks = <&cpg CPG_MOD 620>; 1112e0768073SGeert Uytterhoeven dmas = <&dmac0 0x45>, <&dmac0 0x44>, 1113e0768073SGeert Uytterhoeven <&dmac1 0x45>, <&dmac1 0x44>; 1114e0768073SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1115e0768073SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1116e0768073SGeert Uytterhoeven resets = <&cpg 620>; 1117e0768073SGeert Uytterhoeven #address-cells = <1>; 1118e0768073SGeert Uytterhoeven #size-cells = <0>; 1119e0768073SGeert Uytterhoeven status = "disabled"; 1120e0768073SGeert Uytterhoeven }; 1121e0768073SGeert Uytterhoeven 1122e0768073SGeert Uytterhoeven msiof3: spi@e6c10000 { 1123e0768073SGeert Uytterhoeven compatible = "renesas,msiof-r8a779g0", 1124e0768073SGeert Uytterhoeven "renesas,rcar-gen4-msiof"; 1125e0768073SGeert Uytterhoeven reg = <0 0xe6c10000 0 0x0064>; 1126e0768073SGeert Uytterhoeven interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1127e0768073SGeert Uytterhoeven clocks = <&cpg CPG_MOD 621>; 1128e0768073SGeert Uytterhoeven dmas = <&dmac0 0x47>, <&dmac0 0x46>, 1129e0768073SGeert Uytterhoeven <&dmac1 0x47>, <&dmac1 0x46>; 1130e0768073SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1131e0768073SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1132e0768073SGeert Uytterhoeven resets = <&cpg 621>; 1133e0768073SGeert Uytterhoeven #address-cells = <1>; 1134e0768073SGeert Uytterhoeven #size-cells = <0>; 1135e0768073SGeert Uytterhoeven status = "disabled"; 1136e0768073SGeert Uytterhoeven }; 1137e0768073SGeert Uytterhoeven 1138e0768073SGeert Uytterhoeven msiof4: spi@e6c20000 { 1139e0768073SGeert Uytterhoeven compatible = "renesas,msiof-r8a779g0", 1140e0768073SGeert Uytterhoeven "renesas,rcar-gen4-msiof"; 1141e0768073SGeert Uytterhoeven reg = <0 0xe6c20000 0 0x0064>; 1142e0768073SGeert Uytterhoeven interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1143e0768073SGeert Uytterhoeven clocks = <&cpg CPG_MOD 622>; 1144e0768073SGeert Uytterhoeven dmas = <&dmac0 0x49>, <&dmac0 0x48>, 1145e0768073SGeert Uytterhoeven <&dmac1 0x49>, <&dmac1 0x48>; 1146e0768073SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1147e0768073SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1148e0768073SGeert Uytterhoeven resets = <&cpg 622>; 1149e0768073SGeert Uytterhoeven #address-cells = <1>; 1150e0768073SGeert Uytterhoeven #size-cells = <0>; 1151e0768073SGeert Uytterhoeven status = "disabled"; 1152e0768073SGeert Uytterhoeven }; 1153e0768073SGeert Uytterhoeven 1154e0768073SGeert Uytterhoeven msiof5: spi@e6c28000 { 1155e0768073SGeert Uytterhoeven compatible = "renesas,msiof-r8a779g0", 1156e0768073SGeert Uytterhoeven "renesas,rcar-gen4-msiof"; 1157e0768073SGeert Uytterhoeven reg = <0 0xe6c28000 0 0x0064>; 1158e0768073SGeert Uytterhoeven interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1159e0768073SGeert Uytterhoeven clocks = <&cpg CPG_MOD 623>; 1160e0768073SGeert Uytterhoeven dmas = <&dmac0 0x4b>, <&dmac0 0x4a>, 1161e0768073SGeert Uytterhoeven <&dmac1 0x4b>, <&dmac1 0x4a>; 1162e0768073SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1163e0768073SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1164e0768073SGeert Uytterhoeven resets = <&cpg 623>; 1165e0768073SGeert Uytterhoeven #address-cells = <1>; 1166e0768073SGeert Uytterhoeven #size-cells = <0>; 1167e0768073SGeert Uytterhoeven status = "disabled"; 1168e0768073SGeert Uytterhoeven }; 1169e0768073SGeert Uytterhoeven 1170*d435d437SNiklas Söderlund vin00: video@e6ef0000 { 1171*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1172*d435d437SNiklas Söderlund reg = <0 0xe6ef0000 0 0x1000>; 1173*d435d437SNiklas Söderlund interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1174*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 730>; 1175*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1176*d435d437SNiklas Söderlund resets = <&cpg 730>; 1177*d435d437SNiklas Söderlund renesas,id = <0>; 1178*d435d437SNiklas Söderlund status = "disabled"; 1179*d435d437SNiklas Söderlund 1180*d435d437SNiklas Söderlund ports { 1181*d435d437SNiklas Söderlund #address-cells = <1>; 1182*d435d437SNiklas Söderlund #size-cells = <0>; 1183*d435d437SNiklas Söderlund 1184*d435d437SNiklas Söderlund port@2 { 1185*d435d437SNiklas Söderlund #address-cells = <1>; 1186*d435d437SNiklas Söderlund #size-cells = <0>; 1187*d435d437SNiklas Söderlund 1188*d435d437SNiklas Söderlund reg = <2>; 1189*d435d437SNiklas Söderlund 1190*d435d437SNiklas Söderlund vin00isp0: endpoint@0 { 1191*d435d437SNiklas Söderlund reg = <0>; 1192*d435d437SNiklas Söderlund remote-endpoint = <&isp0vin00>; 1193*d435d437SNiklas Söderlund }; 1194*d435d437SNiklas Söderlund }; 1195*d435d437SNiklas Söderlund }; 1196*d435d437SNiklas Söderlund }; 1197*d435d437SNiklas Söderlund 1198*d435d437SNiklas Söderlund vin01: video@e6ef1000 { 1199*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1200*d435d437SNiklas Söderlund reg = <0 0xe6ef1000 0 0x1000>; 1201*d435d437SNiklas Söderlund interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1202*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 731>; 1203*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1204*d435d437SNiklas Söderlund resets = <&cpg 731>; 1205*d435d437SNiklas Söderlund renesas,id = <1>; 1206*d435d437SNiklas Söderlund status = "disabled"; 1207*d435d437SNiklas Söderlund 1208*d435d437SNiklas Söderlund ports { 1209*d435d437SNiklas Söderlund #address-cells = <1>; 1210*d435d437SNiklas Söderlund #size-cells = <0>; 1211*d435d437SNiklas Söderlund 1212*d435d437SNiklas Söderlund port@2 { 1213*d435d437SNiklas Söderlund #address-cells = <1>; 1214*d435d437SNiklas Söderlund #size-cells = <0>; 1215*d435d437SNiklas Söderlund 1216*d435d437SNiklas Söderlund reg = <2>; 1217*d435d437SNiklas Söderlund 1218*d435d437SNiklas Söderlund vin01isp0: endpoint@0 { 1219*d435d437SNiklas Söderlund reg = <0>; 1220*d435d437SNiklas Söderlund remote-endpoint = <&isp0vin01>; 1221*d435d437SNiklas Söderlund }; 1222*d435d437SNiklas Söderlund }; 1223*d435d437SNiklas Söderlund }; 1224*d435d437SNiklas Söderlund }; 1225*d435d437SNiklas Söderlund 1226*d435d437SNiklas Söderlund vin02: video@e6ef2000 { 1227*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1228*d435d437SNiklas Söderlund reg = <0 0xe6ef2000 0 0x1000>; 1229*d435d437SNiklas Söderlund interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1230*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 800>; 1231*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1232*d435d437SNiklas Söderlund resets = <&cpg 800>; 1233*d435d437SNiklas Söderlund renesas,id = <2>; 1234*d435d437SNiklas Söderlund status = "disabled"; 1235*d435d437SNiklas Söderlund 1236*d435d437SNiklas Söderlund ports { 1237*d435d437SNiklas Söderlund #address-cells = <1>; 1238*d435d437SNiklas Söderlund #size-cells = <0>; 1239*d435d437SNiklas Söderlund 1240*d435d437SNiklas Söderlund port@2 { 1241*d435d437SNiklas Söderlund #address-cells = <1>; 1242*d435d437SNiklas Söderlund #size-cells = <0>; 1243*d435d437SNiklas Söderlund 1244*d435d437SNiklas Söderlund reg = <2>; 1245*d435d437SNiklas Söderlund 1246*d435d437SNiklas Söderlund vin02isp0: endpoint@0 { 1247*d435d437SNiklas Söderlund reg = <0>; 1248*d435d437SNiklas Söderlund remote-endpoint = <&isp0vin02>; 1249*d435d437SNiklas Söderlund }; 1250*d435d437SNiklas Söderlund }; 1251*d435d437SNiklas Söderlund }; 1252*d435d437SNiklas Söderlund }; 1253*d435d437SNiklas Söderlund 1254*d435d437SNiklas Söderlund vin03: video@e6ef3000 { 1255*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1256*d435d437SNiklas Söderlund reg = <0 0xe6ef3000 0 0x1000>; 1257*d435d437SNiklas Söderlund interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>; 1258*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 801>; 1259*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1260*d435d437SNiklas Söderlund resets = <&cpg 801>; 1261*d435d437SNiklas Söderlund renesas,id = <3>; 1262*d435d437SNiklas Söderlund status = "disabled"; 1263*d435d437SNiklas Söderlund 1264*d435d437SNiklas Söderlund ports { 1265*d435d437SNiklas Söderlund #address-cells = <1>; 1266*d435d437SNiklas Söderlund #size-cells = <0>; 1267*d435d437SNiklas Söderlund 1268*d435d437SNiklas Söderlund port@2 { 1269*d435d437SNiklas Söderlund #address-cells = <1>; 1270*d435d437SNiklas Söderlund #size-cells = <0>; 1271*d435d437SNiklas Söderlund 1272*d435d437SNiklas Söderlund reg = <2>; 1273*d435d437SNiklas Söderlund 1274*d435d437SNiklas Söderlund vin03isp0: endpoint@0 { 1275*d435d437SNiklas Söderlund reg = <0>; 1276*d435d437SNiklas Söderlund remote-endpoint = <&isp0vin03>; 1277*d435d437SNiklas Söderlund }; 1278*d435d437SNiklas Söderlund }; 1279*d435d437SNiklas Söderlund }; 1280*d435d437SNiklas Söderlund }; 1281*d435d437SNiklas Söderlund 1282*d435d437SNiklas Söderlund vin04: video@e6ef4000 { 1283*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1284*d435d437SNiklas Söderlund reg = <0 0xe6ef4000 0 0x1000>; 1285*d435d437SNiklas Söderlund interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 1286*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 802>; 1287*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1288*d435d437SNiklas Söderlund resets = <&cpg 802>; 1289*d435d437SNiklas Söderlund renesas,id = <4>; 1290*d435d437SNiklas Söderlund status = "disabled"; 1291*d435d437SNiklas Söderlund 1292*d435d437SNiklas Söderlund ports { 1293*d435d437SNiklas Söderlund #address-cells = <1>; 1294*d435d437SNiklas Söderlund #size-cells = <0>; 1295*d435d437SNiklas Söderlund 1296*d435d437SNiklas Söderlund port@2 { 1297*d435d437SNiklas Söderlund #address-cells = <1>; 1298*d435d437SNiklas Söderlund #size-cells = <0>; 1299*d435d437SNiklas Söderlund 1300*d435d437SNiklas Söderlund reg = <2>; 1301*d435d437SNiklas Söderlund 1302*d435d437SNiklas Söderlund vin04isp0: endpoint@0 { 1303*d435d437SNiklas Söderlund reg = <0>; 1304*d435d437SNiklas Söderlund remote-endpoint = <&isp0vin04>; 1305*d435d437SNiklas Söderlund }; 1306*d435d437SNiklas Söderlund }; 1307*d435d437SNiklas Söderlund }; 1308*d435d437SNiklas Söderlund }; 1309*d435d437SNiklas Söderlund 1310*d435d437SNiklas Söderlund vin05: video@e6ef5000 { 1311*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1312*d435d437SNiklas Söderlund reg = <0 0xe6ef5000 0 0x1000>; 1313*d435d437SNiklas Söderlund interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>; 1314*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 803>; 1315*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1316*d435d437SNiklas Söderlund resets = <&cpg 803>; 1317*d435d437SNiklas Söderlund renesas,id = <5>; 1318*d435d437SNiklas Söderlund status = "disabled"; 1319*d435d437SNiklas Söderlund 1320*d435d437SNiklas Söderlund ports { 1321*d435d437SNiklas Söderlund #address-cells = <1>; 1322*d435d437SNiklas Söderlund #size-cells = <0>; 1323*d435d437SNiklas Söderlund 1324*d435d437SNiklas Söderlund port@2 { 1325*d435d437SNiklas Söderlund #address-cells = <1>; 1326*d435d437SNiklas Söderlund #size-cells = <0>; 1327*d435d437SNiklas Söderlund 1328*d435d437SNiklas Söderlund reg = <2>; 1329*d435d437SNiklas Söderlund 1330*d435d437SNiklas Söderlund vin05isp0: endpoint@0 { 1331*d435d437SNiklas Söderlund reg = <0>; 1332*d435d437SNiklas Söderlund remote-endpoint = <&isp0vin05>; 1333*d435d437SNiklas Söderlund }; 1334*d435d437SNiklas Söderlund }; 1335*d435d437SNiklas Söderlund }; 1336*d435d437SNiklas Söderlund }; 1337*d435d437SNiklas Söderlund 1338*d435d437SNiklas Söderlund vin06: video@e6ef6000 { 1339*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1340*d435d437SNiklas Söderlund reg = <0 0xe6ef6000 0 0x1000>; 1341*d435d437SNiklas Söderlund interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1342*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 804>; 1343*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1344*d435d437SNiklas Söderlund resets = <&cpg 804>; 1345*d435d437SNiklas Söderlund renesas,id = <6>; 1346*d435d437SNiklas Söderlund status = "disabled"; 1347*d435d437SNiklas Söderlund 1348*d435d437SNiklas Söderlund ports { 1349*d435d437SNiklas Söderlund #address-cells = <1>; 1350*d435d437SNiklas Söderlund #size-cells = <0>; 1351*d435d437SNiklas Söderlund 1352*d435d437SNiklas Söderlund port@2 { 1353*d435d437SNiklas Söderlund #address-cells = <1>; 1354*d435d437SNiklas Söderlund #size-cells = <0>; 1355*d435d437SNiklas Söderlund 1356*d435d437SNiklas Söderlund reg = <2>; 1357*d435d437SNiklas Söderlund 1358*d435d437SNiklas Söderlund vin06isp0: endpoint@0 { 1359*d435d437SNiklas Söderlund reg = <0>; 1360*d435d437SNiklas Söderlund remote-endpoint = <&isp0vin06>; 1361*d435d437SNiklas Söderlund }; 1362*d435d437SNiklas Söderlund }; 1363*d435d437SNiklas Söderlund }; 1364*d435d437SNiklas Söderlund }; 1365*d435d437SNiklas Söderlund 1366*d435d437SNiklas Söderlund vin07: video@e6ef7000 { 1367*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1368*d435d437SNiklas Söderlund reg = <0 0xe6ef7000 0 0x1000>; 1369*d435d437SNiklas Söderlund interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1370*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 805>; 1371*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1372*d435d437SNiklas Söderlund resets = <&cpg 805>; 1373*d435d437SNiklas Söderlund renesas,id = <7>; 1374*d435d437SNiklas Söderlund status = "disabled"; 1375*d435d437SNiklas Söderlund 1376*d435d437SNiklas Söderlund ports { 1377*d435d437SNiklas Söderlund #address-cells = <1>; 1378*d435d437SNiklas Söderlund #size-cells = <0>; 1379*d435d437SNiklas Söderlund 1380*d435d437SNiklas Söderlund port@2 { 1381*d435d437SNiklas Söderlund #address-cells = <1>; 1382*d435d437SNiklas Söderlund #size-cells = <0>; 1383*d435d437SNiklas Söderlund 1384*d435d437SNiklas Söderlund reg = <2>; 1385*d435d437SNiklas Söderlund 1386*d435d437SNiklas Söderlund vin07isp0: endpoint@0 { 1387*d435d437SNiklas Söderlund reg = <0>; 1388*d435d437SNiklas Söderlund remote-endpoint = <&isp0vin07>; 1389*d435d437SNiklas Söderlund }; 1390*d435d437SNiklas Söderlund }; 1391*d435d437SNiklas Söderlund }; 1392*d435d437SNiklas Söderlund }; 1393*d435d437SNiklas Söderlund 1394*d435d437SNiklas Söderlund vin08: video@e6ef8000 { 1395*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1396*d435d437SNiklas Söderlund reg = <0 0xe6ef8000 0 0x1000>; 1397*d435d437SNiklas Söderlund interrupts = <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>; 1398*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 806>; 1399*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1400*d435d437SNiklas Söderlund resets = <&cpg 806>; 1401*d435d437SNiklas Söderlund renesas,id = <8>; 1402*d435d437SNiklas Söderlund status = "disabled"; 1403*d435d437SNiklas Söderlund 1404*d435d437SNiklas Söderlund ports { 1405*d435d437SNiklas Söderlund #address-cells = <1>; 1406*d435d437SNiklas Söderlund #size-cells = <0>; 1407*d435d437SNiklas Söderlund 1408*d435d437SNiklas Söderlund port@2 { 1409*d435d437SNiklas Söderlund #address-cells = <1>; 1410*d435d437SNiklas Söderlund #size-cells = <0>; 1411*d435d437SNiklas Söderlund 1412*d435d437SNiklas Söderlund reg = <2>; 1413*d435d437SNiklas Söderlund 1414*d435d437SNiklas Söderlund vin08isp1: endpoint@1 { 1415*d435d437SNiklas Söderlund reg = <1>; 1416*d435d437SNiklas Söderlund remote-endpoint = <&isp1vin08>; 1417*d435d437SNiklas Söderlund }; 1418*d435d437SNiklas Söderlund }; 1419*d435d437SNiklas Söderlund }; 1420*d435d437SNiklas Söderlund }; 1421*d435d437SNiklas Söderlund 1422*d435d437SNiklas Söderlund vin09: video@e6ef9000 { 1423*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1424*d435d437SNiklas Söderlund reg = <0 0xe6ef9000 0 0x1000>; 1425*d435d437SNiklas Söderlund interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>; 1426*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 807>; 1427*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1428*d435d437SNiklas Söderlund resets = <&cpg 807>; 1429*d435d437SNiklas Söderlund renesas,id = <9>; 1430*d435d437SNiklas Söderlund status = "disabled"; 1431*d435d437SNiklas Söderlund 1432*d435d437SNiklas Söderlund ports { 1433*d435d437SNiklas Söderlund #address-cells = <1>; 1434*d435d437SNiklas Söderlund #size-cells = <0>; 1435*d435d437SNiklas Söderlund 1436*d435d437SNiklas Söderlund port@2 { 1437*d435d437SNiklas Söderlund #address-cells = <1>; 1438*d435d437SNiklas Söderlund #size-cells = <0>; 1439*d435d437SNiklas Söderlund 1440*d435d437SNiklas Söderlund reg = <2>; 1441*d435d437SNiklas Söderlund 1442*d435d437SNiklas Söderlund vin09isp1: endpoint@1 { 1443*d435d437SNiklas Söderlund reg = <1>; 1444*d435d437SNiklas Söderlund remote-endpoint = <&isp1vin09>; 1445*d435d437SNiklas Söderlund }; 1446*d435d437SNiklas Söderlund }; 1447*d435d437SNiklas Söderlund }; 1448*d435d437SNiklas Söderlund }; 1449*d435d437SNiklas Söderlund 1450*d435d437SNiklas Söderlund vin10: video@e6efa000 { 1451*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1452*d435d437SNiklas Söderlund reg = <0 0xe6efa000 0 0x1000>; 1453*d435d437SNiklas Söderlund interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>; 1454*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 808>; 1455*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1456*d435d437SNiklas Söderlund resets = <&cpg 808>; 1457*d435d437SNiklas Söderlund renesas,id = <10>; 1458*d435d437SNiklas Söderlund status = "disabled"; 1459*d435d437SNiklas Söderlund 1460*d435d437SNiklas Söderlund ports { 1461*d435d437SNiklas Söderlund #address-cells = <1>; 1462*d435d437SNiklas Söderlund #size-cells = <0>; 1463*d435d437SNiklas Söderlund 1464*d435d437SNiklas Söderlund port@2 { 1465*d435d437SNiklas Söderlund #address-cells = <1>; 1466*d435d437SNiklas Söderlund #size-cells = <0>; 1467*d435d437SNiklas Söderlund 1468*d435d437SNiklas Söderlund reg = <2>; 1469*d435d437SNiklas Söderlund 1470*d435d437SNiklas Söderlund vin10isp1: endpoint@1 { 1471*d435d437SNiklas Söderlund reg = <1>; 1472*d435d437SNiklas Söderlund remote-endpoint = <&isp1vin10>; 1473*d435d437SNiklas Söderlund }; 1474*d435d437SNiklas Söderlund }; 1475*d435d437SNiklas Söderlund }; 1476*d435d437SNiklas Söderlund }; 1477*d435d437SNiklas Söderlund 1478*d435d437SNiklas Söderlund vin11: video@e6efb000 { 1479*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1480*d435d437SNiklas Söderlund reg = <0 0xe6efb000 0 0x1000>; 1481*d435d437SNiklas Söderlund interrupts = <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>; 1482*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 809>; 1483*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1484*d435d437SNiklas Söderlund resets = <&cpg 809>; 1485*d435d437SNiklas Söderlund renesas,id = <11>; 1486*d435d437SNiklas Söderlund status = "disabled"; 1487*d435d437SNiklas Söderlund 1488*d435d437SNiklas Söderlund ports { 1489*d435d437SNiklas Söderlund #address-cells = <1>; 1490*d435d437SNiklas Söderlund #size-cells = <0>; 1491*d435d437SNiklas Söderlund 1492*d435d437SNiklas Söderlund port@2 { 1493*d435d437SNiklas Söderlund #address-cells = <1>; 1494*d435d437SNiklas Söderlund #size-cells = <0>; 1495*d435d437SNiklas Söderlund 1496*d435d437SNiklas Söderlund reg = <2>; 1497*d435d437SNiklas Söderlund 1498*d435d437SNiklas Söderlund vin11isp1: endpoint@1 { 1499*d435d437SNiklas Söderlund reg = <1>; 1500*d435d437SNiklas Söderlund remote-endpoint = <&isp1vin11>; 1501*d435d437SNiklas Söderlund }; 1502*d435d437SNiklas Söderlund }; 1503*d435d437SNiklas Söderlund }; 1504*d435d437SNiklas Söderlund }; 1505*d435d437SNiklas Söderlund 1506*d435d437SNiklas Söderlund vin12: video@e6efc000 { 1507*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1508*d435d437SNiklas Söderlund reg = <0 0xe6efc000 0 0x1000>; 1509*d435d437SNiklas Söderlund interrupts = <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>; 1510*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 810>; 1511*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1512*d435d437SNiklas Söderlund resets = <&cpg 810>; 1513*d435d437SNiklas Söderlund renesas,id = <12>; 1514*d435d437SNiklas Söderlund status = "disabled"; 1515*d435d437SNiklas Söderlund 1516*d435d437SNiklas Söderlund ports { 1517*d435d437SNiklas Söderlund #address-cells = <1>; 1518*d435d437SNiklas Söderlund #size-cells = <0>; 1519*d435d437SNiklas Söderlund 1520*d435d437SNiklas Söderlund port@2 { 1521*d435d437SNiklas Söderlund #address-cells = <1>; 1522*d435d437SNiklas Söderlund #size-cells = <0>; 1523*d435d437SNiklas Söderlund 1524*d435d437SNiklas Söderlund reg = <2>; 1525*d435d437SNiklas Söderlund 1526*d435d437SNiklas Söderlund vin12isp1: endpoint@1 { 1527*d435d437SNiklas Söderlund reg = <1>; 1528*d435d437SNiklas Söderlund remote-endpoint = <&isp1vin12>; 1529*d435d437SNiklas Söderlund }; 1530*d435d437SNiklas Söderlund }; 1531*d435d437SNiklas Söderlund }; 1532*d435d437SNiklas Söderlund }; 1533*d435d437SNiklas Söderlund 1534*d435d437SNiklas Söderlund vin13: video@e6efd000 { 1535*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1536*d435d437SNiklas Söderlund reg = <0 0xe6efd000 0 0x1000>; 1537*d435d437SNiklas Söderlund interrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>; 1538*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 811>; 1539*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1540*d435d437SNiklas Söderlund resets = <&cpg 811>; 1541*d435d437SNiklas Söderlund renesas,id = <13>; 1542*d435d437SNiklas Söderlund status = "disabled"; 1543*d435d437SNiklas Söderlund 1544*d435d437SNiklas Söderlund ports { 1545*d435d437SNiklas Söderlund #address-cells = <1>; 1546*d435d437SNiklas Söderlund #size-cells = <0>; 1547*d435d437SNiklas Söderlund 1548*d435d437SNiklas Söderlund port@2 { 1549*d435d437SNiklas Söderlund #address-cells = <1>; 1550*d435d437SNiklas Söderlund #size-cells = <0>; 1551*d435d437SNiklas Söderlund 1552*d435d437SNiklas Söderlund reg = <2>; 1553*d435d437SNiklas Söderlund 1554*d435d437SNiklas Söderlund vin13isp1: endpoint@1 { 1555*d435d437SNiklas Söderlund reg = <1>; 1556*d435d437SNiklas Söderlund remote-endpoint = <&isp1vin13>; 1557*d435d437SNiklas Söderlund }; 1558*d435d437SNiklas Söderlund }; 1559*d435d437SNiklas Söderlund }; 1560*d435d437SNiklas Söderlund }; 1561*d435d437SNiklas Söderlund 1562*d435d437SNiklas Söderlund vin14: video@e6efe000 { 1563*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1564*d435d437SNiklas Söderlund reg = <0 0xe6efe000 0 0x1000>; 1565*d435d437SNiklas Söderlund interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>; 1566*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 812>; 1567*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1568*d435d437SNiklas Söderlund resets = <&cpg 812>; 1569*d435d437SNiklas Söderlund renesas,id = <14>; 1570*d435d437SNiklas Söderlund status = "disabled"; 1571*d435d437SNiklas Söderlund 1572*d435d437SNiklas Söderlund ports { 1573*d435d437SNiklas Söderlund #address-cells = <1>; 1574*d435d437SNiklas Söderlund #size-cells = <0>; 1575*d435d437SNiklas Söderlund 1576*d435d437SNiklas Söderlund port@2 { 1577*d435d437SNiklas Söderlund #address-cells = <1>; 1578*d435d437SNiklas Söderlund #size-cells = <0>; 1579*d435d437SNiklas Söderlund 1580*d435d437SNiklas Söderlund reg = <2>; 1581*d435d437SNiklas Söderlund 1582*d435d437SNiklas Söderlund vin14isp1: endpoint@1 { 1583*d435d437SNiklas Söderlund reg = <1>; 1584*d435d437SNiklas Söderlund remote-endpoint = <&isp1vin14>; 1585*d435d437SNiklas Söderlund }; 1586*d435d437SNiklas Söderlund }; 1587*d435d437SNiklas Söderlund }; 1588*d435d437SNiklas Söderlund }; 1589*d435d437SNiklas Söderlund 1590*d435d437SNiklas Söderlund vin15: video@e6eff000 { 1591*d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1592*d435d437SNiklas Söderlund reg = <0 0xe6eff000 0 0x1000>; 1593*d435d437SNiklas Söderlund interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1594*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 813>; 1595*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1596*d435d437SNiklas Söderlund resets = <&cpg 813>; 1597*d435d437SNiklas Söderlund renesas,id = <15>; 1598*d435d437SNiklas Söderlund status = "disabled"; 1599*d435d437SNiklas Söderlund 1600*d435d437SNiklas Söderlund ports { 1601*d435d437SNiklas Söderlund #address-cells = <1>; 1602*d435d437SNiklas Söderlund #size-cells = <0>; 1603*d435d437SNiklas Söderlund 1604*d435d437SNiklas Söderlund port@2 { 1605*d435d437SNiklas Söderlund #address-cells = <1>; 1606*d435d437SNiklas Söderlund #size-cells = <0>; 1607*d435d437SNiklas Söderlund 1608*d435d437SNiklas Söderlund reg = <2>; 1609*d435d437SNiklas Söderlund 1610*d435d437SNiklas Söderlund vin15isp1: endpoint@1 { 1611*d435d437SNiklas Söderlund reg = <1>; 1612*d435d437SNiklas Söderlund remote-endpoint = <&isp1vin15>; 1613*d435d437SNiklas Söderlund }; 1614*d435d437SNiklas Söderlund }; 1615*d435d437SNiklas Söderlund }; 1616*d435d437SNiklas Söderlund }; 1617*d435d437SNiklas Söderlund 161808f28288SGeert Uytterhoeven dmac0: dma-controller@e7350000 { 161908f28288SGeert Uytterhoeven compatible = "renesas,dmac-r8a779g0", 162008f28288SGeert Uytterhoeven "renesas,rcar-gen4-dmac"; 162108f28288SGeert Uytterhoeven reg = <0 0xe7350000 0 0x1000>, 162208f28288SGeert Uytterhoeven <0 0xe7300000 0 0x10000>; 162308f28288SGeert Uytterhoeven interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 162408f28288SGeert Uytterhoeven <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 162508f28288SGeert Uytterhoeven <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 162608f28288SGeert Uytterhoeven <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 162708f28288SGeert Uytterhoeven <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 162808f28288SGeert Uytterhoeven <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 162908f28288SGeert Uytterhoeven <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 163008f28288SGeert Uytterhoeven <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 163108f28288SGeert Uytterhoeven <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 163208f28288SGeert Uytterhoeven <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 163308f28288SGeert Uytterhoeven <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 163408f28288SGeert Uytterhoeven <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 163508f28288SGeert Uytterhoeven <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 163608f28288SGeert Uytterhoeven <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 163708f28288SGeert Uytterhoeven <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 163808f28288SGeert Uytterhoeven <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 163908f28288SGeert Uytterhoeven <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 164008f28288SGeert Uytterhoeven interrupt-names = "error", 164108f28288SGeert Uytterhoeven "ch0", "ch1", "ch2", "ch3", "ch4", 164208f28288SGeert Uytterhoeven "ch5", "ch6", "ch7", "ch8", "ch9", 164308f28288SGeert Uytterhoeven "ch10", "ch11", "ch12", "ch13", 164408f28288SGeert Uytterhoeven "ch14", "ch15"; 164508f28288SGeert Uytterhoeven clocks = <&cpg CPG_MOD 709>; 164608f28288SGeert Uytterhoeven clock-names = "fck"; 164708f28288SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 164808f28288SGeert Uytterhoeven resets = <&cpg 709>; 164908f28288SGeert Uytterhoeven #dma-cells = <1>; 165008f28288SGeert Uytterhoeven dma-channels = <16>; 165108f28288SGeert Uytterhoeven }; 165208f28288SGeert Uytterhoeven 165308f28288SGeert Uytterhoeven dmac1: dma-controller@e7351000 { 165408f28288SGeert Uytterhoeven compatible = "renesas,dmac-r8a779g0", 165508f28288SGeert Uytterhoeven "renesas,rcar-gen4-dmac"; 165608f28288SGeert Uytterhoeven reg = <0 0xe7351000 0 0x1000>, 165708f28288SGeert Uytterhoeven <0 0xe7310000 0 0x10000>; 165808f28288SGeert Uytterhoeven interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 165908f28288SGeert Uytterhoeven <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 166008f28288SGeert Uytterhoeven <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 166108f28288SGeert Uytterhoeven <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 166208f28288SGeert Uytterhoeven <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 166308f28288SGeert Uytterhoeven <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 166408f28288SGeert Uytterhoeven <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 166508f28288SGeert Uytterhoeven <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 166608f28288SGeert Uytterhoeven <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 166708f28288SGeert Uytterhoeven <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 166808f28288SGeert Uytterhoeven <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 166908f28288SGeert Uytterhoeven <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 167008f28288SGeert Uytterhoeven <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 167108f28288SGeert Uytterhoeven <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 167208f28288SGeert Uytterhoeven <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 167308f28288SGeert Uytterhoeven <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 167408f28288SGeert Uytterhoeven <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 167508f28288SGeert Uytterhoeven interrupt-names = "error", 167608f28288SGeert Uytterhoeven "ch0", "ch1", "ch2", "ch3", "ch4", 167708f28288SGeert Uytterhoeven "ch5", "ch6", "ch7", "ch8", "ch9", 167808f28288SGeert Uytterhoeven "ch10", "ch11", "ch12", "ch13", 167908f28288SGeert Uytterhoeven "ch14", "ch15"; 168008f28288SGeert Uytterhoeven clocks = <&cpg CPG_MOD 710>; 168108f28288SGeert Uytterhoeven clock-names = "fck"; 168208f28288SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 168308f28288SGeert Uytterhoeven resets = <&cpg 710>; 168408f28288SGeert Uytterhoeven #dma-cells = <1>; 168508f28288SGeert Uytterhoeven dma-channels = <16>; 168608f28288SGeert Uytterhoeven }; 168708f28288SGeert Uytterhoeven 1688bc7bf913SGeert Uytterhoeven mmc0: mmc@ee140000 { 1689bc7bf913SGeert Uytterhoeven compatible = "renesas,sdhi-r8a779g0", 1690bc7bf913SGeert Uytterhoeven "renesas,rcar-gen4-sdhi"; 1691bc7bf913SGeert Uytterhoeven reg = <0 0xee140000 0 0x2000>; 1692bc7bf913SGeert Uytterhoeven interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 1693bc7bf913SGeert Uytterhoeven clocks = <&cpg CPG_MOD 706>, 1694bc7bf913SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SD0H>; 1695bc7bf913SGeert Uytterhoeven clock-names = "core", "clkh"; 1696bc7bf913SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1697bc7bf913SGeert Uytterhoeven resets = <&cpg 706>; 1698bc7bf913SGeert Uytterhoeven max-frequency = <200000000>; 1699bc7bf913SGeert Uytterhoeven status = "disabled"; 1700bc7bf913SGeert Uytterhoeven }; 1701bc7bf913SGeert Uytterhoeven 1702d5014bedSHai Pham rpc: spi@ee200000 { 1703d5014bedSHai Pham compatible = "renesas,r8a779g0-rpc-if", 1704d5014bedSHai Pham "renesas,rcar-gen4-rpc-if"; 1705d5014bedSHai Pham reg = <0 0xee200000 0 0x200>, 1706d5014bedSHai Pham <0 0x08000000 0 0x04000000>, 1707d5014bedSHai Pham <0 0xee208000 0 0x100>; 1708d5014bedSHai Pham reg-names = "regs", "dirmap", "wbuf"; 1709d5014bedSHai Pham interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1710d5014bedSHai Pham clocks = <&cpg CPG_MOD 629>; 1711d5014bedSHai Pham power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1712d5014bedSHai Pham resets = <&cpg 629>; 1713d5014bedSHai Pham #address-cells = <1>; 1714d5014bedSHai Pham #size-cells = <0>; 1715d5014bedSHai Pham status = "disabled"; 1716d5014bedSHai Pham }; 1717d5014bedSHai Pham 1718987da486SYoshihiro Shimoda gic: interrupt-controller@f1000000 { 1719987da486SYoshihiro Shimoda compatible = "arm,gic-v3"; 1720987da486SYoshihiro Shimoda #interrupt-cells = <3>; 1721987da486SYoshihiro Shimoda #address-cells = <0>; 1722987da486SYoshihiro Shimoda interrupt-controller; 1723987da486SYoshihiro Shimoda reg = <0x0 0xf1000000 0 0x20000>, 1724987da486SYoshihiro Shimoda <0x0 0xf1060000 0 0x110000>; 17258b6a006cSLad Prabhakar interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1726987da486SYoshihiro Shimoda }; 1727987da486SYoshihiro Shimoda 1728*d435d437SNiklas Söderlund csi40: csi2@fe500000 { 1729*d435d437SNiklas Söderlund compatible = "renesas,r8a779g0-csi2"; 1730*d435d437SNiklas Söderlund reg = <0 0xfe500000 0 0x40000>; 1731*d435d437SNiklas Söderlund interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>; 1732*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 331>; 1733*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1734*d435d437SNiklas Söderlund resets = <&cpg 331>; 1735*d435d437SNiklas Söderlund status = "disabled"; 1736*d435d437SNiklas Söderlund 1737*d435d437SNiklas Söderlund ports { 1738*d435d437SNiklas Söderlund #address-cells = <1>; 1739*d435d437SNiklas Söderlund #size-cells = <0>; 1740*d435d437SNiklas Söderlund 1741*d435d437SNiklas Söderlund port@0 { 1742*d435d437SNiklas Söderlund reg = <0>; 1743*d435d437SNiklas Söderlund }; 1744*d435d437SNiklas Söderlund 1745*d435d437SNiklas Söderlund port@1 { 1746*d435d437SNiklas Söderlund reg = <1>; 1747*d435d437SNiklas Söderlund csi40isp0: endpoint { 1748*d435d437SNiklas Söderlund remote-endpoint = <&isp0csi40>; 1749*d435d437SNiklas Söderlund }; 1750*d435d437SNiklas Söderlund }; 1751*d435d437SNiklas Söderlund }; 1752*d435d437SNiklas Söderlund }; 1753*d435d437SNiklas Söderlund 1754*d435d437SNiklas Söderlund csi41: csi2@fe540000 { 1755*d435d437SNiklas Söderlund compatible = "renesas,r8a779g0-csi2"; 1756*d435d437SNiklas Söderlund reg = <0 0xfe540000 0 0x40000>; 1757*d435d437SNiklas Söderlund interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>; 1758*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 400>; 1759*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1760*d435d437SNiklas Söderlund resets = <&cpg 400>; 1761*d435d437SNiklas Söderlund status = "disabled"; 1762*d435d437SNiklas Söderlund 1763*d435d437SNiklas Söderlund ports { 1764*d435d437SNiklas Söderlund #address-cells = <1>; 1765*d435d437SNiklas Söderlund #size-cells = <0>; 1766*d435d437SNiklas Söderlund 1767*d435d437SNiklas Söderlund port@0 { 1768*d435d437SNiklas Söderlund reg = <0>; 1769*d435d437SNiklas Söderlund }; 1770*d435d437SNiklas Söderlund 1771*d435d437SNiklas Söderlund port@1 { 1772*d435d437SNiklas Söderlund reg = <1>; 1773*d435d437SNiklas Söderlund csi41isp1: endpoint { 1774*d435d437SNiklas Söderlund remote-endpoint = <&isp1csi41>; 1775*d435d437SNiklas Söderlund }; 1776*d435d437SNiklas Söderlund }; 1777*d435d437SNiklas Söderlund }; 1778*d435d437SNiklas Söderlund }; 1779*d435d437SNiklas Söderlund 178095d60f13STomi Valkeinen fcpvd0: fcp@fea10000 { 178195d60f13STomi Valkeinen compatible = "renesas,fcpv"; 178295d60f13STomi Valkeinen reg = <0 0xfea10000 0 0x200>; 178395d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 508>; 178495d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 178595d60f13STomi Valkeinen resets = <&cpg 508>; 178695d60f13STomi Valkeinen }; 178795d60f13STomi Valkeinen 178895d60f13STomi Valkeinen fcpvd1: fcp@fea11000 { 178995d60f13STomi Valkeinen compatible = "renesas,fcpv"; 179095d60f13STomi Valkeinen reg = <0 0xfea11000 0 0x200>; 179195d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 509>; 179295d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 179395d60f13STomi Valkeinen resets = <&cpg 509>; 179495d60f13STomi Valkeinen }; 179595d60f13STomi Valkeinen 179695d60f13STomi Valkeinen vspd0: vsp@fea20000 { 179795d60f13STomi Valkeinen compatible = "renesas,vsp2"; 179895d60f13STomi Valkeinen reg = <0 0xfea20000 0 0x7000>; 179995d60f13STomi Valkeinen interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; 180095d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 830>; 180195d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 180295d60f13STomi Valkeinen resets = <&cpg 830>; 180395d60f13STomi Valkeinen 180495d60f13STomi Valkeinen renesas,fcp = <&fcpvd0>; 180595d60f13STomi Valkeinen }; 180695d60f13STomi Valkeinen 180795d60f13STomi Valkeinen vspd1: vsp@fea28000 { 180895d60f13STomi Valkeinen compatible = "renesas,vsp2"; 180995d60f13STomi Valkeinen reg = <0 0xfea28000 0 0x7000>; 181095d60f13STomi Valkeinen interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 181195d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 831>; 181295d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 181395d60f13STomi Valkeinen resets = <&cpg 831>; 181495d60f13STomi Valkeinen 181595d60f13STomi Valkeinen renesas,fcp = <&fcpvd1>; 181695d60f13STomi Valkeinen }; 181795d60f13STomi Valkeinen 181895d60f13STomi Valkeinen du: display@feb00000 { 181995d60f13STomi Valkeinen compatible = "renesas,du-r8a779g0"; 182095d60f13STomi Valkeinen reg = <0 0xfeb00000 0 0x40000>; 182195d60f13STomi Valkeinen interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 182295d60f13STomi Valkeinen <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>; 182395d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 411>; 182495d60f13STomi Valkeinen clock-names = "du.0"; 182595d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 182695d60f13STomi Valkeinen resets = <&cpg 411>; 182795d60f13STomi Valkeinen reset-names = "du.0"; 182895d60f13STomi Valkeinen renesas,vsps = <&vspd0 0>, <&vspd1 0>; 182995d60f13STomi Valkeinen 183095d60f13STomi Valkeinen status = "disabled"; 183195d60f13STomi Valkeinen 183295d60f13STomi Valkeinen ports { 183395d60f13STomi Valkeinen #address-cells = <1>; 183495d60f13STomi Valkeinen #size-cells = <0>; 183595d60f13STomi Valkeinen 183695d60f13STomi Valkeinen port@0 { 183795d60f13STomi Valkeinen reg = <0>; 183895d60f13STomi Valkeinen du_out_dsi0: endpoint { 183995d60f13STomi Valkeinen remote-endpoint = <&dsi0_in>; 184095d60f13STomi Valkeinen }; 184195d60f13STomi Valkeinen }; 184295d60f13STomi Valkeinen 184395d60f13STomi Valkeinen port@1 { 184495d60f13STomi Valkeinen reg = <1>; 184595d60f13STomi Valkeinen du_out_dsi1: endpoint { 184695d60f13STomi Valkeinen remote-endpoint = <&dsi1_in>; 184795d60f13STomi Valkeinen }; 184895d60f13STomi Valkeinen }; 184995d60f13STomi Valkeinen }; 185095d60f13STomi Valkeinen }; 185195d60f13STomi Valkeinen 1852*d435d437SNiklas Söderlund isp0: isp@fed00000 { 1853*d435d437SNiklas Söderlund compatible = "renesas,r8a779g0-isp"; 1854*d435d437SNiklas Söderlund reg = <0 0xfed00000 0 0x10000>; 1855*d435d437SNiklas Söderlund interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>; 1856*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 612>; 1857*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_A3ISP0>; 1858*d435d437SNiklas Söderlund resets = <&cpg 612>; 1859*d435d437SNiklas Söderlund status = "disabled"; 1860*d435d437SNiklas Söderlund 1861*d435d437SNiklas Söderlund ports { 1862*d435d437SNiklas Söderlund #address-cells = <1>; 1863*d435d437SNiklas Söderlund #size-cells = <0>; 1864*d435d437SNiklas Söderlund 1865*d435d437SNiklas Söderlund port@0 { 1866*d435d437SNiklas Söderlund #address-cells = <1>; 1867*d435d437SNiklas Söderlund #size-cells = <0>; 1868*d435d437SNiklas Söderlund 1869*d435d437SNiklas Söderlund reg = <0>; 1870*d435d437SNiklas Söderlund 1871*d435d437SNiklas Söderlund isp0csi40: endpoint@0 { 1872*d435d437SNiklas Söderlund reg = <0>; 1873*d435d437SNiklas Söderlund remote-endpoint = <&csi40isp0>; 1874*d435d437SNiklas Söderlund }; 1875*d435d437SNiklas Söderlund }; 1876*d435d437SNiklas Söderlund 1877*d435d437SNiklas Söderlund port@1 { 1878*d435d437SNiklas Söderlund reg = <1>; 1879*d435d437SNiklas Söderlund isp0vin00: endpoint { 1880*d435d437SNiklas Söderlund remote-endpoint = <&vin00isp0>; 1881*d435d437SNiklas Söderlund }; 1882*d435d437SNiklas Söderlund }; 1883*d435d437SNiklas Söderlund 1884*d435d437SNiklas Söderlund port@2 { 1885*d435d437SNiklas Söderlund reg = <2>; 1886*d435d437SNiklas Söderlund isp0vin01: endpoint { 1887*d435d437SNiklas Söderlund remote-endpoint = <&vin01isp0>; 1888*d435d437SNiklas Söderlund }; 1889*d435d437SNiklas Söderlund }; 1890*d435d437SNiklas Söderlund 1891*d435d437SNiklas Söderlund port@3 { 1892*d435d437SNiklas Söderlund reg = <3>; 1893*d435d437SNiklas Söderlund isp0vin02: endpoint { 1894*d435d437SNiklas Söderlund remote-endpoint = <&vin02isp0>; 1895*d435d437SNiklas Söderlund }; 1896*d435d437SNiklas Söderlund }; 1897*d435d437SNiklas Söderlund 1898*d435d437SNiklas Söderlund port@4 { 1899*d435d437SNiklas Söderlund reg = <4>; 1900*d435d437SNiklas Söderlund isp0vin03: endpoint { 1901*d435d437SNiklas Söderlund remote-endpoint = <&vin03isp0>; 1902*d435d437SNiklas Söderlund }; 1903*d435d437SNiklas Söderlund }; 1904*d435d437SNiklas Söderlund 1905*d435d437SNiklas Söderlund port@5 { 1906*d435d437SNiklas Söderlund reg = <5>; 1907*d435d437SNiklas Söderlund isp0vin04: endpoint { 1908*d435d437SNiklas Söderlund remote-endpoint = <&vin04isp0>; 1909*d435d437SNiklas Söderlund }; 1910*d435d437SNiklas Söderlund }; 1911*d435d437SNiklas Söderlund 1912*d435d437SNiklas Söderlund port@6 { 1913*d435d437SNiklas Söderlund reg = <6>; 1914*d435d437SNiklas Söderlund isp0vin05: endpoint { 1915*d435d437SNiklas Söderlund remote-endpoint = <&vin05isp0>; 1916*d435d437SNiklas Söderlund }; 1917*d435d437SNiklas Söderlund }; 1918*d435d437SNiklas Söderlund 1919*d435d437SNiklas Söderlund port@7 { 1920*d435d437SNiklas Söderlund reg = <7>; 1921*d435d437SNiklas Söderlund isp0vin06: endpoint { 1922*d435d437SNiklas Söderlund remote-endpoint = <&vin06isp0>; 1923*d435d437SNiklas Söderlund }; 1924*d435d437SNiklas Söderlund }; 1925*d435d437SNiklas Söderlund 1926*d435d437SNiklas Söderlund port@8 { 1927*d435d437SNiklas Söderlund reg = <8>; 1928*d435d437SNiklas Söderlund isp0vin07: endpoint { 1929*d435d437SNiklas Söderlund remote-endpoint = <&vin07isp0>; 1930*d435d437SNiklas Söderlund }; 1931*d435d437SNiklas Söderlund }; 1932*d435d437SNiklas Söderlund }; 1933*d435d437SNiklas Söderlund }; 1934*d435d437SNiklas Söderlund 1935*d435d437SNiklas Söderlund isp1: isp@fed20000 { 1936*d435d437SNiklas Söderlund compatible = "renesas,r8a779g0-isp"; 1937*d435d437SNiklas Söderlund reg = <0 0xfed20000 0 0x10000>; 1938*d435d437SNiklas Söderlund interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>; 1939*d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 613>; 1940*d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_A3ISP1>; 1941*d435d437SNiklas Söderlund resets = <&cpg 613>; 1942*d435d437SNiklas Söderlund status = "disabled"; 1943*d435d437SNiklas Söderlund 1944*d435d437SNiklas Söderlund ports { 1945*d435d437SNiklas Söderlund #address-cells = <1>; 1946*d435d437SNiklas Söderlund #size-cells = <0>; 1947*d435d437SNiklas Söderlund 1948*d435d437SNiklas Söderlund port@0 { 1949*d435d437SNiklas Söderlund #address-cells = <1>; 1950*d435d437SNiklas Söderlund #size-cells = <0>; 1951*d435d437SNiklas Söderlund 1952*d435d437SNiklas Söderlund reg = <0>; 1953*d435d437SNiklas Söderlund 1954*d435d437SNiklas Söderlund isp1csi41: endpoint@1 { 1955*d435d437SNiklas Söderlund reg = <1>; 1956*d435d437SNiklas Söderlund remote-endpoint = <&csi41isp1>; 1957*d435d437SNiklas Söderlund }; 1958*d435d437SNiklas Söderlund }; 1959*d435d437SNiklas Söderlund 1960*d435d437SNiklas Söderlund port@1 { 1961*d435d437SNiklas Söderlund reg = <1>; 1962*d435d437SNiklas Söderlund isp1vin08: endpoint { 1963*d435d437SNiklas Söderlund remote-endpoint = <&vin08isp1>; 1964*d435d437SNiklas Söderlund }; 1965*d435d437SNiklas Söderlund }; 1966*d435d437SNiklas Söderlund 1967*d435d437SNiklas Söderlund port@2 { 1968*d435d437SNiklas Söderlund reg = <2>; 1969*d435d437SNiklas Söderlund isp1vin09: endpoint { 1970*d435d437SNiklas Söderlund remote-endpoint = <&vin09isp1>; 1971*d435d437SNiklas Söderlund }; 1972*d435d437SNiklas Söderlund }; 1973*d435d437SNiklas Söderlund 1974*d435d437SNiklas Söderlund port@3 { 1975*d435d437SNiklas Söderlund reg = <3>; 1976*d435d437SNiklas Söderlund isp1vin10: endpoint { 1977*d435d437SNiklas Söderlund remote-endpoint = <&vin10isp1>; 1978*d435d437SNiklas Söderlund }; 1979*d435d437SNiklas Söderlund }; 1980*d435d437SNiklas Söderlund 1981*d435d437SNiklas Söderlund port@4 { 1982*d435d437SNiklas Söderlund reg = <4>; 1983*d435d437SNiklas Söderlund isp1vin11: endpoint { 1984*d435d437SNiklas Söderlund remote-endpoint = <&vin11isp1>; 1985*d435d437SNiklas Söderlund }; 1986*d435d437SNiklas Söderlund }; 1987*d435d437SNiklas Söderlund 1988*d435d437SNiklas Söderlund port@5 { 1989*d435d437SNiklas Söderlund reg = <5>; 1990*d435d437SNiklas Söderlund isp1vin12: endpoint { 1991*d435d437SNiklas Söderlund remote-endpoint = <&vin12isp1>; 1992*d435d437SNiklas Söderlund }; 1993*d435d437SNiklas Söderlund }; 1994*d435d437SNiklas Söderlund 1995*d435d437SNiklas Söderlund port@6 { 1996*d435d437SNiklas Söderlund reg = <6>; 1997*d435d437SNiklas Söderlund isp1vin13: endpoint { 1998*d435d437SNiklas Söderlund remote-endpoint = <&vin13isp1>; 1999*d435d437SNiklas Söderlund }; 2000*d435d437SNiklas Söderlund }; 2001*d435d437SNiklas Söderlund 2002*d435d437SNiklas Söderlund port@7 { 2003*d435d437SNiklas Söderlund reg = <7>; 2004*d435d437SNiklas Söderlund isp1vin14: endpoint { 2005*d435d437SNiklas Söderlund remote-endpoint = <&vin14isp1>; 2006*d435d437SNiklas Söderlund }; 2007*d435d437SNiklas Söderlund }; 2008*d435d437SNiklas Söderlund 2009*d435d437SNiklas Söderlund port@8 { 2010*d435d437SNiklas Söderlund reg = <8>; 2011*d435d437SNiklas Söderlund isp1vin15: endpoint { 2012*d435d437SNiklas Söderlund remote-endpoint = <&vin15isp1>; 2013*d435d437SNiklas Söderlund }; 2014*d435d437SNiklas Söderlund }; 2015*d435d437SNiklas Söderlund }; 2016*d435d437SNiklas Söderlund }; 2017*d435d437SNiklas Söderlund 201895d60f13STomi Valkeinen dsi0: dsi-encoder@fed80000 { 201995d60f13STomi Valkeinen compatible = "renesas,r8a779g0-dsi-csi2-tx"; 202095d60f13STomi Valkeinen reg = <0 0xfed80000 0 0x10000>; 202195d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 415>, 202295d60f13STomi Valkeinen <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, 202395d60f13STomi Valkeinen <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; 202495d60f13STomi Valkeinen clock-names = "fck", "dsi", "pll"; 202595d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 202695d60f13STomi Valkeinen resets = <&cpg 415>; 202795d60f13STomi Valkeinen 202895d60f13STomi Valkeinen status = "disabled"; 202995d60f13STomi Valkeinen 203095d60f13STomi Valkeinen ports { 203195d60f13STomi Valkeinen #address-cells = <1>; 203295d60f13STomi Valkeinen #size-cells = <0>; 203395d60f13STomi Valkeinen 203495d60f13STomi Valkeinen port@0 { 203595d60f13STomi Valkeinen reg = <0>; 203695d60f13STomi Valkeinen dsi0_in: endpoint { 203795d60f13STomi Valkeinen remote-endpoint = <&du_out_dsi0>; 203895d60f13STomi Valkeinen }; 203995d60f13STomi Valkeinen }; 204095d60f13STomi Valkeinen 204195d60f13STomi Valkeinen port@1 { 204295d60f13STomi Valkeinen reg = <1>; 204395d60f13STomi Valkeinen }; 204495d60f13STomi Valkeinen }; 204595d60f13STomi Valkeinen }; 204695d60f13STomi Valkeinen 204795d60f13STomi Valkeinen dsi1: dsi-encoder@fed90000 { 204895d60f13STomi Valkeinen compatible = "renesas,r8a779g0-dsi-csi2-tx"; 204995d60f13STomi Valkeinen reg = <0 0xfed90000 0 0x10000>; 205095d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 416>, 205195d60f13STomi Valkeinen <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, 205295d60f13STomi Valkeinen <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; 205395d60f13STomi Valkeinen clock-names = "fck", "dsi", "pll"; 205495d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 205595d60f13STomi Valkeinen resets = <&cpg 416>; 205695d60f13STomi Valkeinen 205795d60f13STomi Valkeinen status = "disabled"; 205895d60f13STomi Valkeinen 205995d60f13STomi Valkeinen ports { 206095d60f13STomi Valkeinen #address-cells = <1>; 206195d60f13STomi Valkeinen #size-cells = <0>; 206295d60f13STomi Valkeinen 206395d60f13STomi Valkeinen port@0 { 206495d60f13STomi Valkeinen reg = <0>; 206595d60f13STomi Valkeinen dsi1_in: endpoint { 206695d60f13STomi Valkeinen remote-endpoint = <&du_out_dsi1>; 206795d60f13STomi Valkeinen }; 206895d60f13STomi Valkeinen }; 206995d60f13STomi Valkeinen 207095d60f13STomi Valkeinen port@1 { 207195d60f13STomi Valkeinen reg = <1>; 207295d60f13STomi Valkeinen }; 207395d60f13STomi Valkeinen }; 207495d60f13STomi Valkeinen }; 207595d60f13STomi Valkeinen 2076987da486SYoshihiro Shimoda prr: chipid@fff00044 { 2077987da486SYoshihiro Shimoda compatible = "renesas,prr"; 2078987da486SYoshihiro Shimoda reg = <0 0xfff00044 0 4>; 2079987da486SYoshihiro Shimoda }; 2080987da486SYoshihiro Shimoda }; 2081987da486SYoshihiro Shimoda 2082d8ac71d2SGeert Uytterhoeven thermal-zones { 2083d8ac71d2SGeert Uytterhoeven sensor_thermal_cr52: sensor1-thermal { 2084d8ac71d2SGeert Uytterhoeven polling-delay-passive = <250>; 2085d8ac71d2SGeert Uytterhoeven polling-delay = <1000>; 2086d8ac71d2SGeert Uytterhoeven thermal-sensors = <&tsc 0>; 2087d8ac71d2SGeert Uytterhoeven 2088d8ac71d2SGeert Uytterhoeven trips { 2089d8ac71d2SGeert Uytterhoeven sensor1_crit: sensor1-crit { 2090d8ac71d2SGeert Uytterhoeven temperature = <120000>; 2091d8ac71d2SGeert Uytterhoeven hysteresis = <1000>; 2092d8ac71d2SGeert Uytterhoeven type = "critical"; 2093d8ac71d2SGeert Uytterhoeven }; 2094d8ac71d2SGeert Uytterhoeven }; 2095d8ac71d2SGeert Uytterhoeven }; 2096d8ac71d2SGeert Uytterhoeven 2097d8ac71d2SGeert Uytterhoeven sensor_thermal_cnn: sensor2-thermal { 2098d8ac71d2SGeert Uytterhoeven polling-delay-passive = <250>; 2099d8ac71d2SGeert Uytterhoeven polling-delay = <1000>; 2100d8ac71d2SGeert Uytterhoeven thermal-sensors = <&tsc 1>; 2101d8ac71d2SGeert Uytterhoeven 2102d8ac71d2SGeert Uytterhoeven trips { 2103d8ac71d2SGeert Uytterhoeven sensor2_crit: sensor2-crit { 2104d8ac71d2SGeert Uytterhoeven temperature = <120000>; 2105d8ac71d2SGeert Uytterhoeven hysteresis = <1000>; 2106d8ac71d2SGeert Uytterhoeven type = "critical"; 2107d8ac71d2SGeert Uytterhoeven }; 2108d8ac71d2SGeert Uytterhoeven }; 2109d8ac71d2SGeert Uytterhoeven }; 2110d8ac71d2SGeert Uytterhoeven 2111d8ac71d2SGeert Uytterhoeven sensor_thermal_ca76: sensor3-thermal { 2112d8ac71d2SGeert Uytterhoeven polling-delay-passive = <250>; 2113d8ac71d2SGeert Uytterhoeven polling-delay = <1000>; 2114d8ac71d2SGeert Uytterhoeven thermal-sensors = <&tsc 2>; 2115d8ac71d2SGeert Uytterhoeven 2116d8ac71d2SGeert Uytterhoeven trips { 2117d8ac71d2SGeert Uytterhoeven sensor3_crit: sensor3-crit { 2118d8ac71d2SGeert Uytterhoeven temperature = <120000>; 2119d8ac71d2SGeert Uytterhoeven hysteresis = <1000>; 2120d8ac71d2SGeert Uytterhoeven type = "critical"; 2121d8ac71d2SGeert Uytterhoeven }; 2122d8ac71d2SGeert Uytterhoeven }; 2123d8ac71d2SGeert Uytterhoeven }; 2124d8ac71d2SGeert Uytterhoeven 2125d8ac71d2SGeert Uytterhoeven sensor_thermal_ddr1: sensor4-thermal { 2126d8ac71d2SGeert Uytterhoeven polling-delay-passive = <250>; 2127d8ac71d2SGeert Uytterhoeven polling-delay = <1000>; 2128d8ac71d2SGeert Uytterhoeven thermal-sensors = <&tsc 3>; 2129d8ac71d2SGeert Uytterhoeven 2130d8ac71d2SGeert Uytterhoeven trips { 2131d8ac71d2SGeert Uytterhoeven sensor4_crit: sensor4-crit { 2132d8ac71d2SGeert Uytterhoeven temperature = <120000>; 2133d8ac71d2SGeert Uytterhoeven hysteresis = <1000>; 2134d8ac71d2SGeert Uytterhoeven type = "critical"; 2135d8ac71d2SGeert Uytterhoeven }; 2136d8ac71d2SGeert Uytterhoeven }; 2137d8ac71d2SGeert Uytterhoeven }; 2138d8ac71d2SGeert Uytterhoeven }; 2139d8ac71d2SGeert Uytterhoeven 2140987da486SYoshihiro Shimoda timer { 2141987da486SYoshihiro Shimoda compatible = "arm,armv8-timer"; 21428b6a006cSLad Prabhakar interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 21438b6a006cSLad Prabhakar <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 21448b6a006cSLad Prabhakar <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 21458b6a006cSLad Prabhakar <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2146987da486SYoshihiro Shimoda }; 2147987da486SYoshihiro Shimoda}; 2148