1987da486SYoshihiro Shimoda// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2987da486SYoshihiro Shimoda/* 3987da486SYoshihiro Shimoda * Device Tree Source for the R-Car V4H (R8A779G0) SoC 4987da486SYoshihiro Shimoda * 5987da486SYoshihiro Shimoda * Copyright (C) 2022 Renesas Electronics Corp. 6987da486SYoshihiro Shimoda */ 7987da486SYoshihiro Shimoda 8987da486SYoshihiro Shimoda#include <dt-bindings/clock/r8a779g0-cpg-mssr.h> 9987da486SYoshihiro Shimoda#include <dt-bindings/interrupt-controller/arm-gic.h> 10987da486SYoshihiro Shimoda#include <dt-bindings/power/r8a779g0-sysc.h> 11987da486SYoshihiro Shimoda 12987da486SYoshihiro Shimoda/ { 13987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0"; 14987da486SYoshihiro Shimoda #address-cells = <2>; 15987da486SYoshihiro Shimoda #size-cells = <2>; 16987da486SYoshihiro Shimoda 17987da486SYoshihiro Shimoda cpus { 18987da486SYoshihiro Shimoda #address-cells = <1>; 19987da486SYoshihiro Shimoda #size-cells = <0>; 20987da486SYoshihiro Shimoda 21987da486SYoshihiro Shimoda a76_0: cpu@0 { 22987da486SYoshihiro Shimoda compatible = "arm,cortex-a76"; 23987da486SYoshihiro Shimoda reg = <0>; 24987da486SYoshihiro Shimoda device_type = "cpu"; 25987da486SYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; 26987da486SYoshihiro Shimoda }; 27987da486SYoshihiro Shimoda }; 28987da486SYoshihiro Shimoda 29987da486SYoshihiro Shimoda extal_clk: extal { 30987da486SYoshihiro Shimoda compatible = "fixed-clock"; 31987da486SYoshihiro Shimoda #clock-cells = <0>; 32987da486SYoshihiro Shimoda /* This value must be overridden by the board */ 33987da486SYoshihiro Shimoda clock-frequency = <0>; 34987da486SYoshihiro Shimoda }; 35987da486SYoshihiro Shimoda 36987da486SYoshihiro Shimoda extalr_clk: extalr { 37987da486SYoshihiro Shimoda compatible = "fixed-clock"; 38987da486SYoshihiro Shimoda #clock-cells = <0>; 39987da486SYoshihiro Shimoda /* This value must be overridden by the board */ 40987da486SYoshihiro Shimoda clock-frequency = <0>; 41987da486SYoshihiro Shimoda }; 42987da486SYoshihiro Shimoda 43987da486SYoshihiro Shimoda pmu_a76 { 44987da486SYoshihiro Shimoda compatible = "arm,cortex-a76-pmu"; 45987da486SYoshihiro Shimoda interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 46987da486SYoshihiro Shimoda }; 47987da486SYoshihiro Shimoda 48987da486SYoshihiro Shimoda /* External SCIF clock - to be overridden by boards that provide it */ 49987da486SYoshihiro Shimoda scif_clk: scif { 50987da486SYoshihiro Shimoda compatible = "fixed-clock"; 51987da486SYoshihiro Shimoda #clock-cells = <0>; 52987da486SYoshihiro Shimoda clock-frequency = <0>; 53987da486SYoshihiro Shimoda }; 54987da486SYoshihiro Shimoda 55987da486SYoshihiro Shimoda soc: soc { 56987da486SYoshihiro Shimoda compatible = "simple-bus"; 57987da486SYoshihiro Shimoda interrupt-parent = <&gic>; 58987da486SYoshihiro Shimoda #address-cells = <2>; 59987da486SYoshihiro Shimoda #size-cells = <2>; 60987da486SYoshihiro Shimoda ranges; 61987da486SYoshihiro Shimoda 62a43306faSGeert Uytterhoeven rwdt: watchdog@e6020000 { 63a43306faSGeert Uytterhoeven compatible = "renesas,r8a779g0-wdt", 64a43306faSGeert Uytterhoeven "renesas,rcar-gen4-wdt"; 65a43306faSGeert Uytterhoeven reg = <0 0xe6020000 0 0x0c>; 66a43306faSGeert Uytterhoeven interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 67a43306faSGeert Uytterhoeven clocks = <&cpg CPG_MOD 907>; 68a43306faSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 69a43306faSGeert Uytterhoeven resets = <&cpg 907>; 70a43306faSGeert Uytterhoeven status = "disabled"; 71a43306faSGeert Uytterhoeven }; 72a43306faSGeert Uytterhoeven 73*4cebce25SGeert Uytterhoeven pfc: pinctrl@e6050000 { 74*4cebce25SGeert Uytterhoeven compatible = "renesas,pfc-r8a779g0"; 75*4cebce25SGeert Uytterhoeven reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 76*4cebce25SGeert Uytterhoeven <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, 77*4cebce25SGeert Uytterhoeven <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, 78*4cebce25SGeert Uytterhoeven <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, 79*4cebce25SGeert Uytterhoeven <0 0xe6068000 0 0x16c>; 80*4cebce25SGeert Uytterhoeven }; 81*4cebce25SGeert Uytterhoeven 82987da486SYoshihiro Shimoda cpg: clock-controller@e6150000 { 83987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0-cpg-mssr"; 84987da486SYoshihiro Shimoda reg = <0 0xe6150000 0 0x4000>; 85987da486SYoshihiro Shimoda clocks = <&extal_clk>, <&extalr_clk>; 86987da486SYoshihiro Shimoda clock-names = "extal", "extalr"; 87987da486SYoshihiro Shimoda #clock-cells = <2>; 88987da486SYoshihiro Shimoda #power-domain-cells = <0>; 89987da486SYoshihiro Shimoda #reset-cells = <1>; 90987da486SYoshihiro Shimoda }; 91987da486SYoshihiro Shimoda 92987da486SYoshihiro Shimoda rst: reset-controller@e6160000 { 93987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0-rst"; 94987da486SYoshihiro Shimoda reg = <0 0xe6160000 0 0x4000>; 95987da486SYoshihiro Shimoda }; 96987da486SYoshihiro Shimoda 97987da486SYoshihiro Shimoda sysc: system-controller@e6180000 { 98987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0-sysc"; 99987da486SYoshihiro Shimoda reg = <0 0xe6180000 0 0x4000>; 100987da486SYoshihiro Shimoda #power-domain-cells = <1>; 101987da486SYoshihiro Shimoda }; 102987da486SYoshihiro Shimoda 103987da486SYoshihiro Shimoda hscif0: serial@e6540000 { 104987da486SYoshihiro Shimoda compatible = "renesas,hscif-r8a779g0", 105987da486SYoshihiro Shimoda "renesas,rcar-gen4-hscif", 106987da486SYoshihiro Shimoda "renesas,hscif"; 107987da486SYoshihiro Shimoda reg = <0 0xe6540000 0 96>; 108ab2866f1SGeert Uytterhoeven interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 109987da486SYoshihiro Shimoda clocks = <&cpg CPG_MOD 514>, 110987da486SYoshihiro Shimoda <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>, 111987da486SYoshihiro Shimoda <&scif_clk>; 112987da486SYoshihiro Shimoda clock-names = "fck", "brg_int", "scif_clk"; 113987da486SYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 114987da486SYoshihiro Shimoda resets = <&cpg 514>; 115987da486SYoshihiro Shimoda status = "disabled"; 116987da486SYoshihiro Shimoda }; 117987da486SYoshihiro Shimoda 118987da486SYoshihiro Shimoda gic: interrupt-controller@f1000000 { 119987da486SYoshihiro Shimoda compatible = "arm,gic-v3"; 120987da486SYoshihiro Shimoda #interrupt-cells = <3>; 121987da486SYoshihiro Shimoda #address-cells = <0>; 122987da486SYoshihiro Shimoda interrupt-controller; 123987da486SYoshihiro Shimoda reg = <0x0 0xf1000000 0 0x20000>, 124987da486SYoshihiro Shimoda <0x0 0xf1060000 0 0x110000>; 125987da486SYoshihiro Shimoda interrupts = <GIC_PPI 9 126987da486SYoshihiro Shimoda (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 127987da486SYoshihiro Shimoda }; 128987da486SYoshihiro Shimoda 129987da486SYoshihiro Shimoda prr: chipid@fff00044 { 130987da486SYoshihiro Shimoda compatible = "renesas,prr"; 131987da486SYoshihiro Shimoda reg = <0 0xfff00044 0 4>; 132987da486SYoshihiro Shimoda }; 133987da486SYoshihiro Shimoda }; 134987da486SYoshihiro Shimoda 135987da486SYoshihiro Shimoda timer { 136987da486SYoshihiro Shimoda compatible = "arm,armv8-timer"; 137987da486SYoshihiro Shimoda interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 138987da486SYoshihiro Shimoda <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 139987da486SYoshihiro Shimoda <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 140987da486SYoshihiro Shimoda <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 141987da486SYoshihiro Shimoda }; 142987da486SYoshihiro Shimoda}; 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