1987da486SYoshihiro Shimoda// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2987da486SYoshihiro Shimoda/* 3987da486SYoshihiro Shimoda * Device Tree Source for the R-Car V4H (R8A779G0) SoC 4987da486SYoshihiro Shimoda * 5987da486SYoshihiro Shimoda * Copyright (C) 2022 Renesas Electronics Corp. 6987da486SYoshihiro Shimoda */ 7987da486SYoshihiro Shimoda 8987da486SYoshihiro Shimoda#include <dt-bindings/clock/r8a779g0-cpg-mssr.h> 9987da486SYoshihiro Shimoda#include <dt-bindings/interrupt-controller/arm-gic.h> 10987da486SYoshihiro Shimoda#include <dt-bindings/power/r8a779g0-sysc.h> 11987da486SYoshihiro Shimoda 12987da486SYoshihiro Shimoda/ { 13987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0"; 14987da486SYoshihiro Shimoda #address-cells = <2>; 15987da486SYoshihiro Shimoda #size-cells = <2>; 16987da486SYoshihiro Shimoda 176cf8e3d7SKuninori Morimoto /* External Audio clock - to be overridden by boards that provide it */ 186cf8e3d7SKuninori Morimoto audio_clkin: audio_clkin { 196cf8e3d7SKuninori Morimoto compatible = "fixed-clock"; 206cf8e3d7SKuninori Morimoto #clock-cells = <0>; 216cf8e3d7SKuninori Morimoto clock-frequency = <0>; 226cf8e3d7SKuninori Morimoto }; 236cf8e3d7SKuninori Morimoto 245056a0c7SGeert Uytterhoeven /* External CAN clock - to be overridden by boards that provide it */ 255056a0c7SGeert Uytterhoeven can_clk: can { 265056a0c7SGeert Uytterhoeven compatible = "fixed-clock"; 275056a0c7SGeert Uytterhoeven #clock-cells = <0>; 285056a0c7SGeert Uytterhoeven clock-frequency = <0>; 295056a0c7SGeert Uytterhoeven }; 305056a0c7SGeert Uytterhoeven 319a0e6306SGeert Uytterhoeven cluster0_opp: opp-table-0 { 329a0e6306SGeert Uytterhoeven compatible = "operating-points-v2"; 339a0e6306SGeert Uytterhoeven opp-shared; 349a0e6306SGeert Uytterhoeven 359a0e6306SGeert Uytterhoeven opp-500000000 { 369a0e6306SGeert Uytterhoeven opp-hz = /bits/ 64 <500000000>; 379a0e6306SGeert Uytterhoeven opp-microvolt = <825000>; 389a0e6306SGeert Uytterhoeven clock-latency-ns = <500000>; 399a0e6306SGeert Uytterhoeven }; 409a0e6306SGeert Uytterhoeven opp-1000000000 { 419a0e6306SGeert Uytterhoeven opp-hz = /bits/ 64 <1000000000>; 429a0e6306SGeert Uytterhoeven opp-microvolt = <825000>; 439a0e6306SGeert Uytterhoeven clock-latency-ns = <500000>; 449a0e6306SGeert Uytterhoeven }; 459a0e6306SGeert Uytterhoeven opp-1500000000 { 469a0e6306SGeert Uytterhoeven opp-hz = /bits/ 64 <1500000000>; 479a0e6306SGeert Uytterhoeven opp-microvolt = <825000>; 489a0e6306SGeert Uytterhoeven clock-latency-ns = <500000>; 499a0e6306SGeert Uytterhoeven }; 509a0e6306SGeert Uytterhoeven opp-1700000000 { 519a0e6306SGeert Uytterhoeven opp-hz = /bits/ 64 <1700000000>; 529a0e6306SGeert Uytterhoeven opp-microvolt = <825000>; 539a0e6306SGeert Uytterhoeven clock-latency-ns = <500000>; 549a0e6306SGeert Uytterhoeven opp-suspend; 559a0e6306SGeert Uytterhoeven }; 5687d85b48SGeert Uytterhoeven opp-1800000000 { 5787d85b48SGeert Uytterhoeven opp-hz = /bits/ 64 <1800000000>; 5887d85b48SGeert Uytterhoeven opp-microvolt = <880000>; 5987d85b48SGeert Uytterhoeven clock-latency-ns = <500000>; 6087d85b48SGeert Uytterhoeven turbo-mode; 6187d85b48SGeert Uytterhoeven }; 629a0e6306SGeert Uytterhoeven }; 639a0e6306SGeert Uytterhoeven 64987da486SYoshihiro Shimoda cpus { 65987da486SYoshihiro Shimoda #address-cells = <1>; 66987da486SYoshihiro Shimoda #size-cells = <0>; 67987da486SYoshihiro Shimoda 6868c9c53dSGeert Uytterhoeven cpu-map { 6968c9c53dSGeert Uytterhoeven cluster0 { 7068c9c53dSGeert Uytterhoeven core0 { 7168c9c53dSGeert Uytterhoeven cpu = <&a76_0>; 7268c9c53dSGeert Uytterhoeven }; 7368c9c53dSGeert Uytterhoeven core1 { 7468c9c53dSGeert Uytterhoeven cpu = <&a76_1>; 7568c9c53dSGeert Uytterhoeven }; 7668c9c53dSGeert Uytterhoeven }; 7768c9c53dSGeert Uytterhoeven 7868c9c53dSGeert Uytterhoeven cluster1 { 7968c9c53dSGeert Uytterhoeven core0 { 8068c9c53dSGeert Uytterhoeven cpu = <&a76_2>; 8168c9c53dSGeert Uytterhoeven }; 8268c9c53dSGeert Uytterhoeven core1 { 8368c9c53dSGeert Uytterhoeven cpu = <&a76_3>; 8468c9c53dSGeert Uytterhoeven }; 8568c9c53dSGeert Uytterhoeven }; 8668c9c53dSGeert Uytterhoeven }; 8768c9c53dSGeert Uytterhoeven 88987da486SYoshihiro Shimoda a76_0: cpu@0 { 89987da486SYoshihiro Shimoda compatible = "arm,cortex-a76"; 90987da486SYoshihiro Shimoda reg = <0>; 91987da486SYoshihiro Shimoda device_type = "cpu"; 92987da486SYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; 93f0840721SGeert Uytterhoeven next-level-cache = <&L3_CA76_0>; 9468c9c53dSGeert Uytterhoeven enable-method = "psci"; 955bb355a8SGeert Uytterhoeven cpu-idle-states = <&CPU_SLEEP_0>; 96ee8ce199SGeert Uytterhoeven clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; 979a0e6306SGeert Uytterhoeven operating-points-v2 = <&cluster0_opp>; 9868c9c53dSGeert Uytterhoeven }; 9968c9c53dSGeert Uytterhoeven 10068c9c53dSGeert Uytterhoeven a76_1: cpu@100 { 10168c9c53dSGeert Uytterhoeven compatible = "arm,cortex-a76"; 10268c9c53dSGeert Uytterhoeven reg = <0x100>; 10368c9c53dSGeert Uytterhoeven device_type = "cpu"; 10468c9c53dSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_A1E0D0C1>; 10568c9c53dSGeert Uytterhoeven next-level-cache = <&L3_CA76_0>; 10668c9c53dSGeert Uytterhoeven enable-method = "psci"; 1075bb355a8SGeert Uytterhoeven cpu-idle-states = <&CPU_SLEEP_0>; 108ee8ce199SGeert Uytterhoeven clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; 1099a0e6306SGeert Uytterhoeven operating-points-v2 = <&cluster0_opp>; 11068c9c53dSGeert Uytterhoeven }; 11168c9c53dSGeert Uytterhoeven 11268c9c53dSGeert Uytterhoeven a76_2: cpu@10000 { 11368c9c53dSGeert Uytterhoeven compatible = "arm,cortex-a76"; 11468c9c53dSGeert Uytterhoeven reg = <0x10000>; 11568c9c53dSGeert Uytterhoeven device_type = "cpu"; 11668c9c53dSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_A1E0D1C0>; 11768c9c53dSGeert Uytterhoeven next-level-cache = <&L3_CA76_1>; 11868c9c53dSGeert Uytterhoeven enable-method = "psci"; 1195bb355a8SGeert Uytterhoeven cpu-idle-states = <&CPU_SLEEP_0>; 120ee8ce199SGeert Uytterhoeven clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; 1219a0e6306SGeert Uytterhoeven operating-points-v2 = <&cluster0_opp>; 12268c9c53dSGeert Uytterhoeven }; 12368c9c53dSGeert Uytterhoeven 12468c9c53dSGeert Uytterhoeven a76_3: cpu@10100 { 12568c9c53dSGeert Uytterhoeven compatible = "arm,cortex-a76"; 12668c9c53dSGeert Uytterhoeven reg = <0x10100>; 12768c9c53dSGeert Uytterhoeven device_type = "cpu"; 12868c9c53dSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_A1E0D1C1>; 12968c9c53dSGeert Uytterhoeven next-level-cache = <&L3_CA76_1>; 13068c9c53dSGeert Uytterhoeven enable-method = "psci"; 1315bb355a8SGeert Uytterhoeven cpu-idle-states = <&CPU_SLEEP_0>; 132ee8ce199SGeert Uytterhoeven clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; 1339a0e6306SGeert Uytterhoeven operating-points-v2 = <&cluster0_opp>; 1345bb355a8SGeert Uytterhoeven }; 1355bb355a8SGeert Uytterhoeven 1365bb355a8SGeert Uytterhoeven idle-states { 1375bb355a8SGeert Uytterhoeven entry-method = "psci"; 1385bb355a8SGeert Uytterhoeven 1395bb355a8SGeert Uytterhoeven CPU_SLEEP_0: cpu-sleep-0 { 1405bb355a8SGeert Uytterhoeven compatible = "arm,idle-state"; 1415bb355a8SGeert Uytterhoeven arm,psci-suspend-param = <0x0010000>; 1425bb355a8SGeert Uytterhoeven local-timer-stop; 1435bb355a8SGeert Uytterhoeven entry-latency-us = <400>; 1445bb355a8SGeert Uytterhoeven exit-latency-us = <500>; 1455bb355a8SGeert Uytterhoeven min-residency-us = <4000>; 1465bb355a8SGeert Uytterhoeven }; 147f0840721SGeert Uytterhoeven }; 148f0840721SGeert Uytterhoeven 149f0840721SGeert Uytterhoeven L3_CA76_0: cache-controller-0 { 150f0840721SGeert Uytterhoeven compatible = "cache"; 151f0840721SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_A2E0D0>; 152f0840721SGeert Uytterhoeven cache-unified; 153f0840721SGeert Uytterhoeven cache-level = <3>; 154987da486SYoshihiro Shimoda }; 15568c9c53dSGeert Uytterhoeven 15668c9c53dSGeert Uytterhoeven L3_CA76_1: cache-controller-1 { 15768c9c53dSGeert Uytterhoeven compatible = "cache"; 15868c9c53dSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_A2E0D1>; 15968c9c53dSGeert Uytterhoeven cache-unified; 16068c9c53dSGeert Uytterhoeven cache-level = <3>; 16168c9c53dSGeert Uytterhoeven }; 16268c9c53dSGeert Uytterhoeven }; 16368c9c53dSGeert Uytterhoeven 16468c9c53dSGeert Uytterhoeven psci { 16568c9c53dSGeert Uytterhoeven compatible = "arm,psci-1.0", "arm,psci-0.2"; 16668c9c53dSGeert Uytterhoeven method = "smc"; 167987da486SYoshihiro Shimoda }; 168987da486SYoshihiro Shimoda 169987da486SYoshihiro Shimoda extal_clk: extal { 170987da486SYoshihiro Shimoda compatible = "fixed-clock"; 171987da486SYoshihiro Shimoda #clock-cells = <0>; 172987da486SYoshihiro Shimoda /* This value must be overridden by the board */ 173987da486SYoshihiro Shimoda clock-frequency = <0>; 174987da486SYoshihiro Shimoda }; 175987da486SYoshihiro Shimoda 176987da486SYoshihiro Shimoda extalr_clk: extalr { 177987da486SYoshihiro Shimoda compatible = "fixed-clock"; 178987da486SYoshihiro Shimoda #clock-cells = <0>; 179987da486SYoshihiro Shimoda /* This value must be overridden by the board */ 180987da486SYoshihiro Shimoda clock-frequency = <0>; 181987da486SYoshihiro Shimoda }; 182987da486SYoshihiro Shimoda 183987da486SYoshihiro Shimoda pmu_a76 { 184987da486SYoshihiro Shimoda compatible = "arm,cortex-a76-pmu"; 185987da486SYoshihiro Shimoda interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 186987da486SYoshihiro Shimoda }; 187987da486SYoshihiro Shimoda 188987da486SYoshihiro Shimoda /* External SCIF clock - to be overridden by boards that provide it */ 189987da486SYoshihiro Shimoda scif_clk: scif { 190987da486SYoshihiro Shimoda compatible = "fixed-clock"; 191987da486SYoshihiro Shimoda #clock-cells = <0>; 192987da486SYoshihiro Shimoda clock-frequency = <0>; 193987da486SYoshihiro Shimoda }; 194987da486SYoshihiro Shimoda 195987da486SYoshihiro Shimoda soc: soc { 196987da486SYoshihiro Shimoda compatible = "simple-bus"; 197987da486SYoshihiro Shimoda interrupt-parent = <&gic>; 198987da486SYoshihiro Shimoda #address-cells = <2>; 199987da486SYoshihiro Shimoda #size-cells = <2>; 200987da486SYoshihiro Shimoda ranges; 201987da486SYoshihiro Shimoda 202a43306faSGeert Uytterhoeven rwdt: watchdog@e6020000 { 203a43306faSGeert Uytterhoeven compatible = "renesas,r8a779g0-wdt", 204a43306faSGeert Uytterhoeven "renesas,rcar-gen4-wdt"; 205a43306faSGeert Uytterhoeven reg = <0 0xe6020000 0 0x0c>; 206a43306faSGeert Uytterhoeven interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 207a43306faSGeert Uytterhoeven clocks = <&cpg CPG_MOD 907>; 208a43306faSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 209a43306faSGeert Uytterhoeven resets = <&cpg 907>; 210a43306faSGeert Uytterhoeven status = "disabled"; 211a43306faSGeert Uytterhoeven }; 212a43306faSGeert Uytterhoeven 2134cebce25SGeert Uytterhoeven pfc: pinctrl@e6050000 { 2144cebce25SGeert Uytterhoeven compatible = "renesas,pfc-r8a779g0"; 2154cebce25SGeert Uytterhoeven reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 2164cebce25SGeert Uytterhoeven <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, 2174cebce25SGeert Uytterhoeven <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, 2184cebce25SGeert Uytterhoeven <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, 2194cebce25SGeert Uytterhoeven <0 0xe6068000 0 0x16c>; 2204cebce25SGeert Uytterhoeven }; 2214cebce25SGeert Uytterhoeven 222120c7a58SGeert Uytterhoeven gpio0: gpio@e6050180 { 223120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 224120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 225120c7a58SGeert Uytterhoeven reg = <0 0xe6050180 0 0x54>; 226120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>; 227120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 915>; 228120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 229120c7a58SGeert Uytterhoeven resets = <&cpg 915>; 230120c7a58SGeert Uytterhoeven gpio-controller; 231120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 232120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 0 19>; 233120c7a58SGeert Uytterhoeven interrupt-controller; 234120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 235120c7a58SGeert Uytterhoeven }; 236120c7a58SGeert Uytterhoeven 237120c7a58SGeert Uytterhoeven gpio1: gpio@e6050980 { 238120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 239120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 240120c7a58SGeert Uytterhoeven reg = <0 0xe6050980 0 0x54>; 241120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>; 242120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 915>; 243120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 244120c7a58SGeert Uytterhoeven resets = <&cpg 915>; 245120c7a58SGeert Uytterhoeven gpio-controller; 246120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 247120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 32 29>; 248120c7a58SGeert Uytterhoeven interrupt-controller; 249120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 250120c7a58SGeert Uytterhoeven }; 251120c7a58SGeert Uytterhoeven 252120c7a58SGeert Uytterhoeven gpio2: gpio@e6058180 { 253120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 254120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 255120c7a58SGeert Uytterhoeven reg = <0 0xe6058180 0 0x54>; 256120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>; 257120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 916>; 258120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 259120c7a58SGeert Uytterhoeven resets = <&cpg 916>; 260120c7a58SGeert Uytterhoeven gpio-controller; 261120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 262120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 64 20>; 263120c7a58SGeert Uytterhoeven interrupt-controller; 264120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 265120c7a58SGeert Uytterhoeven }; 266120c7a58SGeert Uytterhoeven 267120c7a58SGeert Uytterhoeven gpio3: gpio@e6058980 { 268120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 269120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 270120c7a58SGeert Uytterhoeven reg = <0 0xe6058980 0 0x54>; 271120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>; 272120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 916>; 273120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 274120c7a58SGeert Uytterhoeven resets = <&cpg 916>; 275120c7a58SGeert Uytterhoeven gpio-controller; 276120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 277120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 96 30>; 278120c7a58SGeert Uytterhoeven interrupt-controller; 279120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 280120c7a58SGeert Uytterhoeven }; 281120c7a58SGeert Uytterhoeven 282120c7a58SGeert Uytterhoeven gpio4: gpio@e6060180 { 283120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 284120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 285120c7a58SGeert Uytterhoeven reg = <0 0xe6060180 0 0x54>; 286120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>; 287120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 917>; 288120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 289120c7a58SGeert Uytterhoeven resets = <&cpg 917>; 290120c7a58SGeert Uytterhoeven gpio-controller; 291120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 292120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 128 25>; 293120c7a58SGeert Uytterhoeven interrupt-controller; 294120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 295120c7a58SGeert Uytterhoeven }; 296120c7a58SGeert Uytterhoeven 297120c7a58SGeert Uytterhoeven gpio5: gpio@e6060980 { 298120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 299120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 300120c7a58SGeert Uytterhoeven reg = <0 0xe6060980 0 0x54>; 301120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; 302120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 917>; 303120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 304120c7a58SGeert Uytterhoeven resets = <&cpg 917>; 305120c7a58SGeert Uytterhoeven gpio-controller; 306120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 307120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 160 21>; 308120c7a58SGeert Uytterhoeven interrupt-controller; 309120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 310120c7a58SGeert Uytterhoeven }; 311120c7a58SGeert Uytterhoeven 312120c7a58SGeert Uytterhoeven gpio6: gpio@e6061180 { 313120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 314120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 315120c7a58SGeert Uytterhoeven reg = <0 0xe6061180 0 0x54>; 316120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 317120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 917>; 318120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 319120c7a58SGeert Uytterhoeven resets = <&cpg 917>; 320120c7a58SGeert Uytterhoeven gpio-controller; 321120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 322120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 192 21>; 323120c7a58SGeert Uytterhoeven interrupt-controller; 324120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 325120c7a58SGeert Uytterhoeven }; 326120c7a58SGeert Uytterhoeven 327120c7a58SGeert Uytterhoeven gpio7: gpio@e6061980 { 328120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 329120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 330120c7a58SGeert Uytterhoeven reg = <0 0xe6061980 0 0x54>; 331120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>; 332120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 917>; 333120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 334120c7a58SGeert Uytterhoeven resets = <&cpg 917>; 335120c7a58SGeert Uytterhoeven gpio-controller; 336120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 337120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 224 21>; 338120c7a58SGeert Uytterhoeven interrupt-controller; 339120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 340120c7a58SGeert Uytterhoeven }; 341120c7a58SGeert Uytterhoeven 342120c7a58SGeert Uytterhoeven gpio8: gpio@e6068180 { 343120c7a58SGeert Uytterhoeven compatible = "renesas,gpio-r8a779g0", 344120c7a58SGeert Uytterhoeven "renesas,rcar-gen4-gpio"; 345120c7a58SGeert Uytterhoeven reg = <0 0xe6068180 0 0x54>; 346120c7a58SGeert Uytterhoeven interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>; 347120c7a58SGeert Uytterhoeven clocks = <&cpg CPG_MOD 918>; 348120c7a58SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 349120c7a58SGeert Uytterhoeven resets = <&cpg 918>; 350120c7a58SGeert Uytterhoeven gpio-controller; 351120c7a58SGeert Uytterhoeven #gpio-cells = <2>; 352120c7a58SGeert Uytterhoeven gpio-ranges = <&pfc 0 256 14>; 353120c7a58SGeert Uytterhoeven interrupt-controller; 354120c7a58SGeert Uytterhoeven #interrupt-cells = <2>; 355120c7a58SGeert Uytterhoeven }; 356120c7a58SGeert Uytterhoeven 35740a6dd7bSThanh Quan cmt0: timer@e60f0000 { 35840a6dd7bSThanh Quan compatible = "renesas,r8a779g0-cmt0", 35940a6dd7bSThanh Quan "renesas,rcar-gen4-cmt0"; 36040a6dd7bSThanh Quan reg = <0 0xe60f0000 0 0x1004>; 36140a6dd7bSThanh Quan interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 36240a6dd7bSThanh Quan <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 36340a6dd7bSThanh Quan clocks = <&cpg CPG_MOD 910>; 36440a6dd7bSThanh Quan clock-names = "fck"; 36540a6dd7bSThanh Quan power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 36640a6dd7bSThanh Quan resets = <&cpg 910>; 36740a6dd7bSThanh Quan status = "disabled"; 36840a6dd7bSThanh Quan }; 36940a6dd7bSThanh Quan 37040a6dd7bSThanh Quan cmt1: timer@e6130000 { 37140a6dd7bSThanh Quan compatible = "renesas,r8a779g0-cmt1", 37240a6dd7bSThanh Quan "renesas,rcar-gen4-cmt1"; 37340a6dd7bSThanh Quan reg = <0 0xe6130000 0 0x1004>; 37440a6dd7bSThanh Quan interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 37540a6dd7bSThanh Quan <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 37640a6dd7bSThanh Quan <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 37740a6dd7bSThanh Quan <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 37840a6dd7bSThanh Quan <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 37940a6dd7bSThanh Quan <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 38040a6dd7bSThanh Quan <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 38140a6dd7bSThanh Quan <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 38240a6dd7bSThanh Quan clocks = <&cpg CPG_MOD 911>; 38340a6dd7bSThanh Quan clock-names = "fck"; 38440a6dd7bSThanh Quan power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 38540a6dd7bSThanh Quan resets = <&cpg 911>; 38640a6dd7bSThanh Quan status = "disabled"; 38740a6dd7bSThanh Quan }; 38840a6dd7bSThanh Quan 38940a6dd7bSThanh Quan cmt2: timer@e6140000 { 39040a6dd7bSThanh Quan compatible = "renesas,r8a779g0-cmt1", 39140a6dd7bSThanh Quan "renesas,rcar-gen4-cmt1"; 39240a6dd7bSThanh Quan reg = <0 0xe6140000 0 0x1004>; 39340a6dd7bSThanh Quan interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 39440a6dd7bSThanh Quan <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 39540a6dd7bSThanh Quan <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 39640a6dd7bSThanh Quan <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 39740a6dd7bSThanh Quan <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 39840a6dd7bSThanh Quan <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 39940a6dd7bSThanh Quan <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 40040a6dd7bSThanh Quan <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 40140a6dd7bSThanh Quan clocks = <&cpg CPG_MOD 912>; 40240a6dd7bSThanh Quan clock-names = "fck"; 40340a6dd7bSThanh Quan power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 40440a6dd7bSThanh Quan resets = <&cpg 912>; 40540a6dd7bSThanh Quan status = "disabled"; 40640a6dd7bSThanh Quan }; 40740a6dd7bSThanh Quan 40840a6dd7bSThanh Quan cmt3: timer@e6148000 { 40940a6dd7bSThanh Quan compatible = "renesas,r8a779g0-cmt1", 41040a6dd7bSThanh Quan "renesas,rcar-gen4-cmt1"; 41140a6dd7bSThanh Quan reg = <0 0xe6148000 0 0x1004>; 41240a6dd7bSThanh Quan interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 41340a6dd7bSThanh Quan <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 41440a6dd7bSThanh Quan <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 41540a6dd7bSThanh Quan <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 41640a6dd7bSThanh Quan <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 41740a6dd7bSThanh Quan <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 41840a6dd7bSThanh Quan <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 41940a6dd7bSThanh Quan <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 42040a6dd7bSThanh Quan clocks = <&cpg CPG_MOD 913>; 42140a6dd7bSThanh Quan clock-names = "fck"; 42240a6dd7bSThanh Quan power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 42340a6dd7bSThanh Quan resets = <&cpg 913>; 42440a6dd7bSThanh Quan status = "disabled"; 42540a6dd7bSThanh Quan }; 42640a6dd7bSThanh Quan 427987da486SYoshihiro Shimoda cpg: clock-controller@e6150000 { 428987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0-cpg-mssr"; 429987da486SYoshihiro Shimoda reg = <0 0xe6150000 0 0x4000>; 430987da486SYoshihiro Shimoda clocks = <&extal_clk>, <&extalr_clk>; 431987da486SYoshihiro Shimoda clock-names = "extal", "extalr"; 432987da486SYoshihiro Shimoda #clock-cells = <2>; 433987da486SYoshihiro Shimoda #power-domain-cells = <0>; 434987da486SYoshihiro Shimoda #reset-cells = <1>; 435987da486SYoshihiro Shimoda }; 436987da486SYoshihiro Shimoda 437987da486SYoshihiro Shimoda rst: reset-controller@e6160000 { 438987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0-rst"; 439987da486SYoshihiro Shimoda reg = <0 0xe6160000 0 0x4000>; 440987da486SYoshihiro Shimoda }; 441987da486SYoshihiro Shimoda 442987da486SYoshihiro Shimoda sysc: system-controller@e6180000 { 443987da486SYoshihiro Shimoda compatible = "renesas,r8a779g0-sysc"; 444987da486SYoshihiro Shimoda reg = <0 0xe6180000 0 0x4000>; 445987da486SYoshihiro Shimoda #power-domain-cells = <1>; 446987da486SYoshihiro Shimoda }; 447987da486SYoshihiro Shimoda 448d8ac71d2SGeert Uytterhoeven tsc: thermal@e6198000 { 449d8ac71d2SGeert Uytterhoeven compatible = "renesas,r8a779g0-thermal"; 450d8ac71d2SGeert Uytterhoeven reg = <0 0xe6198000 0 0x200>, 451d8ac71d2SGeert Uytterhoeven <0 0xe61a0000 0 0x200>, 452d8ac71d2SGeert Uytterhoeven <0 0xe61a8000 0 0x200>, 453d8ac71d2SGeert Uytterhoeven <0 0xe61b0000 0 0x200>; 454d8ac71d2SGeert Uytterhoeven clocks = <&cpg CPG_MOD 919>; 455d8ac71d2SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 456d8ac71d2SGeert Uytterhoeven resets = <&cpg 919>; 457d8ac71d2SGeert Uytterhoeven #thermal-sensor-cells = <1>; 458d8ac71d2SGeert Uytterhoeven }; 459d8ac71d2SGeert Uytterhoeven 460b6ce840bSGeert Uytterhoeven intc_ex: interrupt-controller@e61c0000 { 461b6ce840bSGeert Uytterhoeven compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc"; 462b6ce840bSGeert Uytterhoeven #interrupt-cells = <2>; 463b6ce840bSGeert Uytterhoeven interrupt-controller; 464b6ce840bSGeert Uytterhoeven reg = <0 0xe61c0000 0 0x200>; 465b6ce840bSGeert Uytterhoeven interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 466b6ce840bSGeert Uytterhoeven <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 467b6ce840bSGeert Uytterhoeven <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 468b6ce840bSGeert Uytterhoeven <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 469b6ce840bSGeert Uytterhoeven <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 470b6ce840bSGeert Uytterhoeven <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 471b6ce840bSGeert Uytterhoeven clocks = <&cpg CPG_MOD 611>; 472b6ce840bSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 473b6ce840bSGeert Uytterhoeven resets = <&cpg 611>; 474b6ce840bSGeert Uytterhoeven }; 475b6ce840bSGeert Uytterhoeven 47652478925SWolfram Sang tmu0: timer@e61e0000 { 47752478925SWolfram Sang compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 47852478925SWolfram Sang reg = <0 0xe61e0000 0 0x30>; 47952478925SWolfram Sang interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 48052478925SWolfram Sang <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 48152478925SWolfram Sang <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; 48252478925SWolfram Sang clocks = <&cpg CPG_MOD 713>; 48352478925SWolfram Sang clock-names = "fck"; 48452478925SWolfram Sang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 48552478925SWolfram Sang resets = <&cpg 713>; 48652478925SWolfram Sang status = "disabled"; 48752478925SWolfram Sang }; 48852478925SWolfram Sang 48952478925SWolfram Sang tmu1: timer@e6fc0000 { 49052478925SWolfram Sang compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 49152478925SWolfram Sang reg = <0 0xe6fc0000 0 0x30>; 49252478925SWolfram Sang interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 49352478925SWolfram Sang <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 49452478925SWolfram Sang <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 49552478925SWolfram Sang clocks = <&cpg CPG_MOD 714>; 49652478925SWolfram Sang clock-names = "fck"; 49752478925SWolfram Sang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 49852478925SWolfram Sang resets = <&cpg 714>; 49952478925SWolfram Sang status = "disabled"; 50052478925SWolfram Sang }; 50152478925SWolfram Sang 50252478925SWolfram Sang tmu2: timer@e6fd0000 { 50352478925SWolfram Sang compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 50452478925SWolfram Sang reg = <0 0xe6fd0000 0 0x30>; 50552478925SWolfram Sang interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 50652478925SWolfram Sang <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 50752478925SWolfram Sang <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 50852478925SWolfram Sang clocks = <&cpg CPG_MOD 715>; 50952478925SWolfram Sang clock-names = "fck"; 51052478925SWolfram Sang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 51152478925SWolfram Sang resets = <&cpg 715>; 51252478925SWolfram Sang status = "disabled"; 51352478925SWolfram Sang }; 51452478925SWolfram Sang 51552478925SWolfram Sang tmu3: timer@e6fe0000 { 51652478925SWolfram Sang compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 51752478925SWolfram Sang reg = <0 0xe6fe0000 0 0x30>; 51852478925SWolfram Sang interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 51952478925SWolfram Sang <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 52052478925SWolfram Sang <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 52152478925SWolfram Sang clocks = <&cpg CPG_MOD 716>; 52252478925SWolfram Sang clock-names = "fck"; 52352478925SWolfram Sang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 52452478925SWolfram Sang resets = <&cpg 716>; 52552478925SWolfram Sang status = "disabled"; 52652478925SWolfram Sang }; 52752478925SWolfram Sang 52852478925SWolfram Sang tmu4: timer@ffc00000 { 52952478925SWolfram Sang compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; 53052478925SWolfram Sang reg = <0 0xffc00000 0 0x30>; 53152478925SWolfram Sang interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 53252478925SWolfram Sang <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 53352478925SWolfram Sang <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 53452478925SWolfram Sang clocks = <&cpg CPG_MOD 717>; 53552478925SWolfram Sang clock-names = "fck"; 53652478925SWolfram Sang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 53752478925SWolfram Sang resets = <&cpg 717>; 53852478925SWolfram Sang status = "disabled"; 53952478925SWolfram Sang }; 54052478925SWolfram Sang 541ff77ba05SGeert Uytterhoeven i2c0: i2c@e6500000 { 542ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 543ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 544ff77ba05SGeert Uytterhoeven reg = <0 0xe6500000 0 0x40>; 545ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 546ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 518>; 54708f28288SGeert Uytterhoeven dmas = <&dmac0 0x91>, <&dmac0 0x90>, 54808f28288SGeert Uytterhoeven <&dmac1 0x91>, <&dmac1 0x90>; 54908f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 550ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 551ff77ba05SGeert Uytterhoeven resets = <&cpg 518>; 552ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 553ff77ba05SGeert Uytterhoeven #address-cells = <1>; 554ff77ba05SGeert Uytterhoeven #size-cells = <0>; 555ff77ba05SGeert Uytterhoeven status = "disabled"; 556ff77ba05SGeert Uytterhoeven }; 557ff77ba05SGeert Uytterhoeven 558ff77ba05SGeert Uytterhoeven i2c1: i2c@e6508000 { 559ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 560ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 561ff77ba05SGeert Uytterhoeven reg = <0 0xe6508000 0 0x40>; 562ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; 563ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 519>; 56408f28288SGeert Uytterhoeven dmas = <&dmac0 0x93>, <&dmac0 0x92>, 56508f28288SGeert Uytterhoeven <&dmac1 0x93>, <&dmac1 0x92>; 56608f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 567ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 568ff77ba05SGeert Uytterhoeven resets = <&cpg 519>; 569ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 570ff77ba05SGeert Uytterhoeven #address-cells = <1>; 571ff77ba05SGeert Uytterhoeven #size-cells = <0>; 572ff77ba05SGeert Uytterhoeven status = "disabled"; 573ff77ba05SGeert Uytterhoeven }; 574ff77ba05SGeert Uytterhoeven 575ff77ba05SGeert Uytterhoeven i2c2: i2c@e6510000 { 576ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 577ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 578ff77ba05SGeert Uytterhoeven reg = <0 0xe6510000 0 0x40>; 579ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; 580ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 520>; 58108f28288SGeert Uytterhoeven dmas = <&dmac0 0x95>, <&dmac0 0x94>, 58208f28288SGeert Uytterhoeven <&dmac1 0x95>, <&dmac1 0x94>; 58308f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 584ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 585ff77ba05SGeert Uytterhoeven resets = <&cpg 520>; 586ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 587ff77ba05SGeert Uytterhoeven #address-cells = <1>; 588ff77ba05SGeert Uytterhoeven #size-cells = <0>; 589ff77ba05SGeert Uytterhoeven status = "disabled"; 590ff77ba05SGeert Uytterhoeven }; 591ff77ba05SGeert Uytterhoeven 592ff77ba05SGeert Uytterhoeven i2c3: i2c@e66d0000 { 593ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 594ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 595ff77ba05SGeert Uytterhoeven reg = <0 0xe66d0000 0 0x40>; 596ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 597ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 521>; 59808f28288SGeert Uytterhoeven dmas = <&dmac0 0x97>, <&dmac0 0x96>, 59908f28288SGeert Uytterhoeven <&dmac1 0x97>, <&dmac1 0x96>; 60008f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 601ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 602ff77ba05SGeert Uytterhoeven resets = <&cpg 521>; 603ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 604ff77ba05SGeert Uytterhoeven #address-cells = <1>; 605ff77ba05SGeert Uytterhoeven #size-cells = <0>; 606ff77ba05SGeert Uytterhoeven status = "disabled"; 607ff77ba05SGeert Uytterhoeven }; 608ff77ba05SGeert Uytterhoeven 609ff77ba05SGeert Uytterhoeven i2c4: i2c@e66d8000 { 610ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 611ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 612ff77ba05SGeert Uytterhoeven reg = <0 0xe66d8000 0 0x40>; 613ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 614ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 522>; 61508f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 61608f28288SGeert Uytterhoeven dmas = <&dmac0 0x99>, <&dmac0 0x98>, 61708f28288SGeert Uytterhoeven <&dmac1 0x99>, <&dmac1 0x98>; 618ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 619ff77ba05SGeert Uytterhoeven resets = <&cpg 522>; 620ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 621ff77ba05SGeert Uytterhoeven #address-cells = <1>; 622ff77ba05SGeert Uytterhoeven #size-cells = <0>; 623ff77ba05SGeert Uytterhoeven status = "disabled"; 624ff77ba05SGeert Uytterhoeven }; 625ff77ba05SGeert Uytterhoeven 626ff77ba05SGeert Uytterhoeven i2c5: i2c@e66e0000 { 627ff77ba05SGeert Uytterhoeven compatible = "renesas,i2c-r8a779g0", 628ff77ba05SGeert Uytterhoeven "renesas,rcar-gen4-i2c"; 629ff77ba05SGeert Uytterhoeven reg = <0 0xe66e0000 0 0x40>; 630ff77ba05SGeert Uytterhoeven interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>; 631ff77ba05SGeert Uytterhoeven clocks = <&cpg CPG_MOD 523>; 63208f28288SGeert Uytterhoeven dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 63308f28288SGeert Uytterhoeven <&dmac1 0x9b>, <&dmac1 0x9a>; 63408f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 635ff77ba05SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 636ff77ba05SGeert Uytterhoeven resets = <&cpg 523>; 637ff77ba05SGeert Uytterhoeven i2c-scl-internal-delay-ns = <110>; 638ff77ba05SGeert Uytterhoeven #address-cells = <1>; 639ff77ba05SGeert Uytterhoeven #size-cells = <0>; 640ff77ba05SGeert Uytterhoeven status = "disabled"; 641ff77ba05SGeert Uytterhoeven }; 642ff77ba05SGeert Uytterhoeven 643987da486SYoshihiro Shimoda hscif0: serial@e6540000 { 644987da486SYoshihiro Shimoda compatible = "renesas,hscif-r8a779g0", 64539d9dfc6SGeert Uytterhoeven "renesas,rcar-gen4-hscif", "renesas,hscif"; 64639d9dfc6SGeert Uytterhoeven reg = <0 0xe6540000 0 0x60>; 647ab2866f1SGeert Uytterhoeven interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 648987da486SYoshihiro Shimoda clocks = <&cpg CPG_MOD 514>, 649a4290d40SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 650987da486SYoshihiro Shimoda <&scif_clk>; 651987da486SYoshihiro Shimoda clock-names = "fck", "brg_int", "scif_clk"; 65208f28288SGeert Uytterhoeven dmas = <&dmac0 0x31>, <&dmac0 0x30>, 65308f28288SGeert Uytterhoeven <&dmac1 0x31>, <&dmac1 0x30>; 65408f28288SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 655987da486SYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 656987da486SYoshihiro Shimoda resets = <&cpg 514>; 657987da486SYoshihiro Shimoda status = "disabled"; 658987da486SYoshihiro Shimoda }; 659987da486SYoshihiro Shimoda 66039d9dfc6SGeert Uytterhoeven hscif1: serial@e6550000 { 66139d9dfc6SGeert Uytterhoeven compatible = "renesas,hscif-r8a779g0", 66239d9dfc6SGeert Uytterhoeven "renesas,rcar-gen4-hscif", "renesas,hscif"; 66339d9dfc6SGeert Uytterhoeven reg = <0 0xe6550000 0 0x60>; 66439d9dfc6SGeert Uytterhoeven interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 66539d9dfc6SGeert Uytterhoeven clocks = <&cpg CPG_MOD 515>, 66639d9dfc6SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 66739d9dfc6SGeert Uytterhoeven <&scif_clk>; 66839d9dfc6SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 66939d9dfc6SGeert Uytterhoeven dmas = <&dmac0 0x33>, <&dmac0 0x32>, 67039d9dfc6SGeert Uytterhoeven <&dmac1 0x33>, <&dmac1 0x32>; 67139d9dfc6SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 67239d9dfc6SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 67339d9dfc6SGeert Uytterhoeven resets = <&cpg 515>; 67439d9dfc6SGeert Uytterhoeven status = "disabled"; 67539d9dfc6SGeert Uytterhoeven }; 67639d9dfc6SGeert Uytterhoeven 67739d9dfc6SGeert Uytterhoeven hscif2: serial@e6560000 { 67839d9dfc6SGeert Uytterhoeven compatible = "renesas,hscif-r8a779g0", 67939d9dfc6SGeert Uytterhoeven "renesas,rcar-gen4-hscif", "renesas,hscif"; 68039d9dfc6SGeert Uytterhoeven reg = <0 0xe6560000 0 0x60>; 68139d9dfc6SGeert Uytterhoeven interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 68239d9dfc6SGeert Uytterhoeven clocks = <&cpg CPG_MOD 516>, 68339d9dfc6SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 68439d9dfc6SGeert Uytterhoeven <&scif_clk>; 68539d9dfc6SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 68639d9dfc6SGeert Uytterhoeven dmas = <&dmac0 0x35>, <&dmac0 0x34>, 68739d9dfc6SGeert Uytterhoeven <&dmac1 0x35>, <&dmac1 0x34>; 68839d9dfc6SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 68939d9dfc6SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 69039d9dfc6SGeert Uytterhoeven resets = <&cpg 516>; 69139d9dfc6SGeert Uytterhoeven status = "disabled"; 69239d9dfc6SGeert Uytterhoeven }; 69339d9dfc6SGeert Uytterhoeven 69439d9dfc6SGeert Uytterhoeven hscif3: serial@e66a0000 { 69539d9dfc6SGeert Uytterhoeven compatible = "renesas,hscif-r8a779g0", 69639d9dfc6SGeert Uytterhoeven "renesas,rcar-gen4-hscif", "renesas,hscif"; 69739d9dfc6SGeert Uytterhoeven reg = <0 0xe66a0000 0 0x60>; 69839d9dfc6SGeert Uytterhoeven interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 69939d9dfc6SGeert Uytterhoeven clocks = <&cpg CPG_MOD 517>, 70039d9dfc6SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 70139d9dfc6SGeert Uytterhoeven <&scif_clk>; 70239d9dfc6SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 70339d9dfc6SGeert Uytterhoeven dmas = <&dmac0 0x37>, <&dmac0 0x36>, 70439d9dfc6SGeert Uytterhoeven <&dmac1 0x37>, <&dmac1 0x36>; 70539d9dfc6SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 70639d9dfc6SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 70739d9dfc6SGeert Uytterhoeven resets = <&cpg 517>; 70839d9dfc6SGeert Uytterhoeven status = "disabled"; 70939d9dfc6SGeert Uytterhoeven }; 71039d9dfc6SGeert Uytterhoeven 7115056a0c7SGeert Uytterhoeven canfd: can@e6660000 { 7125056a0c7SGeert Uytterhoeven compatible = "renesas,r8a779g0-canfd", 7135056a0c7SGeert Uytterhoeven "renesas,rcar-gen4-canfd"; 7145056a0c7SGeert Uytterhoeven reg = <0 0xe6660000 0 0x8500>; 7155056a0c7SGeert Uytterhoeven interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 7165056a0c7SGeert Uytterhoeven <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 7175056a0c7SGeert Uytterhoeven interrupt-names = "ch_int", "g_int"; 7185056a0c7SGeert Uytterhoeven clocks = <&cpg CPG_MOD 328>, 7195056a0c7SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_CANFD>, 7205056a0c7SGeert Uytterhoeven <&can_clk>; 7215056a0c7SGeert Uytterhoeven clock-names = "fck", "canfd", "can_clk"; 7225056a0c7SGeert Uytterhoeven assigned-clocks = <&cpg CPG_CORE R8A779G0_CLK_CANFD>; 7235056a0c7SGeert Uytterhoeven assigned-clock-rates = <80000000>; 7245056a0c7SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 7255056a0c7SGeert Uytterhoeven resets = <&cpg 328>; 7265056a0c7SGeert Uytterhoeven status = "disabled"; 7275056a0c7SGeert Uytterhoeven 7285056a0c7SGeert Uytterhoeven channel0 { 7295056a0c7SGeert Uytterhoeven status = "disabled"; 7305056a0c7SGeert Uytterhoeven }; 7315056a0c7SGeert Uytterhoeven 7325056a0c7SGeert Uytterhoeven channel1 { 7335056a0c7SGeert Uytterhoeven status = "disabled"; 7345056a0c7SGeert Uytterhoeven }; 7355056a0c7SGeert Uytterhoeven 7365056a0c7SGeert Uytterhoeven channel2 { 7375056a0c7SGeert Uytterhoeven status = "disabled"; 7385056a0c7SGeert Uytterhoeven }; 7395056a0c7SGeert Uytterhoeven 7405056a0c7SGeert Uytterhoeven channel3 { 7415056a0c7SGeert Uytterhoeven status = "disabled"; 7425056a0c7SGeert Uytterhoeven }; 7435056a0c7SGeert Uytterhoeven 7445056a0c7SGeert Uytterhoeven channel4 { 7455056a0c7SGeert Uytterhoeven status = "disabled"; 7465056a0c7SGeert Uytterhoeven }; 7475056a0c7SGeert Uytterhoeven 7485056a0c7SGeert Uytterhoeven channel5 { 7495056a0c7SGeert Uytterhoeven status = "disabled"; 7505056a0c7SGeert Uytterhoeven }; 7515056a0c7SGeert Uytterhoeven 7525056a0c7SGeert Uytterhoeven channel6 { 7535056a0c7SGeert Uytterhoeven status = "disabled"; 7545056a0c7SGeert Uytterhoeven }; 7555056a0c7SGeert Uytterhoeven 7565056a0c7SGeert Uytterhoeven channel7 { 7575056a0c7SGeert Uytterhoeven status = "disabled"; 7585056a0c7SGeert Uytterhoeven }; 7595056a0c7SGeert Uytterhoeven }; 7605056a0c7SGeert Uytterhoeven 761848c82dbSGeert Uytterhoeven avb0: ethernet@e6800000 { 762848c82dbSGeert Uytterhoeven compatible = "renesas,etheravb-r8a779g0", 763848c82dbSGeert Uytterhoeven "renesas,etheravb-rcar-gen4"; 764848c82dbSGeert Uytterhoeven reg = <0 0xe6800000 0 0x800>; 765848c82dbSGeert Uytterhoeven interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 766848c82dbSGeert Uytterhoeven <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 767848c82dbSGeert Uytterhoeven <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 768848c82dbSGeert Uytterhoeven <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 769848c82dbSGeert Uytterhoeven <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 770848c82dbSGeert Uytterhoeven <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 771848c82dbSGeert Uytterhoeven <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 772848c82dbSGeert Uytterhoeven <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 773848c82dbSGeert Uytterhoeven <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 774848c82dbSGeert Uytterhoeven <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 775848c82dbSGeert Uytterhoeven <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 776848c82dbSGeert Uytterhoeven <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 777848c82dbSGeert Uytterhoeven <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 778848c82dbSGeert Uytterhoeven <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 779848c82dbSGeert Uytterhoeven <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 780848c82dbSGeert Uytterhoeven <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 781848c82dbSGeert Uytterhoeven <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 782848c82dbSGeert Uytterhoeven <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 783848c82dbSGeert Uytterhoeven <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 784848c82dbSGeert Uytterhoeven <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 785848c82dbSGeert Uytterhoeven <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 786848c82dbSGeert Uytterhoeven <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 787848c82dbSGeert Uytterhoeven <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 788848c82dbSGeert Uytterhoeven <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 789848c82dbSGeert Uytterhoeven <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 790848c82dbSGeert Uytterhoeven interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", 791848c82dbSGeert Uytterhoeven "ch5", "ch6", "ch7", "ch8", "ch9", 792848c82dbSGeert Uytterhoeven "ch10", "ch11", "ch12", "ch13", 793848c82dbSGeert Uytterhoeven "ch14", "ch15", "ch16", "ch17", 794848c82dbSGeert Uytterhoeven "ch18", "ch19", "ch20", "ch21", 795848c82dbSGeert Uytterhoeven "ch22", "ch23", "ch24"; 796848c82dbSGeert Uytterhoeven clocks = <&cpg CPG_MOD 211>; 797848c82dbSGeert Uytterhoeven clock-names = "fck"; 798848c82dbSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 799848c82dbSGeert Uytterhoeven resets = <&cpg 211>; 800848c82dbSGeert Uytterhoeven phy-mode = "rgmii"; 801848c82dbSGeert Uytterhoeven rx-internal-delay-ps = <0>; 802848c82dbSGeert Uytterhoeven tx-internal-delay-ps = <0>; 803848c82dbSGeert Uytterhoeven #address-cells = <1>; 804848c82dbSGeert Uytterhoeven #size-cells = <0>; 805848c82dbSGeert Uytterhoeven status = "disabled"; 806848c82dbSGeert Uytterhoeven }; 807848c82dbSGeert Uytterhoeven 808848c82dbSGeert Uytterhoeven avb1: ethernet@e6810000 { 809848c82dbSGeert Uytterhoeven compatible = "renesas,etheravb-r8a779g0", 810848c82dbSGeert Uytterhoeven "renesas,etheravb-rcar-gen4"; 811848c82dbSGeert Uytterhoeven reg = <0 0xe6810000 0 0x800>; 812848c82dbSGeert Uytterhoeven interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 813848c82dbSGeert Uytterhoeven <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 814848c82dbSGeert Uytterhoeven <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 815848c82dbSGeert Uytterhoeven <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 816848c82dbSGeert Uytterhoeven <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 817848c82dbSGeert Uytterhoeven <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 818848c82dbSGeert Uytterhoeven <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 819848c82dbSGeert Uytterhoeven <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 820848c82dbSGeert Uytterhoeven <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 821848c82dbSGeert Uytterhoeven <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 822848c82dbSGeert Uytterhoeven <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 823848c82dbSGeert Uytterhoeven <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 824848c82dbSGeert Uytterhoeven <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 825848c82dbSGeert Uytterhoeven <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 826848c82dbSGeert Uytterhoeven <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 827848c82dbSGeert Uytterhoeven <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 828848c82dbSGeert Uytterhoeven <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 829848c82dbSGeert Uytterhoeven <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 830848c82dbSGeert Uytterhoeven <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 831848c82dbSGeert Uytterhoeven <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 832848c82dbSGeert Uytterhoeven <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 833848c82dbSGeert Uytterhoeven <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 834848c82dbSGeert Uytterhoeven <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 835848c82dbSGeert Uytterhoeven <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 836848c82dbSGeert Uytterhoeven <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 837848c82dbSGeert Uytterhoeven interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", 838848c82dbSGeert Uytterhoeven "ch5", "ch6", "ch7", "ch8", "ch9", 839848c82dbSGeert Uytterhoeven "ch10", "ch11", "ch12", "ch13", 840848c82dbSGeert Uytterhoeven "ch14", "ch15", "ch16", "ch17", 841848c82dbSGeert Uytterhoeven "ch18", "ch19", "ch20", "ch21", 842848c82dbSGeert Uytterhoeven "ch22", "ch23", "ch24"; 843848c82dbSGeert Uytterhoeven clocks = <&cpg CPG_MOD 212>; 844848c82dbSGeert Uytterhoeven clock-names = "fck"; 845848c82dbSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 846848c82dbSGeert Uytterhoeven resets = <&cpg 212>; 847848c82dbSGeert Uytterhoeven phy-mode = "rgmii"; 848848c82dbSGeert Uytterhoeven rx-internal-delay-ps = <0>; 849848c82dbSGeert Uytterhoeven tx-internal-delay-ps = <0>; 850848c82dbSGeert Uytterhoeven #address-cells = <1>; 851848c82dbSGeert Uytterhoeven #size-cells = <0>; 852848c82dbSGeert Uytterhoeven status = "disabled"; 853848c82dbSGeert Uytterhoeven }; 854848c82dbSGeert Uytterhoeven 855848c82dbSGeert Uytterhoeven avb2: ethernet@e6820000 { 856848c82dbSGeert Uytterhoeven compatible = "renesas,etheravb-r8a779g0", 857848c82dbSGeert Uytterhoeven "renesas,etheravb-rcar-gen4"; 858848c82dbSGeert Uytterhoeven reg = <0 0xe6820000 0 0x1000>; 859848c82dbSGeert Uytterhoeven interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 860848c82dbSGeert Uytterhoeven <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 861848c82dbSGeert Uytterhoeven <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 862848c82dbSGeert Uytterhoeven <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 863848c82dbSGeert Uytterhoeven <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 864848c82dbSGeert Uytterhoeven <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 865848c82dbSGeert Uytterhoeven <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 866848c82dbSGeert Uytterhoeven <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 867848c82dbSGeert Uytterhoeven <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 868848c82dbSGeert Uytterhoeven <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 869848c82dbSGeert Uytterhoeven <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 870848c82dbSGeert Uytterhoeven <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 871848c82dbSGeert Uytterhoeven <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 872848c82dbSGeert Uytterhoeven <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 873848c82dbSGeert Uytterhoeven <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 874848c82dbSGeert Uytterhoeven <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 875848c82dbSGeert Uytterhoeven <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 876848c82dbSGeert Uytterhoeven <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 877848c82dbSGeert Uytterhoeven <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 878848c82dbSGeert Uytterhoeven <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 879848c82dbSGeert Uytterhoeven <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 880848c82dbSGeert Uytterhoeven <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 881848c82dbSGeert Uytterhoeven <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 882848c82dbSGeert Uytterhoeven <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 883848c82dbSGeert Uytterhoeven <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 884848c82dbSGeert Uytterhoeven interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", 885848c82dbSGeert Uytterhoeven "ch5", "ch6", "ch7", "ch8", "ch9", 886848c82dbSGeert Uytterhoeven "ch10", "ch11", "ch12", "ch13", 887848c82dbSGeert Uytterhoeven "ch14", "ch15", "ch16", "ch17", 888848c82dbSGeert Uytterhoeven "ch18", "ch19", "ch20", "ch21", 889848c82dbSGeert Uytterhoeven "ch22", "ch23", "ch24"; 890848c82dbSGeert Uytterhoeven clocks = <&cpg CPG_MOD 213>; 891848c82dbSGeert Uytterhoeven clock-names = "fck"; 892848c82dbSGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 893848c82dbSGeert Uytterhoeven resets = <&cpg 213>; 894848c82dbSGeert Uytterhoeven phy-mode = "rgmii"; 895848c82dbSGeert Uytterhoeven rx-internal-delay-ps = <0>; 896848c82dbSGeert Uytterhoeven tx-internal-delay-ps = <0>; 897848c82dbSGeert Uytterhoeven #address-cells = <1>; 898848c82dbSGeert Uytterhoeven #size-cells = <0>; 899848c82dbSGeert Uytterhoeven status = "disabled"; 900848c82dbSGeert Uytterhoeven }; 901848c82dbSGeert Uytterhoeven 9025b9d1306SCongDang pwm0: pwm@e6e30000 { 9035b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9045b9d1306SCongDang reg = <0 0xe6e30000 0 0x10>; 9055b9d1306SCongDang #pwm-cells = <2>; 9065b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9075b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9085b9d1306SCongDang resets = <&cpg 628>; 9095b9d1306SCongDang status = "disabled"; 9105b9d1306SCongDang }; 9115b9d1306SCongDang 9125b9d1306SCongDang pwm1: pwm@e6e31000 { 9135b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9145b9d1306SCongDang reg = <0 0xe6e31000 0 0x10>; 9155b9d1306SCongDang #pwm-cells = <2>; 9165b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9175b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9185b9d1306SCongDang resets = <&cpg 628>; 9195b9d1306SCongDang status = "disabled"; 9205b9d1306SCongDang }; 9215b9d1306SCongDang 9225b9d1306SCongDang pwm2: pwm@e6e32000 { 9235b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9245b9d1306SCongDang reg = <0 0xe6e32000 0 0x10>; 9255b9d1306SCongDang #pwm-cells = <2>; 9265b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9275b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9285b9d1306SCongDang resets = <&cpg 628>; 9295b9d1306SCongDang status = "disabled"; 9305b9d1306SCongDang }; 9315b9d1306SCongDang 9325b9d1306SCongDang pwm3: pwm@e6e33000 { 9335b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9345b9d1306SCongDang reg = <0 0xe6e33000 0 0x10>; 9355b9d1306SCongDang #pwm-cells = <2>; 9365b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9375b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9385b9d1306SCongDang resets = <&cpg 628>; 9395b9d1306SCongDang status = "disabled"; 9405b9d1306SCongDang }; 9415b9d1306SCongDang 9425b9d1306SCongDang pwm4: pwm@e6e34000 { 9435b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9445b9d1306SCongDang reg = <0 0xe6e34000 0 0x10>; 9455b9d1306SCongDang #pwm-cells = <2>; 9465b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9475b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9485b9d1306SCongDang resets = <&cpg 628>; 9495b9d1306SCongDang status = "disabled"; 9505b9d1306SCongDang }; 9515b9d1306SCongDang 9525b9d1306SCongDang pwm5: pwm@e6e35000 { 9535b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9545b9d1306SCongDang reg = <0 0xe6e35000 0 0x10>; 9555b9d1306SCongDang #pwm-cells = <2>; 9565b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9575b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9585b9d1306SCongDang resets = <&cpg 628>; 9595b9d1306SCongDang status = "disabled"; 9605b9d1306SCongDang }; 9615b9d1306SCongDang 9625b9d1306SCongDang pwm6: pwm@e6e36000 { 9635b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9645b9d1306SCongDang reg = <0 0xe6e36000 0 0x10>; 9655b9d1306SCongDang #pwm-cells = <2>; 9665b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9675b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9685b9d1306SCongDang resets = <&cpg 628>; 9695b9d1306SCongDang status = "disabled"; 9705b9d1306SCongDang }; 9715b9d1306SCongDang 9725b9d1306SCongDang pwm7: pwm@e6e37000 { 9735b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9745b9d1306SCongDang reg = <0 0xe6e37000 0 0x10>; 9755b9d1306SCongDang #pwm-cells = <2>; 9765b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9775b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9785b9d1306SCongDang resets = <&cpg 628>; 9795b9d1306SCongDang status = "disabled"; 9805b9d1306SCongDang }; 9815b9d1306SCongDang 9825b9d1306SCongDang pwm8: pwm@e6e38000 { 9835b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9845b9d1306SCongDang reg = <0 0xe6e38000 0 0x10>; 9855b9d1306SCongDang #pwm-cells = <2>; 9865b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9875b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9885b9d1306SCongDang resets = <&cpg 628>; 9895b9d1306SCongDang status = "disabled"; 9905b9d1306SCongDang }; 9915b9d1306SCongDang 9925b9d1306SCongDang pwm9: pwm@e6e39000 { 9935b9d1306SCongDang compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; 9945b9d1306SCongDang reg = <0 0xe6e39000 0 0x10>; 9955b9d1306SCongDang #pwm-cells = <2>; 9965b9d1306SCongDang clocks = <&cpg CPG_MOD 628>; 9975b9d1306SCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 9985b9d1306SCongDang resets = <&cpg 628>; 9995b9d1306SCongDang status = "disabled"; 10005b9d1306SCongDang }; 10015b9d1306SCongDang 1002a4c31c56SGeert Uytterhoeven scif0: serial@e6e60000 { 1003a4c31c56SGeert Uytterhoeven compatible = "renesas,scif-r8a779g0", 1004a4c31c56SGeert Uytterhoeven "renesas,rcar-gen4-scif", "renesas,scif"; 1005a4c31c56SGeert Uytterhoeven reg = <0 0xe6e60000 0 64>; 1006a4c31c56SGeert Uytterhoeven interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 1007a4c31c56SGeert Uytterhoeven clocks = <&cpg CPG_MOD 702>, 1008a4c31c56SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 1009a4c31c56SGeert Uytterhoeven <&scif_clk>; 1010a4c31c56SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 1011a4c31c56SGeert Uytterhoeven dmas = <&dmac0 0x51>, <&dmac0 0x50>, 1012a4c31c56SGeert Uytterhoeven <&dmac1 0x51>, <&dmac1 0x50>; 1013a4c31c56SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1014a4c31c56SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1015a4c31c56SGeert Uytterhoeven resets = <&cpg 702>; 1016a4c31c56SGeert Uytterhoeven status = "disabled"; 1017a4c31c56SGeert Uytterhoeven }; 1018a4c31c56SGeert Uytterhoeven 1019a4c31c56SGeert Uytterhoeven scif1: serial@e6e68000 { 1020a4c31c56SGeert Uytterhoeven compatible = "renesas,scif-r8a779g0", 1021a4c31c56SGeert Uytterhoeven "renesas,rcar-gen4-scif", "renesas,scif"; 1022a4c31c56SGeert Uytterhoeven reg = <0 0xe6e68000 0 64>; 1023a4c31c56SGeert Uytterhoeven interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 1024a4c31c56SGeert Uytterhoeven clocks = <&cpg CPG_MOD 703>, 1025a4c31c56SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 1026a4c31c56SGeert Uytterhoeven <&scif_clk>; 1027a4c31c56SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 1028a4c31c56SGeert Uytterhoeven dmas = <&dmac0 0x53>, <&dmac0 0x52>, 1029a4c31c56SGeert Uytterhoeven <&dmac1 0x53>, <&dmac1 0x52>; 1030a4c31c56SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1031a4c31c56SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1032a4c31c56SGeert Uytterhoeven resets = <&cpg 703>; 1033a4c31c56SGeert Uytterhoeven status = "disabled"; 1034a4c31c56SGeert Uytterhoeven }; 1035a4c31c56SGeert Uytterhoeven 1036a4c31c56SGeert Uytterhoeven scif3: serial@e6c50000 { 1037a4c31c56SGeert Uytterhoeven compatible = "renesas,scif-r8a779g0", 1038a4c31c56SGeert Uytterhoeven "renesas,rcar-gen4-scif", "renesas,scif"; 1039a4c31c56SGeert Uytterhoeven reg = <0 0xe6c50000 0 64>; 1040a4c31c56SGeert Uytterhoeven interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 1041a4c31c56SGeert Uytterhoeven clocks = <&cpg CPG_MOD 704>, 1042a4c31c56SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 1043a4c31c56SGeert Uytterhoeven <&scif_clk>; 1044a4c31c56SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 1045a4c31c56SGeert Uytterhoeven dmas = <&dmac0 0x57>, <&dmac0 0x56>, 1046a4c31c56SGeert Uytterhoeven <&dmac1 0x57>, <&dmac1 0x56>; 1047a4c31c56SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1048a4c31c56SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1049a4c31c56SGeert Uytterhoeven resets = <&cpg 704>; 1050a4c31c56SGeert Uytterhoeven status = "disabled"; 1051a4c31c56SGeert Uytterhoeven }; 1052a4c31c56SGeert Uytterhoeven 1053a4c31c56SGeert Uytterhoeven scif4: serial@e6c40000 { 1054a4c31c56SGeert Uytterhoeven compatible = "renesas,scif-r8a779g0", 1055a4c31c56SGeert Uytterhoeven "renesas,rcar-gen4-scif", "renesas,scif"; 1056a4c31c56SGeert Uytterhoeven reg = <0 0xe6c40000 0 64>; 1057a4c31c56SGeert Uytterhoeven interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1058a4c31c56SGeert Uytterhoeven clocks = <&cpg CPG_MOD 705>, 1059a4c31c56SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, 1060a4c31c56SGeert Uytterhoeven <&scif_clk>; 1061a4c31c56SGeert Uytterhoeven clock-names = "fck", "brg_int", "scif_clk"; 1062a4c31c56SGeert Uytterhoeven dmas = <&dmac0 0x59>, <&dmac0 0x58>, 1063a4c31c56SGeert Uytterhoeven <&dmac1 0x59>, <&dmac1 0x58>; 1064a4c31c56SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1065a4c31c56SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1066a4c31c56SGeert Uytterhoeven resets = <&cpg 705>; 1067a4c31c56SGeert Uytterhoeven status = "disabled"; 1068a4c31c56SGeert Uytterhoeven }; 1069a4c31c56SGeert Uytterhoeven 10704a76d4abSCongDang tpu: pwm@e6e80000 { 10714a76d4abSCongDang compatible = "renesas,tpu-r8a779g0", "renesas,tpu"; 10724a76d4abSCongDang reg = <0 0xe6e80000 0 0x148>; 10734a76d4abSCongDang interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 10744a76d4abSCongDang clocks = <&cpg CPG_MOD 718>; 10754a76d4abSCongDang power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 10764a76d4abSCongDang resets = <&cpg 718>; 10774a76d4abSCongDang #pwm-cells = <3>; 10784a76d4abSCongDang status = "disabled"; 10794a76d4abSCongDang }; 10804a76d4abSCongDang 1081e0768073SGeert Uytterhoeven msiof0: spi@e6e90000 { 1082e0768073SGeert Uytterhoeven compatible = "renesas,msiof-r8a779g0", 1083e0768073SGeert Uytterhoeven "renesas,rcar-gen4-msiof"; 1084e0768073SGeert Uytterhoeven reg = <0 0xe6e90000 0 0x0064>; 1085e0768073SGeert Uytterhoeven interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1086e0768073SGeert Uytterhoeven clocks = <&cpg CPG_MOD 618>; 1087e0768073SGeert Uytterhoeven dmas = <&dmac0 0x41>, <&dmac0 0x40>, 1088e0768073SGeert Uytterhoeven <&dmac1 0x41>, <&dmac1 0x40>; 1089e0768073SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1090e0768073SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1091e0768073SGeert Uytterhoeven resets = <&cpg 618>; 1092e0768073SGeert Uytterhoeven #address-cells = <1>; 1093e0768073SGeert Uytterhoeven #size-cells = <0>; 1094e0768073SGeert Uytterhoeven status = "disabled"; 1095e0768073SGeert Uytterhoeven }; 1096e0768073SGeert Uytterhoeven 1097e0768073SGeert Uytterhoeven msiof1: spi@e6ea0000 { 1098e0768073SGeert Uytterhoeven compatible = "renesas,msiof-r8a779g0", 1099e0768073SGeert Uytterhoeven "renesas,rcar-gen4-msiof"; 1100e0768073SGeert Uytterhoeven reg = <0 0xe6ea0000 0 0x0064>; 1101e0768073SGeert Uytterhoeven interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1102e0768073SGeert Uytterhoeven clocks = <&cpg CPG_MOD 619>; 1103e0768073SGeert Uytterhoeven dmas = <&dmac0 0x43>, <&dmac0 0x42>, 1104e0768073SGeert Uytterhoeven <&dmac1 0x43>, <&dmac1 0x42>; 1105e0768073SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1106e0768073SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1107e0768073SGeert Uytterhoeven resets = <&cpg 619>; 1108e0768073SGeert Uytterhoeven #address-cells = <1>; 1109e0768073SGeert Uytterhoeven #size-cells = <0>; 1110e0768073SGeert Uytterhoeven status = "disabled"; 1111e0768073SGeert Uytterhoeven }; 1112e0768073SGeert Uytterhoeven 1113e0768073SGeert Uytterhoeven msiof2: spi@e6c00000 { 1114e0768073SGeert Uytterhoeven compatible = "renesas,msiof-r8a779g0", 1115e0768073SGeert Uytterhoeven "renesas,rcar-gen4-msiof"; 1116e0768073SGeert Uytterhoeven reg = <0 0xe6c00000 0 0x0064>; 1117e0768073SGeert Uytterhoeven interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1118e0768073SGeert Uytterhoeven clocks = <&cpg CPG_MOD 620>; 1119e0768073SGeert Uytterhoeven dmas = <&dmac0 0x45>, <&dmac0 0x44>, 1120e0768073SGeert Uytterhoeven <&dmac1 0x45>, <&dmac1 0x44>; 1121e0768073SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1122e0768073SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1123e0768073SGeert Uytterhoeven resets = <&cpg 620>; 1124e0768073SGeert Uytterhoeven #address-cells = <1>; 1125e0768073SGeert Uytterhoeven #size-cells = <0>; 1126e0768073SGeert Uytterhoeven status = "disabled"; 1127e0768073SGeert Uytterhoeven }; 1128e0768073SGeert Uytterhoeven 1129e0768073SGeert Uytterhoeven msiof3: spi@e6c10000 { 1130e0768073SGeert Uytterhoeven compatible = "renesas,msiof-r8a779g0", 1131e0768073SGeert Uytterhoeven "renesas,rcar-gen4-msiof"; 1132e0768073SGeert Uytterhoeven reg = <0 0xe6c10000 0 0x0064>; 1133e0768073SGeert Uytterhoeven interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1134e0768073SGeert Uytterhoeven clocks = <&cpg CPG_MOD 621>; 1135e0768073SGeert Uytterhoeven dmas = <&dmac0 0x47>, <&dmac0 0x46>, 1136e0768073SGeert Uytterhoeven <&dmac1 0x47>, <&dmac1 0x46>; 1137e0768073SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1138e0768073SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1139e0768073SGeert Uytterhoeven resets = <&cpg 621>; 1140e0768073SGeert Uytterhoeven #address-cells = <1>; 1141e0768073SGeert Uytterhoeven #size-cells = <0>; 1142e0768073SGeert Uytterhoeven status = "disabled"; 1143e0768073SGeert Uytterhoeven }; 1144e0768073SGeert Uytterhoeven 1145e0768073SGeert Uytterhoeven msiof4: spi@e6c20000 { 1146e0768073SGeert Uytterhoeven compatible = "renesas,msiof-r8a779g0", 1147e0768073SGeert Uytterhoeven "renesas,rcar-gen4-msiof"; 1148e0768073SGeert Uytterhoeven reg = <0 0xe6c20000 0 0x0064>; 1149e0768073SGeert Uytterhoeven interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1150e0768073SGeert Uytterhoeven clocks = <&cpg CPG_MOD 622>; 1151e0768073SGeert Uytterhoeven dmas = <&dmac0 0x49>, <&dmac0 0x48>, 1152e0768073SGeert Uytterhoeven <&dmac1 0x49>, <&dmac1 0x48>; 1153e0768073SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1154e0768073SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1155e0768073SGeert Uytterhoeven resets = <&cpg 622>; 1156e0768073SGeert Uytterhoeven #address-cells = <1>; 1157e0768073SGeert Uytterhoeven #size-cells = <0>; 1158e0768073SGeert Uytterhoeven status = "disabled"; 1159e0768073SGeert Uytterhoeven }; 1160e0768073SGeert Uytterhoeven 1161e0768073SGeert Uytterhoeven msiof5: spi@e6c28000 { 1162e0768073SGeert Uytterhoeven compatible = "renesas,msiof-r8a779g0", 1163e0768073SGeert Uytterhoeven "renesas,rcar-gen4-msiof"; 1164e0768073SGeert Uytterhoeven reg = <0 0xe6c28000 0 0x0064>; 1165e0768073SGeert Uytterhoeven interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1166e0768073SGeert Uytterhoeven clocks = <&cpg CPG_MOD 623>; 1167e0768073SGeert Uytterhoeven dmas = <&dmac0 0x4b>, <&dmac0 0x4a>, 1168e0768073SGeert Uytterhoeven <&dmac1 0x4b>, <&dmac1 0x4a>; 1169e0768073SGeert Uytterhoeven dma-names = "tx", "rx", "tx", "rx"; 1170e0768073SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1171e0768073SGeert Uytterhoeven resets = <&cpg 623>; 1172e0768073SGeert Uytterhoeven #address-cells = <1>; 1173e0768073SGeert Uytterhoeven #size-cells = <0>; 1174e0768073SGeert Uytterhoeven status = "disabled"; 1175e0768073SGeert Uytterhoeven }; 1176e0768073SGeert Uytterhoeven 1177d435d437SNiklas Söderlund vin00: video@e6ef0000 { 1178d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1179d435d437SNiklas Söderlund reg = <0 0xe6ef0000 0 0x1000>; 1180d435d437SNiklas Söderlund interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1181d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 730>; 1182d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1183d435d437SNiklas Söderlund resets = <&cpg 730>; 1184d435d437SNiklas Söderlund renesas,id = <0>; 1185d435d437SNiklas Söderlund status = "disabled"; 1186d435d437SNiklas Söderlund 1187d435d437SNiklas Söderlund ports { 1188d435d437SNiklas Söderlund #address-cells = <1>; 1189d435d437SNiklas Söderlund #size-cells = <0>; 1190d435d437SNiklas Söderlund 1191d435d437SNiklas Söderlund port@2 { 1192d435d437SNiklas Söderlund #address-cells = <1>; 1193d435d437SNiklas Söderlund #size-cells = <0>; 1194d435d437SNiklas Söderlund 1195d435d437SNiklas Söderlund reg = <2>; 1196d435d437SNiklas Söderlund 1197d435d437SNiklas Söderlund vin00isp0: endpoint@0 { 1198d435d437SNiklas Söderlund reg = <0>; 1199d435d437SNiklas Söderlund remote-endpoint = <&isp0vin00>; 1200d435d437SNiklas Söderlund }; 1201d435d437SNiklas Söderlund }; 1202d435d437SNiklas Söderlund }; 1203d435d437SNiklas Söderlund }; 1204d435d437SNiklas Söderlund 1205d435d437SNiklas Söderlund vin01: video@e6ef1000 { 1206d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1207d435d437SNiklas Söderlund reg = <0 0xe6ef1000 0 0x1000>; 1208d435d437SNiklas Söderlund interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1209d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 731>; 1210d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1211d435d437SNiklas Söderlund resets = <&cpg 731>; 1212d435d437SNiklas Söderlund renesas,id = <1>; 1213d435d437SNiklas Söderlund status = "disabled"; 1214d435d437SNiklas Söderlund 1215d435d437SNiklas Söderlund ports { 1216d435d437SNiklas Söderlund #address-cells = <1>; 1217d435d437SNiklas Söderlund #size-cells = <0>; 1218d435d437SNiklas Söderlund 1219d435d437SNiklas Söderlund port@2 { 1220d435d437SNiklas Söderlund #address-cells = <1>; 1221d435d437SNiklas Söderlund #size-cells = <0>; 1222d435d437SNiklas Söderlund 1223d435d437SNiklas Söderlund reg = <2>; 1224d435d437SNiklas Söderlund 1225d435d437SNiklas Söderlund vin01isp0: endpoint@0 { 1226d435d437SNiklas Söderlund reg = <0>; 1227d435d437SNiklas Söderlund remote-endpoint = <&isp0vin01>; 1228d435d437SNiklas Söderlund }; 1229d435d437SNiklas Söderlund }; 1230d435d437SNiklas Söderlund }; 1231d435d437SNiklas Söderlund }; 1232d435d437SNiklas Söderlund 1233d435d437SNiklas Söderlund vin02: video@e6ef2000 { 1234d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1235d435d437SNiklas Söderlund reg = <0 0xe6ef2000 0 0x1000>; 1236d435d437SNiklas Söderlund interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1237d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 800>; 1238d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1239d435d437SNiklas Söderlund resets = <&cpg 800>; 1240d435d437SNiklas Söderlund renesas,id = <2>; 1241d435d437SNiklas Söderlund status = "disabled"; 1242d435d437SNiklas Söderlund 1243d435d437SNiklas Söderlund ports { 1244d435d437SNiklas Söderlund #address-cells = <1>; 1245d435d437SNiklas Söderlund #size-cells = <0>; 1246d435d437SNiklas Söderlund 1247d435d437SNiklas Söderlund port@2 { 1248d435d437SNiklas Söderlund #address-cells = <1>; 1249d435d437SNiklas Söderlund #size-cells = <0>; 1250d435d437SNiklas Söderlund 1251d435d437SNiklas Söderlund reg = <2>; 1252d435d437SNiklas Söderlund 1253d435d437SNiklas Söderlund vin02isp0: endpoint@0 { 1254d435d437SNiklas Söderlund reg = <0>; 1255d435d437SNiklas Söderlund remote-endpoint = <&isp0vin02>; 1256d435d437SNiklas Söderlund }; 1257d435d437SNiklas Söderlund }; 1258d435d437SNiklas Söderlund }; 1259d435d437SNiklas Söderlund }; 1260d435d437SNiklas Söderlund 1261d435d437SNiklas Söderlund vin03: video@e6ef3000 { 1262d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1263d435d437SNiklas Söderlund reg = <0 0xe6ef3000 0 0x1000>; 1264d435d437SNiklas Söderlund interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>; 1265d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 801>; 1266d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1267d435d437SNiklas Söderlund resets = <&cpg 801>; 1268d435d437SNiklas Söderlund renesas,id = <3>; 1269d435d437SNiklas Söderlund status = "disabled"; 1270d435d437SNiklas Söderlund 1271d435d437SNiklas Söderlund ports { 1272d435d437SNiklas Söderlund #address-cells = <1>; 1273d435d437SNiklas Söderlund #size-cells = <0>; 1274d435d437SNiklas Söderlund 1275d435d437SNiklas Söderlund port@2 { 1276d435d437SNiklas Söderlund #address-cells = <1>; 1277d435d437SNiklas Söderlund #size-cells = <0>; 1278d435d437SNiklas Söderlund 1279d435d437SNiklas Söderlund reg = <2>; 1280d435d437SNiklas Söderlund 1281d435d437SNiklas Söderlund vin03isp0: endpoint@0 { 1282d435d437SNiklas Söderlund reg = <0>; 1283d435d437SNiklas Söderlund remote-endpoint = <&isp0vin03>; 1284d435d437SNiklas Söderlund }; 1285d435d437SNiklas Söderlund }; 1286d435d437SNiklas Söderlund }; 1287d435d437SNiklas Söderlund }; 1288d435d437SNiklas Söderlund 1289d435d437SNiklas Söderlund vin04: video@e6ef4000 { 1290d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1291d435d437SNiklas Söderlund reg = <0 0xe6ef4000 0 0x1000>; 1292d435d437SNiklas Söderlund interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 1293d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 802>; 1294d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1295d435d437SNiklas Söderlund resets = <&cpg 802>; 1296d435d437SNiklas Söderlund renesas,id = <4>; 1297d435d437SNiklas Söderlund status = "disabled"; 1298d435d437SNiklas Söderlund 1299d435d437SNiklas Söderlund ports { 1300d435d437SNiklas Söderlund #address-cells = <1>; 1301d435d437SNiklas Söderlund #size-cells = <0>; 1302d435d437SNiklas Söderlund 1303d435d437SNiklas Söderlund port@2 { 1304d435d437SNiklas Söderlund #address-cells = <1>; 1305d435d437SNiklas Söderlund #size-cells = <0>; 1306d435d437SNiklas Söderlund 1307d435d437SNiklas Söderlund reg = <2>; 1308d435d437SNiklas Söderlund 1309d435d437SNiklas Söderlund vin04isp0: endpoint@0 { 1310d435d437SNiklas Söderlund reg = <0>; 1311d435d437SNiklas Söderlund remote-endpoint = <&isp0vin04>; 1312d435d437SNiklas Söderlund }; 1313d435d437SNiklas Söderlund }; 1314d435d437SNiklas Söderlund }; 1315d435d437SNiklas Söderlund }; 1316d435d437SNiklas Söderlund 1317d435d437SNiklas Söderlund vin05: video@e6ef5000 { 1318d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1319d435d437SNiklas Söderlund reg = <0 0xe6ef5000 0 0x1000>; 1320d435d437SNiklas Söderlund interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>; 1321d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 803>; 1322d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1323d435d437SNiklas Söderlund resets = <&cpg 803>; 1324d435d437SNiklas Söderlund renesas,id = <5>; 1325d435d437SNiklas Söderlund status = "disabled"; 1326d435d437SNiklas Söderlund 1327d435d437SNiklas Söderlund ports { 1328d435d437SNiklas Söderlund #address-cells = <1>; 1329d435d437SNiklas Söderlund #size-cells = <0>; 1330d435d437SNiklas Söderlund 1331d435d437SNiklas Söderlund port@2 { 1332d435d437SNiklas Söderlund #address-cells = <1>; 1333d435d437SNiklas Söderlund #size-cells = <0>; 1334d435d437SNiklas Söderlund 1335d435d437SNiklas Söderlund reg = <2>; 1336d435d437SNiklas Söderlund 1337d435d437SNiklas Söderlund vin05isp0: endpoint@0 { 1338d435d437SNiklas Söderlund reg = <0>; 1339d435d437SNiklas Söderlund remote-endpoint = <&isp0vin05>; 1340d435d437SNiklas Söderlund }; 1341d435d437SNiklas Söderlund }; 1342d435d437SNiklas Söderlund }; 1343d435d437SNiklas Söderlund }; 1344d435d437SNiklas Söderlund 1345d435d437SNiklas Söderlund vin06: video@e6ef6000 { 1346d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1347d435d437SNiklas Söderlund reg = <0 0xe6ef6000 0 0x1000>; 1348d435d437SNiklas Söderlund interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1349d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 804>; 1350d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1351d435d437SNiklas Söderlund resets = <&cpg 804>; 1352d435d437SNiklas Söderlund renesas,id = <6>; 1353d435d437SNiklas Söderlund status = "disabled"; 1354d435d437SNiklas Söderlund 1355d435d437SNiklas Söderlund ports { 1356d435d437SNiklas Söderlund #address-cells = <1>; 1357d435d437SNiklas Söderlund #size-cells = <0>; 1358d435d437SNiklas Söderlund 1359d435d437SNiklas Söderlund port@2 { 1360d435d437SNiklas Söderlund #address-cells = <1>; 1361d435d437SNiklas Söderlund #size-cells = <0>; 1362d435d437SNiklas Söderlund 1363d435d437SNiklas Söderlund reg = <2>; 1364d435d437SNiklas Söderlund 1365d435d437SNiklas Söderlund vin06isp0: endpoint@0 { 1366d435d437SNiklas Söderlund reg = <0>; 1367d435d437SNiklas Söderlund remote-endpoint = <&isp0vin06>; 1368d435d437SNiklas Söderlund }; 1369d435d437SNiklas Söderlund }; 1370d435d437SNiklas Söderlund }; 1371d435d437SNiklas Söderlund }; 1372d435d437SNiklas Söderlund 1373d435d437SNiklas Söderlund vin07: video@e6ef7000 { 1374d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1375d435d437SNiklas Söderlund reg = <0 0xe6ef7000 0 0x1000>; 1376d435d437SNiklas Söderlund interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1377d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 805>; 1378d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1379d435d437SNiklas Söderlund resets = <&cpg 805>; 1380d435d437SNiklas Söderlund renesas,id = <7>; 1381d435d437SNiklas Söderlund status = "disabled"; 1382d435d437SNiklas Söderlund 1383d435d437SNiklas Söderlund ports { 1384d435d437SNiklas Söderlund #address-cells = <1>; 1385d435d437SNiklas Söderlund #size-cells = <0>; 1386d435d437SNiklas Söderlund 1387d435d437SNiklas Söderlund port@2 { 1388d435d437SNiklas Söderlund #address-cells = <1>; 1389d435d437SNiklas Söderlund #size-cells = <0>; 1390d435d437SNiklas Söderlund 1391d435d437SNiklas Söderlund reg = <2>; 1392d435d437SNiklas Söderlund 1393d435d437SNiklas Söderlund vin07isp0: endpoint@0 { 1394d435d437SNiklas Söderlund reg = <0>; 1395d435d437SNiklas Söderlund remote-endpoint = <&isp0vin07>; 1396d435d437SNiklas Söderlund }; 1397d435d437SNiklas Söderlund }; 1398d435d437SNiklas Söderlund }; 1399d435d437SNiklas Söderlund }; 1400d435d437SNiklas Söderlund 1401d435d437SNiklas Söderlund vin08: video@e6ef8000 { 1402d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1403d435d437SNiklas Söderlund reg = <0 0xe6ef8000 0 0x1000>; 1404d435d437SNiklas Söderlund interrupts = <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>; 1405d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 806>; 1406d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1407d435d437SNiklas Söderlund resets = <&cpg 806>; 1408d435d437SNiklas Söderlund renesas,id = <8>; 1409d435d437SNiklas Söderlund status = "disabled"; 1410d435d437SNiklas Söderlund 1411d435d437SNiklas Söderlund ports { 1412d435d437SNiklas Söderlund #address-cells = <1>; 1413d435d437SNiklas Söderlund #size-cells = <0>; 1414d435d437SNiklas Söderlund 1415d435d437SNiklas Söderlund port@2 { 1416d435d437SNiklas Söderlund #address-cells = <1>; 1417d435d437SNiklas Söderlund #size-cells = <0>; 1418d435d437SNiklas Söderlund 1419d435d437SNiklas Söderlund reg = <2>; 1420d435d437SNiklas Söderlund 1421d435d437SNiklas Söderlund vin08isp1: endpoint@1 { 1422d435d437SNiklas Söderlund reg = <1>; 1423d435d437SNiklas Söderlund remote-endpoint = <&isp1vin08>; 1424d435d437SNiklas Söderlund }; 1425d435d437SNiklas Söderlund }; 1426d435d437SNiklas Söderlund }; 1427d435d437SNiklas Söderlund }; 1428d435d437SNiklas Söderlund 1429d435d437SNiklas Söderlund vin09: video@e6ef9000 { 1430d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1431d435d437SNiklas Söderlund reg = <0 0xe6ef9000 0 0x1000>; 1432d435d437SNiklas Söderlund interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>; 1433d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 807>; 1434d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1435d435d437SNiklas Söderlund resets = <&cpg 807>; 1436d435d437SNiklas Söderlund renesas,id = <9>; 1437d435d437SNiklas Söderlund status = "disabled"; 1438d435d437SNiklas Söderlund 1439d435d437SNiklas Söderlund ports { 1440d435d437SNiklas Söderlund #address-cells = <1>; 1441d435d437SNiklas Söderlund #size-cells = <0>; 1442d435d437SNiklas Söderlund 1443d435d437SNiklas Söderlund port@2 { 1444d435d437SNiklas Söderlund #address-cells = <1>; 1445d435d437SNiklas Söderlund #size-cells = <0>; 1446d435d437SNiklas Söderlund 1447d435d437SNiklas Söderlund reg = <2>; 1448d435d437SNiklas Söderlund 1449d435d437SNiklas Söderlund vin09isp1: endpoint@1 { 1450d435d437SNiklas Söderlund reg = <1>; 1451d435d437SNiklas Söderlund remote-endpoint = <&isp1vin09>; 1452d435d437SNiklas Söderlund }; 1453d435d437SNiklas Söderlund }; 1454d435d437SNiklas Söderlund }; 1455d435d437SNiklas Söderlund }; 1456d435d437SNiklas Söderlund 1457d435d437SNiklas Söderlund vin10: video@e6efa000 { 1458d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1459d435d437SNiklas Söderlund reg = <0 0xe6efa000 0 0x1000>; 1460d435d437SNiklas Söderlund interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>; 1461d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 808>; 1462d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1463d435d437SNiklas Söderlund resets = <&cpg 808>; 1464d435d437SNiklas Söderlund renesas,id = <10>; 1465d435d437SNiklas Söderlund status = "disabled"; 1466d435d437SNiklas Söderlund 1467d435d437SNiklas Söderlund ports { 1468d435d437SNiklas Söderlund #address-cells = <1>; 1469d435d437SNiklas Söderlund #size-cells = <0>; 1470d435d437SNiklas Söderlund 1471d435d437SNiklas Söderlund port@2 { 1472d435d437SNiklas Söderlund #address-cells = <1>; 1473d435d437SNiklas Söderlund #size-cells = <0>; 1474d435d437SNiklas Söderlund 1475d435d437SNiklas Söderlund reg = <2>; 1476d435d437SNiklas Söderlund 1477d435d437SNiklas Söderlund vin10isp1: endpoint@1 { 1478d435d437SNiklas Söderlund reg = <1>; 1479d435d437SNiklas Söderlund remote-endpoint = <&isp1vin10>; 1480d435d437SNiklas Söderlund }; 1481d435d437SNiklas Söderlund }; 1482d435d437SNiklas Söderlund }; 1483d435d437SNiklas Söderlund }; 1484d435d437SNiklas Söderlund 1485d435d437SNiklas Söderlund vin11: video@e6efb000 { 1486d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1487d435d437SNiklas Söderlund reg = <0 0xe6efb000 0 0x1000>; 1488d435d437SNiklas Söderlund interrupts = <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>; 1489d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 809>; 1490d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1491d435d437SNiklas Söderlund resets = <&cpg 809>; 1492d435d437SNiklas Söderlund renesas,id = <11>; 1493d435d437SNiklas Söderlund status = "disabled"; 1494d435d437SNiklas Söderlund 1495d435d437SNiklas Söderlund ports { 1496d435d437SNiklas Söderlund #address-cells = <1>; 1497d435d437SNiklas Söderlund #size-cells = <0>; 1498d435d437SNiklas Söderlund 1499d435d437SNiklas Söderlund port@2 { 1500d435d437SNiklas Söderlund #address-cells = <1>; 1501d435d437SNiklas Söderlund #size-cells = <0>; 1502d435d437SNiklas Söderlund 1503d435d437SNiklas Söderlund reg = <2>; 1504d435d437SNiklas Söderlund 1505d435d437SNiklas Söderlund vin11isp1: endpoint@1 { 1506d435d437SNiklas Söderlund reg = <1>; 1507d435d437SNiklas Söderlund remote-endpoint = <&isp1vin11>; 1508d435d437SNiklas Söderlund }; 1509d435d437SNiklas Söderlund }; 1510d435d437SNiklas Söderlund }; 1511d435d437SNiklas Söderlund }; 1512d435d437SNiklas Söderlund 1513d435d437SNiklas Söderlund vin12: video@e6efc000 { 1514d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1515d435d437SNiklas Söderlund reg = <0 0xe6efc000 0 0x1000>; 1516d435d437SNiklas Söderlund interrupts = <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>; 1517d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 810>; 1518d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1519d435d437SNiklas Söderlund resets = <&cpg 810>; 1520d435d437SNiklas Söderlund renesas,id = <12>; 1521d435d437SNiklas Söderlund status = "disabled"; 1522d435d437SNiklas Söderlund 1523d435d437SNiklas Söderlund ports { 1524d435d437SNiklas Söderlund #address-cells = <1>; 1525d435d437SNiklas Söderlund #size-cells = <0>; 1526d435d437SNiklas Söderlund 1527d435d437SNiklas Söderlund port@2 { 1528d435d437SNiklas Söderlund #address-cells = <1>; 1529d435d437SNiklas Söderlund #size-cells = <0>; 1530d435d437SNiklas Söderlund 1531d435d437SNiklas Söderlund reg = <2>; 1532d435d437SNiklas Söderlund 1533d435d437SNiklas Söderlund vin12isp1: endpoint@1 { 1534d435d437SNiklas Söderlund reg = <1>; 1535d435d437SNiklas Söderlund remote-endpoint = <&isp1vin12>; 1536d435d437SNiklas Söderlund }; 1537d435d437SNiklas Söderlund }; 1538d435d437SNiklas Söderlund }; 1539d435d437SNiklas Söderlund }; 1540d435d437SNiklas Söderlund 1541d435d437SNiklas Söderlund vin13: video@e6efd000 { 1542d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1543d435d437SNiklas Söderlund reg = <0 0xe6efd000 0 0x1000>; 1544d435d437SNiklas Söderlund interrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>; 1545d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 811>; 1546d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1547d435d437SNiklas Söderlund resets = <&cpg 811>; 1548d435d437SNiklas Söderlund renesas,id = <13>; 1549d435d437SNiklas Söderlund status = "disabled"; 1550d435d437SNiklas Söderlund 1551d435d437SNiklas Söderlund ports { 1552d435d437SNiklas Söderlund #address-cells = <1>; 1553d435d437SNiklas Söderlund #size-cells = <0>; 1554d435d437SNiklas Söderlund 1555d435d437SNiklas Söderlund port@2 { 1556d435d437SNiklas Söderlund #address-cells = <1>; 1557d435d437SNiklas Söderlund #size-cells = <0>; 1558d435d437SNiklas Söderlund 1559d435d437SNiklas Söderlund reg = <2>; 1560d435d437SNiklas Söderlund 1561d435d437SNiklas Söderlund vin13isp1: endpoint@1 { 1562d435d437SNiklas Söderlund reg = <1>; 1563d435d437SNiklas Söderlund remote-endpoint = <&isp1vin13>; 1564d435d437SNiklas Söderlund }; 1565d435d437SNiklas Söderlund }; 1566d435d437SNiklas Söderlund }; 1567d435d437SNiklas Söderlund }; 1568d435d437SNiklas Söderlund 1569d435d437SNiklas Söderlund vin14: video@e6efe000 { 1570d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1571d435d437SNiklas Söderlund reg = <0 0xe6efe000 0 0x1000>; 1572d435d437SNiklas Söderlund interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>; 1573d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 812>; 1574d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1575d435d437SNiklas Söderlund resets = <&cpg 812>; 1576d435d437SNiklas Söderlund renesas,id = <14>; 1577d435d437SNiklas Söderlund status = "disabled"; 1578d435d437SNiklas Söderlund 1579d435d437SNiklas Söderlund ports { 1580d435d437SNiklas Söderlund #address-cells = <1>; 1581d435d437SNiklas Söderlund #size-cells = <0>; 1582d435d437SNiklas Söderlund 1583d435d437SNiklas Söderlund port@2 { 1584d435d437SNiklas Söderlund #address-cells = <1>; 1585d435d437SNiklas Söderlund #size-cells = <0>; 1586d435d437SNiklas Söderlund 1587d435d437SNiklas Söderlund reg = <2>; 1588d435d437SNiklas Söderlund 1589d435d437SNiklas Söderlund vin14isp1: endpoint@1 { 1590d435d437SNiklas Söderlund reg = <1>; 1591d435d437SNiklas Söderlund remote-endpoint = <&isp1vin14>; 1592d435d437SNiklas Söderlund }; 1593d435d437SNiklas Söderlund }; 1594d435d437SNiklas Söderlund }; 1595d435d437SNiklas Söderlund }; 1596d435d437SNiklas Söderlund 1597d435d437SNiklas Söderlund vin15: video@e6eff000 { 1598d435d437SNiklas Söderlund compatible = "renesas,vin-r8a779g0"; 1599d435d437SNiklas Söderlund reg = <0 0xe6eff000 0 0x1000>; 1600d435d437SNiklas Söderlund interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1601d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 813>; 1602d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1603d435d437SNiklas Söderlund resets = <&cpg 813>; 1604d435d437SNiklas Söderlund renesas,id = <15>; 1605d435d437SNiklas Söderlund status = "disabled"; 1606d435d437SNiklas Söderlund 1607d435d437SNiklas Söderlund ports { 1608d435d437SNiklas Söderlund #address-cells = <1>; 1609d435d437SNiklas Söderlund #size-cells = <0>; 1610d435d437SNiklas Söderlund 1611d435d437SNiklas Söderlund port@2 { 1612d435d437SNiklas Söderlund #address-cells = <1>; 1613d435d437SNiklas Söderlund #size-cells = <0>; 1614d435d437SNiklas Söderlund 1615d435d437SNiklas Söderlund reg = <2>; 1616d435d437SNiklas Söderlund 1617d435d437SNiklas Söderlund vin15isp1: endpoint@1 { 1618d435d437SNiklas Söderlund reg = <1>; 1619d435d437SNiklas Söderlund remote-endpoint = <&isp1vin15>; 1620d435d437SNiklas Söderlund }; 1621d435d437SNiklas Söderlund }; 1622d435d437SNiklas Söderlund }; 1623d435d437SNiklas Söderlund }; 1624d435d437SNiklas Söderlund 162508f28288SGeert Uytterhoeven dmac0: dma-controller@e7350000 { 162608f28288SGeert Uytterhoeven compatible = "renesas,dmac-r8a779g0", 162708f28288SGeert Uytterhoeven "renesas,rcar-gen4-dmac"; 162808f28288SGeert Uytterhoeven reg = <0 0xe7350000 0 0x1000>, 162908f28288SGeert Uytterhoeven <0 0xe7300000 0 0x10000>; 163008f28288SGeert Uytterhoeven interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 163108f28288SGeert Uytterhoeven <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 163208f28288SGeert Uytterhoeven <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 163308f28288SGeert Uytterhoeven <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 163408f28288SGeert Uytterhoeven <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 163508f28288SGeert Uytterhoeven <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 163608f28288SGeert Uytterhoeven <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 163708f28288SGeert Uytterhoeven <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 163808f28288SGeert Uytterhoeven <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 163908f28288SGeert Uytterhoeven <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 164008f28288SGeert Uytterhoeven <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 164108f28288SGeert Uytterhoeven <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 164208f28288SGeert Uytterhoeven <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 164308f28288SGeert Uytterhoeven <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 164408f28288SGeert Uytterhoeven <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 164508f28288SGeert Uytterhoeven <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 164608f28288SGeert Uytterhoeven <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 164708f28288SGeert Uytterhoeven interrupt-names = "error", 164808f28288SGeert Uytterhoeven "ch0", "ch1", "ch2", "ch3", "ch4", 164908f28288SGeert Uytterhoeven "ch5", "ch6", "ch7", "ch8", "ch9", 165008f28288SGeert Uytterhoeven "ch10", "ch11", "ch12", "ch13", 165108f28288SGeert Uytterhoeven "ch14", "ch15"; 165208f28288SGeert Uytterhoeven clocks = <&cpg CPG_MOD 709>; 165308f28288SGeert Uytterhoeven clock-names = "fck"; 165408f28288SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 165508f28288SGeert Uytterhoeven resets = <&cpg 709>; 165608f28288SGeert Uytterhoeven #dma-cells = <1>; 165708f28288SGeert Uytterhoeven dma-channels = <16>; 1658*00a9526bSYoshihiro Shimoda iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 1659*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 1660*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 1661*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 1662*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 1663*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 1664*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 1665*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 166608f28288SGeert Uytterhoeven }; 166708f28288SGeert Uytterhoeven 166808f28288SGeert Uytterhoeven dmac1: dma-controller@e7351000 { 166908f28288SGeert Uytterhoeven compatible = "renesas,dmac-r8a779g0", 167008f28288SGeert Uytterhoeven "renesas,rcar-gen4-dmac"; 167108f28288SGeert Uytterhoeven reg = <0 0xe7351000 0 0x1000>, 167208f28288SGeert Uytterhoeven <0 0xe7310000 0 0x10000>; 167308f28288SGeert Uytterhoeven interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 167408f28288SGeert Uytterhoeven <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 167508f28288SGeert Uytterhoeven <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 167608f28288SGeert Uytterhoeven <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 167708f28288SGeert Uytterhoeven <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 167808f28288SGeert Uytterhoeven <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 167908f28288SGeert Uytterhoeven <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 168008f28288SGeert Uytterhoeven <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 168108f28288SGeert Uytterhoeven <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 168208f28288SGeert Uytterhoeven <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 168308f28288SGeert Uytterhoeven <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 168408f28288SGeert Uytterhoeven <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 168508f28288SGeert Uytterhoeven <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 168608f28288SGeert Uytterhoeven <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 168708f28288SGeert Uytterhoeven <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 168808f28288SGeert Uytterhoeven <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 168908f28288SGeert Uytterhoeven <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 169008f28288SGeert Uytterhoeven interrupt-names = "error", 169108f28288SGeert Uytterhoeven "ch0", "ch1", "ch2", "ch3", "ch4", 169208f28288SGeert Uytterhoeven "ch5", "ch6", "ch7", "ch8", "ch9", 169308f28288SGeert Uytterhoeven "ch10", "ch11", "ch12", "ch13", 169408f28288SGeert Uytterhoeven "ch14", "ch15"; 169508f28288SGeert Uytterhoeven clocks = <&cpg CPG_MOD 710>; 169608f28288SGeert Uytterhoeven clock-names = "fck"; 169708f28288SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 169808f28288SGeert Uytterhoeven resets = <&cpg 710>; 169908f28288SGeert Uytterhoeven #dma-cells = <1>; 170008f28288SGeert Uytterhoeven dma-channels = <16>; 1701*00a9526bSYoshihiro Shimoda iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, 1702*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, 1703*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, 1704*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, 1705*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, 1706*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, 1707*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, 1708*00a9526bSYoshihiro Shimoda <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; 170908f28288SGeert Uytterhoeven }; 171008f28288SGeert Uytterhoeven 17116cf8e3d7SKuninori Morimoto rcar_sound: sound@ec5a0000 { 17126cf8e3d7SKuninori Morimoto /* 17136cf8e3d7SKuninori Morimoto * #sound-dai-cells is required 17146cf8e3d7SKuninori Morimoto * 17156cf8e3d7SKuninori Morimoto * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 17166cf8e3d7SKuninori Morimoto * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 17176cf8e3d7SKuninori Morimoto */ 17186cf8e3d7SKuninori Morimoto /* 17196cf8e3d7SKuninori Morimoto * #clock-cells is required 17206cf8e3d7SKuninori Morimoto * 17216cf8e3d7SKuninori Morimoto * clkout : #clock-cells = <0>; <&rcar_sound>; 17226cf8e3d7SKuninori Morimoto * audio_clkout0/1/2/3 : #clock-cells = <1>; <&rcar_sound N>; 17236cf8e3d7SKuninori Morimoto */ 17246cf8e3d7SKuninori Morimoto compatible = "renesas,rcar_sound-r8a779g0", "renesas,rcar_sound-gen4"; 17256cf8e3d7SKuninori Morimoto reg = <0 0xec5a0000 0 0x020>, 17266cf8e3d7SKuninori Morimoto <0 0xec540000 0 0x1000>, 17276cf8e3d7SKuninori Morimoto <0 0xec541000 0 0x050>, 17286cf8e3d7SKuninori Morimoto <0 0xec400000 0 0x40000>; 17296cf8e3d7SKuninori Morimoto reg-names = "adg", "ssiu", "ssi", "sdmc"; 17306cf8e3d7SKuninori Morimoto 17316cf8e3d7SKuninori Morimoto clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>; 17326cf8e3d7SKuninori Morimoto clock-names = "ssiu.0", "ssi.0", "clkin"; 17336cf8e3d7SKuninori Morimoto power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 17346cf8e3d7SKuninori Morimoto resets = <&cpg 2926>, <&cpg 2927>; 17356cf8e3d7SKuninori Morimoto reset-names = "ssiu.0", "ssi.0"; 17366cf8e3d7SKuninori Morimoto status = "disabled"; 17376cf8e3d7SKuninori Morimoto 17386cf8e3d7SKuninori Morimoto rcar_sound,ssiu { 17396cf8e3d7SKuninori Morimoto ssiu00: ssiu-0 { 17406cf8e3d7SKuninori Morimoto dmas = <&dmac0 0x6e>, <&dmac0 0x6f>; 17416cf8e3d7SKuninori Morimoto dma-names = "tx", "rx"; 17426cf8e3d7SKuninori Morimoto }; 17436cf8e3d7SKuninori Morimoto ssiu01: ssiu-1 { 17446cf8e3d7SKuninori Morimoto dmas = <&dmac0 0x6c>, <&dmac0 0x6d>; 17456cf8e3d7SKuninori Morimoto dma-names = "tx", "rx"; 17466cf8e3d7SKuninori Morimoto }; 17476cf8e3d7SKuninori Morimoto ssiu02: ssiu-2 { 17486cf8e3d7SKuninori Morimoto dmas = <&dmac0 0x6a>, <&dmac0 0x6b>; 17496cf8e3d7SKuninori Morimoto dma-names = "tx", "rx"; 17506cf8e3d7SKuninori Morimoto }; 17516cf8e3d7SKuninori Morimoto ssiu03: ssiu-3 { 17526cf8e3d7SKuninori Morimoto dmas = <&dmac0 0x68>, <&dmac0 0x69>; 17536cf8e3d7SKuninori Morimoto dma-names = "tx", "rx"; 17546cf8e3d7SKuninori Morimoto }; 17556cf8e3d7SKuninori Morimoto ssiu04: ssiu-4 { 17566cf8e3d7SKuninori Morimoto dmas = <&dmac0 0x66>, <&dmac0 0x67>; 17576cf8e3d7SKuninori Morimoto dma-names = "tx", "rx"; 17586cf8e3d7SKuninori Morimoto }; 17596cf8e3d7SKuninori Morimoto ssiu05: ssiu-5 { 17606cf8e3d7SKuninori Morimoto dmas = <&dmac0 0x64>, <&dmac0 0x65>; 17616cf8e3d7SKuninori Morimoto dma-names = "tx", "rx"; 17626cf8e3d7SKuninori Morimoto }; 17636cf8e3d7SKuninori Morimoto ssiu06: ssiu-6 { 17646cf8e3d7SKuninori Morimoto dmas = <&dmac0 0x62>, <&dmac0 0x63>; 17656cf8e3d7SKuninori Morimoto dma-names = "tx", "rx"; 17666cf8e3d7SKuninori Morimoto }; 17676cf8e3d7SKuninori Morimoto ssiu07: ssiu-7 { 17686cf8e3d7SKuninori Morimoto dmas = <&dmac0 0x60>, <&dmac0 0x61>; 17696cf8e3d7SKuninori Morimoto dma-names = "tx", "rx"; 17706cf8e3d7SKuninori Morimoto }; 17716cf8e3d7SKuninori Morimoto }; 17726cf8e3d7SKuninori Morimoto 17736cf8e3d7SKuninori Morimoto rcar_sound,ssi { 17746cf8e3d7SKuninori Morimoto ssi0: ssi-0 { 17756cf8e3d7SKuninori Morimoto interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 17766cf8e3d7SKuninori Morimoto }; 17776cf8e3d7SKuninori Morimoto }; 17786cf8e3d7SKuninori Morimoto }; 17796cf8e3d7SKuninori Morimoto 1780432d5fedSYoshihiro Shimoda ipmmu_rt0: iommu@ee480000 { 1781432d5fedSYoshihiro Shimoda compatible = "renesas,ipmmu-r8a779g0", 1782432d5fedSYoshihiro Shimoda "renesas,rcar-gen4-ipmmu-vmsa"; 1783432d5fedSYoshihiro Shimoda reg = <0 0xee480000 0 0x20000>; 1784432d5fedSYoshihiro Shimoda renesas,ipmmu-main = <&ipmmu_mm>; 1785432d5fedSYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1786432d5fedSYoshihiro Shimoda #iommu-cells = <1>; 1787432d5fedSYoshihiro Shimoda }; 1788432d5fedSYoshihiro Shimoda 1789432d5fedSYoshihiro Shimoda ipmmu_rt1: iommu@ee4c0000 { 1790432d5fedSYoshihiro Shimoda compatible = "renesas,ipmmu-r8a779g0", 1791432d5fedSYoshihiro Shimoda "renesas,rcar-gen4-ipmmu-vmsa"; 1792432d5fedSYoshihiro Shimoda reg = <0 0xee4c0000 0 0x20000>; 1793432d5fedSYoshihiro Shimoda renesas,ipmmu-main = <&ipmmu_mm>; 1794432d5fedSYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1795432d5fedSYoshihiro Shimoda #iommu-cells = <1>; 1796432d5fedSYoshihiro Shimoda }; 1797432d5fedSYoshihiro Shimoda 1798432d5fedSYoshihiro Shimoda ipmmu_ds0: iommu@eed00000 { 1799432d5fedSYoshihiro Shimoda compatible = "renesas,ipmmu-r8a779g0", 1800432d5fedSYoshihiro Shimoda "renesas,rcar-gen4-ipmmu-vmsa"; 1801432d5fedSYoshihiro Shimoda reg = <0 0xeed00000 0 0x20000>; 1802432d5fedSYoshihiro Shimoda renesas,ipmmu-main = <&ipmmu_mm>; 1803432d5fedSYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1804432d5fedSYoshihiro Shimoda #iommu-cells = <1>; 1805432d5fedSYoshihiro Shimoda }; 1806432d5fedSYoshihiro Shimoda 1807432d5fedSYoshihiro Shimoda ipmmu_hc: iommu@eed40000 { 1808432d5fedSYoshihiro Shimoda compatible = "renesas,ipmmu-r8a779g0", 1809432d5fedSYoshihiro Shimoda "renesas,rcar-gen4-ipmmu-vmsa"; 1810432d5fedSYoshihiro Shimoda reg = <0 0xeed40000 0 0x20000>; 1811432d5fedSYoshihiro Shimoda renesas,ipmmu-main = <&ipmmu_mm>; 1812432d5fedSYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1813432d5fedSYoshihiro Shimoda #iommu-cells = <1>; 1814432d5fedSYoshihiro Shimoda }; 1815432d5fedSYoshihiro Shimoda 1816432d5fedSYoshihiro Shimoda ipmmu_ir: iommu@eed80000 { 1817432d5fedSYoshihiro Shimoda compatible = "renesas,ipmmu-r8a779g0", 1818432d5fedSYoshihiro Shimoda "renesas,rcar-gen4-ipmmu-vmsa"; 1819432d5fedSYoshihiro Shimoda reg = <0 0xeed80000 0 0x20000>; 1820432d5fedSYoshihiro Shimoda renesas,ipmmu-main = <&ipmmu_mm>; 1821432d5fedSYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_A3IR>; 1822432d5fedSYoshihiro Shimoda #iommu-cells = <1>; 1823432d5fedSYoshihiro Shimoda }; 1824432d5fedSYoshihiro Shimoda 1825432d5fedSYoshihiro Shimoda ipmmu_vc: iommu@eedc0000 { 1826432d5fedSYoshihiro Shimoda compatible = "renesas,ipmmu-r8a779g0", 1827432d5fedSYoshihiro Shimoda "renesas,rcar-gen4-ipmmu-vmsa"; 1828432d5fedSYoshihiro Shimoda reg = <0 0xeedc0000 0 0x20000>; 1829432d5fedSYoshihiro Shimoda renesas,ipmmu-main = <&ipmmu_mm>; 1830432d5fedSYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1831432d5fedSYoshihiro Shimoda #iommu-cells = <1>; 1832432d5fedSYoshihiro Shimoda }; 1833432d5fedSYoshihiro Shimoda 1834432d5fedSYoshihiro Shimoda ipmmu_3dg: iommu@eee00000 { 1835432d5fedSYoshihiro Shimoda compatible = "renesas,ipmmu-r8a779g0", 1836432d5fedSYoshihiro Shimoda "renesas,rcar-gen4-ipmmu-vmsa"; 1837432d5fedSYoshihiro Shimoda reg = <0 0xeee00000 0 0x20000>; 1838432d5fedSYoshihiro Shimoda renesas,ipmmu-main = <&ipmmu_mm>; 1839432d5fedSYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1840432d5fedSYoshihiro Shimoda #iommu-cells = <1>; 1841432d5fedSYoshihiro Shimoda }; 1842432d5fedSYoshihiro Shimoda 1843432d5fedSYoshihiro Shimoda ipmmu_vi0: iommu@eee80000 { 1844432d5fedSYoshihiro Shimoda compatible = "renesas,ipmmu-r8a779g0", 1845432d5fedSYoshihiro Shimoda "renesas,rcar-gen4-ipmmu-vmsa"; 1846432d5fedSYoshihiro Shimoda reg = <0 0xeee80000 0 0x20000>; 1847432d5fedSYoshihiro Shimoda renesas,ipmmu-main = <&ipmmu_mm>; 1848432d5fedSYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1849432d5fedSYoshihiro Shimoda #iommu-cells = <1>; 1850432d5fedSYoshihiro Shimoda }; 1851432d5fedSYoshihiro Shimoda 1852432d5fedSYoshihiro Shimoda ipmmu_vi1: iommu@eeec0000 { 1853432d5fedSYoshihiro Shimoda compatible = "renesas,ipmmu-r8a779g0", 1854432d5fedSYoshihiro Shimoda "renesas,rcar-gen4-ipmmu-vmsa"; 1855432d5fedSYoshihiro Shimoda reg = <0 0xeeec0000 0 0x20000>; 1856432d5fedSYoshihiro Shimoda renesas,ipmmu-main = <&ipmmu_mm>; 1857432d5fedSYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1858432d5fedSYoshihiro Shimoda #iommu-cells = <1>; 1859432d5fedSYoshihiro Shimoda }; 1860432d5fedSYoshihiro Shimoda 1861432d5fedSYoshihiro Shimoda ipmmu_vip0: iommu@eef00000 { 1862432d5fedSYoshihiro Shimoda compatible = "renesas,ipmmu-r8a779g0", 1863432d5fedSYoshihiro Shimoda "renesas,rcar-gen4-ipmmu-vmsa"; 1864432d5fedSYoshihiro Shimoda reg = <0 0xeef00000 0 0x20000>; 1865432d5fedSYoshihiro Shimoda renesas,ipmmu-main = <&ipmmu_mm>; 1866432d5fedSYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1867432d5fedSYoshihiro Shimoda #iommu-cells = <1>; 1868432d5fedSYoshihiro Shimoda }; 1869432d5fedSYoshihiro Shimoda 1870432d5fedSYoshihiro Shimoda ipmmu_vip1: iommu@eef40000 { 1871432d5fedSYoshihiro Shimoda compatible = "renesas,ipmmu-r8a779g0", 1872432d5fedSYoshihiro Shimoda "renesas,rcar-gen4-ipmmu-vmsa"; 1873432d5fedSYoshihiro Shimoda reg = <0 0xeef40000 0 0x20000>; 1874432d5fedSYoshihiro Shimoda renesas,ipmmu-main = <&ipmmu_mm>; 1875432d5fedSYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1876432d5fedSYoshihiro Shimoda #iommu-cells = <1>; 1877432d5fedSYoshihiro Shimoda }; 1878432d5fedSYoshihiro Shimoda 1879432d5fedSYoshihiro Shimoda ipmmu_mm: iommu@eefc0000 { 1880432d5fedSYoshihiro Shimoda compatible = "renesas,ipmmu-r8a779g0", 1881432d5fedSYoshihiro Shimoda "renesas,rcar-gen4-ipmmu-vmsa"; 1882432d5fedSYoshihiro Shimoda reg = <0 0xeefc0000 0 0x20000>; 1883432d5fedSYoshihiro Shimoda interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1884432d5fedSYoshihiro Shimoda <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 1885432d5fedSYoshihiro Shimoda power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1886432d5fedSYoshihiro Shimoda #iommu-cells = <1>; 1887432d5fedSYoshihiro Shimoda }; 1888432d5fedSYoshihiro Shimoda 1889bc7bf913SGeert Uytterhoeven mmc0: mmc@ee140000 { 1890bc7bf913SGeert Uytterhoeven compatible = "renesas,sdhi-r8a779g0", 1891bc7bf913SGeert Uytterhoeven "renesas,rcar-gen4-sdhi"; 1892bc7bf913SGeert Uytterhoeven reg = <0 0xee140000 0 0x2000>; 1893bc7bf913SGeert Uytterhoeven interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 1894bc7bf913SGeert Uytterhoeven clocks = <&cpg CPG_MOD 706>, 1895bc7bf913SGeert Uytterhoeven <&cpg CPG_CORE R8A779G0_CLK_SD0H>; 1896bc7bf913SGeert Uytterhoeven clock-names = "core", "clkh"; 1897bc7bf913SGeert Uytterhoeven power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1898bc7bf913SGeert Uytterhoeven resets = <&cpg 706>; 1899bc7bf913SGeert Uytterhoeven max-frequency = <200000000>; 1900bc7bf913SGeert Uytterhoeven status = "disabled"; 1901bc7bf913SGeert Uytterhoeven }; 1902bc7bf913SGeert Uytterhoeven 1903d5014bedSHai Pham rpc: spi@ee200000 { 1904d5014bedSHai Pham compatible = "renesas,r8a779g0-rpc-if", 1905d5014bedSHai Pham "renesas,rcar-gen4-rpc-if"; 1906d5014bedSHai Pham reg = <0 0xee200000 0 0x200>, 1907d5014bedSHai Pham <0 0x08000000 0 0x04000000>, 1908d5014bedSHai Pham <0 0xee208000 0 0x100>; 1909d5014bedSHai Pham reg-names = "regs", "dirmap", "wbuf"; 1910d5014bedSHai Pham interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1911d5014bedSHai Pham clocks = <&cpg CPG_MOD 629>; 1912d5014bedSHai Pham power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1913d5014bedSHai Pham resets = <&cpg 629>; 1914d5014bedSHai Pham #address-cells = <1>; 1915d5014bedSHai Pham #size-cells = <0>; 1916d5014bedSHai Pham status = "disabled"; 1917d5014bedSHai Pham }; 1918d5014bedSHai Pham 1919987da486SYoshihiro Shimoda gic: interrupt-controller@f1000000 { 1920987da486SYoshihiro Shimoda compatible = "arm,gic-v3"; 1921987da486SYoshihiro Shimoda #interrupt-cells = <3>; 1922987da486SYoshihiro Shimoda #address-cells = <0>; 1923987da486SYoshihiro Shimoda interrupt-controller; 1924987da486SYoshihiro Shimoda reg = <0x0 0xf1000000 0 0x20000>, 1925987da486SYoshihiro Shimoda <0x0 0xf1060000 0 0x110000>; 19268b6a006cSLad Prabhakar interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1927987da486SYoshihiro Shimoda }; 1928987da486SYoshihiro Shimoda 1929d435d437SNiklas Söderlund csi40: csi2@fe500000 { 1930d435d437SNiklas Söderlund compatible = "renesas,r8a779g0-csi2"; 1931d435d437SNiklas Söderlund reg = <0 0xfe500000 0 0x40000>; 1932d435d437SNiklas Söderlund interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>; 1933d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 331>; 1934d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1935d435d437SNiklas Söderlund resets = <&cpg 331>; 1936d435d437SNiklas Söderlund status = "disabled"; 1937d435d437SNiklas Söderlund 1938d435d437SNiklas Söderlund ports { 1939d435d437SNiklas Söderlund #address-cells = <1>; 1940d435d437SNiklas Söderlund #size-cells = <0>; 1941d435d437SNiklas Söderlund 1942d435d437SNiklas Söderlund port@0 { 1943d435d437SNiklas Söderlund reg = <0>; 1944d435d437SNiklas Söderlund }; 1945d435d437SNiklas Söderlund 1946d435d437SNiklas Söderlund port@1 { 1947d435d437SNiklas Söderlund reg = <1>; 1948d435d437SNiklas Söderlund csi40isp0: endpoint { 1949d435d437SNiklas Söderlund remote-endpoint = <&isp0csi40>; 1950d435d437SNiklas Söderlund }; 1951d435d437SNiklas Söderlund }; 1952d435d437SNiklas Söderlund }; 1953d435d437SNiklas Söderlund }; 1954d435d437SNiklas Söderlund 1955d435d437SNiklas Söderlund csi41: csi2@fe540000 { 1956d435d437SNiklas Söderlund compatible = "renesas,r8a779g0-csi2"; 1957d435d437SNiklas Söderlund reg = <0 0xfe540000 0 0x40000>; 1958d435d437SNiklas Söderlund interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>; 1959d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 400>; 1960d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 1961d435d437SNiklas Söderlund resets = <&cpg 400>; 1962d435d437SNiklas Söderlund status = "disabled"; 1963d435d437SNiklas Söderlund 1964d435d437SNiklas Söderlund ports { 1965d435d437SNiklas Söderlund #address-cells = <1>; 1966d435d437SNiklas Söderlund #size-cells = <0>; 1967d435d437SNiklas Söderlund 1968d435d437SNiklas Söderlund port@0 { 1969d435d437SNiklas Söderlund reg = <0>; 1970d435d437SNiklas Söderlund }; 1971d435d437SNiklas Söderlund 1972d435d437SNiklas Söderlund port@1 { 1973d435d437SNiklas Söderlund reg = <1>; 1974d435d437SNiklas Söderlund csi41isp1: endpoint { 1975d435d437SNiklas Söderlund remote-endpoint = <&isp1csi41>; 1976d435d437SNiklas Söderlund }; 1977d435d437SNiklas Söderlund }; 1978d435d437SNiklas Söderlund }; 1979d435d437SNiklas Söderlund }; 1980d435d437SNiklas Söderlund 198195d60f13STomi Valkeinen fcpvd0: fcp@fea10000 { 198295d60f13STomi Valkeinen compatible = "renesas,fcpv"; 198395d60f13STomi Valkeinen reg = <0 0xfea10000 0 0x200>; 198495d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 508>; 198595d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 198695d60f13STomi Valkeinen resets = <&cpg 508>; 198795d60f13STomi Valkeinen }; 198895d60f13STomi Valkeinen 198995d60f13STomi Valkeinen fcpvd1: fcp@fea11000 { 199095d60f13STomi Valkeinen compatible = "renesas,fcpv"; 199195d60f13STomi Valkeinen reg = <0 0xfea11000 0 0x200>; 199295d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 509>; 199395d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 199495d60f13STomi Valkeinen resets = <&cpg 509>; 199595d60f13STomi Valkeinen }; 199695d60f13STomi Valkeinen 199795d60f13STomi Valkeinen vspd0: vsp@fea20000 { 199895d60f13STomi Valkeinen compatible = "renesas,vsp2"; 199995d60f13STomi Valkeinen reg = <0 0xfea20000 0 0x7000>; 200095d60f13STomi Valkeinen interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; 200195d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 830>; 200295d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 200395d60f13STomi Valkeinen resets = <&cpg 830>; 200495d60f13STomi Valkeinen 200595d60f13STomi Valkeinen renesas,fcp = <&fcpvd0>; 200695d60f13STomi Valkeinen }; 200795d60f13STomi Valkeinen 200895d60f13STomi Valkeinen vspd1: vsp@fea28000 { 200995d60f13STomi Valkeinen compatible = "renesas,vsp2"; 201095d60f13STomi Valkeinen reg = <0 0xfea28000 0 0x7000>; 201195d60f13STomi Valkeinen interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 201295d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 831>; 201395d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 201495d60f13STomi Valkeinen resets = <&cpg 831>; 201595d60f13STomi Valkeinen 201695d60f13STomi Valkeinen renesas,fcp = <&fcpvd1>; 201795d60f13STomi Valkeinen }; 201895d60f13STomi Valkeinen 201995d60f13STomi Valkeinen du: display@feb00000 { 202095d60f13STomi Valkeinen compatible = "renesas,du-r8a779g0"; 202195d60f13STomi Valkeinen reg = <0 0xfeb00000 0 0x40000>; 202295d60f13STomi Valkeinen interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 202395d60f13STomi Valkeinen <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>; 202495d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 411>; 202595d60f13STomi Valkeinen clock-names = "du.0"; 202695d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 202795d60f13STomi Valkeinen resets = <&cpg 411>; 202895d60f13STomi Valkeinen reset-names = "du.0"; 202995d60f13STomi Valkeinen renesas,vsps = <&vspd0 0>, <&vspd1 0>; 203095d60f13STomi Valkeinen 203195d60f13STomi Valkeinen status = "disabled"; 203295d60f13STomi Valkeinen 203395d60f13STomi Valkeinen ports { 203495d60f13STomi Valkeinen #address-cells = <1>; 203595d60f13STomi Valkeinen #size-cells = <0>; 203695d60f13STomi Valkeinen 203795d60f13STomi Valkeinen port@0 { 203895d60f13STomi Valkeinen reg = <0>; 203995d60f13STomi Valkeinen du_out_dsi0: endpoint { 204095d60f13STomi Valkeinen remote-endpoint = <&dsi0_in>; 204195d60f13STomi Valkeinen }; 204295d60f13STomi Valkeinen }; 204395d60f13STomi Valkeinen 204495d60f13STomi Valkeinen port@1 { 204595d60f13STomi Valkeinen reg = <1>; 204695d60f13STomi Valkeinen du_out_dsi1: endpoint { 204795d60f13STomi Valkeinen remote-endpoint = <&dsi1_in>; 204895d60f13STomi Valkeinen }; 204995d60f13STomi Valkeinen }; 205095d60f13STomi Valkeinen }; 205195d60f13STomi Valkeinen }; 205295d60f13STomi Valkeinen 2053d435d437SNiklas Söderlund isp0: isp@fed00000 { 2054d435d437SNiklas Söderlund compatible = "renesas,r8a779g0-isp"; 2055d435d437SNiklas Söderlund reg = <0 0xfed00000 0 0x10000>; 2056d435d437SNiklas Söderlund interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_LOW>; 2057d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 612>; 2058d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_A3ISP0>; 2059d435d437SNiklas Söderlund resets = <&cpg 612>; 2060d435d437SNiklas Söderlund status = "disabled"; 2061d435d437SNiklas Söderlund 2062d435d437SNiklas Söderlund ports { 2063d435d437SNiklas Söderlund #address-cells = <1>; 2064d435d437SNiklas Söderlund #size-cells = <0>; 2065d435d437SNiklas Söderlund 2066d435d437SNiklas Söderlund port@0 { 2067d435d437SNiklas Söderlund #address-cells = <1>; 2068d435d437SNiklas Söderlund #size-cells = <0>; 2069d435d437SNiklas Söderlund 2070d435d437SNiklas Söderlund reg = <0>; 2071d435d437SNiklas Söderlund 2072d435d437SNiklas Söderlund isp0csi40: endpoint@0 { 2073d435d437SNiklas Söderlund reg = <0>; 2074d435d437SNiklas Söderlund remote-endpoint = <&csi40isp0>; 2075d435d437SNiklas Söderlund }; 2076d435d437SNiklas Söderlund }; 2077d435d437SNiklas Söderlund 2078d435d437SNiklas Söderlund port@1 { 2079d435d437SNiklas Söderlund reg = <1>; 2080d435d437SNiklas Söderlund isp0vin00: endpoint { 2081d435d437SNiklas Söderlund remote-endpoint = <&vin00isp0>; 2082d435d437SNiklas Söderlund }; 2083d435d437SNiklas Söderlund }; 2084d435d437SNiklas Söderlund 2085d435d437SNiklas Söderlund port@2 { 2086d435d437SNiklas Söderlund reg = <2>; 2087d435d437SNiklas Söderlund isp0vin01: endpoint { 2088d435d437SNiklas Söderlund remote-endpoint = <&vin01isp0>; 2089d435d437SNiklas Söderlund }; 2090d435d437SNiklas Söderlund }; 2091d435d437SNiklas Söderlund 2092d435d437SNiklas Söderlund port@3 { 2093d435d437SNiklas Söderlund reg = <3>; 2094d435d437SNiklas Söderlund isp0vin02: endpoint { 2095d435d437SNiklas Söderlund remote-endpoint = <&vin02isp0>; 2096d435d437SNiklas Söderlund }; 2097d435d437SNiklas Söderlund }; 2098d435d437SNiklas Söderlund 2099d435d437SNiklas Söderlund port@4 { 2100d435d437SNiklas Söderlund reg = <4>; 2101d435d437SNiklas Söderlund isp0vin03: endpoint { 2102d435d437SNiklas Söderlund remote-endpoint = <&vin03isp0>; 2103d435d437SNiklas Söderlund }; 2104d435d437SNiklas Söderlund }; 2105d435d437SNiklas Söderlund 2106d435d437SNiklas Söderlund port@5 { 2107d435d437SNiklas Söderlund reg = <5>; 2108d435d437SNiklas Söderlund isp0vin04: endpoint { 2109d435d437SNiklas Söderlund remote-endpoint = <&vin04isp0>; 2110d435d437SNiklas Söderlund }; 2111d435d437SNiklas Söderlund }; 2112d435d437SNiklas Söderlund 2113d435d437SNiklas Söderlund port@6 { 2114d435d437SNiklas Söderlund reg = <6>; 2115d435d437SNiklas Söderlund isp0vin05: endpoint { 2116d435d437SNiklas Söderlund remote-endpoint = <&vin05isp0>; 2117d435d437SNiklas Söderlund }; 2118d435d437SNiklas Söderlund }; 2119d435d437SNiklas Söderlund 2120d435d437SNiklas Söderlund port@7 { 2121d435d437SNiklas Söderlund reg = <7>; 2122d435d437SNiklas Söderlund isp0vin06: endpoint { 2123d435d437SNiklas Söderlund remote-endpoint = <&vin06isp0>; 2124d435d437SNiklas Söderlund }; 2125d435d437SNiklas Söderlund }; 2126d435d437SNiklas Söderlund 2127d435d437SNiklas Söderlund port@8 { 2128d435d437SNiklas Söderlund reg = <8>; 2129d435d437SNiklas Söderlund isp0vin07: endpoint { 2130d435d437SNiklas Söderlund remote-endpoint = <&vin07isp0>; 2131d435d437SNiklas Söderlund }; 2132d435d437SNiklas Söderlund }; 2133d435d437SNiklas Söderlund }; 2134d435d437SNiklas Söderlund }; 2135d435d437SNiklas Söderlund 2136d435d437SNiklas Söderlund isp1: isp@fed20000 { 2137d435d437SNiklas Söderlund compatible = "renesas,r8a779g0-isp"; 2138d435d437SNiklas Söderlund reg = <0 0xfed20000 0 0x10000>; 2139d435d437SNiklas Söderlund interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_LOW>; 2140d435d437SNiklas Söderlund clocks = <&cpg CPG_MOD 613>; 2141d435d437SNiklas Söderlund power-domains = <&sysc R8A779G0_PD_A3ISP1>; 2142d435d437SNiklas Söderlund resets = <&cpg 613>; 2143d435d437SNiklas Söderlund status = "disabled"; 2144d435d437SNiklas Söderlund 2145d435d437SNiklas Söderlund ports { 2146d435d437SNiklas Söderlund #address-cells = <1>; 2147d435d437SNiklas Söderlund #size-cells = <0>; 2148d435d437SNiklas Söderlund 2149d435d437SNiklas Söderlund port@0 { 2150d435d437SNiklas Söderlund #address-cells = <1>; 2151d435d437SNiklas Söderlund #size-cells = <0>; 2152d435d437SNiklas Söderlund 2153d435d437SNiklas Söderlund reg = <0>; 2154d435d437SNiklas Söderlund 2155d435d437SNiklas Söderlund isp1csi41: endpoint@1 { 2156d435d437SNiklas Söderlund reg = <1>; 2157d435d437SNiklas Söderlund remote-endpoint = <&csi41isp1>; 2158d435d437SNiklas Söderlund }; 2159d435d437SNiklas Söderlund }; 2160d435d437SNiklas Söderlund 2161d435d437SNiklas Söderlund port@1 { 2162d435d437SNiklas Söderlund reg = <1>; 2163d435d437SNiklas Söderlund isp1vin08: endpoint { 2164d435d437SNiklas Söderlund remote-endpoint = <&vin08isp1>; 2165d435d437SNiklas Söderlund }; 2166d435d437SNiklas Söderlund }; 2167d435d437SNiklas Söderlund 2168d435d437SNiklas Söderlund port@2 { 2169d435d437SNiklas Söderlund reg = <2>; 2170d435d437SNiklas Söderlund isp1vin09: endpoint { 2171d435d437SNiklas Söderlund remote-endpoint = <&vin09isp1>; 2172d435d437SNiklas Söderlund }; 2173d435d437SNiklas Söderlund }; 2174d435d437SNiklas Söderlund 2175d435d437SNiklas Söderlund port@3 { 2176d435d437SNiklas Söderlund reg = <3>; 2177d435d437SNiklas Söderlund isp1vin10: endpoint { 2178d435d437SNiklas Söderlund remote-endpoint = <&vin10isp1>; 2179d435d437SNiklas Söderlund }; 2180d435d437SNiklas Söderlund }; 2181d435d437SNiklas Söderlund 2182d435d437SNiklas Söderlund port@4 { 2183d435d437SNiklas Söderlund reg = <4>; 2184d435d437SNiklas Söderlund isp1vin11: endpoint { 2185d435d437SNiklas Söderlund remote-endpoint = <&vin11isp1>; 2186d435d437SNiklas Söderlund }; 2187d435d437SNiklas Söderlund }; 2188d435d437SNiklas Söderlund 2189d435d437SNiklas Söderlund port@5 { 2190d435d437SNiklas Söderlund reg = <5>; 2191d435d437SNiklas Söderlund isp1vin12: endpoint { 2192d435d437SNiklas Söderlund remote-endpoint = <&vin12isp1>; 2193d435d437SNiklas Söderlund }; 2194d435d437SNiklas Söderlund }; 2195d435d437SNiklas Söderlund 2196d435d437SNiklas Söderlund port@6 { 2197d435d437SNiklas Söderlund reg = <6>; 2198d435d437SNiklas Söderlund isp1vin13: endpoint { 2199d435d437SNiklas Söderlund remote-endpoint = <&vin13isp1>; 2200d435d437SNiklas Söderlund }; 2201d435d437SNiklas Söderlund }; 2202d435d437SNiklas Söderlund 2203d435d437SNiklas Söderlund port@7 { 2204d435d437SNiklas Söderlund reg = <7>; 2205d435d437SNiklas Söderlund isp1vin14: endpoint { 2206d435d437SNiklas Söderlund remote-endpoint = <&vin14isp1>; 2207d435d437SNiklas Söderlund }; 2208d435d437SNiklas Söderlund }; 2209d435d437SNiklas Söderlund 2210d435d437SNiklas Söderlund port@8 { 2211d435d437SNiklas Söderlund reg = <8>; 2212d435d437SNiklas Söderlund isp1vin15: endpoint { 2213d435d437SNiklas Söderlund remote-endpoint = <&vin15isp1>; 2214d435d437SNiklas Söderlund }; 2215d435d437SNiklas Söderlund }; 2216d435d437SNiklas Söderlund }; 2217d435d437SNiklas Söderlund }; 2218d435d437SNiklas Söderlund 221995d60f13STomi Valkeinen dsi0: dsi-encoder@fed80000 { 222095d60f13STomi Valkeinen compatible = "renesas,r8a779g0-dsi-csi2-tx"; 222195d60f13STomi Valkeinen reg = <0 0xfed80000 0 0x10000>; 222295d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 415>, 222395d60f13STomi Valkeinen <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, 222495d60f13STomi Valkeinen <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; 222595d60f13STomi Valkeinen clock-names = "fck", "dsi", "pll"; 222695d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 222795d60f13STomi Valkeinen resets = <&cpg 415>; 222895d60f13STomi Valkeinen 222995d60f13STomi Valkeinen status = "disabled"; 223095d60f13STomi Valkeinen 223195d60f13STomi Valkeinen ports { 223295d60f13STomi Valkeinen #address-cells = <1>; 223395d60f13STomi Valkeinen #size-cells = <0>; 223495d60f13STomi Valkeinen 223595d60f13STomi Valkeinen port@0 { 223695d60f13STomi Valkeinen reg = <0>; 223795d60f13STomi Valkeinen dsi0_in: endpoint { 223895d60f13STomi Valkeinen remote-endpoint = <&du_out_dsi0>; 223995d60f13STomi Valkeinen }; 224095d60f13STomi Valkeinen }; 224195d60f13STomi Valkeinen 224295d60f13STomi Valkeinen port@1 { 224395d60f13STomi Valkeinen reg = <1>; 224495d60f13STomi Valkeinen }; 224595d60f13STomi Valkeinen }; 224695d60f13STomi Valkeinen }; 224795d60f13STomi Valkeinen 224895d60f13STomi Valkeinen dsi1: dsi-encoder@fed90000 { 224995d60f13STomi Valkeinen compatible = "renesas,r8a779g0-dsi-csi2-tx"; 225095d60f13STomi Valkeinen reg = <0 0xfed90000 0 0x10000>; 225195d60f13STomi Valkeinen clocks = <&cpg CPG_MOD 416>, 225295d60f13STomi Valkeinen <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>, 225395d60f13STomi Valkeinen <&cpg CPG_CORE R8A779G0_CLK_DSIREF>; 225495d60f13STomi Valkeinen clock-names = "fck", "dsi", "pll"; 225595d60f13STomi Valkeinen power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; 225695d60f13STomi Valkeinen resets = <&cpg 416>; 225795d60f13STomi Valkeinen 225895d60f13STomi Valkeinen status = "disabled"; 225995d60f13STomi Valkeinen 226095d60f13STomi Valkeinen ports { 226195d60f13STomi Valkeinen #address-cells = <1>; 226295d60f13STomi Valkeinen #size-cells = <0>; 226395d60f13STomi Valkeinen 226495d60f13STomi Valkeinen port@0 { 226595d60f13STomi Valkeinen reg = <0>; 226695d60f13STomi Valkeinen dsi1_in: endpoint { 226795d60f13STomi Valkeinen remote-endpoint = <&du_out_dsi1>; 226895d60f13STomi Valkeinen }; 226995d60f13STomi Valkeinen }; 227095d60f13STomi Valkeinen 227195d60f13STomi Valkeinen port@1 { 227295d60f13STomi Valkeinen reg = <1>; 227395d60f13STomi Valkeinen }; 227495d60f13STomi Valkeinen }; 227595d60f13STomi Valkeinen }; 227695d60f13STomi Valkeinen 2277987da486SYoshihiro Shimoda prr: chipid@fff00044 { 2278987da486SYoshihiro Shimoda compatible = "renesas,prr"; 2279987da486SYoshihiro Shimoda reg = <0 0xfff00044 0 4>; 2280987da486SYoshihiro Shimoda }; 2281987da486SYoshihiro Shimoda }; 2282987da486SYoshihiro Shimoda 2283d8ac71d2SGeert Uytterhoeven thermal-zones { 2284d8ac71d2SGeert Uytterhoeven sensor_thermal_cr52: sensor1-thermal { 2285d8ac71d2SGeert Uytterhoeven polling-delay-passive = <250>; 2286d8ac71d2SGeert Uytterhoeven polling-delay = <1000>; 2287d8ac71d2SGeert Uytterhoeven thermal-sensors = <&tsc 0>; 2288d8ac71d2SGeert Uytterhoeven 2289d8ac71d2SGeert Uytterhoeven trips { 2290d8ac71d2SGeert Uytterhoeven sensor1_crit: sensor1-crit { 2291d8ac71d2SGeert Uytterhoeven temperature = <120000>; 2292d8ac71d2SGeert Uytterhoeven hysteresis = <1000>; 2293d8ac71d2SGeert Uytterhoeven type = "critical"; 2294d8ac71d2SGeert Uytterhoeven }; 2295d8ac71d2SGeert Uytterhoeven }; 2296d8ac71d2SGeert Uytterhoeven }; 2297d8ac71d2SGeert Uytterhoeven 2298d8ac71d2SGeert Uytterhoeven sensor_thermal_cnn: sensor2-thermal { 2299d8ac71d2SGeert Uytterhoeven polling-delay-passive = <250>; 2300d8ac71d2SGeert Uytterhoeven polling-delay = <1000>; 2301d8ac71d2SGeert Uytterhoeven thermal-sensors = <&tsc 1>; 2302d8ac71d2SGeert Uytterhoeven 2303d8ac71d2SGeert Uytterhoeven trips { 2304d8ac71d2SGeert Uytterhoeven sensor2_crit: sensor2-crit { 2305d8ac71d2SGeert Uytterhoeven temperature = <120000>; 2306d8ac71d2SGeert Uytterhoeven hysteresis = <1000>; 2307d8ac71d2SGeert Uytterhoeven type = "critical"; 2308d8ac71d2SGeert Uytterhoeven }; 2309d8ac71d2SGeert Uytterhoeven }; 2310d8ac71d2SGeert Uytterhoeven }; 2311d8ac71d2SGeert Uytterhoeven 2312d8ac71d2SGeert Uytterhoeven sensor_thermal_ca76: sensor3-thermal { 2313d8ac71d2SGeert Uytterhoeven polling-delay-passive = <250>; 2314d8ac71d2SGeert Uytterhoeven polling-delay = <1000>; 2315d8ac71d2SGeert Uytterhoeven thermal-sensors = <&tsc 2>; 2316d8ac71d2SGeert Uytterhoeven 2317d8ac71d2SGeert Uytterhoeven trips { 2318d8ac71d2SGeert Uytterhoeven sensor3_crit: sensor3-crit { 2319d8ac71d2SGeert Uytterhoeven temperature = <120000>; 2320d8ac71d2SGeert Uytterhoeven hysteresis = <1000>; 2321d8ac71d2SGeert Uytterhoeven type = "critical"; 2322d8ac71d2SGeert Uytterhoeven }; 2323d8ac71d2SGeert Uytterhoeven }; 2324d8ac71d2SGeert Uytterhoeven }; 2325d8ac71d2SGeert Uytterhoeven 2326d8ac71d2SGeert Uytterhoeven sensor_thermal_ddr1: sensor4-thermal { 2327d8ac71d2SGeert Uytterhoeven polling-delay-passive = <250>; 2328d8ac71d2SGeert Uytterhoeven polling-delay = <1000>; 2329d8ac71d2SGeert Uytterhoeven thermal-sensors = <&tsc 3>; 2330d8ac71d2SGeert Uytterhoeven 2331d8ac71d2SGeert Uytterhoeven trips { 2332d8ac71d2SGeert Uytterhoeven sensor4_crit: sensor4-crit { 2333d8ac71d2SGeert Uytterhoeven temperature = <120000>; 2334d8ac71d2SGeert Uytterhoeven hysteresis = <1000>; 2335d8ac71d2SGeert Uytterhoeven type = "critical"; 2336d8ac71d2SGeert Uytterhoeven }; 2337d8ac71d2SGeert Uytterhoeven }; 2338d8ac71d2SGeert Uytterhoeven }; 2339d8ac71d2SGeert Uytterhoeven }; 2340d8ac71d2SGeert Uytterhoeven 2341987da486SYoshihiro Shimoda timer { 2342987da486SYoshihiro Shimoda compatible = "arm,armv8-timer"; 23438b6a006cSLad Prabhakar interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 23448b6a006cSLad Prabhakar <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 23458b6a006cSLad Prabhakar <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 23468b6a006cSLad Prabhakar <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2347987da486SYoshihiro Shimoda }; 2348987da486SYoshihiro Shimoda}; 2349