1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a779a0-sysc.h>
11
12/ {
13	compatible = "renesas,r8a779a0";
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		a76_0: cpu@0 {
22			compatible = "arm,cortex-a76";
23			reg = <0>;
24			device_type = "cpu";
25			power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
26			next-level-cache = <&L3_CA76_0>;
27		};
28
29		L3_CA76_0: cache-controller-0 {
30			compatible = "cache";
31			power-domains = <&sysc R8A779A0_PD_A2E0D0>;
32			cache-unified;
33			cache-level = <3>;
34		};
35	};
36
37	extal_clk: extal {
38		compatible = "fixed-clock";
39		#clock-cells = <0>;
40		/* This value must be overridden by the board */
41		clock-frequency = <0>;
42	};
43
44	extalr_clk: extalr {
45		compatible = "fixed-clock";
46		#clock-cells = <0>;
47		/* This value must be overridden by the board */
48		clock-frequency = <0>;
49	};
50
51	pmu_a76 {
52		compatible = "arm,cortex-a76-pmu";
53		interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
54				      <&gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
55				      <&gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
56				      <&gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
57	};
58
59	/* External SCIF clock - to be overridden by boards that provide it */
60	scif_clk: scif {
61		compatible = "fixed-clock";
62		#clock-cells = <0>;
63		clock-frequency = <0>;
64	};
65
66	soc: soc {
67		compatible = "simple-bus";
68		interrupt-parent = <&gic>;
69		#address-cells = <2>;
70		#size-cells = <2>;
71		ranges;
72
73		cpg: clock-controller@e6150000 {
74			compatible = "renesas,r8a779a0-cpg-mssr";
75			reg = <0 0xe6150000 0 0x4000>;
76			clocks = <&extal_clk>, <&extalr_clk>;
77			clock-names = "extal", "extalr";
78			#clock-cells = <2>;
79			#power-domain-cells = <0>;
80			#reset-cells = <1>;
81		};
82
83		rst: reset-controller@e6160000 {
84			compatible = "renesas,r8a779a0-rst";
85			reg = <0 0xe6160000 0 0x4000>;
86		};
87
88		sysc: system-controller@e6180000 {
89			compatible = "renesas,r8a779a0-sysc";
90			reg = <0 0xe6180000 0 0x4000>;
91			#power-domain-cells = <1>;
92		};
93
94		scif0: serial@e6e60000 {
95			compatible = "renesas,scif-r8a779a0",
96				     "renesas,rcar-gen3-scif", "renesas,scif";
97			reg = <0 0xe6e60000 0 64>;
98			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
99			clocks = <&cpg CPG_MOD 702>,
100				 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
101				 <&scif_clk>;
102			clock-names = "fck", "brg_int", "scif_clk";
103			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
104			resets = <&cpg 702>;
105			status = "disabled";
106		};
107
108		gic: interrupt-controller@f1000000 {
109			compatible = "arm,gic-v3";
110			#interrupt-cells = <3>;
111			#address-cells = <0>;
112			interrupt-controller;
113			reg = <0x0 0xf1000000 0 0x20000>,
114			      <0x0 0xf1060000 0 0x110000>;
115			interrupts = <GIC_PPI 9
116				      (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
117			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
118		};
119
120		prr: chipid@fff00044 {
121			compatible = "renesas,prr";
122			reg = <0 0xfff00044 0 4>;
123		};
124	};
125
126	timer {
127		compatible = "arm,armv8-timer";
128		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
129				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
130				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
131				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
132	};
133};
134