1/* 2 * Device Tree Source for the r8a77995 SoC 3 * 4 * Copyright (C) 2016 Renesas Electronics Corp. 5 * Copyright (C) 2017 Glider bvba 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12#include <dt-bindings/clock/r8a77995-cpg-mssr.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/r8a77995-sysc.h> 15 16/ { 17 compatible = "renesas,r8a77995"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 /* External CAN clock - to be overridden by boards that provide it */ 22 can_clk: can { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 a53_0: cpu@0 { 33 compatible = "arm,cortex-a53", "arm,armv8"; 34 reg = <0x0>; 35 device_type = "cpu"; 36 power-domains = <&sysc R8A77995_PD_CA53_CPU0>; 37 next-level-cache = <&L2_CA53>; 38 enable-method = "psci"; 39 }; 40 41 L2_CA53: cache-controller-1 { 42 compatible = "cache"; 43 power-domains = <&sysc R8A77995_PD_CA53_SCU>; 44 cache-unified; 45 cache-level = <2>; 46 }; 47 }; 48 49 extal_clk: extal { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 /* This value must be overridden by the board */ 53 clock-frequency = <0>; 54 }; 55 56 pmu_a53 { 57 compatible = "arm,cortex-a53-pmu"; 58 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 59 }; 60 61 psci { 62 compatible = "arm,psci-1.0", "arm,psci-0.2"; 63 method = "smc"; 64 }; 65 66 scif_clk: scif { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <0>; 70 }; 71 72 soc { 73 compatible = "simple-bus"; 74 interrupt-parent = <&gic>; 75 #address-cells = <2>; 76 #size-cells = <2>; 77 ranges; 78 79 rwdt: watchdog@e6020000 { 80 compatible = "renesas,r8a77995-wdt", 81 "renesas,rcar-gen3-wdt"; 82 reg = <0 0xe6020000 0 0x0c>; 83 clocks = <&cpg CPG_MOD 402>; 84 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 85 resets = <&cpg 402>; 86 status = "disabled"; 87 }; 88 89 gpio0: gpio@e6050000 { 90 compatible = "renesas,gpio-r8a77995", 91 "renesas,rcar-gen3-gpio", 92 "renesas,gpio-rcar"; 93 reg = <0 0xe6050000 0 0x50>; 94 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 95 #gpio-cells = <2>; 96 gpio-controller; 97 gpio-ranges = <&pfc 0 0 9>; 98 #interrupt-cells = <2>; 99 interrupt-controller; 100 clocks = <&cpg CPG_MOD 912>; 101 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 102 resets = <&cpg 912>; 103 }; 104 105 gpio1: gpio@e6051000 { 106 compatible = "renesas,gpio-r8a77995", 107 "renesas,rcar-gen3-gpio", 108 "renesas,gpio-rcar"; 109 reg = <0 0xe6051000 0 0x50>; 110 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 111 #gpio-cells = <2>; 112 gpio-controller; 113 gpio-ranges = <&pfc 0 32 32>; 114 #interrupt-cells = <2>; 115 interrupt-controller; 116 clocks = <&cpg CPG_MOD 911>; 117 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 118 resets = <&cpg 911>; 119 }; 120 121 gpio2: gpio@e6052000 { 122 compatible = "renesas,gpio-r8a77995", 123 "renesas,rcar-gen3-gpio", 124 "renesas,gpio-rcar"; 125 reg = <0 0xe6052000 0 0x50>; 126 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 127 #gpio-cells = <2>; 128 gpio-controller; 129 gpio-ranges = <&pfc 0 64 32>; 130 #interrupt-cells = <2>; 131 interrupt-controller; 132 clocks = <&cpg CPG_MOD 910>; 133 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 134 resets = <&cpg 910>; 135 }; 136 137 gpio3: gpio@e6053000 { 138 compatible = "renesas,gpio-r8a77995", 139 "renesas,rcar-gen3-gpio", 140 "renesas,gpio-rcar"; 141 reg = <0 0xe6053000 0 0x50>; 142 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 143 #gpio-cells = <2>; 144 gpio-controller; 145 gpio-ranges = <&pfc 0 96 10>; 146 #interrupt-cells = <2>; 147 interrupt-controller; 148 clocks = <&cpg CPG_MOD 909>; 149 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 150 resets = <&cpg 909>; 151 }; 152 153 gpio4: gpio@e6054000 { 154 compatible = "renesas,gpio-r8a77995", 155 "renesas,rcar-gen3-gpio", 156 "renesas,gpio-rcar"; 157 reg = <0 0xe6054000 0 0x50>; 158 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 159 #gpio-cells = <2>; 160 gpio-controller; 161 gpio-ranges = <&pfc 0 128 32>; 162 #interrupt-cells = <2>; 163 interrupt-controller; 164 clocks = <&cpg CPG_MOD 908>; 165 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 166 resets = <&cpg 908>; 167 }; 168 169 gpio5: gpio@e6055000 { 170 compatible = "renesas,gpio-r8a77995", 171 "renesas,rcar-gen3-gpio", 172 "renesas,gpio-rcar"; 173 reg = <0 0xe6055000 0 0x50>; 174 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 175 #gpio-cells = <2>; 176 gpio-controller; 177 gpio-ranges = <&pfc 0 160 21>; 178 #interrupt-cells = <2>; 179 interrupt-controller; 180 clocks = <&cpg CPG_MOD 907>; 181 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 182 resets = <&cpg 907>; 183 }; 184 185 gpio6: gpio@e6055400 { 186 compatible = "renesas,gpio-r8a77995", 187 "renesas,rcar-gen3-gpio", 188 "renesas,gpio-rcar"; 189 reg = <0 0xe6055400 0 0x50>; 190 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 191 #gpio-cells = <2>; 192 gpio-controller; 193 gpio-ranges = <&pfc 0 192 14>; 194 #interrupt-cells = <2>; 195 interrupt-controller; 196 clocks = <&cpg CPG_MOD 906>; 197 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 198 resets = <&cpg 906>; 199 }; 200 201 pfc: pin-controller@e6060000 { 202 compatible = "renesas,pfc-r8a77995"; 203 reg = <0 0xe6060000 0 0x508>; 204 }; 205 206 cpg: clock-controller@e6150000 { 207 compatible = "renesas,r8a77995-cpg-mssr"; 208 reg = <0 0xe6150000 0 0x1000>; 209 clocks = <&extal_clk>; 210 clock-names = "extal"; 211 #clock-cells = <2>; 212 #power-domain-cells = <0>; 213 #reset-cells = <1>; 214 }; 215 216 rst: reset-controller@e6160000 { 217 compatible = "renesas,r8a77995-rst"; 218 reg = <0 0xe6160000 0 0x0200>; 219 }; 220 221 sysc: system-controller@e6180000 { 222 compatible = "renesas,r8a77995-sysc"; 223 reg = <0 0xe6180000 0 0x0400>; 224 #power-domain-cells = <1>; 225 }; 226 227 intc_ex: interrupt-controller@e61c0000 { 228 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; 229 #interrupt-cells = <2>; 230 interrupt-controller; 231 reg = <0 0xe61c0000 0 0x200>; 232 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 233 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 234 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 235 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 236 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 237 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&cpg CPG_MOD 407>; 239 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 240 resets = <&cpg 407>; 241 }; 242 243 i2c0: i2c@e6500000 { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 compatible = "renesas,i2c-r8a77995", 247 "renesas,rcar-gen3-i2c"; 248 reg = <0 0xe6500000 0 0x40>; 249 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&cpg CPG_MOD 931>; 251 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 252 resets = <&cpg 931>; 253 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 254 <&dmac2 0x91>, <&dmac2 0x90>; 255 dma-names = "tx", "rx", "tx", "rx"; 256 i2c-scl-internal-delay-ns = <6>; 257 status = "disabled"; 258 }; 259 260 i2c1: i2c@e6508000 { 261 #address-cells = <1>; 262 #size-cells = <0>; 263 compatible = "renesas,i2c-r8a77995", 264 "renesas,rcar-gen3-i2c"; 265 reg = <0 0xe6508000 0 0x40>; 266 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cpg CPG_MOD 930>; 268 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 269 resets = <&cpg 930>; 270 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 271 <&dmac2 0x93>, <&dmac2 0x92>; 272 dma-names = "tx", "rx", "tx", "rx"; 273 i2c-scl-internal-delay-ns = <6>; 274 status = "disabled"; 275 }; 276 277 i2c2: i2c@e6510000 { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 compatible = "renesas,i2c-r8a77995", 281 "renesas,rcar-gen3-i2c"; 282 reg = <0 0xe6510000 0 0x40>; 283 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&cpg CPG_MOD 929>; 285 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 286 resets = <&cpg 929>; 287 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 288 <&dmac2 0x95>, <&dmac2 0x94>; 289 dma-names = "tx", "rx", "tx", "rx"; 290 i2c-scl-internal-delay-ns = <6>; 291 status = "disabled"; 292 }; 293 294 i2c3: i2c@e66d0000 { 295 #address-cells = <1>; 296 #size-cells = <0>; 297 compatible = "renesas,i2c-r8a77995", 298 "renesas,rcar-gen3-i2c"; 299 reg = <0 0xe66d0000 0 0x40>; 300 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&cpg CPG_MOD 928>; 302 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 303 resets = <&cpg 928>; 304 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 305 dma-names = "tx", "rx"; 306 i2c-scl-internal-delay-ns = <6>; 307 status = "disabled"; 308 }; 309 310 canfd: can@e66c0000 { 311 compatible = "renesas,r8a77995-canfd", 312 "renesas,rcar-gen3-canfd"; 313 reg = <0 0xe66c0000 0 0x8000>; 314 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&cpg CPG_MOD 914>, 317 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 318 <&can_clk>; 319 clock-names = "fck", "canfd", "can_clk"; 320 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 321 assigned-clock-rates = <40000000>; 322 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 323 resets = <&cpg 914>; 324 status = "disabled"; 325 326 channel0 { 327 status = "disabled"; 328 }; 329 330 channel1 { 331 status = "disabled"; 332 }; 333 }; 334 335 dmac0: dma-controller@e6700000 { 336 compatible = "renesas,dmac-r8a77995", 337 "renesas,rcar-dmac"; 338 reg = <0 0xe6700000 0 0x10000>; 339 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 342 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 343 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 344 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 345 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 346 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 347 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 348 interrupt-names = "error", 349 "ch0", "ch1", "ch2", "ch3", 350 "ch4", "ch5", "ch6", "ch7"; 351 clocks = <&cpg CPG_MOD 219>; 352 clock-names = "fck"; 353 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 354 resets = <&cpg 219>; 355 #dma-cells = <1>; 356 dma-channels = <8>; 357 }; 358 359 dmac1: dma-controller@e7300000 { 360 compatible = "renesas,dmac-r8a77995", 361 "renesas,rcar-dmac"; 362 reg = <0 0xe7300000 0 0x10000>; 363 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 364 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 365 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 366 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 367 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 368 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 369 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 370 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 371 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 372 interrupt-names = "error", 373 "ch0", "ch1", "ch2", "ch3", 374 "ch4", "ch5", "ch6", "ch7"; 375 clocks = <&cpg CPG_MOD 218>; 376 clock-names = "fck"; 377 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 378 resets = <&cpg 218>; 379 #dma-cells = <1>; 380 dma-channels = <8>; 381 }; 382 383 dmac2: dma-controller@e7310000 { 384 compatible = "renesas,dmac-r8a77995", 385 "renesas,rcar-dmac"; 386 reg = <0 0xe7310000 0 0x10000>; 387 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 388 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 389 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 390 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 391 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 392 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 393 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 394 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 395 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 396 interrupt-names = "error", 397 "ch0", "ch1", "ch2", "ch3", 398 "ch4", "ch5", "ch6", "ch7"; 399 clocks = <&cpg CPG_MOD 217>; 400 clock-names = "fck"; 401 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 402 resets = <&cpg 217>; 403 #dma-cells = <1>; 404 dma-channels = <8>; 405 }; 406 407 ipmmu_ds0: mmu@e6740000 { 408 compatible = "renesas,ipmmu-r8a77995"; 409 reg = <0 0xe6740000 0 0x1000>; 410 renesas,ipmmu-main = <&ipmmu_mm 0>; 411 #iommu-cells = <1>; 412 }; 413 414 ipmmu_ds1: mmu@e7740000 { 415 compatible = "renesas,ipmmu-r8a77995"; 416 reg = <0 0xe7740000 0 0x1000>; 417 renesas,ipmmu-main = <&ipmmu_mm 1>; 418 #iommu-cells = <1>; 419 }; 420 421 ipmmu_hc: mmu@e6570000 { 422 compatible = "renesas,ipmmu-r8a77995"; 423 reg = <0 0xe6570000 0 0x1000>; 424 renesas,ipmmu-main = <&ipmmu_mm 2>; 425 #iommu-cells = <1>; 426 }; 427 428 ipmmu_mm: mmu@e67b0000 { 429 compatible = "renesas,ipmmu-r8a77995"; 430 reg = <0 0xe67b0000 0 0x1000>; 431 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 433 #iommu-cells = <1>; 434 }; 435 436 ipmmu_mp: mmu@ec670000 { 437 compatible = "renesas,ipmmu-r8a77995"; 438 reg = <0 0xec670000 0 0x1000>; 439 renesas,ipmmu-main = <&ipmmu_mm 4>; 440 #iommu-cells = <1>; 441 }; 442 443 ipmmu_pv0: mmu@fd800000 { 444 compatible = "renesas,ipmmu-r8a77995"; 445 reg = <0 0xfd800000 0 0x1000>; 446 renesas,ipmmu-main = <&ipmmu_mm 6>; 447 #iommu-cells = <1>; 448 }; 449 450 ipmmu_rt: mmu@ffc80000 { 451 compatible = "renesas,ipmmu-r8a77995"; 452 reg = <0 0xffc80000 0 0x1000>; 453 renesas,ipmmu-main = <&ipmmu_mm 10>; 454 #iommu-cells = <1>; 455 }; 456 457 ipmmu_vc0: mmu@fe6b0000 { 458 compatible = "renesas,ipmmu-r8a77995"; 459 reg = <0 0xfe6b0000 0 0x1000>; 460 renesas,ipmmu-main = <&ipmmu_mm 12>; 461 #iommu-cells = <1>; 462 }; 463 464 ipmmu_vi0: mmu@febd0000 { 465 compatible = "renesas,ipmmu-r8a77995"; 466 reg = <0 0xfebd0000 0 0x1000>; 467 renesas,ipmmu-main = <&ipmmu_mm 14>; 468 #iommu-cells = <1>; 469 }; 470 471 ipmmu_vp0: mmu@fe990000 { 472 compatible = "renesas,ipmmu-r8a77995"; 473 reg = <0 0xfe990000 0 0x1000>; 474 renesas,ipmmu-main = <&ipmmu_mm 16>; 475 #iommu-cells = <1>; 476 }; 477 478 avb: ethernet@e6800000 { 479 compatible = "renesas,etheravb-r8a77995", 480 "renesas,etheravb-rcar-gen3"; 481 reg = <0 0xe6800000 0 0x800>; 482 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 507 interrupt-names = "ch0", "ch1", "ch2", "ch3", 508 "ch4", "ch5", "ch6", "ch7", 509 "ch8", "ch9", "ch10", "ch11", 510 "ch12", "ch13", "ch14", "ch15", 511 "ch16", "ch17", "ch18", "ch19", 512 "ch20", "ch21", "ch22", "ch23", 513 "ch24"; 514 clocks = <&cpg CPG_MOD 812>; 515 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 516 resets = <&cpg 812>; 517 phy-mode = "rgmii"; 518 iommus = <&ipmmu_ds0 16>; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 status = "disabled"; 522 }; 523 524 can0: can@e6c30000 { 525 compatible = "renesas,can-r8a77995", 526 "renesas,rcar-gen3-can"; 527 reg = <0 0xe6c30000 0 0x1000>; 528 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&cpg CPG_MOD 916>, 530 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 531 <&can_clk>; 532 clock-names = "clkp1", "clkp2", "can_clk"; 533 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 534 assigned-clock-rates = <40000000>; 535 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 536 resets = <&cpg 916>; 537 status = "disabled"; 538 }; 539 540 can1: can@e6c38000 { 541 compatible = "renesas,can-r8a77995", 542 "renesas,rcar-gen3-can"; 543 reg = <0 0xe6c38000 0 0x1000>; 544 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&cpg CPG_MOD 915>, 546 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 547 <&can_clk>; 548 clock-names = "clkp1", "clkp2", "can_clk"; 549 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 550 assigned-clock-rates = <40000000>; 551 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 552 resets = <&cpg 915>; 553 status = "disabled"; 554 }; 555 556 pwm0: pwm@e6e30000 { 557 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 558 reg = <0 0xe6e30000 0 0x8>; 559 #pwm-cells = <2>; 560 clocks = <&cpg CPG_MOD 523>; 561 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 562 resets = <&cpg 523>; 563 status = "disabled"; 564 }; 565 566 pwm1: pwm@e6e31000 { 567 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 568 reg = <0 0xe6e31000 0 0x8>; 569 #pwm-cells = <2>; 570 clocks = <&cpg CPG_MOD 523>; 571 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 572 resets = <&cpg 523>; 573 status = "disabled"; 574 }; 575 576 pwm2: pwm@e6e32000 { 577 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 578 reg = <0 0xe6e32000 0 0x8>; 579 #pwm-cells = <2>; 580 clocks = <&cpg CPG_MOD 523>; 581 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 582 resets = <&cpg 523>; 583 status = "disabled"; 584 }; 585 586 pwm3: pwm@e6e33000 { 587 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 588 reg = <0 0xe6e33000 0 0x8>; 589 #pwm-cells = <2>; 590 clocks = <&cpg CPG_MOD 523>; 591 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 592 resets = <&cpg 523>; 593 status = "disabled"; 594 }; 595 596 scif2: serial@e6e88000 { 597 compatible = "renesas,scif-r8a77995", 598 "renesas,rcar-gen3-scif", "renesas,scif"; 599 reg = <0 0xe6e88000 0 64>; 600 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&cpg CPG_MOD 310>, 602 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 603 <&scif_clk>; 604 clock-names = "fck", "brg_int", "scif_clk"; 605 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 606 <&dmac2 0x13>, <&dmac2 0x12>; 607 dma-names = "tx", "rx", "tx", "rx"; 608 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 609 resets = <&cpg 310>; 610 status = "disabled"; 611 }; 612 613 vin4: video@e6ef4000 { 614 compatible = "renesas,vin-r8a77995"; 615 reg = <0 0xe6ef4000 0 0x1000>; 616 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&cpg CPG_MOD 807>; 618 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 619 resets = <&cpg 807>; 620 renesas,id = <4>; 621 status = "disabled"; 622 }; 623 624 ohci0: usb@ee080000 { 625 compatible = "generic-ohci"; 626 reg = <0 0xee080000 0 0x100>; 627 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&cpg CPG_MOD 703>; 629 phys = <&usb2_phy0>; 630 phy-names = "usb"; 631 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 632 resets = <&cpg 703>; 633 status = "disabled"; 634 }; 635 636 ehci0: usb@ee080100 { 637 compatible = "generic-ehci"; 638 reg = <0 0xee080100 0 0x100>; 639 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&cpg CPG_MOD 703>; 641 phys = <&usb2_phy0>; 642 phy-names = "usb"; 643 companion = <&ohci0>; 644 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 645 resets = <&cpg 703>; 646 status = "disabled"; 647 }; 648 649 usb2_phy0: usb-phy@ee080200 { 650 compatible = "renesas,usb2-phy-r8a77995", 651 "renesas,rcar-gen3-usb2-phy"; 652 reg = <0 0xee080200 0 0x700>; 653 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&cpg CPG_MOD 703>; 655 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 656 resets = <&cpg 703>; 657 #phy-cells = <0>; 658 status = "disabled"; 659 }; 660 661 sdhi2: sd@ee140000 { 662 compatible = "renesas,sdhi-r8a77995", 663 "renesas,rcar-gen3-sdhi"; 664 reg = <0 0xee140000 0 0x2000>; 665 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cpg CPG_MOD 312>; 667 max-frequency = <200000000>; 668 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 669 resets = <&cpg 312>; 670 status = "disabled"; 671 }; 672 673 gic: interrupt-controller@f1010000 { 674 compatible = "arm,gic-400"; 675 #interrupt-cells = <3>; 676 #address-cells = <0>; 677 interrupt-controller; 678 reg = <0x0 0xf1010000 0 0x1000>, 679 <0x0 0xf1020000 0 0x20000>, 680 <0x0 0xf1040000 0 0x20000>, 681 <0x0 0xf1060000 0 0x20000>; 682 interrupts = <GIC_PPI 9 683 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 684 clocks = <&cpg CPG_MOD 408>; 685 clock-names = "clk"; 686 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 687 resets = <&cpg 408>; 688 }; 689 690 vspbs: vsp@fe960000 { 691 compatible = "renesas,vsp2"; 692 reg = <0 0xfe960000 0 0x8000>; 693 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&cpg CPG_MOD 627>; 695 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 696 resets = <&cpg 627>; 697 renesas,fcp = <&fcpvb0>; 698 }; 699 700 vspd0: vsp@fea20000 { 701 compatible = "renesas,vsp2"; 702 reg = <0 0xfea20000 0 0x8000>; 703 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&cpg CPG_MOD 623>; 705 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 706 resets = <&cpg 623>; 707 renesas,fcp = <&fcpvd0>; 708 }; 709 710 vspd1: vsp@fea28000 { 711 compatible = "renesas,vsp2"; 712 reg = <0 0xfea28000 0 0x8000>; 713 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&cpg CPG_MOD 622>; 715 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 716 resets = <&cpg 622>; 717 renesas,fcp = <&fcpvd1>; 718 }; 719 720 fcpvb0: fcp@fe96f000 { 721 compatible = "renesas,fcpv"; 722 reg = <0 0xfe96f000 0 0x200>; 723 clocks = <&cpg CPG_MOD 607>; 724 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 725 resets = <&cpg 607>; 726 iommus = <&ipmmu_vp0 5>; 727 }; 728 729 fcpvd0: fcp@fea27000 { 730 compatible = "renesas,fcpv"; 731 reg = <0 0xfea27000 0 0x200>; 732 clocks = <&cpg CPG_MOD 603>; 733 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 734 resets = <&cpg 603>; 735 iommus = <&ipmmu_vi0 8>; 736 }; 737 738 fcpvd1: fcp@fea2f000 { 739 compatible = "renesas,fcpv"; 740 reg = <0 0xfea2f000 0 0x200>; 741 clocks = <&cpg CPG_MOD 602>; 742 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 743 resets = <&cpg 602>; 744 iommus = <&ipmmu_vi0 9>; 745 }; 746 747 du: display@feb00000 { 748 compatible = "renesas,du-r8a77995"; 749 reg = <0 0xfeb00000 0 0x80000>; 750 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&cpg CPG_MOD 724>, 753 <&cpg CPG_MOD 723>; 754 clock-names = "du.0", "du.1"; 755 vsps = <&vspd0 0 &vspd1 0>; 756 status = "disabled"; 757 758 ports { 759 #address-cells = <1>; 760 #size-cells = <0>; 761 762 port@0 { 763 reg = <0>; 764 du_out_rgb: endpoint { 765 }; 766 }; 767 768 port@1 { 769 reg = <1>; 770 du_out_lvds0: endpoint { 771 }; 772 }; 773 774 port@2 { 775 reg = <2>; 776 du_out_lvds1: endpoint { 777 }; 778 }; 779 }; 780 }; 781 782 prr: chipid@fff00044 { 783 compatible = "renesas,prr"; 784 reg = <0 0xfff00044 0 4>; 785 }; 786 }; 787 788 timer { 789 compatible = "arm,armv8-timer"; 790 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 791 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 792 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 793 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 794 }; 795}; 796