1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car D3 (R8A77995) SoC 4 * 5 * Copyright (C) 2016 Renesas Electronics Corp. 6 * Copyright (C) 2017 Glider bvba 7 */ 8 9#include <dt-bindings/clock/r8a77995-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/r8a77995-sysc.h> 12 13/ { 14 compatible = "renesas,r8a77995"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* External CAN clock - to be overridden by boards that provide it */ 19 can_clk: can { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <0>; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 a53_0: cpu@0 { 30 compatible = "arm,cortex-a53"; 31 reg = <0x0>; 32 device_type = "cpu"; 33 power-domains = <&sysc R8A77995_PD_CA53_CPU0>; 34 next-level-cache = <&L2_CA53>; 35 enable-method = "psci"; 36 }; 37 38 L2_CA53: cache-controller-1 { 39 compatible = "cache"; 40 power-domains = <&sysc R8A77995_PD_CA53_SCU>; 41 cache-unified; 42 cache-level = <2>; 43 }; 44 }; 45 46 extal_clk: extal { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 /* This value must be overridden by the board */ 50 clock-frequency = <0>; 51 }; 52 53 pmu_a53 { 54 compatible = "arm,cortex-a53-pmu"; 55 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 56 }; 57 58 psci { 59 compatible = "arm,psci-1.0", "arm,psci-0.2"; 60 method = "smc"; 61 }; 62 63 scif_clk: scif { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 67 }; 68 69 soc { 70 compatible = "simple-bus"; 71 interrupt-parent = <&gic>; 72 #address-cells = <2>; 73 #size-cells = <2>; 74 ranges; 75 76 rwdt: watchdog@e6020000 { 77 compatible = "renesas,r8a77995-wdt", 78 "renesas,rcar-gen3-wdt"; 79 reg = <0 0xe6020000 0 0x0c>; 80 clocks = <&cpg CPG_MOD 402>; 81 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 82 resets = <&cpg 402>; 83 status = "disabled"; 84 }; 85 86 gpio0: gpio@e6050000 { 87 compatible = "renesas,gpio-r8a77995", 88 "renesas,rcar-gen3-gpio"; 89 reg = <0 0xe6050000 0 0x50>; 90 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 91 #gpio-cells = <2>; 92 gpio-controller; 93 gpio-ranges = <&pfc 0 0 9>; 94 #interrupt-cells = <2>; 95 interrupt-controller; 96 clocks = <&cpg CPG_MOD 912>; 97 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 98 resets = <&cpg 912>; 99 }; 100 101 gpio1: gpio@e6051000 { 102 compatible = "renesas,gpio-r8a77995", 103 "renesas,rcar-gen3-gpio"; 104 reg = <0 0xe6051000 0 0x50>; 105 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 106 #gpio-cells = <2>; 107 gpio-controller; 108 gpio-ranges = <&pfc 0 32 32>; 109 #interrupt-cells = <2>; 110 interrupt-controller; 111 clocks = <&cpg CPG_MOD 911>; 112 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 113 resets = <&cpg 911>; 114 }; 115 116 gpio2: gpio@e6052000 { 117 compatible = "renesas,gpio-r8a77995", 118 "renesas,rcar-gen3-gpio"; 119 reg = <0 0xe6052000 0 0x50>; 120 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 121 #gpio-cells = <2>; 122 gpio-controller; 123 gpio-ranges = <&pfc 0 64 32>; 124 #interrupt-cells = <2>; 125 interrupt-controller; 126 clocks = <&cpg CPG_MOD 910>; 127 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 128 resets = <&cpg 910>; 129 }; 130 131 gpio3: gpio@e6053000 { 132 compatible = "renesas,gpio-r8a77995", 133 "renesas,rcar-gen3-gpio"; 134 reg = <0 0xe6053000 0 0x50>; 135 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 136 #gpio-cells = <2>; 137 gpio-controller; 138 gpio-ranges = <&pfc 0 96 10>; 139 #interrupt-cells = <2>; 140 interrupt-controller; 141 clocks = <&cpg CPG_MOD 909>; 142 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 143 resets = <&cpg 909>; 144 }; 145 146 gpio4: gpio@e6054000 { 147 compatible = "renesas,gpio-r8a77995", 148 "renesas,rcar-gen3-gpio"; 149 reg = <0 0xe6054000 0 0x50>; 150 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 151 #gpio-cells = <2>; 152 gpio-controller; 153 gpio-ranges = <&pfc 0 128 32>; 154 #interrupt-cells = <2>; 155 interrupt-controller; 156 clocks = <&cpg CPG_MOD 908>; 157 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 158 resets = <&cpg 908>; 159 }; 160 161 gpio5: gpio@e6055000 { 162 compatible = "renesas,gpio-r8a77995", 163 "renesas,rcar-gen3-gpio"; 164 reg = <0 0xe6055000 0 0x50>; 165 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 166 #gpio-cells = <2>; 167 gpio-controller; 168 gpio-ranges = <&pfc 0 160 21>; 169 #interrupt-cells = <2>; 170 interrupt-controller; 171 clocks = <&cpg CPG_MOD 907>; 172 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 173 resets = <&cpg 907>; 174 }; 175 176 gpio6: gpio@e6055400 { 177 compatible = "renesas,gpio-r8a77995", 178 "renesas,rcar-gen3-gpio"; 179 reg = <0 0xe6055400 0 0x50>; 180 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 181 #gpio-cells = <2>; 182 gpio-controller; 183 gpio-ranges = <&pfc 0 192 14>; 184 #interrupt-cells = <2>; 185 interrupt-controller; 186 clocks = <&cpg CPG_MOD 906>; 187 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 188 resets = <&cpg 906>; 189 }; 190 191 pfc: pinctrl@e6060000 { 192 compatible = "renesas,pfc-r8a77995"; 193 reg = <0 0xe6060000 0 0x508>; 194 }; 195 196 cmt0: timer@e60f0000 { 197 compatible = "renesas,r8a77995-cmt0", 198 "renesas,rcar-gen3-cmt0"; 199 reg = <0 0xe60f0000 0 0x1004>; 200 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&cpg CPG_MOD 303>; 203 clock-names = "fck"; 204 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 205 resets = <&cpg 303>; 206 status = "disabled"; 207 }; 208 209 cmt1: timer@e6130000 { 210 compatible = "renesas,r8a77995-cmt1", 211 "renesas,rcar-gen3-cmt1"; 212 reg = <0 0xe6130000 0 0x1004>; 213 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&cpg CPG_MOD 302>; 222 clock-names = "fck"; 223 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 224 resets = <&cpg 302>; 225 status = "disabled"; 226 }; 227 228 cmt2: timer@e6140000 { 229 compatible = "renesas,r8a77995-cmt1", 230 "renesas,rcar-gen3-cmt1"; 231 reg = <0 0xe6140000 0 0x1004>; 232 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&cpg CPG_MOD 301>; 241 clock-names = "fck"; 242 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 243 resets = <&cpg 301>; 244 status = "disabled"; 245 }; 246 247 cmt3: timer@e6148000 { 248 compatible = "renesas,r8a77995-cmt1", 249 "renesas,rcar-gen3-cmt1"; 250 reg = <0 0xe6148000 0 0x1004>; 251 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&cpg CPG_MOD 300>; 260 clock-names = "fck"; 261 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 262 resets = <&cpg 300>; 263 status = "disabled"; 264 }; 265 266 cpg: clock-controller@e6150000 { 267 compatible = "renesas,r8a77995-cpg-mssr"; 268 reg = <0 0xe6150000 0 0x1000>; 269 clocks = <&extal_clk>; 270 clock-names = "extal"; 271 #clock-cells = <2>; 272 #power-domain-cells = <0>; 273 #reset-cells = <1>; 274 }; 275 276 rst: reset-controller@e6160000 { 277 compatible = "renesas,r8a77995-rst"; 278 reg = <0 0xe6160000 0 0x0200>; 279 }; 280 281 sysc: system-controller@e6180000 { 282 compatible = "renesas,r8a77995-sysc"; 283 reg = <0 0xe6180000 0 0x0400>; 284 #power-domain-cells = <1>; 285 }; 286 287 thermal: thermal@e6190000 { 288 compatible = "renesas,thermal-r8a77995"; 289 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 290 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&cpg CPG_MOD 522>; 294 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 295 resets = <&cpg 522>; 296 #thermal-sensor-cells = <0>; 297 }; 298 299 intc_ex: interrupt-controller@e61c0000 { 300 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; 301 #interrupt-cells = <2>; 302 interrupt-controller; 303 reg = <0 0xe61c0000 0 0x200>; 304 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cpg CPG_MOD 407>; 311 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 312 resets = <&cpg 407>; 313 }; 314 315 tmu0: timer@e61e0000 { 316 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 317 reg = <0 0xe61e0000 0 0x30>; 318 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&cpg CPG_MOD 125>; 322 clock-names = "fck"; 323 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 324 resets = <&cpg 125>; 325 status = "disabled"; 326 }; 327 328 tmu1: timer@e6fc0000 { 329 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 330 reg = <0 0xe6fc0000 0 0x30>; 331 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&cpg CPG_MOD 124>; 335 clock-names = "fck"; 336 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 337 resets = <&cpg 124>; 338 status = "disabled"; 339 }; 340 341 tmu2: timer@e6fd0000 { 342 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 343 reg = <0 0xe6fd0000 0 0x30>; 344 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&cpg CPG_MOD 123>; 348 clock-names = "fck"; 349 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 350 resets = <&cpg 123>; 351 status = "disabled"; 352 }; 353 354 tmu3: timer@e6fe0000 { 355 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 356 reg = <0 0xe6fe0000 0 0x30>; 357 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&cpg CPG_MOD 122>; 361 clock-names = "fck"; 362 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 363 resets = <&cpg 122>; 364 status = "disabled"; 365 }; 366 367 tmu4: timer@ffc00000 { 368 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 369 reg = <0 0xffc00000 0 0x30>; 370 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&cpg CPG_MOD 121>; 374 clock-names = "fck"; 375 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 376 resets = <&cpg 121>; 377 status = "disabled"; 378 }; 379 380 i2c0: i2c@e6500000 { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 compatible = "renesas,i2c-r8a77995", 384 "renesas,rcar-gen3-i2c"; 385 reg = <0 0xe6500000 0 0x40>; 386 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&cpg CPG_MOD 931>; 388 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 389 resets = <&cpg 931>; 390 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 391 <&dmac2 0x91>, <&dmac2 0x90>; 392 dma-names = "tx", "rx", "tx", "rx"; 393 i2c-scl-internal-delay-ns = <6>; 394 status = "disabled"; 395 }; 396 397 i2c1: i2c@e6508000 { 398 #address-cells = <1>; 399 #size-cells = <0>; 400 compatible = "renesas,i2c-r8a77995", 401 "renesas,rcar-gen3-i2c"; 402 reg = <0 0xe6508000 0 0x40>; 403 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&cpg CPG_MOD 930>; 405 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 406 resets = <&cpg 930>; 407 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 408 <&dmac2 0x93>, <&dmac2 0x92>; 409 dma-names = "tx", "rx", "tx", "rx"; 410 i2c-scl-internal-delay-ns = <6>; 411 status = "disabled"; 412 }; 413 414 i2c2: i2c@e6510000 { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 compatible = "renesas,i2c-r8a77995", 418 "renesas,rcar-gen3-i2c"; 419 reg = <0 0xe6510000 0 0x40>; 420 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&cpg CPG_MOD 929>; 422 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 423 resets = <&cpg 929>; 424 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 425 <&dmac2 0x95>, <&dmac2 0x94>; 426 dma-names = "tx", "rx", "tx", "rx"; 427 i2c-scl-internal-delay-ns = <6>; 428 status = "disabled"; 429 }; 430 431 i2c3: i2c@e66d0000 { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 compatible = "renesas,i2c-r8a77995", 435 "renesas,rcar-gen3-i2c"; 436 reg = <0 0xe66d0000 0 0x40>; 437 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cpg CPG_MOD 928>; 439 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 440 resets = <&cpg 928>; 441 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 442 dma-names = "tx", "rx"; 443 i2c-scl-internal-delay-ns = <6>; 444 status = "disabled"; 445 }; 446 447 hscif0: serial@e6540000 { 448 compatible = "renesas,hscif-r8a77995", 449 "renesas,rcar-gen3-hscif", 450 "renesas,hscif"; 451 reg = <0 0xe6540000 0 0x60>; 452 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&cpg CPG_MOD 520>, 454 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 455 <&scif_clk>; 456 clock-names = "fck", "brg_int", "scif_clk"; 457 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 458 <&dmac2 0x31>, <&dmac2 0x30>; 459 dma-names = "tx", "rx", "tx", "rx"; 460 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 461 resets = <&cpg 520>; 462 status = "disabled"; 463 }; 464 465 hscif3: serial@e66a0000 { 466 compatible = "renesas,hscif-r8a77995", 467 "renesas,rcar-gen3-hscif", 468 "renesas,hscif"; 469 reg = <0 0xe66a0000 0 0x60>; 470 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&cpg CPG_MOD 517>, 472 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 473 <&scif_clk>; 474 clock-names = "fck", "brg_int", "scif_clk"; 475 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 476 dma-names = "tx", "rx"; 477 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 478 resets = <&cpg 517>; 479 status = "disabled"; 480 }; 481 482 hsusb: usb@e6590000 { 483 compatible = "renesas,usbhs-r8a77995", 484 "renesas,rcar-gen3-usbhs"; 485 reg = <0 0xe6590000 0 0x200>; 486 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 488 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 489 <&usb_dmac1 0>, <&usb_dmac1 1>; 490 dma-names = "ch0", "ch1", "ch2", "ch3"; 491 renesas,buswait = <11>; 492 phys = <&usb2_phy0 3>; 493 phy-names = "usb"; 494 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 495 resets = <&cpg 704>, <&cpg 703>; 496 status = "disabled"; 497 }; 498 499 usb_dmac0: dma-controller@e65a0000 { 500 compatible = "renesas,r8a77995-usb-dmac", 501 "renesas,usb-dmac"; 502 reg = <0 0xe65a0000 0 0x100>; 503 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-names = "ch0", "ch1"; 506 clocks = <&cpg CPG_MOD 330>; 507 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 508 resets = <&cpg 330>; 509 #dma-cells = <1>; 510 dma-channels = <2>; 511 }; 512 513 usb_dmac1: dma-controller@e65b0000 { 514 compatible = "renesas,r8a77995-usb-dmac", 515 "renesas,usb-dmac"; 516 reg = <0 0xe65b0000 0 0x100>; 517 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 519 interrupt-names = "ch0", "ch1"; 520 clocks = <&cpg CPG_MOD 331>; 521 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 522 resets = <&cpg 331>; 523 #dma-cells = <1>; 524 dma-channels = <2>; 525 }; 526 527 arm_cc630p: crypto@e6601000 { 528 compatible = "arm,cryptocell-630p-ree"; 529 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 530 reg = <0x0 0xe6601000 0 0x1000>; 531 clocks = <&cpg CPG_MOD 229>; 532 resets = <&cpg 229>; 533 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 534 }; 535 536 canfd: can@e66c0000 { 537 compatible = "renesas,r8a77995-canfd", 538 "renesas,rcar-gen3-canfd"; 539 reg = <0 0xe66c0000 0 0x8000>; 540 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&cpg CPG_MOD 914>, 543 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 544 <&can_clk>; 545 clock-names = "fck", "canfd", "can_clk"; 546 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 547 assigned-clock-rates = <40000000>; 548 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 549 resets = <&cpg 914>; 550 status = "disabled"; 551 552 channel0 { 553 status = "disabled"; 554 }; 555 556 channel1 { 557 status = "disabled"; 558 }; 559 }; 560 561 dmac0: dma-controller@e6700000 { 562 compatible = "renesas,dmac-r8a77995", 563 "renesas,rcar-dmac"; 564 reg = <0 0xe6700000 0 0x10000>; 565 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "error", 575 "ch0", "ch1", "ch2", "ch3", 576 "ch4", "ch5", "ch6", "ch7"; 577 clocks = <&cpg CPG_MOD 219>; 578 clock-names = "fck"; 579 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 580 resets = <&cpg 219>; 581 #dma-cells = <1>; 582 dma-channels = <8>; 583 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 584 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 585 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 586 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>; 587 }; 588 589 dmac1: dma-controller@e7300000 { 590 compatible = "renesas,dmac-r8a77995", 591 "renesas,rcar-dmac"; 592 reg = <0 0xe7300000 0 0x10000>; 593 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 602 interrupt-names = "error", 603 "ch0", "ch1", "ch2", "ch3", 604 "ch4", "ch5", "ch6", "ch7"; 605 clocks = <&cpg CPG_MOD 218>; 606 clock-names = "fck"; 607 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 608 resets = <&cpg 218>; 609 #dma-cells = <1>; 610 dma-channels = <8>; 611 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 612 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 613 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 614 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 615 }; 616 617 dmac2: dma-controller@e7310000 { 618 compatible = "renesas,dmac-r8a77995", 619 "renesas,rcar-dmac"; 620 reg = <0 0xe7310000 0 0x10000>; 621 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 630 interrupt-names = "error", 631 "ch0", "ch1", "ch2", "ch3", 632 "ch4", "ch5", "ch6", "ch7"; 633 clocks = <&cpg CPG_MOD 217>; 634 clock-names = "fck"; 635 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 636 resets = <&cpg 217>; 637 #dma-cells = <1>; 638 dma-channels = <8>; 639 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 640 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 641 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 642 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 643 }; 644 645 ipmmu_ds0: iommu@e6740000 { 646 compatible = "renesas,ipmmu-r8a77995"; 647 reg = <0 0xe6740000 0 0x1000>; 648 renesas,ipmmu-main = <&ipmmu_mm 0>; 649 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 650 #iommu-cells = <1>; 651 }; 652 653 ipmmu_ds1: iommu@e7740000 { 654 compatible = "renesas,ipmmu-r8a77995"; 655 reg = <0 0xe7740000 0 0x1000>; 656 renesas,ipmmu-main = <&ipmmu_mm 1>; 657 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 658 #iommu-cells = <1>; 659 }; 660 661 ipmmu_hc: iommu@e6570000 { 662 compatible = "renesas,ipmmu-r8a77995"; 663 reg = <0 0xe6570000 0 0x1000>; 664 renesas,ipmmu-main = <&ipmmu_mm 2>; 665 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 666 #iommu-cells = <1>; 667 }; 668 669 ipmmu_mm: iommu@e67b0000 { 670 compatible = "renesas,ipmmu-r8a77995"; 671 reg = <0 0xe67b0000 0 0x1000>; 672 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 674 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 675 #iommu-cells = <1>; 676 }; 677 678 ipmmu_mp: iommu@ec670000 { 679 compatible = "renesas,ipmmu-r8a77995"; 680 reg = <0 0xec670000 0 0x1000>; 681 renesas,ipmmu-main = <&ipmmu_mm 4>; 682 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 683 #iommu-cells = <1>; 684 }; 685 686 ipmmu_pv0: iommu@fd800000 { 687 compatible = "renesas,ipmmu-r8a77995"; 688 reg = <0 0xfd800000 0 0x1000>; 689 renesas,ipmmu-main = <&ipmmu_mm 6>; 690 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 691 #iommu-cells = <1>; 692 }; 693 694 ipmmu_rt: iommu@ffc80000 { 695 compatible = "renesas,ipmmu-r8a77995"; 696 reg = <0 0xffc80000 0 0x1000>; 697 renesas,ipmmu-main = <&ipmmu_mm 10>; 698 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 699 #iommu-cells = <1>; 700 }; 701 702 ipmmu_vc0: iommu@fe6b0000 { 703 compatible = "renesas,ipmmu-r8a77995"; 704 reg = <0 0xfe6b0000 0 0x1000>; 705 renesas,ipmmu-main = <&ipmmu_mm 12>; 706 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 707 #iommu-cells = <1>; 708 }; 709 710 ipmmu_vi0: iommu@febd0000 { 711 compatible = "renesas,ipmmu-r8a77995"; 712 reg = <0 0xfebd0000 0 0x1000>; 713 renesas,ipmmu-main = <&ipmmu_mm 14>; 714 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 715 #iommu-cells = <1>; 716 }; 717 718 ipmmu_vp0: iommu@fe990000 { 719 compatible = "renesas,ipmmu-r8a77995"; 720 reg = <0 0xfe990000 0 0x1000>; 721 renesas,ipmmu-main = <&ipmmu_mm 16>; 722 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 723 #iommu-cells = <1>; 724 }; 725 726 avb: ethernet@e6800000 { 727 compatible = "renesas,etheravb-r8a77995", 728 "renesas,etheravb-rcar-gen3"; 729 reg = <0 0xe6800000 0 0x800>; 730 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 755 interrupt-names = "ch0", "ch1", "ch2", "ch3", 756 "ch4", "ch5", "ch6", "ch7", 757 "ch8", "ch9", "ch10", "ch11", 758 "ch12", "ch13", "ch14", "ch15", 759 "ch16", "ch17", "ch18", "ch19", 760 "ch20", "ch21", "ch22", "ch23", 761 "ch24"; 762 clocks = <&cpg CPG_MOD 812>; 763 clock-names = "fck"; 764 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 765 resets = <&cpg 812>; 766 phy-mode = "rgmii"; 767 rx-internal-delay-ps = <1800>; 768 iommus = <&ipmmu_ds0 16>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 status = "disabled"; 772 }; 773 774 can0: can@e6c30000 { 775 compatible = "renesas,can-r8a77995", 776 "renesas,rcar-gen3-can"; 777 reg = <0 0xe6c30000 0 0x1000>; 778 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&cpg CPG_MOD 916>, 780 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 781 <&can_clk>; 782 clock-names = "clkp1", "clkp2", "can_clk"; 783 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 784 assigned-clock-rates = <40000000>; 785 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 786 resets = <&cpg 916>; 787 status = "disabled"; 788 }; 789 790 can1: can@e6c38000 { 791 compatible = "renesas,can-r8a77995", 792 "renesas,rcar-gen3-can"; 793 reg = <0 0xe6c38000 0 0x1000>; 794 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&cpg CPG_MOD 915>, 796 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 797 <&can_clk>; 798 clock-names = "clkp1", "clkp2", "can_clk"; 799 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 800 assigned-clock-rates = <40000000>; 801 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 802 resets = <&cpg 915>; 803 status = "disabled"; 804 }; 805 806 pwm0: pwm@e6e30000 { 807 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 808 reg = <0 0xe6e30000 0 0x8>; 809 #pwm-cells = <2>; 810 clocks = <&cpg CPG_MOD 523>; 811 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 812 resets = <&cpg 523>; 813 status = "disabled"; 814 }; 815 816 pwm1: pwm@e6e31000 { 817 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 818 reg = <0 0xe6e31000 0 0x8>; 819 #pwm-cells = <2>; 820 clocks = <&cpg CPG_MOD 523>; 821 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 822 resets = <&cpg 523>; 823 status = "disabled"; 824 }; 825 826 pwm2: pwm@e6e32000 { 827 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 828 reg = <0 0xe6e32000 0 0x8>; 829 #pwm-cells = <2>; 830 clocks = <&cpg CPG_MOD 523>; 831 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 832 resets = <&cpg 523>; 833 status = "disabled"; 834 }; 835 836 pwm3: pwm@e6e33000 { 837 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 838 reg = <0 0xe6e33000 0 0x8>; 839 #pwm-cells = <2>; 840 clocks = <&cpg CPG_MOD 523>; 841 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 842 resets = <&cpg 523>; 843 status = "disabled"; 844 }; 845 846 scif0: serial@e6e60000 { 847 compatible = "renesas,scif-r8a77995", 848 "renesas,rcar-gen3-scif", "renesas,scif"; 849 reg = <0 0xe6e60000 0 64>; 850 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&cpg CPG_MOD 207>, 852 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 853 <&scif_clk>; 854 clock-names = "fck", "brg_int", "scif_clk"; 855 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 856 <&dmac2 0x51>, <&dmac2 0x50>; 857 dma-names = "tx", "rx", "tx", "rx"; 858 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 859 resets = <&cpg 207>; 860 status = "disabled"; 861 }; 862 863 scif1: serial@e6e68000 { 864 compatible = "renesas,scif-r8a77995", 865 "renesas,rcar-gen3-scif", "renesas,scif"; 866 reg = <0 0xe6e68000 0 64>; 867 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cpg CPG_MOD 206>, 869 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 870 <&scif_clk>; 871 clock-names = "fck", "brg_int", "scif_clk"; 872 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 873 <&dmac2 0x53>, <&dmac2 0x52>; 874 dma-names = "tx", "rx", "tx", "rx"; 875 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 876 resets = <&cpg 206>; 877 status = "disabled"; 878 }; 879 880 scif2: serial@e6e88000 { 881 compatible = "renesas,scif-r8a77995", 882 "renesas,rcar-gen3-scif", "renesas,scif"; 883 reg = <0 0xe6e88000 0 64>; 884 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&cpg CPG_MOD 310>, 886 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 887 <&scif_clk>; 888 clock-names = "fck", "brg_int", "scif_clk"; 889 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 890 <&dmac2 0x13>, <&dmac2 0x12>; 891 dma-names = "tx", "rx", "tx", "rx"; 892 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 893 resets = <&cpg 310>; 894 status = "disabled"; 895 }; 896 897 scif3: serial@e6c50000 { 898 compatible = "renesas,scif-r8a77995", 899 "renesas,rcar-gen3-scif", "renesas,scif"; 900 reg = <0 0xe6c50000 0 64>; 901 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&cpg CPG_MOD 204>, 903 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 904 <&scif_clk>; 905 clock-names = "fck", "brg_int", "scif_clk"; 906 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 907 dma-names = "tx", "rx"; 908 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 909 resets = <&cpg 204>; 910 status = "disabled"; 911 }; 912 913 scif4: serial@e6c40000 { 914 compatible = "renesas,scif-r8a77995", 915 "renesas,rcar-gen3-scif", "renesas,scif"; 916 reg = <0 0xe6c40000 0 64>; 917 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&cpg CPG_MOD 203>, 919 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 920 <&scif_clk>; 921 clock-names = "fck", "brg_int", "scif_clk"; 922 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 923 dma-names = "tx", "rx"; 924 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 925 resets = <&cpg 203>; 926 status = "disabled"; 927 }; 928 929 scif5: serial@e6f30000 { 930 compatible = "renesas,scif-r8a77995", 931 "renesas,rcar-gen3-scif", "renesas,scif"; 932 reg = <0 0xe6f30000 0 64>; 933 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&cpg CPG_MOD 202>, 935 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 936 <&scif_clk>; 937 clock-names = "fck", "brg_int", "scif_clk"; 938 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 939 <&dmac2 0x5b>, <&dmac2 0x5a>; 940 dma-names = "tx", "rx", "tx", "rx"; 941 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 942 resets = <&cpg 202>; 943 status = "disabled"; 944 }; 945 946 msiof0: spi@e6e90000 { 947 compatible = "renesas,msiof-r8a77995", 948 "renesas,rcar-gen3-msiof"; 949 reg = <0 0xe6e90000 0 0x64>; 950 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&cpg CPG_MOD 211>; 952 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 953 <&dmac2 0x41>, <&dmac2 0x40>; 954 dma-names = "tx", "rx", "tx", "rx"; 955 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 956 resets = <&cpg 211>; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 status = "disabled"; 960 }; 961 962 msiof1: spi@e6ea0000 { 963 compatible = "renesas,msiof-r8a77995", 964 "renesas,rcar-gen3-msiof"; 965 reg = <0 0xe6ea0000 0 0x64>; 966 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&cpg CPG_MOD 210>; 968 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 969 <&dmac2 0x43>, <&dmac2 0x42>; 970 dma-names = "tx", "rx", "tx", "rx"; 971 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 972 resets = <&cpg 210>; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 status = "disabled"; 976 }; 977 978 msiof2: spi@e6c00000 { 979 compatible = "renesas,msiof-r8a77995", 980 "renesas,rcar-gen3-msiof"; 981 reg = <0 0xe6c00000 0 0x64>; 982 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&cpg CPG_MOD 209>; 984 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 985 dma-names = "tx", "rx"; 986 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 987 resets = <&cpg 209>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 status = "disabled"; 991 }; 992 993 msiof3: spi@e6c10000 { 994 compatible = "renesas,msiof-r8a77995", 995 "renesas,rcar-gen3-msiof"; 996 reg = <0 0xe6c10000 0 0x64>; 997 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&cpg CPG_MOD 208>; 999 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1000 dma-names = "tx", "rx"; 1001 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1002 resets = <&cpg 208>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 status = "disabled"; 1006 }; 1007 1008 vin4: video@e6ef4000 { 1009 compatible = "renesas,vin-r8a77995"; 1010 reg = <0 0xe6ef4000 0 0x1000>; 1011 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&cpg CPG_MOD 807>; 1013 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1014 resets = <&cpg 807>; 1015 renesas,id = <4>; 1016 status = "disabled"; 1017 }; 1018 1019 ohci0: usb@ee080000 { 1020 compatible = "generic-ohci"; 1021 reg = <0 0xee080000 0 0x100>; 1022 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1024 phys = <&usb2_phy0 1>; 1025 phy-names = "usb"; 1026 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1027 resets = <&cpg 703>, <&cpg 704>; 1028 status = "disabled"; 1029 }; 1030 1031 ehci0: usb@ee080100 { 1032 compatible = "generic-ehci"; 1033 reg = <0 0xee080100 0 0x100>; 1034 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1036 phys = <&usb2_phy0 2>; 1037 phy-names = "usb"; 1038 companion = <&ohci0>; 1039 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1040 resets = <&cpg 703>, <&cpg 704>; 1041 status = "disabled"; 1042 }; 1043 1044 usb2_phy0: usb-phy@ee080200 { 1045 compatible = "renesas,usb2-phy-r8a77995", 1046 "renesas,rcar-gen3-usb2-phy"; 1047 reg = <0 0xee080200 0 0x700>; 1048 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1050 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1051 resets = <&cpg 703>, <&cpg 704>; 1052 #phy-cells = <1>; 1053 status = "disabled"; 1054 }; 1055 1056 sdhi2: mmc@ee140000 { 1057 compatible = "renesas,sdhi-r8a77995", 1058 "renesas,rcar-gen3-sdhi"; 1059 reg = <0 0xee140000 0 0x2000>; 1060 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1061 clocks = <&cpg CPG_MOD 312>; 1062 max-frequency = <200000000>; 1063 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1064 resets = <&cpg 312>; 1065 iommus = <&ipmmu_ds1 34>; 1066 status = "disabled"; 1067 }; 1068 1069 gic: interrupt-controller@f1010000 { 1070 compatible = "arm,gic-400"; 1071 #interrupt-cells = <3>; 1072 #address-cells = <0>; 1073 interrupt-controller; 1074 reg = <0x0 0xf1010000 0 0x1000>, 1075 <0x0 0xf1020000 0 0x20000>, 1076 <0x0 0xf1040000 0 0x20000>, 1077 <0x0 0xf1060000 0 0x20000>; 1078 interrupts = <GIC_PPI 9 1079 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 1080 clocks = <&cpg CPG_MOD 408>; 1081 clock-names = "clk"; 1082 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1083 resets = <&cpg 408>; 1084 }; 1085 1086 vspbs: vsp@fe960000 { 1087 compatible = "renesas,vsp2"; 1088 reg = <0 0xfe960000 0 0x8000>; 1089 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&cpg CPG_MOD 627>; 1091 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1092 resets = <&cpg 627>; 1093 renesas,fcp = <&fcpvb0>; 1094 }; 1095 1096 vspd0: vsp@fea20000 { 1097 compatible = "renesas,vsp2"; 1098 reg = <0 0xfea20000 0 0x5000>; 1099 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&cpg CPG_MOD 623>; 1101 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1102 resets = <&cpg 623>; 1103 renesas,fcp = <&fcpvd0>; 1104 }; 1105 1106 vspd1: vsp@fea28000 { 1107 compatible = "renesas,vsp2"; 1108 reg = <0 0xfea28000 0 0x5000>; 1109 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&cpg CPG_MOD 622>; 1111 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1112 resets = <&cpg 622>; 1113 renesas,fcp = <&fcpvd1>; 1114 }; 1115 1116 fcpvb0: fcp@fe96f000 { 1117 compatible = "renesas,fcpv"; 1118 reg = <0 0xfe96f000 0 0x200>; 1119 clocks = <&cpg CPG_MOD 607>; 1120 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1121 resets = <&cpg 607>; 1122 iommus = <&ipmmu_vp0 5>; 1123 }; 1124 1125 fcpvd0: fcp@fea27000 { 1126 compatible = "renesas,fcpv"; 1127 reg = <0 0xfea27000 0 0x200>; 1128 clocks = <&cpg CPG_MOD 603>; 1129 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1130 resets = <&cpg 603>; 1131 iommus = <&ipmmu_vi0 8>; 1132 }; 1133 1134 fcpvd1: fcp@fea2f000 { 1135 compatible = "renesas,fcpv"; 1136 reg = <0 0xfea2f000 0 0x200>; 1137 clocks = <&cpg CPG_MOD 602>; 1138 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1139 resets = <&cpg 602>; 1140 iommus = <&ipmmu_vi0 9>; 1141 }; 1142 1143 cmm0: cmm@fea40000 { 1144 compatible = "renesas,r8a77995-cmm", 1145 "renesas,rcar-gen3-cmm"; 1146 reg = <0 0xfea40000 0 0x1000>; 1147 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1148 clocks = <&cpg CPG_MOD 711>; 1149 resets = <&cpg 711>; 1150 }; 1151 1152 cmm1: cmm@fea50000 { 1153 compatible = "renesas,r8a77995-cmm", 1154 "renesas,rcar-gen3-cmm"; 1155 reg = <0 0xfea50000 0 0x1000>; 1156 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1157 clocks = <&cpg CPG_MOD 710>; 1158 resets = <&cpg 710>; 1159 }; 1160 1161 du: display@feb00000 { 1162 compatible = "renesas,du-r8a77995"; 1163 reg = <0 0xfeb00000 0 0x40000>; 1164 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1166 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1167 clock-names = "du.0", "du.1"; 1168 resets = <&cpg 724>; 1169 reset-names = "du.0"; 1170 1171 renesas,cmms = <&cmm0>, <&cmm1>; 1172 renesas,vsps = <&vspd0 0>, <&vspd1 0>; 1173 1174 status = "disabled"; 1175 1176 ports { 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 1180 port@0 { 1181 reg = <0>; 1182 du_out_rgb: endpoint { 1183 }; 1184 }; 1185 1186 port@1 { 1187 reg = <1>; 1188 du_out_lvds0: endpoint { 1189 remote-endpoint = <&lvds0_in>; 1190 }; 1191 }; 1192 1193 port@2 { 1194 reg = <2>; 1195 du_out_lvds1: endpoint { 1196 remote-endpoint = <&lvds1_in>; 1197 }; 1198 }; 1199 }; 1200 }; 1201 1202 lvds0: lvds-encoder@feb90000 { 1203 compatible = "renesas,r8a77995-lvds"; 1204 reg = <0 0xfeb90000 0 0x20>; 1205 clocks = <&cpg CPG_MOD 727>; 1206 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1207 resets = <&cpg 727>; 1208 status = "disabled"; 1209 1210 renesas,companion = <&lvds1>; 1211 1212 ports { 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 1216 port@0 { 1217 reg = <0>; 1218 lvds0_in: endpoint { 1219 remote-endpoint = <&du_out_lvds0>; 1220 }; 1221 }; 1222 1223 port@1 { 1224 reg = <1>; 1225 lvds0_out: endpoint { 1226 }; 1227 }; 1228 }; 1229 }; 1230 1231 lvds1: lvds-encoder@feb90100 { 1232 compatible = "renesas,r8a77995-lvds"; 1233 reg = <0 0xfeb90100 0 0x20>; 1234 clocks = <&cpg CPG_MOD 727>; 1235 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1236 resets = <&cpg 726>; 1237 status = "disabled"; 1238 1239 ports { 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 1243 port@0 { 1244 reg = <0>; 1245 lvds1_in: endpoint { 1246 remote-endpoint = <&du_out_lvds1>; 1247 }; 1248 }; 1249 1250 port@1 { 1251 reg = <1>; 1252 lvds1_out: endpoint { 1253 }; 1254 }; 1255 }; 1256 }; 1257 1258 prr: chipid@fff00044 { 1259 compatible = "renesas,prr"; 1260 reg = <0 0xfff00044 0 4>; 1261 }; 1262 }; 1263 1264 thermal-zones { 1265 cpu_thermal: cpu-thermal { 1266 polling-delay-passive = <250>; 1267 polling-delay = <1000>; 1268 thermal-sensors = <&thermal>; 1269 1270 cooling-maps { 1271 }; 1272 1273 trips { 1274 cpu-crit { 1275 temperature = <120000>; 1276 hysteresis = <2000>; 1277 type = "critical"; 1278 }; 1279 }; 1280 }; 1281 }; 1282 1283 timer { 1284 compatible = "arm,armv8-timer"; 1285 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1286 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1287 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1288 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 1289 }; 1290}; 1291