1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Draak board with R-Car D3
4 *
5 * Copyright (C) 2016-2018 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba
7 */
8
9/dts-v1/;
10#include "r8a77995.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13
14/ {
15	model = "Renesas Draak board based on r8a77995";
16	compatible = "renesas,draak", "renesas,r8a77995";
17
18	aliases {
19		serial0 = &scif2;
20		ethernet0 = &avb;
21	};
22
23	audio_clkout: audio-clkout {
24		/*
25		 * This is same as <&rcar_sound 0>
26		 * but needed to avoid cs2000/rcar_sound probe dead-lock
27		 */
28		compatible = "fixed-clock";
29		#clock-cells = <0>;
30		clock-frequency = <12288000>;
31	};
32
33	backlight: backlight {
34		compatible = "pwm-backlight";
35		pwms = <&pwm1 0 50000>;
36
37		brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
38		default-brightness-level = <10>;
39
40		power-supply = <&reg_12p0v>;
41		enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
42	};
43
44	chosen {
45		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
46		stdout-path = "serial0:115200n8";
47	};
48
49	composite-in {
50		compatible = "composite-video-connector";
51
52		port {
53			composite_con_in: endpoint {
54				remote-endpoint = <&adv7180_in>;
55			};
56		};
57	};
58
59	hdmi-in {
60		compatible = "hdmi-connector";
61		type = "a";
62
63		port {
64			hdmi_con_in: endpoint {
65				remote-endpoint = <&adv7612_in>;
66			};
67		};
68	};
69
70	hdmi-out {
71		compatible = "hdmi-connector";
72		type = "a";
73
74		port {
75			hdmi_con_out: endpoint {
76				remote-endpoint = <&adv7511_out>;
77			};
78		};
79	};
80
81	keys {
82		compatible = "gpio-keys";
83
84		pinctrl-0 = <&keys_pins>;
85		pinctrl-names = "default";
86
87		key-1 {
88			gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
89			linux,code = <KEY_1>;
90			label = "SW56-1";
91			wakeup-source;
92			debounce-interval = <20>;
93		};
94		key-2 {
95			gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
96			linux,code = <KEY_2>;
97			label = "SW56-2";
98			wakeup-source;
99			debounce-interval = <20>;
100		};
101		key-3 {
102			gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
103			linux,code = <KEY_3>;
104			label = "SW56-3";
105			wakeup-source;
106			debounce-interval = <20>;
107		};
108		key-4 {
109			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
110			linux,code = <KEY_4>;
111			label = "SW56-4";
112			wakeup-source;
113			debounce-interval = <20>;
114		};
115	};
116
117	lvds-decoder {
118		compatible = "thine,thc63lvd1024";
119		vcc-supply = <&reg_3p3v>;
120
121		ports {
122			#address-cells = <1>;
123			#size-cells = <0>;
124
125			port@0 {
126				reg = <0>;
127				thc63lvd1024_in: endpoint {
128					remote-endpoint = <&lvds0_out>;
129				};
130			};
131
132			port@2 {
133				reg = <2>;
134				thc63lvd1024_out: endpoint {
135					remote-endpoint = <&adv7511_in>;
136				};
137			};
138		};
139	};
140
141	memory@48000000 {
142		device_type = "memory";
143		/* first 128MB is reserved for secure area. */
144		reg = <0x0 0x48000000 0x0 0x18000000>;
145	};
146
147	reg_1p8v: regulator-1p8v {
148		compatible = "regulator-fixed";
149		regulator-name = "fixed-1.8V";
150		regulator-min-microvolt = <1800000>;
151		regulator-max-microvolt = <1800000>;
152		regulator-boot-on;
153		regulator-always-on;
154	};
155
156	reg_3p3v: regulator-3p3v {
157		compatible = "regulator-fixed";
158		regulator-name = "fixed-3.3V";
159		regulator-min-microvolt = <3300000>;
160		regulator-max-microvolt = <3300000>;
161		regulator-boot-on;
162		regulator-always-on;
163	};
164
165	reg_12p0v: regulator-12p0v {
166		compatible = "regulator-fixed";
167		regulator-name = "D12.0V";
168		regulator-min-microvolt = <12000000>;
169		regulator-max-microvolt = <12000000>;
170		regulator-boot-on;
171		regulator-always-on;
172	};
173
174	sound_card: sound {
175		compatible = "audio-graph-card";
176
177		dais = <&rsnd_port0	/* ak4613 */
178			/* HDMI is not yet supported */
179		>;
180	};
181
182	vga {
183		compatible = "vga-connector";
184
185		port {
186			vga_in: endpoint {
187				remote-endpoint = <&adv7123_out>;
188			};
189		};
190	};
191
192	vga-encoder {
193		compatible = "adi,adv7123";
194
195		ports {
196			#address-cells = <1>;
197			#size-cells = <0>;
198
199			port@0 {
200				reg = <0>;
201				adv7123_in: endpoint {
202					remote-endpoint = <&du_out_rgb>;
203				};
204			};
205			port@1 {
206				reg = <1>;
207				adv7123_out: endpoint {
208					remote-endpoint = <&vga_in>;
209				};
210			};
211		};
212	};
213
214	x12_clk: x12 {
215		compatible = "fixed-clock";
216		#clock-cells = <0>;
217		clock-frequency = <74250000>;
218	};
219
220	x19_clk: x19 {
221		compatible = "fixed-clock";
222		#clock-cells = <0>;
223		clock-frequency = <24576000>;
224	};
225};
226
227&audio_clk_b {
228	/*
229	 * X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
230	 * and R-Car Sound uses AUDIO_CLKB.
231	 * Note is that schematic indicates VI4_FIELD conection only
232	 * not AUDIO_CLKB at SoC page.
233	 * And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
234	 * SW60 should be 1-2.
235	 */
236
237	clock-frequency = <22579200>;
238};
239
240&avb {
241	pinctrl-0 = <&avb0_pins>;
242	pinctrl-names = "default";
243	renesas,no-ether-link;
244	phy-handle = <&phy0>;
245	status = "okay";
246
247	phy0: ethernet-phy@0 {
248		rxc-skew-ps = <1500>;
249		reg = <0>;
250		interrupt-parent = <&gpio5>;
251		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
252		/*
253		 * TX clock internal delay mode is required for reliable
254		 * 1Gbps communication using the KSZ9031RNX phy present on
255		 * the Draak board, however, TX clock internal delay mode
256		 * isn't supported on r8a77995.  Thus, limit speed to
257		 * 100Mbps for reliable communication.
258		 */
259		max-speed = <100>;
260	};
261};
262
263&can0 {
264	pinctrl-0 = <&can0_pins>;
265	pinctrl-names = "default";
266	status = "okay";
267};
268
269&can1 {
270	pinctrl-0 = <&can1_pins>;
271	pinctrl-names = "default";
272	status = "okay";
273};
274
275&du {
276	pinctrl-0 = <&du_pins>;
277	pinctrl-names = "default";
278	status = "okay";
279
280	clocks = <&cpg CPG_MOD 724>,
281		 <&cpg CPG_MOD 723>,
282		 <&x12_clk>;
283	clock-names = "du.0", "du.1", "dclkin.0";
284
285	ports {
286		port@0 {
287			endpoint {
288				remote-endpoint = <&adv7123_in>;
289			};
290		};
291	};
292};
293
294&ehci0 {
295	dr_mode = "host";
296	status = "okay";
297};
298
299&extal_clk {
300	clock-frequency = <48000000>;
301};
302
303&hsusb {
304	dr_mode = "host";
305	status = "okay";
306};
307
308&i2c0 {
309	pinctrl-0 = <&i2c0_pins>;
310	pinctrl-names = "default";
311	status = "okay";
312
313	ak4613: codec@10 {
314		compatible = "asahi-kasei,ak4613";
315		#sound-dai-cells = <0>;
316		reg = <0x10>;
317		clocks = <&rcar_sound 0>; /* audio_clkout */
318
319		asahi-kasei,in1-single-end;
320		asahi-kasei,in2-single-end;
321		asahi-kasei,out1-single-end;
322		asahi-kasei,out2-single-end;
323		asahi-kasei,out3-single-end;
324		asahi-kasei,out4-single-end;
325		asahi-kasei,out5-single-end;
326		asahi-kasei,out6-single-end;
327
328		port {
329			ak4613_endpoint: endpoint {
330				remote-endpoint = <&rsnd_for_ak4613>;
331			};
332		};
333	};
334
335	composite-in@20 {
336		compatible = "adi,adv7180cp";
337		reg = <0x20>;
338
339		ports {
340			#address-cells = <1>;
341			#size-cells = <0>;
342
343			port@0 {
344				reg = <0>;
345				adv7180_in: endpoint {
346					remote-endpoint = <&composite_con_in>;
347				};
348			};
349
350			port@3 {
351				reg = <3>;
352
353				/*
354				 * The VIN4 video input path is shared between
355				 * CVBS and HDMI inputs through SW[49-53]
356				 * switches.
357				 *
358				 * CVBS is the default selection, link it to
359				 * VIN4 here.
360				 */
361				adv7180_out: endpoint {
362					remote-endpoint = <&vin4_in>;
363				};
364			};
365		};
366
367	};
368
369	hdmi-encoder@39 {
370		compatible = "adi,adv7511w";
371		reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
372		reg-names = "main", "edid", "cec", "packet";
373		interrupt-parent = <&gpio1>;
374		interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
375
376		adi,input-depth = <8>;
377		adi,input-colorspace = "rgb";
378		adi,input-clock = "1x";
379
380		ports {
381			#address-cells = <1>;
382			#size-cells = <0>;
383
384			port@0 {
385				reg = <0>;
386				adv7511_in: endpoint {
387					remote-endpoint = <&thc63lvd1024_out>;
388				};
389			};
390
391			port@1 {
392				reg = <1>;
393				adv7511_out: endpoint {
394					remote-endpoint = <&hdmi_con_out>;
395				};
396			};
397		};
398	};
399
400	hdmi-decoder@4c {
401		compatible = "adi,adv7612";
402		reg = <0x4c>;
403		default-input = <0>;
404
405		ports {
406			#address-cells = <1>;
407			#size-cells = <0>;
408
409			port@0 {
410				reg = <0>;
411
412				adv7612_in: endpoint {
413					remote-endpoint = <&hdmi_con_in>;
414				};
415			};
416
417			port@2 {
418				reg = <2>;
419
420				/*
421				 * The VIN4 video input path is shared between
422				 * CVBS and HDMI inputs through SW[49-53]
423				 * switches.
424				 *
425				 * CVBS is the default selection, leave HDMI
426				 * not connected here.
427				 */
428				adv7612_out: endpoint {
429					pclk-sample = <0>;
430					hsync-active = <0>;
431					vsync-active = <0>;
432				};
433			};
434		};
435	};
436
437	cs2000: clk-multiplier@4f {
438		#clock-cells = <0>;
439		compatible = "cirrus,cs2000-cp";
440		reg = <0x4f>;
441		clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */
442		clock-names = "clk_in", "ref_clk";
443
444		assigned-clocks = <&cs2000>;
445		assigned-clock-rates = <24576000>; /* 1/1 divide */
446	};
447
448	eeprom@50 {
449		compatible = "rohm,br24t01", "atmel,24c01";
450		reg = <0x50>;
451		pagesize = <8>;
452	};
453};
454
455&i2c1 {
456	pinctrl-0 = <&i2c1_pins>;
457	pinctrl-names = "default";
458	status = "okay";
459};
460
461&lvds0 {
462	status = "okay";
463
464	clocks = <&cpg CPG_MOD 727>,
465		 <&x12_clk>,
466		 <&extal_clk>;
467	clock-names = "fck", "dclkin.0", "extal";
468
469	ports {
470		port@1 {
471			lvds0_out: endpoint {
472				remote-endpoint = <&thc63lvd1024_in>;
473			};
474		};
475	};
476};
477
478&lvds1 {
479	/*
480	 * Even though the LVDS1 output is not connected, the encoder must be
481	 * enabled to supply a pixel clock to the DU for the DPAD output when
482	 * LVDS0 is in use.
483	 */
484	status = "okay";
485
486	clocks = <&cpg CPG_MOD 727>,
487		 <&x12_clk>,
488		 <&extal_clk>;
489	clock-names = "fck", "dclkin.0", "extal";
490};
491
492&ohci0 {
493	dr_mode = "host";
494	status = "okay";
495};
496
497&pfc {
498	avb0_pins: avb {
499		groups = "avb0_link", "avb0_mdio", "avb0_mii";
500		function = "avb0";
501	};
502
503	can0_pins: can0 {
504		groups = "can0_data_a";
505		function = "can0";
506	};
507
508	can1_pins: can1 {
509		groups = "can1_data_a";
510		function = "can1";
511	};
512
513	du_pins: du {
514		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
515		function = "du";
516	};
517
518	i2c0_pins: i2c0 {
519		groups = "i2c0";
520		function = "i2c0";
521	};
522
523	i2c1_pins: i2c1 {
524		groups = "i2c1";
525		function = "i2c1";
526	};
527
528	keys_pins: keys {
529		pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15";
530		bias-pull-up;
531	};
532
533	pwm0_pins: pwm0 {
534		groups = "pwm0_c";
535		function = "pwm0";
536	};
537
538	pwm1_pins: pwm1 {
539		groups = "pwm1_c";
540		function = "pwm1";
541	};
542
543	scif2_pins: scif2 {
544		groups = "scif2_data";
545		function = "scif2";
546	};
547
548	sdhi2_pins: sd2 {
549		groups = "mmc_data8", "mmc_ctrl";
550		function = "mmc";
551		power-source = <1800>;
552	};
553
554	sdhi2_pins_uhs: sd2_uhs {
555		groups = "mmc_data8", "mmc_ctrl";
556		function = "mmc";
557		power-source = <1800>;
558	};
559
560	sound_pins: sound {
561		groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a";
562		function = "ssi";
563	};
564
565	sound_clk_pins: sound-clk {
566		groups = "audio_clk_a", "audio_clk_b",
567			 "audio_clkout", "audio_clkout1";
568		function = "audio_clk";
569	};
570
571	usb0_pins: usb0 {
572		groups = "usb0";
573		function = "usb0";
574	};
575
576	vin4_pins_cvbs: vin4 {
577		groups = "vin4_data8", "vin4_sync", "vin4_clk";
578		function = "vin4";
579	};
580};
581
582&pwm0 {
583	pinctrl-0 = <&pwm0_pins>;
584	pinctrl-names = "default";
585
586	status = "okay";
587};
588
589&pwm1 {
590	pinctrl-0 = <&pwm1_pins>;
591	pinctrl-names = "default";
592
593	status = "okay";
594};
595
596&rcar_sound {
597	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
598	pinctrl-names = "default";
599
600	/* Single DAI */
601	#sound-dai-cells = <0>;
602
603	/* audio_clkout0/1 */
604	#clock-cells = <1>;
605	clock-frequency = <12288000 11289600>;
606
607	status = "okay";
608
609	clocks = <&cpg CPG_MOD 1005>,
610		 <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
611		 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
612		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
613		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
614		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
615		 <&cs2000>, <&audio_clk_b>,
616		 <&cpg CPG_CORE R8A77995_CLK_ZA2>;
617
618	ports {
619		rsnd_port0: port {
620			rsnd_for_ak4613: endpoint {
621				remote-endpoint = <&ak4613_endpoint>;
622				dai-format = "left_j";
623				bitclock-master = <&rsnd_for_ak4613>;
624				frame-master = <&rsnd_for_ak4613>;
625				playback = <&ssi3>, <&src5>, <&dvc0>;
626				capture  = <&ssi4>, <&src6>, <&dvc1>;
627			};
628		};
629	};
630};
631
632&rwdt {
633	timeout-sec = <60>;
634	status = "okay";
635};
636
637&scif2 {
638	pinctrl-0 = <&scif2_pins>;
639	pinctrl-names = "default";
640
641	status = "okay";
642};
643
644&sdhi2 {
645	/* used for on-board eMMC */
646	pinctrl-0 = <&sdhi2_pins>;
647	pinctrl-1 = <&sdhi2_pins_uhs>;
648	pinctrl-names = "default", "state_uhs";
649
650	vmmc-supply = <&reg_3p3v>;
651	vqmmc-supply = <&reg_1p8v>;
652	bus-width = <8>;
653	mmc-hs200-1_8v;
654	no-sd;
655	no-sdio;
656	non-removable;
657	status = "okay";
658};
659
660&ssi4 {
661	shared-pin;
662};
663
664&usb2_phy0 {
665	pinctrl-0 = <&usb0_pins>;
666	pinctrl-names = "default";
667
668	renesas,no-otg-pins;
669	status = "okay";
670};
671
672&vin4 {
673	pinctrl-0 = <&vin4_pins_cvbs>;
674	pinctrl-names = "default";
675
676	status = "okay";
677
678	ports {
679		port {
680			vin4_in: endpoint {
681				remote-endpoint = <&adv7180_out>;
682			};
683		};
684	};
685};
686