1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Draak board
4 *
5 * Copyright (C) 2016-2018 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba
7 */
8
9/dts-v1/;
10#include "r8a77995.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14	model = "Renesas Draak board based on r8a77995";
15	compatible = "renesas,draak", "renesas,r8a77995";
16
17	aliases {
18		serial0 = &scif2;
19		ethernet0 = &avb;
20	};
21
22	chosen {
23		bootargs = "ignore_loglevel";
24		stdout-path = "serial0:115200n8";
25	};
26
27	backlight: backlight {
28		compatible = "pwm-backlight";
29		pwms = <&pwm1 0 50000>;
30
31		brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
32		default-brightness-level = <10>;
33
34		power-supply = <&reg_12p0v>;
35		enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
36	};
37
38	composite-in {
39		compatible = "composite-video-connector";
40
41		port {
42			composite_con_in: endpoint {
43				remote-endpoint = <&adv7180_in>;
44			};
45		};
46	};
47
48	hdmi-in {
49		compatible = "hdmi-connector";
50		type = "a";
51
52		port {
53			hdmi_con_in: endpoint {
54				remote-endpoint = <&adv7612_in>;
55			};
56		};
57	};
58
59	hdmi-out {
60		compatible = "hdmi-connector";
61		type = "a";
62
63		port {
64			hdmi_con_out: endpoint {
65				remote-endpoint = <&adv7511_out>;
66			};
67		};
68	};
69
70	lvds-decoder {
71		compatible = "thine,thc63lvd1024";
72		vcc-supply = <&reg_3p3v>;
73
74		ports {
75			#address-cells = <1>;
76			#size-cells = <0>;
77
78			port@0 {
79				reg = <0>;
80				thc63lvd1024_in: endpoint {
81					remote-endpoint = <&lvds0_out>;
82				};
83			};
84
85			port@2 {
86				reg = <2>;
87				thc63lvd1024_out: endpoint {
88					remote-endpoint = <&adv7511_in>;
89				};
90			};
91		};
92	};
93
94	memory@48000000 {
95		device_type = "memory";
96		/* first 128MB is reserved for secure area. */
97		reg = <0x0 0x48000000 0x0 0x18000000>;
98	};
99
100	reg_1p8v: regulator0 {
101		compatible = "regulator-fixed";
102		regulator-name = "fixed-1.8V";
103		regulator-min-microvolt = <1800000>;
104		regulator-max-microvolt = <1800000>;
105		regulator-boot-on;
106		regulator-always-on;
107	};
108
109	reg_3p3v: regulator1 {
110		compatible = "regulator-fixed";
111		regulator-name = "fixed-3.3V";
112		regulator-min-microvolt = <3300000>;
113		regulator-max-microvolt = <3300000>;
114		regulator-boot-on;
115		regulator-always-on;
116	};
117
118	reg_12p0v: regulator1 {
119		compatible = "regulator-fixed";
120		regulator-name = "D12.0V";
121		regulator-min-microvolt = <12000000>;
122		regulator-max-microvolt = <12000000>;
123		regulator-boot-on;
124		regulator-always-on;
125	};
126
127	vga {
128		compatible = "vga-connector";
129
130		port {
131			vga_in: endpoint {
132				remote-endpoint = <&adv7123_out>;
133			};
134		};
135	};
136
137	vga-encoder {
138		compatible = "adi,adv7123";
139
140		ports {
141			#address-cells = <1>;
142			#size-cells = <0>;
143
144			port@0 {
145				reg = <0>;
146				adv7123_in: endpoint {
147					remote-endpoint = <&du_out_rgb>;
148				};
149			};
150			port@1 {
151				reg = <1>;
152				adv7123_out: endpoint {
153					remote-endpoint = <&vga_in>;
154				};
155			};
156		};
157	};
158
159	x12_clk: x12 {
160		compatible = "fixed-clock";
161		#clock-cells = <0>;
162		clock-frequency = <74250000>;
163	};
164};
165
166&avb {
167	pinctrl-0 = <&avb0_pins>;
168	pinctrl-names = "default";
169	renesas,no-ether-link;
170	phy-handle = <&phy0>;
171	phy-mode = "rgmii-txid";
172	status = "okay";
173
174	phy0: ethernet-phy@0 {
175		rxc-skew-ps = <1500>;
176		reg = <0>;
177		interrupt-parent = <&gpio5>;
178		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
179	};
180};
181
182&du {
183	pinctrl-0 = <&du_pins>;
184	pinctrl-names = "default";
185	status = "okay";
186
187	clocks = <&cpg CPG_MOD 724>,
188		 <&cpg CPG_MOD 723>,
189		 <&x12_clk>;
190	clock-names = "du.0", "du.1", "dclkin.0";
191
192	ports {
193		port@0 {
194			endpoint {
195				remote-endpoint = <&adv7123_in>;
196			};
197		};
198	};
199};
200
201&ehci0 {
202	dr_mode = "host";
203	status = "okay";
204};
205
206&extal_clk {
207	clock-frequency = <48000000>;
208};
209
210&hsusb {
211	dr_mode = "host";
212	status = "okay";
213};
214
215&i2c0 {
216	pinctrl-0 = <&i2c0_pins>;
217	pinctrl-names = "default";
218	status = "okay";
219
220	composite-in@20 {
221		compatible = "adi,adv7180cp";
222		reg = <0x20>;
223
224		ports {
225			#address-cells = <1>;
226			#size-cells = <0>;
227
228			port@0 {
229				reg = <0>;
230				adv7180_in: endpoint {
231					remote-endpoint = <&composite_con_in>;
232				};
233			};
234
235			port@3 {
236				reg = <3>;
237
238				/*
239				 * The VIN4 video input path is shared between
240				 * CVBS and HDMI inputs through SW[49-53]
241				 * switches.
242				 *
243				 * CVBS is the default selection, link it to
244				 * VIN4 here.
245				 */
246				adv7180_out: endpoint {
247					remote-endpoint = <&vin4_in>;
248				};
249			};
250		};
251
252	};
253
254	hdmi-encoder@39 {
255		compatible = "adi,adv7511w";
256		reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
257		reg-names = "main", "edid", "packet", "cec";
258		interrupt-parent = <&gpio1>;
259		interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
260
261		/* Depends on LVDS */
262		max-clock = <135000000>;
263		min-vrefresh = <50>;
264
265		adi,input-depth = <8>;
266		adi,input-colorspace = "rgb";
267		adi,input-clock = "1x";
268		adi,input-style = <1>;
269		adi,input-justification = "evenly";
270
271		ports {
272			#address-cells = <1>;
273			#size-cells = <0>;
274
275			port@0 {
276				reg = <0>;
277				adv7511_in: endpoint {
278					remote-endpoint = <&thc63lvd1024_out>;
279				};
280			};
281
282			port@1 {
283				reg = <1>;
284				adv7511_out: endpoint {
285					remote-endpoint = <&hdmi_con_out>;
286				};
287			};
288		};
289	};
290
291	hdmi-decoder@4c {
292		compatible = "adi,adv7612";
293		reg = <0x4c>;
294		default-input = <0>;
295
296		ports {
297			#address-cells = <1>;
298			#size-cells = <0>;
299
300			port@0 {
301				reg = <0>;
302
303				adv7612_in: endpoint {
304					remote-endpoint = <&hdmi_con_in>;
305				};
306			};
307
308			port@2 {
309				reg = <2>;
310
311				/*
312				 * The VIN4 video input path is shared between
313				 * CVBS and HDMI inputs through SW[49-53]
314				 * switches.
315				 *
316				 * CVBS is the default selection, leave HDMI
317				 * not connected here.
318				 */
319				adv7612_out: endpoint {
320					pclk-sample = <0>;
321					hsync-active = <0>;
322					vsync-active = <0>;
323				};
324			};
325		};
326	};
327
328	eeprom@50 {
329		compatible = "rohm,br24t01", "atmel,24c01";
330		reg = <0x50>;
331		pagesize = <8>;
332	};
333};
334
335&i2c1 {
336	pinctrl-0 = <&i2c1_pins>;
337	pinctrl-names = "default";
338	status = "okay";
339};
340
341&lvds0 {
342	status = "okay";
343
344	clocks = <&cpg CPG_MOD 727>,
345		 <&x12_clk>,
346		 <&extal_clk>;
347	clock-names = "fck", "dclkin.0", "extal";
348
349	ports {
350		port@1 {
351			lvds0_out: endpoint {
352				remote-endpoint = <&thc63lvd1024_in>;
353			};
354		};
355	};
356};
357
358&lvds1 {
359	clocks = <&cpg CPG_MOD 727>,
360		 <&x12_clk>,
361		 <&extal_clk>;
362	clock-names = "fck", "dclkin.0", "extal";
363};
364
365&ohci0 {
366	dr_mode = "host";
367	status = "okay";
368};
369
370&pfc {
371	avb0_pins: avb {
372		mux {
373			groups = "avb0_link", "avb0_mdio", "avb0_mii";
374			function = "avb0";
375		};
376	};
377
378	du_pins: du {
379		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
380		function = "du";
381	};
382
383	i2c0_pins: i2c0 {
384		groups = "i2c0";
385		function = "i2c0";
386	};
387
388	i2c1_pins: i2c1 {
389		groups = "i2c1";
390		function = "i2c1";
391	};
392
393	pwm0_pins: pwm0 {
394		groups = "pwm0_c";
395		function = "pwm0";
396	};
397
398	pwm1_pins: pwm1 {
399		groups = "pwm1_c";
400		function = "pwm1";
401	};
402
403	scif2_pins: scif2 {
404		groups = "scif2_data";
405		function = "scif2";
406	};
407
408	sdhi2_pins: sd2 {
409		groups = "mmc_data8", "mmc_ctrl";
410		function = "mmc";
411		power-source = <1800>;
412	};
413
414	sdhi2_pins_uhs: sd2_uhs {
415		groups = "mmc_data8", "mmc_ctrl";
416		function = "mmc";
417		power-source = <1800>;
418	};
419
420	usb0_pins: usb0 {
421		groups = "usb0";
422		function = "usb0";
423	};
424
425	vin4_pins_cvbs: vin4 {
426		groups = "vin4_data8", "vin4_sync", "vin4_clk";
427		function = "vin4";
428	};
429};
430
431&pwm0 {
432	pinctrl-0 = <&pwm0_pins>;
433	pinctrl-names = "default";
434
435	status = "okay";
436};
437
438&pwm1 {
439	pinctrl-0 = <&pwm1_pins>;
440	pinctrl-names = "default";
441
442	status = "okay";
443};
444
445&rwdt {
446	timeout-sec = <60>;
447	status = "okay";
448};
449
450&scif2 {
451	pinctrl-0 = <&scif2_pins>;
452	pinctrl-names = "default";
453
454	status = "okay";
455};
456
457&sdhi2 {
458	/* used for on-board eMMC */
459	pinctrl-0 = <&sdhi2_pins>;
460	pinctrl-1 = <&sdhi2_pins_uhs>;
461	pinctrl-names = "default", "state_uhs";
462
463	vmmc-supply = <&reg_3p3v>;
464	vqmmc-supply = <&reg_1p8v>;
465	bus-width = <8>;
466	mmc-hs200-1_8v;
467	non-removable;
468	status = "okay";
469};
470
471&usb2_phy0 {
472	pinctrl-0 = <&usb0_pins>;
473	pinctrl-names = "default";
474
475	renesas,no-otg-pins;
476	status = "okay";
477};
478
479&vin4 {
480	pinctrl-0 = <&vin4_pins_cvbs>;
481	pinctrl-names = "default";
482
483	status = "okay";
484
485	ports {
486		#address-cells = <1>;
487		#size-cells = <0>;
488
489		port@0 {
490			reg = <0>;
491
492			vin4_in: endpoint {
493				remote-endpoint = <&adv7180_out>;
494			};
495		};
496	};
497};
498