1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77990-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77990-sysc.h> 11 12/ { 13 compatible = "renesas,r8a77990"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 i2c5 = &i2c5; 24 i2c6 = &i2c6; 25 i2c7 = &i2c7; 26 }; 27 28 /* 29 * The external audio clocks are configured as 0 Hz fixed frequency 30 * clocks by default. 31 * Boards that provide audio clocks should override them. 32 */ 33 audio_clk_a: audio_clk_a { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <0>; 37 }; 38 39 audio_clk_b: audio_clk_b { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <0>; 43 }; 44 45 audio_clk_c: audio_clk_c { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <0>; 49 }; 50 51 /* External CAN clock - to be overridden by boards that provide it */ 52 can_clk: can { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <0>; 56 }; 57 58 cluster1_opp: opp_table10 { 59 compatible = "operating-points-v2"; 60 opp-shared; 61 opp-800000000 { 62 opp-hz = /bits/ 64 <800000000>; 63 opp-microvolt = <820000>; 64 clock-latency-ns = <300000>; 65 }; 66 opp-1000000000 { 67 opp-hz = /bits/ 64 <1000000000>; 68 opp-microvolt = <820000>; 69 clock-latency-ns = <300000>; 70 }; 71 opp-1200000000 { 72 opp-hz = /bits/ 64 <1200000000>; 73 opp-microvolt = <820000>; 74 clock-latency-ns = <300000>; 75 opp-suspend; 76 }; 77 }; 78 79 cpus { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 a53_0: cpu@0 { 84 compatible = "arm,cortex-a53"; 85 reg = <0>; 86 device_type = "cpu"; 87 power-domains = <&sysc R8A77990_PD_CA53_CPU0>; 88 next-level-cache = <&L2_CA53>; 89 enable-method = "psci"; 90 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; 91 operating-points-v2 = <&cluster1_opp>; 92 }; 93 94 a53_1: cpu@1 { 95 compatible = "arm,cortex-a53"; 96 reg = <1>; 97 device_type = "cpu"; 98 power-domains = <&sysc R8A77990_PD_CA53_CPU1>; 99 next-level-cache = <&L2_CA53>; 100 enable-method = "psci"; 101 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; 102 operating-points-v2 = <&cluster1_opp>; 103 }; 104 105 L2_CA53: cache-controller-0 { 106 compatible = "cache"; 107 power-domains = <&sysc R8A77990_PD_CA53_SCU>; 108 cache-unified; 109 cache-level = <2>; 110 }; 111 }; 112 113 extal_clk: extal { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 /* This value must be overridden by the board */ 117 clock-frequency = <0>; 118 }; 119 120 /* External PCIe clock - can be overridden by the board */ 121 pcie_bus_clk: pcie_bus { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <0>; 125 }; 126 127 pmu_a53 { 128 compatible = "arm,cortex-a53-pmu"; 129 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 130 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-affinity = <&a53_0>, <&a53_1>; 132 }; 133 134 psci { 135 compatible = "arm,psci-1.0", "arm,psci-0.2"; 136 method = "smc"; 137 }; 138 139 /* External SCIF clock - to be overridden by boards that provide it */ 140 scif_clk: scif { 141 compatible = "fixed-clock"; 142 #clock-cells = <0>; 143 clock-frequency = <0>; 144 }; 145 146 soc: soc { 147 compatible = "simple-bus"; 148 interrupt-parent = <&gic>; 149 #address-cells = <2>; 150 #size-cells = <2>; 151 ranges; 152 153 rwdt: watchdog@e6020000 { 154 compatible = "renesas,r8a77990-wdt", 155 "renesas,rcar-gen3-wdt"; 156 reg = <0 0xe6020000 0 0x0c>; 157 clocks = <&cpg CPG_MOD 402>; 158 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 159 resets = <&cpg 402>; 160 status = "disabled"; 161 }; 162 163 gpio0: gpio@e6050000 { 164 compatible = "renesas,gpio-r8a77990", 165 "renesas,rcar-gen3-gpio"; 166 reg = <0 0xe6050000 0 0x50>; 167 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 168 #gpio-cells = <2>; 169 gpio-controller; 170 gpio-ranges = <&pfc 0 0 18>; 171 #interrupt-cells = <2>; 172 interrupt-controller; 173 clocks = <&cpg CPG_MOD 912>; 174 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 175 resets = <&cpg 912>; 176 }; 177 178 gpio1: gpio@e6051000 { 179 compatible = "renesas,gpio-r8a77990", 180 "renesas,rcar-gen3-gpio"; 181 reg = <0 0xe6051000 0 0x50>; 182 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 183 #gpio-cells = <2>; 184 gpio-controller; 185 gpio-ranges = <&pfc 0 32 23>; 186 #interrupt-cells = <2>; 187 interrupt-controller; 188 clocks = <&cpg CPG_MOD 911>; 189 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 190 resets = <&cpg 911>; 191 }; 192 193 gpio2: gpio@e6052000 { 194 compatible = "renesas,gpio-r8a77990", 195 "renesas,rcar-gen3-gpio"; 196 reg = <0 0xe6052000 0 0x50>; 197 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 198 #gpio-cells = <2>; 199 gpio-controller; 200 gpio-ranges = <&pfc 0 64 26>; 201 #interrupt-cells = <2>; 202 interrupt-controller; 203 clocks = <&cpg CPG_MOD 910>; 204 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 205 resets = <&cpg 910>; 206 }; 207 208 gpio3: gpio@e6053000 { 209 compatible = "renesas,gpio-r8a77990", 210 "renesas,rcar-gen3-gpio"; 211 reg = <0 0xe6053000 0 0x50>; 212 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 213 #gpio-cells = <2>; 214 gpio-controller; 215 gpio-ranges = <&pfc 0 96 16>; 216 #interrupt-cells = <2>; 217 interrupt-controller; 218 clocks = <&cpg CPG_MOD 909>; 219 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 220 resets = <&cpg 909>; 221 }; 222 223 gpio4: gpio@e6054000 { 224 compatible = "renesas,gpio-r8a77990", 225 "renesas,rcar-gen3-gpio"; 226 reg = <0 0xe6054000 0 0x50>; 227 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 228 #gpio-cells = <2>; 229 gpio-controller; 230 gpio-ranges = <&pfc 0 128 11>; 231 #interrupt-cells = <2>; 232 interrupt-controller; 233 clocks = <&cpg CPG_MOD 908>; 234 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 235 resets = <&cpg 908>; 236 }; 237 238 gpio5: gpio@e6055000 { 239 compatible = "renesas,gpio-r8a77990", 240 "renesas,rcar-gen3-gpio"; 241 reg = <0 0xe6055000 0 0x50>; 242 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 243 #gpio-cells = <2>; 244 gpio-controller; 245 gpio-ranges = <&pfc 0 160 20>; 246 #interrupt-cells = <2>; 247 interrupt-controller; 248 clocks = <&cpg CPG_MOD 907>; 249 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 250 resets = <&cpg 907>; 251 }; 252 253 gpio6: gpio@e6055400 { 254 compatible = "renesas,gpio-r8a77990", 255 "renesas,rcar-gen3-gpio"; 256 reg = <0 0xe6055400 0 0x50>; 257 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 258 #gpio-cells = <2>; 259 gpio-controller; 260 gpio-ranges = <&pfc 0 192 18>; 261 #interrupt-cells = <2>; 262 interrupt-controller; 263 clocks = <&cpg CPG_MOD 906>; 264 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 265 resets = <&cpg 906>; 266 }; 267 268 pfc: pin-controller@e6060000 { 269 compatible = "renesas,pfc-r8a77990"; 270 reg = <0 0xe6060000 0 0x508>; 271 }; 272 273 i2c_dvfs: i2c@e60b0000 { 274 #address-cells = <1>; 275 #size-cells = <0>; 276 compatible = "renesas,iic-r8a77990"; 277 reg = <0 0xe60b0000 0 0x15>; 278 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&cpg CPG_MOD 926>; 280 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 281 resets = <&cpg 926>; 282 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 283 dma-names = "tx", "rx"; 284 status = "disabled"; 285 }; 286 287 cpg: clock-controller@e6150000 { 288 compatible = "renesas,r8a77990-cpg-mssr"; 289 reg = <0 0xe6150000 0 0x1000>; 290 clocks = <&extal_clk>; 291 clock-names = "extal"; 292 #clock-cells = <2>; 293 #power-domain-cells = <0>; 294 #reset-cells = <1>; 295 }; 296 297 rst: reset-controller@e6160000 { 298 compatible = "renesas,r8a77990-rst"; 299 reg = <0 0xe6160000 0 0x0200>; 300 }; 301 302 sysc: system-controller@e6180000 { 303 compatible = "renesas,r8a77990-sysc"; 304 reg = <0 0xe6180000 0 0x0400>; 305 #power-domain-cells = <1>; 306 }; 307 308 thermal: thermal@e6190000 { 309 compatible = "renesas,thermal-r8a77990"; 310 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 311 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&cpg CPG_MOD 522>; 315 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 316 resets = <&cpg 522>; 317 #thermal-sensor-cells = <0>; 318 }; 319 320 intc_ex: interrupt-controller@e61c0000 { 321 compatible = "renesas,intc-ex-r8a77990", "renesas,irqc"; 322 #interrupt-cells = <2>; 323 interrupt-controller; 324 reg = <0 0xe61c0000 0 0x200>; 325 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 326 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 327 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 328 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 329 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 330 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&cpg CPG_MOD 407>; 332 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 333 resets = <&cpg 407>; 334 }; 335 336 i2c0: i2c@e6500000 { 337 #address-cells = <1>; 338 #size-cells = <0>; 339 compatible = "renesas,i2c-r8a77990", 340 "renesas,rcar-gen3-i2c"; 341 reg = <0 0xe6500000 0 0x40>; 342 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cpg CPG_MOD 931>; 344 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 345 resets = <&cpg 931>; 346 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 347 <&dmac2 0x91>, <&dmac2 0x90>; 348 dma-names = "tx", "rx", "tx", "rx"; 349 i2c-scl-internal-delay-ns = <110>; 350 status = "disabled"; 351 }; 352 353 i2c1: i2c@e6508000 { 354 #address-cells = <1>; 355 #size-cells = <0>; 356 compatible = "renesas,i2c-r8a77990", 357 "renesas,rcar-gen3-i2c"; 358 reg = <0 0xe6508000 0 0x40>; 359 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&cpg CPG_MOD 930>; 361 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 362 resets = <&cpg 930>; 363 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 364 <&dmac2 0x93>, <&dmac2 0x92>; 365 dma-names = "tx", "rx", "tx", "rx"; 366 i2c-scl-internal-delay-ns = <6>; 367 status = "disabled"; 368 }; 369 370 i2c2: i2c@e6510000 { 371 #address-cells = <1>; 372 #size-cells = <0>; 373 compatible = "renesas,i2c-r8a77990", 374 "renesas,rcar-gen3-i2c"; 375 reg = <0 0xe6510000 0 0x40>; 376 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&cpg CPG_MOD 929>; 378 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 379 resets = <&cpg 929>; 380 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 381 <&dmac2 0x95>, <&dmac2 0x94>; 382 dma-names = "tx", "rx", "tx", "rx"; 383 i2c-scl-internal-delay-ns = <6>; 384 status = "disabled"; 385 }; 386 387 i2c3: i2c@e66d0000 { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 compatible = "renesas,i2c-r8a77990", 391 "renesas,rcar-gen3-i2c"; 392 reg = <0 0xe66d0000 0 0x40>; 393 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&cpg CPG_MOD 928>; 395 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 396 resets = <&cpg 928>; 397 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 398 dma-names = "tx", "rx"; 399 i2c-scl-internal-delay-ns = <110>; 400 status = "disabled"; 401 }; 402 403 i2c4: i2c@e66d8000 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 compatible = "renesas,i2c-r8a77990", 407 "renesas,rcar-gen3-i2c"; 408 reg = <0 0xe66d8000 0 0x40>; 409 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&cpg CPG_MOD 927>; 411 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 412 resets = <&cpg 927>; 413 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 414 dma-names = "tx", "rx"; 415 i2c-scl-internal-delay-ns = <6>; 416 status = "disabled"; 417 }; 418 419 i2c5: i2c@e66e0000 { 420 #address-cells = <1>; 421 #size-cells = <0>; 422 compatible = "renesas,i2c-r8a77990", 423 "renesas,rcar-gen3-i2c"; 424 reg = <0 0xe66e0000 0 0x40>; 425 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&cpg CPG_MOD 919>; 427 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 428 resets = <&cpg 919>; 429 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 430 dma-names = "tx", "rx"; 431 i2c-scl-internal-delay-ns = <6>; 432 status = "disabled"; 433 }; 434 435 i2c6: i2c@e66e8000 { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 compatible = "renesas,i2c-r8a77990", 439 "renesas,rcar-gen3-i2c"; 440 reg = <0 0xe66e8000 0 0x40>; 441 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&cpg CPG_MOD 918>; 443 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 444 resets = <&cpg 918>; 445 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 446 dma-names = "tx", "rx"; 447 i2c-scl-internal-delay-ns = <6>; 448 status = "disabled"; 449 }; 450 451 i2c7: i2c@e6690000 { 452 #address-cells = <1>; 453 #size-cells = <0>; 454 compatible = "renesas,i2c-r8a77990", 455 "renesas,rcar-gen3-i2c"; 456 reg = <0 0xe6690000 0 0x40>; 457 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&cpg CPG_MOD 1003>; 459 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 460 resets = <&cpg 1003>; 461 i2c-scl-internal-delay-ns = <6>; 462 status = "disabled"; 463 }; 464 465 hscif0: serial@e6540000 { 466 compatible = "renesas,hscif-r8a77990", 467 "renesas,rcar-gen3-hscif", 468 "renesas,hscif"; 469 reg = <0 0xe6540000 0 0x60>; 470 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&cpg CPG_MOD 520>, 472 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 473 <&scif_clk>; 474 clock-names = "fck", "brg_int", "scif_clk"; 475 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 476 <&dmac2 0x31>, <&dmac2 0x30>; 477 dma-names = "tx", "rx", "tx", "rx"; 478 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 479 resets = <&cpg 520>; 480 status = "disabled"; 481 }; 482 483 hscif1: serial@e6550000 { 484 compatible = "renesas,hscif-r8a77990", 485 "renesas,rcar-gen3-hscif", 486 "renesas,hscif"; 487 reg = <0 0xe6550000 0 0x60>; 488 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&cpg CPG_MOD 519>, 490 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 491 <&scif_clk>; 492 clock-names = "fck", "brg_int", "scif_clk"; 493 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 494 <&dmac2 0x33>, <&dmac2 0x32>; 495 dma-names = "tx", "rx", "tx", "rx"; 496 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 497 resets = <&cpg 519>; 498 status = "disabled"; 499 }; 500 501 hscif2: serial@e6560000 { 502 compatible = "renesas,hscif-r8a77990", 503 "renesas,rcar-gen3-hscif", 504 "renesas,hscif"; 505 reg = <0 0xe6560000 0 0x60>; 506 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&cpg CPG_MOD 518>, 508 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 509 <&scif_clk>; 510 clock-names = "fck", "brg_int", "scif_clk"; 511 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 512 <&dmac2 0x35>, <&dmac2 0x34>; 513 dma-names = "tx", "rx", "tx", "rx"; 514 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 515 resets = <&cpg 518>; 516 status = "disabled"; 517 }; 518 519 hscif3: serial@e66a0000 { 520 compatible = "renesas,hscif-r8a77990", 521 "renesas,rcar-gen3-hscif", 522 "renesas,hscif"; 523 reg = <0 0xe66a0000 0 0x60>; 524 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&cpg CPG_MOD 517>, 526 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 527 <&scif_clk>; 528 clock-names = "fck", "brg_int", "scif_clk"; 529 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 530 dma-names = "tx", "rx"; 531 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 532 resets = <&cpg 517>; 533 status = "disabled"; 534 }; 535 536 hscif4: serial@e66b0000 { 537 compatible = "renesas,hscif-r8a77990", 538 "renesas,rcar-gen3-hscif", 539 "renesas,hscif"; 540 reg = <0 0xe66b0000 0 0x60>; 541 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&cpg CPG_MOD 516>, 543 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 544 <&scif_clk>; 545 clock-names = "fck", "brg_int", "scif_clk"; 546 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 547 dma-names = "tx", "rx"; 548 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 549 resets = <&cpg 516>; 550 status = "disabled"; 551 }; 552 553 hsusb: usb@e6590000 { 554 compatible = "renesas,usbhs-r8a77990", 555 "renesas,rcar-gen3-usbhs"; 556 reg = <0 0xe6590000 0 0x200>; 557 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 559 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 560 <&usb_dmac1 0>, <&usb_dmac1 1>; 561 dma-names = "ch0", "ch1", "ch2", "ch3"; 562 renesas,buswait = <11>; 563 phys = <&usb2_phy0>; 564 phy-names = "usb"; 565 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 566 resets = <&cpg 704>, <&cpg 703>; 567 status = "disabled"; 568 }; 569 570 usb_dmac0: dma-controller@e65a0000 { 571 compatible = "renesas,r8a77990-usb-dmac", 572 "renesas,usb-dmac"; 573 reg = <0 0xe65a0000 0 0x100>; 574 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 575 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 576 interrupt-names = "ch0", "ch1"; 577 clocks = <&cpg CPG_MOD 330>; 578 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 579 resets = <&cpg 330>; 580 #dma-cells = <1>; 581 dma-channels = <2>; 582 }; 583 584 usb_dmac1: dma-controller@e65b0000 { 585 compatible = "renesas,r8a77990-usb-dmac", 586 "renesas,usb-dmac"; 587 reg = <0 0xe65b0000 0 0x100>; 588 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 589 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 590 interrupt-names = "ch0", "ch1"; 591 clocks = <&cpg CPG_MOD 331>; 592 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 593 resets = <&cpg 331>; 594 #dma-cells = <1>; 595 dma-channels = <2>; 596 }; 597 598 dmac0: dma-controller@e6700000 { 599 compatible = "renesas,dmac-r8a77990", 600 "renesas,rcar-dmac"; 601 reg = <0 0xe6700000 0 0x10000>; 602 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 603 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 604 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 605 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 606 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 607 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 608 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 609 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 610 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 611 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 612 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 613 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 614 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 615 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 616 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 617 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 618 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 619 interrupt-names = "error", 620 "ch0", "ch1", "ch2", "ch3", 621 "ch4", "ch5", "ch6", "ch7", 622 "ch8", "ch9", "ch10", "ch11", 623 "ch12", "ch13", "ch14", "ch15"; 624 clocks = <&cpg CPG_MOD 219>; 625 clock-names = "fck"; 626 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 627 resets = <&cpg 219>; 628 #dma-cells = <1>; 629 dma-channels = <16>; 630 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 631 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 632 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 633 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 634 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 635 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 636 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 637 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 638 }; 639 640 dmac1: dma-controller@e7300000 { 641 compatible = "renesas,dmac-r8a77990", 642 "renesas,rcar-dmac"; 643 reg = <0 0xe7300000 0 0x10000>; 644 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 645 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 646 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 647 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 648 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 649 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 650 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 651 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 652 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 653 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 654 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 655 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 656 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 657 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 658 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 659 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 660 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 661 interrupt-names = "error", 662 "ch0", "ch1", "ch2", "ch3", 663 "ch4", "ch5", "ch6", "ch7", 664 "ch8", "ch9", "ch10", "ch11", 665 "ch12", "ch13", "ch14", "ch15"; 666 clocks = <&cpg CPG_MOD 218>; 667 clock-names = "fck"; 668 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 669 resets = <&cpg 218>; 670 #dma-cells = <1>; 671 dma-channels = <16>; 672 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 673 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 674 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 675 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 676 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 677 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 678 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 679 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 680 }; 681 682 dmac2: dma-controller@e7310000 { 683 compatible = "renesas,dmac-r8a77990", 684 "renesas,rcar-dmac"; 685 reg = <0 0xe7310000 0 0x10000>; 686 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 687 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 688 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 689 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 690 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 691 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 692 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 693 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 694 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 695 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 696 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 697 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 698 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 699 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 700 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 701 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 702 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 703 interrupt-names = "error", 704 "ch0", "ch1", "ch2", "ch3", 705 "ch4", "ch5", "ch6", "ch7", 706 "ch8", "ch9", "ch10", "ch11", 707 "ch12", "ch13", "ch14", "ch15"; 708 clocks = <&cpg CPG_MOD 217>; 709 clock-names = "fck"; 710 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 711 resets = <&cpg 217>; 712 #dma-cells = <1>; 713 dma-channels = <16>; 714 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 715 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 716 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 717 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 718 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 719 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 720 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 721 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 722 }; 723 724 ipmmu_ds0: mmu@e6740000 { 725 compatible = "renesas,ipmmu-r8a77990"; 726 reg = <0 0xe6740000 0 0x1000>; 727 renesas,ipmmu-main = <&ipmmu_mm 0>; 728 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 729 #iommu-cells = <1>; 730 }; 731 732 ipmmu_ds1: mmu@e7740000 { 733 compatible = "renesas,ipmmu-r8a77990"; 734 reg = <0 0xe7740000 0 0x1000>; 735 renesas,ipmmu-main = <&ipmmu_mm 1>; 736 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 737 #iommu-cells = <1>; 738 }; 739 740 ipmmu_hc: mmu@e6570000 { 741 compatible = "renesas,ipmmu-r8a77990"; 742 reg = <0 0xe6570000 0 0x1000>; 743 renesas,ipmmu-main = <&ipmmu_mm 2>; 744 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 745 #iommu-cells = <1>; 746 }; 747 748 ipmmu_mm: mmu@e67b0000 { 749 compatible = "renesas,ipmmu-r8a77990"; 750 reg = <0 0xe67b0000 0 0x1000>; 751 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 753 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 754 #iommu-cells = <1>; 755 }; 756 757 ipmmu_mp: mmu@ec670000 { 758 compatible = "renesas,ipmmu-r8a77990"; 759 reg = <0 0xec670000 0 0x1000>; 760 renesas,ipmmu-main = <&ipmmu_mm 4>; 761 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 762 #iommu-cells = <1>; 763 }; 764 765 ipmmu_pv0: mmu@fd800000 { 766 compatible = "renesas,ipmmu-r8a77990"; 767 reg = <0 0xfd800000 0 0x1000>; 768 renesas,ipmmu-main = <&ipmmu_mm 6>; 769 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 770 #iommu-cells = <1>; 771 }; 772 773 ipmmu_rt: mmu@ffc80000 { 774 compatible = "renesas,ipmmu-r8a77990"; 775 reg = <0 0xffc80000 0 0x1000>; 776 renesas,ipmmu-main = <&ipmmu_mm 10>; 777 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 778 #iommu-cells = <1>; 779 }; 780 781 ipmmu_vc0: mmu@fe6b0000 { 782 compatible = "renesas,ipmmu-r8a77990"; 783 reg = <0 0xfe6b0000 0 0x1000>; 784 renesas,ipmmu-main = <&ipmmu_mm 12>; 785 power-domains = <&sysc R8A77990_PD_A3VC>; 786 #iommu-cells = <1>; 787 }; 788 789 ipmmu_vi0: mmu@febd0000 { 790 compatible = "renesas,ipmmu-r8a77990"; 791 reg = <0 0xfebd0000 0 0x1000>; 792 renesas,ipmmu-main = <&ipmmu_mm 14>; 793 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 794 #iommu-cells = <1>; 795 }; 796 797 ipmmu_vp0: mmu@fe990000 { 798 compatible = "renesas,ipmmu-r8a77990"; 799 reg = <0 0xfe990000 0 0x1000>; 800 renesas,ipmmu-main = <&ipmmu_mm 16>; 801 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 802 #iommu-cells = <1>; 803 }; 804 805 avb: ethernet@e6800000 { 806 compatible = "renesas,etheravb-r8a77990", 807 "renesas,etheravb-rcar-gen3"; 808 reg = <0 0xe6800000 0 0x800>; 809 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 834 interrupt-names = "ch0", "ch1", "ch2", "ch3", 835 "ch4", "ch5", "ch6", "ch7", 836 "ch8", "ch9", "ch10", "ch11", 837 "ch12", "ch13", "ch14", "ch15", 838 "ch16", "ch17", "ch18", "ch19", 839 "ch20", "ch21", "ch22", "ch23", 840 "ch24"; 841 clocks = <&cpg CPG_MOD 812>; 842 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 843 resets = <&cpg 812>; 844 phy-mode = "rgmii"; 845 iommus = <&ipmmu_ds0 16>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 status = "disabled"; 849 }; 850 851 can0: can@e6c30000 { 852 compatible = "renesas,can-r8a77990", 853 "renesas,rcar-gen3-can"; 854 reg = <0 0xe6c30000 0 0x1000>; 855 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&cpg CPG_MOD 916>, 857 <&cpg CPG_CORE R8A77990_CLK_CANFD>, 858 <&can_clk>; 859 clock-names = "clkp1", "clkp2", "can_clk"; 860 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; 861 assigned-clock-rates = <40000000>; 862 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 863 resets = <&cpg 916>; 864 status = "disabled"; 865 }; 866 867 can1: can@e6c38000 { 868 compatible = "renesas,can-r8a77990", 869 "renesas,rcar-gen3-can"; 870 reg = <0 0xe6c38000 0 0x1000>; 871 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&cpg CPG_MOD 915>, 873 <&cpg CPG_CORE R8A77990_CLK_CANFD>, 874 <&can_clk>; 875 clock-names = "clkp1", "clkp2", "can_clk"; 876 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; 877 assigned-clock-rates = <40000000>; 878 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 879 resets = <&cpg 915>; 880 status = "disabled"; 881 }; 882 883 canfd: can@e66c0000 { 884 compatible = "renesas,r8a77990-canfd", 885 "renesas,rcar-gen3-canfd"; 886 reg = <0 0xe66c0000 0 0x8000>; 887 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&cpg CPG_MOD 914>, 890 <&cpg CPG_CORE R8A77990_CLK_CANFD>, 891 <&can_clk>; 892 clock-names = "fck", "canfd", "can_clk"; 893 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; 894 assigned-clock-rates = <40000000>; 895 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 896 resets = <&cpg 914>; 897 status = "disabled"; 898 899 channel0 { 900 status = "disabled"; 901 }; 902 903 channel1 { 904 status = "disabled"; 905 }; 906 }; 907 908 pwm0: pwm@e6e30000 { 909 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 910 reg = <0 0xe6e30000 0 0x8>; 911 clocks = <&cpg CPG_MOD 523>; 912 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 913 resets = <&cpg 523>; 914 #pwm-cells = <2>; 915 status = "disabled"; 916 }; 917 918 pwm1: pwm@e6e31000 { 919 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 920 reg = <0 0xe6e31000 0 0x8>; 921 clocks = <&cpg CPG_MOD 523>; 922 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 923 resets = <&cpg 523>; 924 #pwm-cells = <2>; 925 status = "disabled"; 926 }; 927 928 pwm2: pwm@e6e32000 { 929 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 930 reg = <0 0xe6e32000 0 0x8>; 931 clocks = <&cpg CPG_MOD 523>; 932 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 933 resets = <&cpg 523>; 934 #pwm-cells = <2>; 935 status = "disabled"; 936 }; 937 938 pwm3: pwm@e6e33000 { 939 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 940 reg = <0 0xe6e33000 0 0x8>; 941 clocks = <&cpg CPG_MOD 523>; 942 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 943 resets = <&cpg 523>; 944 #pwm-cells = <2>; 945 status = "disabled"; 946 }; 947 948 pwm4: pwm@e6e34000 { 949 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 950 reg = <0 0xe6e34000 0 0x8>; 951 clocks = <&cpg CPG_MOD 523>; 952 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 953 resets = <&cpg 523>; 954 #pwm-cells = <2>; 955 status = "disabled"; 956 }; 957 958 pwm5: pwm@e6e35000 { 959 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 960 reg = <0 0xe6e35000 0 0x8>; 961 clocks = <&cpg CPG_MOD 523>; 962 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 963 resets = <&cpg 523>; 964 #pwm-cells = <2>; 965 status = "disabled"; 966 }; 967 968 pwm6: pwm@e6e36000 { 969 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 970 reg = <0 0xe6e36000 0 0x8>; 971 clocks = <&cpg CPG_MOD 523>; 972 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 973 resets = <&cpg 523>; 974 #pwm-cells = <2>; 975 status = "disabled"; 976 }; 977 978 scif0: serial@e6e60000 { 979 compatible = "renesas,scif-r8a77990", 980 "renesas,rcar-gen3-scif", "renesas,scif"; 981 reg = <0 0xe6e60000 0 64>; 982 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&cpg CPG_MOD 207>, 984 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 985 <&scif_clk>; 986 clock-names = "fck", "brg_int", "scif_clk"; 987 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 988 <&dmac2 0x51>, <&dmac2 0x50>; 989 dma-names = "tx", "rx", "tx", "rx"; 990 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 991 resets = <&cpg 207>; 992 status = "disabled"; 993 }; 994 995 scif1: serial@e6e68000 { 996 compatible = "renesas,scif-r8a77990", 997 "renesas,rcar-gen3-scif", "renesas,scif"; 998 reg = <0 0xe6e68000 0 64>; 999 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&cpg CPG_MOD 206>, 1001 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 1002 <&scif_clk>; 1003 clock-names = "fck", "brg_int", "scif_clk"; 1004 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1005 <&dmac2 0x53>, <&dmac2 0x52>; 1006 dma-names = "tx", "rx", "tx", "rx"; 1007 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1008 resets = <&cpg 206>; 1009 status = "disabled"; 1010 }; 1011 1012 scif2: serial@e6e88000 { 1013 compatible = "renesas,scif-r8a77990", 1014 "renesas,rcar-gen3-scif", "renesas,scif"; 1015 reg = <0 0xe6e88000 0 64>; 1016 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1017 clocks = <&cpg CPG_MOD 310>, 1018 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 1019 <&scif_clk>; 1020 clock-names = "fck", "brg_int", "scif_clk"; 1021 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1022 <&dmac2 0x13>, <&dmac2 0x12>; 1023 dma-names = "tx", "rx", "tx", "rx"; 1024 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1025 resets = <&cpg 310>; 1026 status = "disabled"; 1027 }; 1028 1029 scif3: serial@e6c50000 { 1030 compatible = "renesas,scif-r8a77990", 1031 "renesas,rcar-gen3-scif", "renesas,scif"; 1032 reg = <0 0xe6c50000 0 64>; 1033 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&cpg CPG_MOD 204>, 1035 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 1036 <&scif_clk>; 1037 clock-names = "fck", "brg_int", "scif_clk"; 1038 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1039 dma-names = "tx", "rx"; 1040 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1041 resets = <&cpg 204>; 1042 status = "disabled"; 1043 }; 1044 1045 scif4: serial@e6c40000 { 1046 compatible = "renesas,scif-r8a77990", 1047 "renesas,rcar-gen3-scif", "renesas,scif"; 1048 reg = <0 0xe6c40000 0 64>; 1049 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&cpg CPG_MOD 203>, 1051 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 1052 <&scif_clk>; 1053 clock-names = "fck", "brg_int", "scif_clk"; 1054 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1055 dma-names = "tx", "rx"; 1056 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1057 resets = <&cpg 203>; 1058 status = "disabled"; 1059 }; 1060 1061 scif5: serial@e6f30000 { 1062 compatible = "renesas,scif-r8a77990", 1063 "renesas,rcar-gen3-scif", "renesas,scif"; 1064 reg = <0 0xe6f30000 0 64>; 1065 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1066 clocks = <&cpg CPG_MOD 202>, 1067 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 1068 <&scif_clk>; 1069 clock-names = "fck", "brg_int", "scif_clk"; 1070 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1071 <&dmac2 0x5b>, <&dmac2 0x5a>; 1072 dma-names = "tx", "rx", "tx", "rx"; 1073 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1074 resets = <&cpg 202>; 1075 status = "disabled"; 1076 }; 1077 1078 msiof0: spi@e6e90000 { 1079 compatible = "renesas,msiof-r8a77990", 1080 "renesas,rcar-gen3-msiof"; 1081 reg = <0 0xe6e90000 0 0x0064>; 1082 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&cpg CPG_MOD 211>; 1084 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1085 <&dmac2 0x41>, <&dmac2 0x40>; 1086 dma-names = "tx", "rx", "tx", "rx"; 1087 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1088 resets = <&cpg 211>; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 status = "disabled"; 1092 }; 1093 1094 msiof1: spi@e6ea0000 { 1095 compatible = "renesas,msiof-r8a77990", 1096 "renesas,rcar-gen3-msiof"; 1097 reg = <0 0xe6ea0000 0 0x0064>; 1098 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&cpg CPG_MOD 210>; 1100 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1101 <&dmac2 0x43>, <&dmac2 0x42>; 1102 dma-names = "tx", "rx", "tx", "rx"; 1103 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1104 resets = <&cpg 210>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 msiof2: spi@e6c00000 { 1111 compatible = "renesas,msiof-r8a77990", 1112 "renesas,rcar-gen3-msiof"; 1113 reg = <0 0xe6c00000 0 0x0064>; 1114 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&cpg CPG_MOD 209>; 1116 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1117 dma-names = "tx", "rx"; 1118 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1119 resets = <&cpg 209>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 status = "disabled"; 1123 }; 1124 1125 msiof3: spi@e6c10000 { 1126 compatible = "renesas,msiof-r8a77990", 1127 "renesas,rcar-gen3-msiof"; 1128 reg = <0 0xe6c10000 0 0x0064>; 1129 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&cpg CPG_MOD 208>; 1131 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1132 dma-names = "tx", "rx"; 1133 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1134 resets = <&cpg 208>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 vin4: video@e6ef4000 { 1141 compatible = "renesas,vin-r8a77990"; 1142 reg = <0 0xe6ef4000 0 0x1000>; 1143 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&cpg CPG_MOD 807>; 1145 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1146 resets = <&cpg 807>; 1147 renesas,id = <4>; 1148 status = "disabled"; 1149 1150 ports { 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 1154 port@1 { 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 1158 reg = <1>; 1159 1160 vin4csi40: endpoint@2 { 1161 reg = <2>; 1162 remote-endpoint= <&csi40vin4>; 1163 }; 1164 }; 1165 }; 1166 }; 1167 1168 vin5: video@e6ef5000 { 1169 compatible = "renesas,vin-r8a77990"; 1170 reg = <0 0xe6ef5000 0 0x1000>; 1171 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&cpg CPG_MOD 806>; 1173 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1174 resets = <&cpg 806>; 1175 renesas,id = <5>; 1176 status = "disabled"; 1177 1178 ports { 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 1182 port@1 { 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 1186 reg = <1>; 1187 1188 vin5csi40: endpoint@2 { 1189 reg = <2>; 1190 remote-endpoint= <&csi40vin5>; 1191 }; 1192 }; 1193 }; 1194 }; 1195 1196 rcar_sound: sound@ec500000 { 1197 /* 1198 * #sound-dai-cells is required 1199 * 1200 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1201 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1202 */ 1203 /* 1204 * #clock-cells is required for audio_clkout0/1/2/3 1205 * 1206 * clkout : #clock-cells = <0>; <&rcar_sound>; 1207 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1208 */ 1209 compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3"; 1210 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1211 <0 0xec5a0000 0 0x100>, /* ADG */ 1212 <0 0xec540000 0 0x1000>, /* SSIU */ 1213 <0 0xec541000 0 0x280>, /* SSI */ 1214 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1215 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1216 1217 clocks = <&cpg CPG_MOD 1005>, 1218 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1219 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1220 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1221 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1222 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1223 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1224 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1225 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1226 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1227 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1228 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1229 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1230 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1231 <&audio_clk_a>, <&audio_clk_b>, 1232 <&audio_clk_c>, 1233 <&cpg CPG_CORE R8A77990_CLK_ZA2>; 1234 clock-names = "ssi-all", 1235 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1236 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1237 "ssi.1", "ssi.0", 1238 "src.9", "src.8", "src.7", "src.6", 1239 "src.5", "src.4", "src.3", "src.2", 1240 "src.1", "src.0", 1241 "mix.1", "mix.0", 1242 "ctu.1", "ctu.0", 1243 "dvc.0", "dvc.1", 1244 "clk_a", "clk_b", "clk_c", "clk_i"; 1245 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1246 resets = <&cpg 1005>, 1247 <&cpg 1006>, <&cpg 1007>, 1248 <&cpg 1008>, <&cpg 1009>, 1249 <&cpg 1010>, <&cpg 1011>, 1250 <&cpg 1012>, <&cpg 1013>, 1251 <&cpg 1014>, <&cpg 1015>; 1252 reset-names = "ssi-all", 1253 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1254 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1255 "ssi.1", "ssi.0"; 1256 status = "disabled"; 1257 1258 rcar_sound,dvc { 1259 dvc0: dvc-0 { 1260 dmas = <&audma0 0xbc>; 1261 dma-names = "tx"; 1262 }; 1263 dvc1: dvc-1 { 1264 dmas = <&audma0 0xbe>; 1265 dma-names = "tx"; 1266 }; 1267 }; 1268 1269 rcar_sound,mix { 1270 mix0: mix-0 { }; 1271 mix1: mix-1 { }; 1272 }; 1273 1274 rcar_sound,ctu { 1275 ctu00: ctu-0 { }; 1276 ctu01: ctu-1 { }; 1277 ctu02: ctu-2 { }; 1278 ctu03: ctu-3 { }; 1279 ctu10: ctu-4 { }; 1280 ctu11: ctu-5 { }; 1281 ctu12: ctu-6 { }; 1282 ctu13: ctu-7 { }; 1283 }; 1284 1285 rcar_sound,src { 1286 src0: src-0 { 1287 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1288 dmas = <&audma0 0x85>, <&audma0 0x9a>; 1289 dma-names = "rx", "tx"; 1290 }; 1291 src1: src-1 { 1292 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1293 dmas = <&audma0 0x87>, <&audma0 0x9c>; 1294 dma-names = "rx", "tx"; 1295 }; 1296 src2: src-2 { 1297 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1298 dmas = <&audma0 0x89>, <&audma0 0x9e>; 1299 dma-names = "rx", "tx"; 1300 }; 1301 src3: src-3 { 1302 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1303 dmas = <&audma0 0x8b>, <&audma0 0xa0>; 1304 dma-names = "rx", "tx"; 1305 }; 1306 src4: src-4 { 1307 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1308 dmas = <&audma0 0x8d>, <&audma0 0xb0>; 1309 dma-names = "rx", "tx"; 1310 }; 1311 src5: src-5 { 1312 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1313 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1314 dma-names = "rx", "tx"; 1315 }; 1316 src6: src-6 { 1317 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1318 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1319 dma-names = "rx", "tx"; 1320 }; 1321 src7: src-7 { 1322 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1323 dmas = <&audma0 0x93>, <&audma0 0xb6>; 1324 dma-names = "rx", "tx"; 1325 }; 1326 src8: src-8 { 1327 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1328 dmas = <&audma0 0x95>, <&audma0 0xb8>; 1329 dma-names = "rx", "tx"; 1330 }; 1331 src9: src-9 { 1332 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1333 dmas = <&audma0 0x97>, <&audma0 0xba>; 1334 dma-names = "rx", "tx"; 1335 }; 1336 }; 1337 1338 rcar_sound,ssi { 1339 ssi0: ssi-0 { 1340 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1341 dmas = <&audma0 0x01>, <&audma0 0x02>, 1342 <&audma0 0x15>, <&audma0 0x16>; 1343 dma-names = "rx", "tx", "rxu", "txu"; 1344 }; 1345 ssi1: ssi-1 { 1346 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1347 dmas = <&audma0 0x03>, <&audma0 0x04>, 1348 <&audma0 0x49>, <&audma0 0x4a>; 1349 dma-names = "rx", "tx", "rxu", "txu"; 1350 }; 1351 ssi2: ssi-2 { 1352 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1353 dmas = <&audma0 0x05>, <&audma0 0x06>, 1354 <&audma0 0x63>, <&audma0 0x64>; 1355 dma-names = "rx", "tx", "rxu", "txu"; 1356 }; 1357 ssi3: ssi-3 { 1358 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1359 dmas = <&audma0 0x07>, <&audma0 0x08>, 1360 <&audma0 0x6f>, <&audma0 0x70>; 1361 dma-names = "rx", "tx", "rxu", "txu"; 1362 }; 1363 ssi4: ssi-4 { 1364 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1365 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1366 <&audma0 0x71>, <&audma0 0x72>; 1367 dma-names = "rx", "tx", "rxu", "txu"; 1368 }; 1369 ssi5: ssi-5 { 1370 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1371 dmas = <&audma0 0x0b>, <&audma0 0x0c>, 1372 <&audma0 0x73>, <&audma0 0x74>; 1373 dma-names = "rx", "tx", "rxu", "txu"; 1374 }; 1375 ssi6: ssi-6 { 1376 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1377 dmas = <&audma0 0x0d>, <&audma0 0x0e>, 1378 <&audma0 0x75>, <&audma0 0x76>; 1379 dma-names = "rx", "tx", "rxu", "txu"; 1380 }; 1381 ssi7: ssi-7 { 1382 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1383 dmas = <&audma0 0x0f>, <&audma0 0x10>, 1384 <&audma0 0x79>, <&audma0 0x7a>; 1385 dma-names = "rx", "tx", "rxu", "txu"; 1386 }; 1387 ssi8: ssi-8 { 1388 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1389 dmas = <&audma0 0x11>, <&audma0 0x12>, 1390 <&audma0 0x7b>, <&audma0 0x7c>; 1391 dma-names = "rx", "tx", "rxu", "txu"; 1392 }; 1393 ssi9: ssi-9 { 1394 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1395 dmas = <&audma0 0x13>, <&audma0 0x14>, 1396 <&audma0 0x7d>, <&audma0 0x7e>; 1397 dma-names = "rx", "tx", "rxu", "txu"; 1398 }; 1399 }; 1400 }; 1401 1402 audma0: dma-controller@ec700000 { 1403 compatible = "renesas,dmac-r8a77990", 1404 "renesas,rcar-dmac"; 1405 reg = <0 0xec700000 0 0x10000>; 1406 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 1407 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 1408 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 1409 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 1410 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 1411 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 1412 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 1413 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 1414 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 1415 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 1416 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 1417 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 1418 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 1419 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 1420 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 1421 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 1422 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1423 interrupt-names = "error", 1424 "ch0", "ch1", "ch2", "ch3", 1425 "ch4", "ch5", "ch6", "ch7", 1426 "ch8", "ch9", "ch10", "ch11", 1427 "ch12", "ch13", "ch14", "ch15"; 1428 clocks = <&cpg CPG_MOD 502>; 1429 clock-names = "fck"; 1430 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1431 resets = <&cpg 502>; 1432 #dma-cells = <1>; 1433 dma-channels = <16>; 1434 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1435 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1436 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1437 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1438 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1439 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1440 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1441 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1442 }; 1443 1444 xhci0: usb@ee000000 { 1445 compatible = "renesas,xhci-r8a77990", 1446 "renesas,rcar-gen3-xhci"; 1447 reg = <0 0xee000000 0 0xc00>; 1448 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1449 clocks = <&cpg CPG_MOD 328>; 1450 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1451 resets = <&cpg 328>; 1452 status = "disabled"; 1453 }; 1454 1455 usb3_peri0: usb@ee020000 { 1456 compatible = "renesas,r8a77990-usb3-peri", 1457 "renesas,rcar-gen3-usb3-peri"; 1458 reg = <0 0xee020000 0 0x400>; 1459 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1460 clocks = <&cpg CPG_MOD 328>; 1461 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1462 resets = <&cpg 328>; 1463 status = "disabled"; 1464 }; 1465 1466 ohci0: usb@ee080000 { 1467 compatible = "generic-ohci"; 1468 reg = <0 0xee080000 0 0x100>; 1469 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1470 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1471 phys = <&usb2_phy0>; 1472 phy-names = "usb"; 1473 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1474 resets = <&cpg 703>, <&cpg 704>; 1475 status = "disabled"; 1476 }; 1477 1478 ehci0: usb@ee080100 { 1479 compatible = "generic-ehci"; 1480 reg = <0 0xee080100 0 0x100>; 1481 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1482 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1483 phys = <&usb2_phy0>; 1484 phy-names = "usb"; 1485 companion = <&ohci0>; 1486 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1487 resets = <&cpg 703>, <&cpg 704>; 1488 status = "disabled"; 1489 }; 1490 1491 usb2_phy0: usb-phy@ee080200 { 1492 compatible = "renesas,usb2-phy-r8a77990", 1493 "renesas,rcar-gen3-usb2-phy"; 1494 reg = <0 0xee080200 0 0x700>; 1495 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1496 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1497 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1498 resets = <&cpg 703>, <&cpg 704>; 1499 #phy-cells = <0>; 1500 status = "disabled"; 1501 }; 1502 1503 sdhi0: sd@ee100000 { 1504 compatible = "renesas,sdhi-r8a77990", 1505 "renesas,rcar-gen3-sdhi"; 1506 reg = <0 0xee100000 0 0x2000>; 1507 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1508 clocks = <&cpg CPG_MOD 314>; 1509 max-frequency = <200000000>; 1510 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1511 resets = <&cpg 314>; 1512 status = "disabled"; 1513 }; 1514 1515 sdhi1: sd@ee120000 { 1516 compatible = "renesas,sdhi-r8a77990", 1517 "renesas,rcar-gen3-sdhi"; 1518 reg = <0 0xee120000 0 0x2000>; 1519 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1520 clocks = <&cpg CPG_MOD 313>; 1521 max-frequency = <200000000>; 1522 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1523 resets = <&cpg 313>; 1524 status = "disabled"; 1525 }; 1526 1527 sdhi3: sd@ee160000 { 1528 compatible = "renesas,sdhi-r8a77990", 1529 "renesas,rcar-gen3-sdhi"; 1530 reg = <0 0xee160000 0 0x2000>; 1531 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1532 clocks = <&cpg CPG_MOD 311>; 1533 max-frequency = <200000000>; 1534 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1535 resets = <&cpg 311>; 1536 status = "disabled"; 1537 }; 1538 1539 gic: interrupt-controller@f1010000 { 1540 compatible = "arm,gic-400"; 1541 #interrupt-cells = <3>; 1542 #address-cells = <0>; 1543 interrupt-controller; 1544 reg = <0x0 0xf1010000 0 0x1000>, 1545 <0x0 0xf1020000 0 0x20000>, 1546 <0x0 0xf1040000 0 0x20000>, 1547 <0x0 0xf1060000 0 0x20000>; 1548 interrupts = <GIC_PPI 9 1549 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1550 clocks = <&cpg CPG_MOD 408>; 1551 clock-names = "clk"; 1552 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1553 resets = <&cpg 408>; 1554 }; 1555 1556 pciec0: pcie@fe000000 { 1557 compatible = "renesas,pcie-r8a77990", 1558 "renesas,pcie-rcar-gen3"; 1559 reg = <0 0xfe000000 0 0x80000>; 1560 #address-cells = <3>; 1561 #size-cells = <2>; 1562 bus-range = <0x00 0xff>; 1563 device_type = "pci"; 1564 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 1565 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 1566 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 1567 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1568 /* Map all possible DDR as inbound ranges */ 1569 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 1570 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1573 #interrupt-cells = <1>; 1574 interrupt-map-mask = <0 0 0 0>; 1575 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1576 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1577 clock-names = "pcie", "pcie_bus"; 1578 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1579 resets = <&cpg 319>; 1580 status = "disabled"; 1581 }; 1582 1583 vspb0: vsp@fe960000 { 1584 compatible = "renesas,vsp2"; 1585 reg = <0 0xfe960000 0 0x8000>; 1586 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1587 clocks = <&cpg CPG_MOD 626>; 1588 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1589 resets = <&cpg 626>; 1590 renesas,fcp = <&fcpvb0>; 1591 }; 1592 1593 fcpvb0: fcp@fe96f000 { 1594 compatible = "renesas,fcpv"; 1595 reg = <0 0xfe96f000 0 0x200>; 1596 clocks = <&cpg CPG_MOD 607>; 1597 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1598 resets = <&cpg 607>; 1599 iommus = <&ipmmu_vp0 5>; 1600 }; 1601 1602 vspi0: vsp@fe9a0000 { 1603 compatible = "renesas,vsp2"; 1604 reg = <0 0xfe9a0000 0 0x8000>; 1605 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1606 clocks = <&cpg CPG_MOD 631>; 1607 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1608 resets = <&cpg 631>; 1609 renesas,fcp = <&fcpvi0>; 1610 }; 1611 1612 fcpvi0: fcp@fe9af000 { 1613 compatible = "renesas,fcpv"; 1614 reg = <0 0xfe9af000 0 0x200>; 1615 clocks = <&cpg CPG_MOD 611>; 1616 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1617 resets = <&cpg 611>; 1618 iommus = <&ipmmu_vp0 8>; 1619 }; 1620 1621 vspd0: vsp@fea20000 { 1622 compatible = "renesas,vsp2"; 1623 reg = <0 0xfea20000 0 0x7000>; 1624 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1625 clocks = <&cpg CPG_MOD 623>; 1626 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1627 resets = <&cpg 623>; 1628 renesas,fcp = <&fcpvd0>; 1629 }; 1630 1631 fcpvd0: fcp@fea27000 { 1632 compatible = "renesas,fcpv"; 1633 reg = <0 0xfea27000 0 0x200>; 1634 clocks = <&cpg CPG_MOD 603>; 1635 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1636 resets = <&cpg 603>; 1637 iommus = <&ipmmu_vi0 8>; 1638 }; 1639 1640 vspd1: vsp@fea28000 { 1641 compatible = "renesas,vsp2"; 1642 reg = <0 0xfea28000 0 0x7000>; 1643 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1644 clocks = <&cpg CPG_MOD 622>; 1645 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1646 resets = <&cpg 622>; 1647 renesas,fcp = <&fcpvd1>; 1648 }; 1649 1650 fcpvd1: fcp@fea2f000 { 1651 compatible = "renesas,fcpv"; 1652 reg = <0 0xfea2f000 0 0x200>; 1653 clocks = <&cpg CPG_MOD 602>; 1654 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1655 resets = <&cpg 602>; 1656 iommus = <&ipmmu_vi0 9>; 1657 }; 1658 1659 csi40: csi2@feaa0000 { 1660 compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2"; 1661 reg = <0 0xfeaa0000 0 0x10000>; 1662 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1663 clocks = <&cpg CPG_MOD 716>; 1664 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1665 resets = <&cpg 716>; 1666 status = "disabled"; 1667 1668 ports { 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 1672 port@1 { 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 1676 reg = <1>; 1677 1678 csi40vin4: endpoint@0 { 1679 reg = <0>; 1680 remote-endpoint = <&vin4csi40>; 1681 }; 1682 csi40vin5: endpoint@1 { 1683 reg = <1>; 1684 remote-endpoint = <&vin5csi40>; 1685 }; 1686 }; 1687 }; 1688 }; 1689 1690 du: display@feb00000 { 1691 compatible = "renesas,du-r8a77990"; 1692 reg = <0 0xfeb00000 0 0x80000>; 1693 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1695 clocks = <&cpg CPG_MOD 724>, 1696 <&cpg CPG_MOD 723>; 1697 clock-names = "du.0", "du.1"; 1698 vsps = <&vspd0 0 &vspd1 0>; 1699 status = "disabled"; 1700 1701 ports { 1702 #address-cells = <1>; 1703 #size-cells = <0>; 1704 1705 port@0 { 1706 reg = <0>; 1707 du_out_rgb: endpoint { 1708 }; 1709 }; 1710 1711 port@1 { 1712 reg = <1>; 1713 du_out_lvds0: endpoint { 1714 remote-endpoint = <&lvds0_in>; 1715 }; 1716 }; 1717 1718 port@2 { 1719 reg = <2>; 1720 du_out_lvds1: endpoint { 1721 remote-endpoint = <&lvds1_in>; 1722 }; 1723 }; 1724 }; 1725 }; 1726 1727 lvds0: lvds-encoder@feb90000 { 1728 compatible = "renesas,r8a77990-lvds"; 1729 reg = <0 0xfeb90000 0 0x20>; 1730 clocks = <&cpg CPG_MOD 727>; 1731 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1732 resets = <&cpg 727>; 1733 status = "disabled"; 1734 1735 ports { 1736 #address-cells = <1>; 1737 #size-cells = <0>; 1738 1739 port@0 { 1740 reg = <0>; 1741 lvds0_in: endpoint { 1742 remote-endpoint = <&du_out_lvds0>; 1743 }; 1744 }; 1745 1746 port@1 { 1747 reg = <1>; 1748 lvds0_out: endpoint { 1749 }; 1750 }; 1751 }; 1752 }; 1753 1754 lvds1: lvds-encoder@feb90100 { 1755 compatible = "renesas,r8a77990-lvds"; 1756 reg = <0 0xfeb90100 0 0x20>; 1757 clocks = <&cpg CPG_MOD 727>; 1758 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 1759 resets = <&cpg 726>; 1760 status = "disabled"; 1761 1762 ports { 1763 #address-cells = <1>; 1764 #size-cells = <0>; 1765 1766 port@0 { 1767 reg = <0>; 1768 lvds1_in: endpoint { 1769 remote-endpoint = <&du_out_lvds1>; 1770 }; 1771 }; 1772 1773 port@1 { 1774 reg = <1>; 1775 lvds1_out: endpoint { 1776 }; 1777 }; 1778 }; 1779 }; 1780 1781 prr: chipid@fff00044 { 1782 compatible = "renesas,prr"; 1783 reg = <0 0xfff00044 0 4>; 1784 }; 1785 }; 1786 1787 thermal-zones { 1788 cpu-thermal { 1789 polling-delay-passive = <250>; 1790 polling-delay = <1000>; 1791 thermal-sensors = <&thermal>; 1792 1793 trips { 1794 cpu-crit { 1795 temperature = <120000>; 1796 hysteresis = <2000>; 1797 type = "critical"; 1798 }; 1799 }; 1800 1801 cooling-maps { 1802 }; 1803 }; 1804 }; 1805 1806 timer { 1807 compatible = "arm,armv8-timer"; 1808 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1809 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1810 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1811 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1812 }; 1813}; 1814